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Merge branch 'misc' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild
[deliverable/linux.git] / drivers / spi / spi-rspi.c
1 /*
2 * SH RSPI driver
3 *
4 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2014 Glider bvba
6 *
7 * Based on spi-sh.c:
8 * Copyright (C) 2011 Renesas Solutions Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/of_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/sh_dma.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/rspi.h>
35
36 #define RSPI_SPCR 0x00 /* Control Register */
37 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
38 #define RSPI_SPPCR 0x02 /* Pin Control Register */
39 #define RSPI_SPSR 0x03 /* Status Register */
40 #define RSPI_SPDR 0x04 /* Data Register */
41 #define RSPI_SPSCR 0x08 /* Sequence Control Register */
42 #define RSPI_SPSSR 0x09 /* Sequence Status Register */
43 #define RSPI_SPBR 0x0a /* Bit Rate Register */
44 #define RSPI_SPDCR 0x0b /* Data Control Register */
45 #define RSPI_SPCKD 0x0c /* Clock Delay Register */
46 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
47 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
48 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
49 #define RSPI_SPCMD0 0x10 /* Command Register 0 */
50 #define RSPI_SPCMD1 0x12 /* Command Register 1 */
51 #define RSPI_SPCMD2 0x14 /* Command Register 2 */
52 #define RSPI_SPCMD3 0x16 /* Command Register 3 */
53 #define RSPI_SPCMD4 0x18 /* Command Register 4 */
54 #define RSPI_SPCMD5 0x1a /* Command Register 5 */
55 #define RSPI_SPCMD6 0x1c /* Command Register 6 */
56 #define RSPI_SPCMD7 0x1e /* Command Register 7 */
57 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
58 #define RSPI_NUM_SPCMD 8
59 #define RSPI_RZ_NUM_SPCMD 4
60 #define QSPI_NUM_SPCMD 4
61
62 /* RSPI on RZ only */
63 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */
64 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
65
66 /* QSPI only */
67 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */
68 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
69 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
70 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
71 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
72 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
73 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
74
75 /* SPCR - Control Register */
76 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
77 #define SPCR_SPE 0x40 /* Function Enable */
78 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
79 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
80 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
81 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
82 /* RSPI on SH only */
83 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
84 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
85 /* QSPI on R-Car Gen2 only */
86 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
87 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
88
89 /* SSLP - Slave Select Polarity Register */
90 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
91 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
92
93 /* SPPCR - Pin Control Register */
94 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
95 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
96 #define SPPCR_SPOM 0x04
97 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
98 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
99
100 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
101 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
102
103 /* SPSR - Status Register */
104 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
105 #define SPSR_TEND 0x40 /* Transmit End */
106 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
107 #define SPSR_PERF 0x08 /* Parity Error Flag */
108 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
109 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
110 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
111
112 /* SPSCR - Sequence Control Register */
113 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
114
115 /* SPSSR - Sequence Status Register */
116 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
117 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
118
119 /* SPDCR - Data Control Register */
120 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
121 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
122 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
123 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
124 #define SPDCR_SPLWORD SPDCR_SPLW1
125 #define SPDCR_SPLBYTE SPDCR_SPLW0
126 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
127 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
128 #define SPDCR_SLSEL1 0x08
129 #define SPDCR_SLSEL0 0x04
130 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
131 #define SPDCR_SPFC1 0x02
132 #define SPDCR_SPFC0 0x01
133 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
134
135 /* SPCKD - Clock Delay Register */
136 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
137
138 /* SSLND - Slave Select Negation Delay Register */
139 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
140
141 /* SPND - Next-Access Delay Register */
142 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
143
144 /* SPCR2 - Control Register 2 */
145 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
146 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
147 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
148 #define SPCR2_SPPE 0x01 /* Parity Enable */
149
150 /* SPCMDn - Command Registers */
151 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
152 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
153 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
154 #define SPCMD_LSBF 0x1000 /* LSB First */
155 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
156 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
157 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
158 #define SPCMD_SPB_16BIT 0x0100
159 #define SPCMD_SPB_20BIT 0x0000
160 #define SPCMD_SPB_24BIT 0x0100
161 #define SPCMD_SPB_32BIT 0x0200
162 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
163 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
164 #define SPCMD_SPIMOD1 0x0040
165 #define SPCMD_SPIMOD0 0x0020
166 #define SPCMD_SPIMOD_SINGLE 0
167 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
168 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
169 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
170 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
171 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
172 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
173 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
174
175 /* SPBFCR - Buffer Control Register */
176 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
177 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
178 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
179 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
180 /* QSPI on R-Car Gen2 */
181 #define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */
182 #define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */
183 #define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */
184 #define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */
185
186 #define QSPI_BUFFER_SIZE 32u
187
188 struct rspi_data {
189 void __iomem *addr;
190 u32 max_speed_hz;
191 struct spi_master *master;
192 wait_queue_head_t wait;
193 struct clk *clk;
194 u16 spcmd;
195 u8 spsr;
196 u8 sppcr;
197 int rx_irq, tx_irq;
198 const struct spi_ops *ops;
199
200 unsigned dma_callbacked:1;
201 unsigned byte_access:1;
202 };
203
204 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
205 {
206 iowrite8(data, rspi->addr + offset);
207 }
208
209 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
210 {
211 iowrite16(data, rspi->addr + offset);
212 }
213
214 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
215 {
216 iowrite32(data, rspi->addr + offset);
217 }
218
219 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
220 {
221 return ioread8(rspi->addr + offset);
222 }
223
224 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
225 {
226 return ioread16(rspi->addr + offset);
227 }
228
229 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
230 {
231 if (rspi->byte_access)
232 rspi_write8(rspi, data, RSPI_SPDR);
233 else /* 16 bit */
234 rspi_write16(rspi, data, RSPI_SPDR);
235 }
236
237 static u16 rspi_read_data(const struct rspi_data *rspi)
238 {
239 if (rspi->byte_access)
240 return rspi_read8(rspi, RSPI_SPDR);
241 else /* 16 bit */
242 return rspi_read16(rspi, RSPI_SPDR);
243 }
244
245 /* optional functions */
246 struct spi_ops {
247 int (*set_config_register)(struct rspi_data *rspi, int access_size);
248 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
249 struct spi_transfer *xfer);
250 u16 mode_bits;
251 u16 flags;
252 u16 fifo_size;
253 };
254
255 /*
256 * functions for RSPI on legacy SH
257 */
258 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
259 {
260 int spbr;
261
262 /* Sets output mode, MOSI signal, and (optionally) loopback */
263 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
264
265 /* Sets transfer bit rate */
266 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
267 2 * rspi->max_speed_hz) - 1;
268 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
269
270 /* Disable dummy transmission, set 16-bit word access, 1 frame */
271 rspi_write8(rspi, 0, RSPI_SPDCR);
272 rspi->byte_access = 0;
273
274 /* Sets RSPCK, SSL, next-access delay value */
275 rspi_write8(rspi, 0x00, RSPI_SPCKD);
276 rspi_write8(rspi, 0x00, RSPI_SSLND);
277 rspi_write8(rspi, 0x00, RSPI_SPND);
278
279 /* Sets parity, interrupt mask */
280 rspi_write8(rspi, 0x00, RSPI_SPCR2);
281
282 /* Sets SPCMD */
283 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
284 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
285
286 /* Sets RSPI mode */
287 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
288
289 return 0;
290 }
291
292 /*
293 * functions for RSPI on RZ
294 */
295 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
296 {
297 int spbr;
298
299 /* Sets output mode, MOSI signal, and (optionally) loopback */
300 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
301
302 /* Sets transfer bit rate */
303 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
304 2 * rspi->max_speed_hz) - 1;
305 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
306
307 /* Disable dummy transmission, set byte access */
308 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
309 rspi->byte_access = 1;
310
311 /* Sets RSPCK, SSL, next-access delay value */
312 rspi_write8(rspi, 0x00, RSPI_SPCKD);
313 rspi_write8(rspi, 0x00, RSPI_SSLND);
314 rspi_write8(rspi, 0x00, RSPI_SPND);
315
316 /* Sets SPCMD */
317 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
318 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
319
320 /* Sets RSPI mode */
321 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
322
323 return 0;
324 }
325
326 /*
327 * functions for QSPI
328 */
329 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
330 {
331 int spbr;
332
333 /* Sets output mode, MOSI signal, and (optionally) loopback */
334 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
335
336 /* Sets transfer bit rate */
337 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
338 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
339
340 /* Disable dummy transmission, set byte access */
341 rspi_write8(rspi, 0, RSPI_SPDCR);
342 rspi->byte_access = 1;
343
344 /* Sets RSPCK, SSL, next-access delay value */
345 rspi_write8(rspi, 0x00, RSPI_SPCKD);
346 rspi_write8(rspi, 0x00, RSPI_SSLND);
347 rspi_write8(rspi, 0x00, RSPI_SPND);
348
349 /* Data Length Setting */
350 if (access_size == 8)
351 rspi->spcmd |= SPCMD_SPB_8BIT;
352 else if (access_size == 16)
353 rspi->spcmd |= SPCMD_SPB_16BIT;
354 else
355 rspi->spcmd |= SPCMD_SPB_32BIT;
356
357 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
358
359 /* Resets transfer data length */
360 rspi_write32(rspi, 0, QSPI_SPBMUL0);
361
362 /* Resets transmit and receive buffer */
363 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
364 /* Sets buffer to allow normal operation */
365 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
366
367 /* Sets SPCMD */
368 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
369
370 /* Enables SPI function in master mode */
371 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
372
373 return 0;
374 }
375
376 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
377 {
378 u8 data;
379
380 data = rspi_read8(rspi, reg);
381 data &= ~mask;
382 data |= (val & mask);
383 rspi_write8(rspi, data, reg);
384 }
385
386 static int qspi_set_send_trigger(struct rspi_data *rspi, unsigned int len)
387 {
388 unsigned int n;
389
390 n = min(len, QSPI_BUFFER_SIZE);
391
392 if (len >= QSPI_BUFFER_SIZE) {
393 /* sets triggering number to 32 bytes */
394 qspi_update(rspi, SPBFCR_TXTRG_MASK,
395 SPBFCR_TXTRG_32B, QSPI_SPBFCR);
396 } else {
397 /* sets triggering number to 1 byte */
398 qspi_update(rspi, SPBFCR_TXTRG_MASK,
399 SPBFCR_TXTRG_1B, QSPI_SPBFCR);
400 }
401
402 return n;
403 }
404
405 static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
406 {
407 unsigned int n;
408
409 n = min(len, QSPI_BUFFER_SIZE);
410
411 if (len >= QSPI_BUFFER_SIZE) {
412 /* sets triggering number to 32 bytes */
413 qspi_update(rspi, SPBFCR_RXTRG_MASK,
414 SPBFCR_RXTRG_32B, QSPI_SPBFCR);
415 } else {
416 /* sets triggering number to 1 byte */
417 qspi_update(rspi, SPBFCR_RXTRG_MASK,
418 SPBFCR_RXTRG_1B, QSPI_SPBFCR);
419 }
420 }
421
422 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
423
424 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
425 {
426 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
427 }
428
429 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
430 {
431 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
432 }
433
434 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
435 u8 enable_bit)
436 {
437 int ret;
438
439 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
440 if (rspi->spsr & wait_mask)
441 return 0;
442
443 rspi_enable_irq(rspi, enable_bit);
444 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
445 if (ret == 0 && !(rspi->spsr & wait_mask))
446 return -ETIMEDOUT;
447
448 return 0;
449 }
450
451 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
452 {
453 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
454 }
455
456 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
457 {
458 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
459 }
460
461 static int rspi_data_out(struct rspi_data *rspi, u8 data)
462 {
463 int error = rspi_wait_for_tx_empty(rspi);
464 if (error < 0) {
465 dev_err(&rspi->master->dev, "transmit timeout\n");
466 return error;
467 }
468 rspi_write_data(rspi, data);
469 return 0;
470 }
471
472 static int rspi_data_in(struct rspi_data *rspi)
473 {
474 int error;
475 u8 data;
476
477 error = rspi_wait_for_rx_full(rspi);
478 if (error < 0) {
479 dev_err(&rspi->master->dev, "receive timeout\n");
480 return error;
481 }
482 data = rspi_read_data(rspi);
483 return data;
484 }
485
486 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
487 unsigned int n)
488 {
489 while (n-- > 0) {
490 if (tx) {
491 int ret = rspi_data_out(rspi, *tx++);
492 if (ret < 0)
493 return ret;
494 }
495 if (rx) {
496 int ret = rspi_data_in(rspi);
497 if (ret < 0)
498 return ret;
499 *rx++ = ret;
500 }
501 }
502
503 return 0;
504 }
505
506 static void rspi_dma_complete(void *arg)
507 {
508 struct rspi_data *rspi = arg;
509
510 rspi->dma_callbacked = 1;
511 wake_up_interruptible(&rspi->wait);
512 }
513
514 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
515 struct sg_table *rx)
516 {
517 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
518 u8 irq_mask = 0;
519 unsigned int other_irq = 0;
520 dma_cookie_t cookie;
521 int ret;
522
523 /* First prepare and submit the DMA request(s), as this may fail */
524 if (rx) {
525 desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx,
526 rx->sgl, rx->nents, DMA_FROM_DEVICE,
527 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
528 if (!desc_rx) {
529 ret = -EAGAIN;
530 goto no_dma_rx;
531 }
532
533 desc_rx->callback = rspi_dma_complete;
534 desc_rx->callback_param = rspi;
535 cookie = dmaengine_submit(desc_rx);
536 if (dma_submit_error(cookie)) {
537 ret = cookie;
538 goto no_dma_rx;
539 }
540
541 irq_mask |= SPCR_SPRIE;
542 }
543
544 if (tx) {
545 desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx,
546 tx->sgl, tx->nents, DMA_TO_DEVICE,
547 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
548 if (!desc_tx) {
549 ret = -EAGAIN;
550 goto no_dma_tx;
551 }
552
553 if (rx) {
554 /* No callback */
555 desc_tx->callback = NULL;
556 } else {
557 desc_tx->callback = rspi_dma_complete;
558 desc_tx->callback_param = rspi;
559 }
560 cookie = dmaengine_submit(desc_tx);
561 if (dma_submit_error(cookie)) {
562 ret = cookie;
563 goto no_dma_tx;
564 }
565
566 irq_mask |= SPCR_SPTIE;
567 }
568
569 /*
570 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
571 * called. So, this driver disables the IRQ while DMA transfer.
572 */
573 if (tx)
574 disable_irq(other_irq = rspi->tx_irq);
575 if (rx && rspi->rx_irq != other_irq)
576 disable_irq(rspi->rx_irq);
577
578 rspi_enable_irq(rspi, irq_mask);
579 rspi->dma_callbacked = 0;
580
581 /* Now start DMA */
582 if (rx)
583 dma_async_issue_pending(rspi->master->dma_rx);
584 if (tx)
585 dma_async_issue_pending(rspi->master->dma_tx);
586
587 ret = wait_event_interruptible_timeout(rspi->wait,
588 rspi->dma_callbacked, HZ);
589 if (ret > 0 && rspi->dma_callbacked)
590 ret = 0;
591 else if (!ret) {
592 dev_err(&rspi->master->dev, "DMA timeout\n");
593 ret = -ETIMEDOUT;
594 if (tx)
595 dmaengine_terminate_all(rspi->master->dma_tx);
596 if (rx)
597 dmaengine_terminate_all(rspi->master->dma_rx);
598 }
599
600 rspi_disable_irq(rspi, irq_mask);
601
602 if (tx)
603 enable_irq(rspi->tx_irq);
604 if (rx && rspi->rx_irq != other_irq)
605 enable_irq(rspi->rx_irq);
606
607 return ret;
608
609 no_dma_tx:
610 if (rx)
611 dmaengine_terminate_all(rspi->master->dma_rx);
612 no_dma_rx:
613 if (ret == -EAGAIN) {
614 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
615 dev_driver_string(&rspi->master->dev),
616 dev_name(&rspi->master->dev));
617 }
618 return ret;
619 }
620
621 static void rspi_receive_init(const struct rspi_data *rspi)
622 {
623 u8 spsr;
624
625 spsr = rspi_read8(rspi, RSPI_SPSR);
626 if (spsr & SPSR_SPRF)
627 rspi_read_data(rspi); /* dummy read */
628 if (spsr & SPSR_OVRF)
629 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
630 RSPI_SPSR);
631 }
632
633 static void rspi_rz_receive_init(const struct rspi_data *rspi)
634 {
635 rspi_receive_init(rspi);
636 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
637 rspi_write8(rspi, 0, RSPI_SPBFCR);
638 }
639
640 static void qspi_receive_init(const struct rspi_data *rspi)
641 {
642 u8 spsr;
643
644 spsr = rspi_read8(rspi, RSPI_SPSR);
645 if (spsr & SPSR_SPRF)
646 rspi_read_data(rspi); /* dummy read */
647 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
648 rspi_write8(rspi, 0, QSPI_SPBFCR);
649 }
650
651 static bool __rspi_can_dma(const struct rspi_data *rspi,
652 const struct spi_transfer *xfer)
653 {
654 return xfer->len > rspi->ops->fifo_size;
655 }
656
657 static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi,
658 struct spi_transfer *xfer)
659 {
660 struct rspi_data *rspi = spi_master_get_devdata(master);
661
662 return __rspi_can_dma(rspi, xfer);
663 }
664
665 static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
666 struct spi_transfer *xfer)
667 {
668 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
669 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
670 int ret = rspi_dma_transfer(rspi, &xfer->tx_sg,
671 xfer->rx_buf ? &xfer->rx_sg : NULL);
672 if (ret != -EAGAIN)
673 return 0;
674 }
675
676 return -EAGAIN;
677 }
678
679 static int rspi_common_transfer(struct rspi_data *rspi,
680 struct spi_transfer *xfer)
681 {
682 int ret;
683
684 ret = rspi_dma_check_then_transfer(rspi, xfer);
685 if (ret != -EAGAIN)
686 return ret;
687
688 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
689 if (ret < 0)
690 return ret;
691
692 /* Wait for the last transmission */
693 rspi_wait_for_tx_empty(rspi);
694
695 return 0;
696 }
697
698 static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
699 struct spi_transfer *xfer)
700 {
701 struct rspi_data *rspi = spi_master_get_devdata(master);
702 u8 spcr;
703
704 spcr = rspi_read8(rspi, RSPI_SPCR);
705 if (xfer->rx_buf) {
706 rspi_receive_init(rspi);
707 spcr &= ~SPCR_TXMD;
708 } else {
709 spcr |= SPCR_TXMD;
710 }
711 rspi_write8(rspi, spcr, RSPI_SPCR);
712
713 return rspi_common_transfer(rspi, xfer);
714 }
715
716 static int rspi_rz_transfer_one(struct spi_master *master,
717 struct spi_device *spi,
718 struct spi_transfer *xfer)
719 {
720 struct rspi_data *rspi = spi_master_get_devdata(master);
721
722 rspi_rz_receive_init(rspi);
723
724 return rspi_common_transfer(rspi, xfer);
725 }
726
727 static int qspi_trigger_transfer_out_int(struct rspi_data *rspi, const u8 *tx,
728 u8 *rx, unsigned int len)
729 {
730 int i, n, ret;
731 int error;
732
733 while (len > 0) {
734 n = qspi_set_send_trigger(rspi, len);
735 qspi_set_receive_trigger(rspi, len);
736 if (n == QSPI_BUFFER_SIZE) {
737 error = rspi_wait_for_tx_empty(rspi);
738 if (error < 0) {
739 dev_err(&rspi->master->dev, "transmit timeout\n");
740 return error;
741 }
742 for (i = 0; i < n; i++)
743 rspi_write_data(rspi, *tx++);
744
745 error = rspi_wait_for_rx_full(rspi);
746 if (error < 0) {
747 dev_err(&rspi->master->dev, "receive timeout\n");
748 return error;
749 }
750 for (i = 0; i < n; i++)
751 *rx++ = rspi_read_data(rspi);
752 } else {
753 ret = rspi_pio_transfer(rspi, tx, rx, n);
754 if (ret < 0)
755 return ret;
756 }
757 len -= n;
758 }
759
760 return 0;
761 }
762
763 static int qspi_transfer_out_in(struct rspi_data *rspi,
764 struct spi_transfer *xfer)
765 {
766 int ret;
767
768 qspi_receive_init(rspi);
769
770 ret = rspi_dma_check_then_transfer(rspi, xfer);
771 if (ret != -EAGAIN)
772 return ret;
773
774 ret = qspi_trigger_transfer_out_int(rspi, xfer->tx_buf,
775 xfer->rx_buf, xfer->len);
776 if (ret < 0)
777 return ret;
778
779 return 0;
780 }
781
782 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
783 {
784 int ret;
785
786 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
787 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
788 if (ret != -EAGAIN)
789 return ret;
790 }
791
792 ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
793 if (ret < 0)
794 return ret;
795
796 /* Wait for the last transmission */
797 rspi_wait_for_tx_empty(rspi);
798
799 return 0;
800 }
801
802 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
803 {
804 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
805 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
806 if (ret != -EAGAIN)
807 return ret;
808 }
809
810 return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
811 }
812
813 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
814 struct spi_transfer *xfer)
815 {
816 struct rspi_data *rspi = spi_master_get_devdata(master);
817
818 if (spi->mode & SPI_LOOP) {
819 return qspi_transfer_out_in(rspi, xfer);
820 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
821 /* Quad or Dual SPI Write */
822 return qspi_transfer_out(rspi, xfer);
823 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
824 /* Quad or Dual SPI Read */
825 return qspi_transfer_in(rspi, xfer);
826 } else {
827 /* Single SPI Transfer */
828 return qspi_transfer_out_in(rspi, xfer);
829 }
830 }
831
832 static int rspi_setup(struct spi_device *spi)
833 {
834 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
835
836 rspi->max_speed_hz = spi->max_speed_hz;
837
838 rspi->spcmd = SPCMD_SSLKP;
839 if (spi->mode & SPI_CPOL)
840 rspi->spcmd |= SPCMD_CPOL;
841 if (spi->mode & SPI_CPHA)
842 rspi->spcmd |= SPCMD_CPHA;
843
844 /* CMOS output mode and MOSI signal from previous transfer */
845 rspi->sppcr = 0;
846 if (spi->mode & SPI_LOOP)
847 rspi->sppcr |= SPPCR_SPLP;
848
849 set_config_register(rspi, 8);
850
851 return 0;
852 }
853
854 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
855 {
856 if (xfer->tx_buf)
857 switch (xfer->tx_nbits) {
858 case SPI_NBITS_QUAD:
859 return SPCMD_SPIMOD_QUAD;
860 case SPI_NBITS_DUAL:
861 return SPCMD_SPIMOD_DUAL;
862 default:
863 return 0;
864 }
865 if (xfer->rx_buf)
866 switch (xfer->rx_nbits) {
867 case SPI_NBITS_QUAD:
868 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
869 case SPI_NBITS_DUAL:
870 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
871 default:
872 return 0;
873 }
874
875 return 0;
876 }
877
878 static int qspi_setup_sequencer(struct rspi_data *rspi,
879 const struct spi_message *msg)
880 {
881 const struct spi_transfer *xfer;
882 unsigned int i = 0, len = 0;
883 u16 current_mode = 0xffff, mode;
884
885 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
886 mode = qspi_transfer_mode(xfer);
887 if (mode == current_mode) {
888 len += xfer->len;
889 continue;
890 }
891
892 /* Transfer mode change */
893 if (i) {
894 /* Set transfer data length of previous transfer */
895 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
896 }
897
898 if (i >= QSPI_NUM_SPCMD) {
899 dev_err(&msg->spi->dev,
900 "Too many different transfer modes");
901 return -EINVAL;
902 }
903
904 /* Program transfer mode for this transfer */
905 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
906 current_mode = mode;
907 len = xfer->len;
908 i++;
909 }
910 if (i) {
911 /* Set final transfer data length and sequence length */
912 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
913 rspi_write8(rspi, i - 1, RSPI_SPSCR);
914 }
915
916 return 0;
917 }
918
919 static int rspi_prepare_message(struct spi_master *master,
920 struct spi_message *msg)
921 {
922 struct rspi_data *rspi = spi_master_get_devdata(master);
923 int ret;
924
925 if (msg->spi->mode &
926 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
927 /* Setup sequencer for messages with multiple transfer modes */
928 ret = qspi_setup_sequencer(rspi, msg);
929 if (ret < 0)
930 return ret;
931 }
932
933 /* Enable SPI function in master mode */
934 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
935 return 0;
936 }
937
938 static int rspi_unprepare_message(struct spi_master *master,
939 struct spi_message *msg)
940 {
941 struct rspi_data *rspi = spi_master_get_devdata(master);
942
943 /* Disable SPI function */
944 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
945
946 /* Reset sequencer for Single SPI Transfers */
947 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
948 rspi_write8(rspi, 0, RSPI_SPSCR);
949 return 0;
950 }
951
952 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
953 {
954 struct rspi_data *rspi = _sr;
955 u8 spsr;
956 irqreturn_t ret = IRQ_NONE;
957 u8 disable_irq = 0;
958
959 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
960 if (spsr & SPSR_SPRF)
961 disable_irq |= SPCR_SPRIE;
962 if (spsr & SPSR_SPTEF)
963 disable_irq |= SPCR_SPTIE;
964
965 if (disable_irq) {
966 ret = IRQ_HANDLED;
967 rspi_disable_irq(rspi, disable_irq);
968 wake_up(&rspi->wait);
969 }
970
971 return ret;
972 }
973
974 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
975 {
976 struct rspi_data *rspi = _sr;
977 u8 spsr;
978
979 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
980 if (spsr & SPSR_SPRF) {
981 rspi_disable_irq(rspi, SPCR_SPRIE);
982 wake_up(&rspi->wait);
983 return IRQ_HANDLED;
984 }
985
986 return 0;
987 }
988
989 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
990 {
991 struct rspi_data *rspi = _sr;
992 u8 spsr;
993
994 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
995 if (spsr & SPSR_SPTEF) {
996 rspi_disable_irq(rspi, SPCR_SPTIE);
997 wake_up(&rspi->wait);
998 return IRQ_HANDLED;
999 }
1000
1001 return 0;
1002 }
1003
1004 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
1005 enum dma_transfer_direction dir,
1006 unsigned int id,
1007 dma_addr_t port_addr)
1008 {
1009 dma_cap_mask_t mask;
1010 struct dma_chan *chan;
1011 struct dma_slave_config cfg;
1012 int ret;
1013
1014 dma_cap_zero(mask);
1015 dma_cap_set(DMA_SLAVE, mask);
1016
1017 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1018 (void *)(unsigned long)id, dev,
1019 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1020 if (!chan) {
1021 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1022 return NULL;
1023 }
1024
1025 memset(&cfg, 0, sizeof(cfg));
1026 cfg.slave_id = id;
1027 cfg.direction = dir;
1028 if (dir == DMA_MEM_TO_DEV) {
1029 cfg.dst_addr = port_addr;
1030 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1031 } else {
1032 cfg.src_addr = port_addr;
1033 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1034 }
1035
1036 ret = dmaengine_slave_config(chan, &cfg);
1037 if (ret) {
1038 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1039 dma_release_channel(chan);
1040 return NULL;
1041 }
1042
1043 return chan;
1044 }
1045
1046 static int rspi_request_dma(struct device *dev, struct spi_master *master,
1047 const struct resource *res)
1048 {
1049 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
1050 unsigned int dma_tx_id, dma_rx_id;
1051
1052 if (dev->of_node) {
1053 /* In the OF case we will get the slave IDs from the DT */
1054 dma_tx_id = 0;
1055 dma_rx_id = 0;
1056 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
1057 dma_tx_id = rspi_pd->dma_tx_id;
1058 dma_rx_id = rspi_pd->dma_rx_id;
1059 } else {
1060 /* The driver assumes no error. */
1061 return 0;
1062 }
1063
1064 master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
1065 res->start + RSPI_SPDR);
1066 if (!master->dma_tx)
1067 return -ENODEV;
1068
1069 master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
1070 res->start + RSPI_SPDR);
1071 if (!master->dma_rx) {
1072 dma_release_channel(master->dma_tx);
1073 master->dma_tx = NULL;
1074 return -ENODEV;
1075 }
1076
1077 master->can_dma = rspi_can_dma;
1078 dev_info(dev, "DMA available");
1079 return 0;
1080 }
1081
1082 static void rspi_release_dma(struct spi_master *master)
1083 {
1084 if (master->dma_tx)
1085 dma_release_channel(master->dma_tx);
1086 if (master->dma_rx)
1087 dma_release_channel(master->dma_rx);
1088 }
1089
1090 static int rspi_remove(struct platform_device *pdev)
1091 {
1092 struct rspi_data *rspi = platform_get_drvdata(pdev);
1093
1094 rspi_release_dma(rspi->master);
1095 pm_runtime_disable(&pdev->dev);
1096
1097 return 0;
1098 }
1099
1100 static const struct spi_ops rspi_ops = {
1101 .set_config_register = rspi_set_config_register,
1102 .transfer_one = rspi_transfer_one,
1103 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1104 .flags = SPI_MASTER_MUST_TX,
1105 .fifo_size = 8,
1106 };
1107
1108 static const struct spi_ops rspi_rz_ops = {
1109 .set_config_register = rspi_rz_set_config_register,
1110 .transfer_one = rspi_rz_transfer_one,
1111 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1112 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1113 .fifo_size = 8, /* 8 for TX, 32 for RX */
1114 };
1115
1116 static const struct spi_ops qspi_ops = {
1117 .set_config_register = qspi_set_config_register,
1118 .transfer_one = qspi_transfer_one,
1119 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1120 SPI_TX_DUAL | SPI_TX_QUAD |
1121 SPI_RX_DUAL | SPI_RX_QUAD,
1122 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1123 .fifo_size = 32,
1124 };
1125
1126 #ifdef CONFIG_OF
1127 static const struct of_device_id rspi_of_match[] = {
1128 /* RSPI on legacy SH */
1129 { .compatible = "renesas,rspi", .data = &rspi_ops },
1130 /* RSPI on RZ/A1H */
1131 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1132 /* QSPI on R-Car Gen2 */
1133 { .compatible = "renesas,qspi", .data = &qspi_ops },
1134 { /* sentinel */ }
1135 };
1136
1137 MODULE_DEVICE_TABLE(of, rspi_of_match);
1138
1139 static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1140 {
1141 u32 num_cs;
1142 int error;
1143
1144 /* Parse DT properties */
1145 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1146 if (error) {
1147 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1148 return error;
1149 }
1150
1151 master->num_chipselect = num_cs;
1152 return 0;
1153 }
1154 #else
1155 #define rspi_of_match NULL
1156 static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1157 {
1158 return -EINVAL;
1159 }
1160 #endif /* CONFIG_OF */
1161
1162 static int rspi_request_irq(struct device *dev, unsigned int irq,
1163 irq_handler_t handler, const char *suffix,
1164 void *dev_id)
1165 {
1166 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
1167 dev_name(dev), suffix);
1168 if (!name)
1169 return -ENOMEM;
1170
1171 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1172 }
1173
1174 static int rspi_probe(struct platform_device *pdev)
1175 {
1176 struct resource *res;
1177 struct spi_master *master;
1178 struct rspi_data *rspi;
1179 int ret;
1180 const struct of_device_id *of_id;
1181 const struct rspi_plat_data *rspi_pd;
1182 const struct spi_ops *ops;
1183
1184 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1185 if (master == NULL) {
1186 dev_err(&pdev->dev, "spi_alloc_master error.\n");
1187 return -ENOMEM;
1188 }
1189
1190 of_id = of_match_device(rspi_of_match, &pdev->dev);
1191 if (of_id) {
1192 ops = of_id->data;
1193 ret = rspi_parse_dt(&pdev->dev, master);
1194 if (ret)
1195 goto error1;
1196 } else {
1197 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1198 rspi_pd = dev_get_platdata(&pdev->dev);
1199 if (rspi_pd && rspi_pd->num_chipselect)
1200 master->num_chipselect = rspi_pd->num_chipselect;
1201 else
1202 master->num_chipselect = 2; /* default */
1203 }
1204
1205 /* ops parameter check */
1206 if (!ops->set_config_register) {
1207 dev_err(&pdev->dev, "there is no set_config_register\n");
1208 ret = -ENODEV;
1209 goto error1;
1210 }
1211
1212 rspi = spi_master_get_devdata(master);
1213 platform_set_drvdata(pdev, rspi);
1214 rspi->ops = ops;
1215 rspi->master = master;
1216
1217 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1218 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1219 if (IS_ERR(rspi->addr)) {
1220 ret = PTR_ERR(rspi->addr);
1221 goto error1;
1222 }
1223
1224 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1225 if (IS_ERR(rspi->clk)) {
1226 dev_err(&pdev->dev, "cannot get clock\n");
1227 ret = PTR_ERR(rspi->clk);
1228 goto error1;
1229 }
1230
1231 pm_runtime_enable(&pdev->dev);
1232
1233 init_waitqueue_head(&rspi->wait);
1234
1235 master->bus_num = pdev->id;
1236 master->setup = rspi_setup;
1237 master->auto_runtime_pm = true;
1238 master->transfer_one = ops->transfer_one;
1239 master->prepare_message = rspi_prepare_message;
1240 master->unprepare_message = rspi_unprepare_message;
1241 master->mode_bits = ops->mode_bits;
1242 master->flags = ops->flags;
1243 master->dev.of_node = pdev->dev.of_node;
1244
1245 ret = platform_get_irq_byname(pdev, "rx");
1246 if (ret < 0) {
1247 ret = platform_get_irq_byname(pdev, "mux");
1248 if (ret < 0)
1249 ret = platform_get_irq(pdev, 0);
1250 if (ret >= 0)
1251 rspi->rx_irq = rspi->tx_irq = ret;
1252 } else {
1253 rspi->rx_irq = ret;
1254 ret = platform_get_irq_byname(pdev, "tx");
1255 if (ret >= 0)
1256 rspi->tx_irq = ret;
1257 }
1258 if (ret < 0) {
1259 dev_err(&pdev->dev, "platform_get_irq error\n");
1260 goto error2;
1261 }
1262
1263 if (rspi->rx_irq == rspi->tx_irq) {
1264 /* Single multiplexed interrupt */
1265 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1266 "mux", rspi);
1267 } else {
1268 /* Multi-interrupt mode, only SPRI and SPTI are used */
1269 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1270 "rx", rspi);
1271 if (!ret)
1272 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1273 rspi_irq_tx, "tx", rspi);
1274 }
1275 if (ret < 0) {
1276 dev_err(&pdev->dev, "request_irq error\n");
1277 goto error2;
1278 }
1279
1280 ret = rspi_request_dma(&pdev->dev, master, res);
1281 if (ret < 0)
1282 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1283
1284 ret = devm_spi_register_master(&pdev->dev, master);
1285 if (ret < 0) {
1286 dev_err(&pdev->dev, "spi_register_master error.\n");
1287 goto error3;
1288 }
1289
1290 dev_info(&pdev->dev, "probed\n");
1291
1292 return 0;
1293
1294 error3:
1295 rspi_release_dma(master);
1296 error2:
1297 pm_runtime_disable(&pdev->dev);
1298 error1:
1299 spi_master_put(master);
1300
1301 return ret;
1302 }
1303
1304 static struct platform_device_id spi_driver_ids[] = {
1305 { "rspi", (kernel_ulong_t)&rspi_ops },
1306 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1307 { "qspi", (kernel_ulong_t)&qspi_ops },
1308 {},
1309 };
1310
1311 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1312
1313 static struct platform_driver rspi_driver = {
1314 .probe = rspi_probe,
1315 .remove = rspi_remove,
1316 .id_table = spi_driver_ids,
1317 .driver = {
1318 .name = "renesas_spi",
1319 .of_match_table = of_match_ptr(rspi_of_match),
1320 },
1321 };
1322 module_platform_driver(rspi_driver);
1323
1324 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1325 MODULE_LICENSE("GPL v2");
1326 MODULE_AUTHOR("Yoshihiro Shimoda");
1327 MODULE_ALIAS("platform:rspi");
Linux kernel - Deliverables
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