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gfs2: Simplify the seq file code for "sbstats"
[deliverable/linux.git] / drivers / spi / spi-rspi.c
1 /*
2 * SH RSPI driver
3 *
4 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2014 Glider bvba
6 *
7 * Based on spi-sh.c:
8 * Copyright (C) 2011 Renesas Solutions Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/of_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/sh_dma.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/rspi.h>
35
36 #define RSPI_SPCR 0x00 /* Control Register */
37 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
38 #define RSPI_SPPCR 0x02 /* Pin Control Register */
39 #define RSPI_SPSR 0x03 /* Status Register */
40 #define RSPI_SPDR 0x04 /* Data Register */
41 #define RSPI_SPSCR 0x08 /* Sequence Control Register */
42 #define RSPI_SPSSR 0x09 /* Sequence Status Register */
43 #define RSPI_SPBR 0x0a /* Bit Rate Register */
44 #define RSPI_SPDCR 0x0b /* Data Control Register */
45 #define RSPI_SPCKD 0x0c /* Clock Delay Register */
46 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
47 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
48 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
49 #define RSPI_SPCMD0 0x10 /* Command Register 0 */
50 #define RSPI_SPCMD1 0x12 /* Command Register 1 */
51 #define RSPI_SPCMD2 0x14 /* Command Register 2 */
52 #define RSPI_SPCMD3 0x16 /* Command Register 3 */
53 #define RSPI_SPCMD4 0x18 /* Command Register 4 */
54 #define RSPI_SPCMD5 0x1a /* Command Register 5 */
55 #define RSPI_SPCMD6 0x1c /* Command Register 6 */
56 #define RSPI_SPCMD7 0x1e /* Command Register 7 */
57 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
58 #define RSPI_NUM_SPCMD 8
59 #define RSPI_RZ_NUM_SPCMD 4
60 #define QSPI_NUM_SPCMD 4
61
62 /* RSPI on RZ only */
63 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */
64 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
65
66 /* QSPI only */
67 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */
68 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
69 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
70 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
71 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
72 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
73 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
74
75 /* SPCR - Control Register */
76 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
77 #define SPCR_SPE 0x40 /* Function Enable */
78 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
79 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
80 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
81 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
82 /* RSPI on SH only */
83 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
84 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
85 /* QSPI on R-Car Gen2 only */
86 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
87 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
88
89 /* SSLP - Slave Select Polarity Register */
90 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
91 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
92
93 /* SPPCR - Pin Control Register */
94 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
95 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
96 #define SPPCR_SPOM 0x04
97 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
98 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
99
100 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
101 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
102
103 /* SPSR - Status Register */
104 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
105 #define SPSR_TEND 0x40 /* Transmit End */
106 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
107 #define SPSR_PERF 0x08 /* Parity Error Flag */
108 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
109 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
110 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
111
112 /* SPSCR - Sequence Control Register */
113 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
114
115 /* SPSSR - Sequence Status Register */
116 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
117 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
118
119 /* SPDCR - Data Control Register */
120 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
121 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
122 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
123 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
124 #define SPDCR_SPLWORD SPDCR_SPLW1
125 #define SPDCR_SPLBYTE SPDCR_SPLW0
126 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
127 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
128 #define SPDCR_SLSEL1 0x08
129 #define SPDCR_SLSEL0 0x04
130 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
131 #define SPDCR_SPFC1 0x02
132 #define SPDCR_SPFC0 0x01
133 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
134
135 /* SPCKD - Clock Delay Register */
136 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
137
138 /* SSLND - Slave Select Negation Delay Register */
139 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
140
141 /* SPND - Next-Access Delay Register */
142 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
143
144 /* SPCR2 - Control Register 2 */
145 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
146 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
147 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
148 #define SPCR2_SPPE 0x01 /* Parity Enable */
149
150 /* SPCMDn - Command Registers */
151 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
152 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
153 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
154 #define SPCMD_LSBF 0x1000 /* LSB First */
155 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
156 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
157 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
158 #define SPCMD_SPB_16BIT 0x0100
159 #define SPCMD_SPB_20BIT 0x0000
160 #define SPCMD_SPB_24BIT 0x0100
161 #define SPCMD_SPB_32BIT 0x0200
162 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
163 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
164 #define SPCMD_SPIMOD1 0x0040
165 #define SPCMD_SPIMOD0 0x0020
166 #define SPCMD_SPIMOD_SINGLE 0
167 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
168 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
169 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
170 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
171 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
172 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
173 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
174
175 /* SPBFCR - Buffer Control Register */
176 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
177 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
178 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
179 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
180 /* QSPI on R-Car Gen2 */
181 #define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */
182 #define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */
183 #define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */
184 #define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */
185
186 #define QSPI_BUFFER_SIZE 32u
187
188 struct rspi_data {
189 void __iomem *addr;
190 u32 max_speed_hz;
191 struct spi_master *master;
192 wait_queue_head_t wait;
193 struct clk *clk;
194 u16 spcmd;
195 u8 spsr;
196 u8 sppcr;
197 int rx_irq, tx_irq;
198 const struct spi_ops *ops;
199
200 unsigned dma_callbacked:1;
201 unsigned byte_access:1;
202 };
203
204 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
205 {
206 iowrite8(data, rspi->addr + offset);
207 }
208
209 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
210 {
211 iowrite16(data, rspi->addr + offset);
212 }
213
214 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
215 {
216 iowrite32(data, rspi->addr + offset);
217 }
218
219 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
220 {
221 return ioread8(rspi->addr + offset);
222 }
223
224 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
225 {
226 return ioread16(rspi->addr + offset);
227 }
228
229 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
230 {
231 if (rspi->byte_access)
232 rspi_write8(rspi, data, RSPI_SPDR);
233 else /* 16 bit */
234 rspi_write16(rspi, data, RSPI_SPDR);
235 }
236
237 static u16 rspi_read_data(const struct rspi_data *rspi)
238 {
239 if (rspi->byte_access)
240 return rspi_read8(rspi, RSPI_SPDR);
241 else /* 16 bit */
242 return rspi_read16(rspi, RSPI_SPDR);
243 }
244
245 /* optional functions */
246 struct spi_ops {
247 int (*set_config_register)(struct rspi_data *rspi, int access_size);
248 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
249 struct spi_transfer *xfer);
250 u16 mode_bits;
251 u16 flags;
252 u16 fifo_size;
253 };
254
255 /*
256 * functions for RSPI on legacy SH
257 */
258 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
259 {
260 int spbr;
261
262 /* Sets output mode, MOSI signal, and (optionally) loopback */
263 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
264
265 /* Sets transfer bit rate */
266 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
267 2 * rspi->max_speed_hz) - 1;
268 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
269
270 /* Disable dummy transmission, set 16-bit word access, 1 frame */
271 rspi_write8(rspi, 0, RSPI_SPDCR);
272 rspi->byte_access = 0;
273
274 /* Sets RSPCK, SSL, next-access delay value */
275 rspi_write8(rspi, 0x00, RSPI_SPCKD);
276 rspi_write8(rspi, 0x00, RSPI_SSLND);
277 rspi_write8(rspi, 0x00, RSPI_SPND);
278
279 /* Sets parity, interrupt mask */
280 rspi_write8(rspi, 0x00, RSPI_SPCR2);
281
282 /* Sets SPCMD */
283 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
284 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
285
286 /* Sets RSPI mode */
287 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
288
289 return 0;
290 }
291
292 /*
293 * functions for RSPI on RZ
294 */
295 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
296 {
297 int spbr;
298
299 /* Sets output mode, MOSI signal, and (optionally) loopback */
300 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
301
302 /* Sets transfer bit rate */
303 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
304 2 * rspi->max_speed_hz) - 1;
305 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
306
307 /* Disable dummy transmission, set byte access */
308 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
309 rspi->byte_access = 1;
310
311 /* Sets RSPCK, SSL, next-access delay value */
312 rspi_write8(rspi, 0x00, RSPI_SPCKD);
313 rspi_write8(rspi, 0x00, RSPI_SSLND);
314 rspi_write8(rspi, 0x00, RSPI_SPND);
315
316 /* Sets SPCMD */
317 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
318 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
319
320 /* Sets RSPI mode */
321 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
322
323 return 0;
324 }
325
326 /*
327 * functions for QSPI
328 */
329 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
330 {
331 int spbr;
332
333 /* Sets output mode, MOSI signal, and (optionally) loopback */
334 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
335
336 /* Sets transfer bit rate */
337 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
338 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
339
340 /* Disable dummy transmission, set byte access */
341 rspi_write8(rspi, 0, RSPI_SPDCR);
342 rspi->byte_access = 1;
343
344 /* Sets RSPCK, SSL, next-access delay value */
345 rspi_write8(rspi, 0x00, RSPI_SPCKD);
346 rspi_write8(rspi, 0x00, RSPI_SSLND);
347 rspi_write8(rspi, 0x00, RSPI_SPND);
348
349 /* Data Length Setting */
350 if (access_size == 8)
351 rspi->spcmd |= SPCMD_SPB_8BIT;
352 else if (access_size == 16)
353 rspi->spcmd |= SPCMD_SPB_16BIT;
354 else
355 rspi->spcmd |= SPCMD_SPB_32BIT;
356
357 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
358
359 /* Resets transfer data length */
360 rspi_write32(rspi, 0, QSPI_SPBMUL0);
361
362 /* Resets transmit and receive buffer */
363 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
364 /* Sets buffer to allow normal operation */
365 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
366
367 /* Sets SPCMD */
368 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
369
370 /* Enables SPI function in master mode */
371 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
372
373 return 0;
374 }
375
376 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
377 {
378 u8 data;
379
380 data = rspi_read8(rspi, reg);
381 data &= ~mask;
382 data |= (val & mask);
383 rspi_write8(rspi, data, reg);
384 }
385
386 static int qspi_set_send_trigger(struct rspi_data *rspi, unsigned int len)
387 {
388 unsigned int n;
389
390 n = min(len, QSPI_BUFFER_SIZE);
391
392 if (len >= QSPI_BUFFER_SIZE) {
393 /* sets triggering number to 32 bytes */
394 qspi_update(rspi, SPBFCR_TXTRG_MASK,
395 SPBFCR_TXTRG_32B, QSPI_SPBFCR);
396 } else {
397 /* sets triggering number to 1 byte */
398 qspi_update(rspi, SPBFCR_TXTRG_MASK,
399 SPBFCR_TXTRG_1B, QSPI_SPBFCR);
400 }
401
402 return n;
403 }
404
405 static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
406 {
407 unsigned int n;
408
409 n = min(len, QSPI_BUFFER_SIZE);
410
411 if (len >= QSPI_BUFFER_SIZE) {
412 /* sets triggering number to 32 bytes */
413 qspi_update(rspi, SPBFCR_RXTRG_MASK,
414 SPBFCR_RXTRG_32B, QSPI_SPBFCR);
415 } else {
416 /* sets triggering number to 1 byte */
417 qspi_update(rspi, SPBFCR_RXTRG_MASK,
418 SPBFCR_RXTRG_1B, QSPI_SPBFCR);
419 }
420 }
421
422 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
423
424 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
425 {
426 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
427 }
428
429 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
430 {
431 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
432 }
433
434 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
435 u8 enable_bit)
436 {
437 int ret;
438
439 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
440 if (rspi->spsr & wait_mask)
441 return 0;
442
443 rspi_enable_irq(rspi, enable_bit);
444 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
445 if (ret == 0 && !(rspi->spsr & wait_mask))
446 return -ETIMEDOUT;
447
448 return 0;
449 }
450
451 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
452 {
453 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
454 }
455
456 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
457 {
458 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
459 }
460
461 static int rspi_data_out(struct rspi_data *rspi, u8 data)
462 {
463 int error = rspi_wait_for_tx_empty(rspi);
464 if (error < 0) {
465 dev_err(&rspi->master->dev, "transmit timeout\n");
466 return error;
467 }
468 rspi_write_data(rspi, data);
469 return 0;
470 }
471
472 static int rspi_data_in(struct rspi_data *rspi)
473 {
474 int error;
475 u8 data;
476
477 error = rspi_wait_for_rx_full(rspi);
478 if (error < 0) {
479 dev_err(&rspi->master->dev, "receive timeout\n");
480 return error;
481 }
482 data = rspi_read_data(rspi);
483 return data;
484 }
485
486 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
487 unsigned int n)
488 {
489 while (n-- > 0) {
490 if (tx) {
491 int ret = rspi_data_out(rspi, *tx++);
492 if (ret < 0)
493 return ret;
494 }
495 if (rx) {
496 int ret = rspi_data_in(rspi);
497 if (ret < 0)
498 return ret;
499 *rx++ = ret;
500 }
501 }
502
503 return 0;
504 }
505
506 static void rspi_dma_complete(void *arg)
507 {
508 struct rspi_data *rspi = arg;
509
510 rspi->dma_callbacked = 1;
511 wake_up_interruptible(&rspi->wait);
512 }
513
514 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
515 struct sg_table *rx)
516 {
517 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
518 u8 irq_mask = 0;
519 unsigned int other_irq = 0;
520 dma_cookie_t cookie;
521 int ret;
522
523 /* First prepare and submit the DMA request(s), as this may fail */
524 if (rx) {
525 desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx,
526 rx->sgl, rx->nents, DMA_FROM_DEVICE,
527 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
528 if (!desc_rx) {
529 ret = -EAGAIN;
530 goto no_dma_rx;
531 }
532
533 desc_rx->callback = rspi_dma_complete;
534 desc_rx->callback_param = rspi;
535 cookie = dmaengine_submit(desc_rx);
536 if (dma_submit_error(cookie)) {
537 ret = cookie;
538 goto no_dma_rx;
539 }
540
541 irq_mask |= SPCR_SPRIE;
542 }
543
544 if (tx) {
545 desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx,
546 tx->sgl, tx->nents, DMA_TO_DEVICE,
547 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
548 if (!desc_tx) {
549 ret = -EAGAIN;
550 goto no_dma_tx;
551 }
552
553 if (rx) {
554 /* No callback */
555 desc_tx->callback = NULL;
556 } else {
557 desc_tx->callback = rspi_dma_complete;
558 desc_tx->callback_param = rspi;
559 }
560 cookie = dmaengine_submit(desc_tx);
561 if (dma_submit_error(cookie)) {
562 ret = cookie;
563 goto no_dma_tx;
564 }
565
566 irq_mask |= SPCR_SPTIE;
567 }
568
569 /*
570 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
571 * called. So, this driver disables the IRQ while DMA transfer.
572 */
573 if (tx)
574 disable_irq(other_irq = rspi->tx_irq);
575 if (rx && rspi->rx_irq != other_irq)
576 disable_irq(rspi->rx_irq);
577
578 rspi_enable_irq(rspi, irq_mask);
579 rspi->dma_callbacked = 0;
580
581 /* Now start DMA */
582 if (rx)
583 dma_async_issue_pending(rspi->master->dma_rx);
584 if (tx)
585 dma_async_issue_pending(rspi->master->dma_tx);
586
587 ret = wait_event_interruptible_timeout(rspi->wait,
588 rspi->dma_callbacked, HZ);
589 if (ret > 0 && rspi->dma_callbacked)
590 ret = 0;
591 else if (!ret) {
592 dev_err(&rspi->master->dev, "DMA timeout\n");
593 ret = -ETIMEDOUT;
594 if (tx)
595 dmaengine_terminate_all(rspi->master->dma_tx);
596 if (rx)
597 dmaengine_terminate_all(rspi->master->dma_rx);
598 }
599
600 rspi_disable_irq(rspi, irq_mask);
601
602 if (tx)
603 enable_irq(rspi->tx_irq);
604 if (rx && rspi->rx_irq != other_irq)
605 enable_irq(rspi->rx_irq);
606
607 return ret;
608
609 no_dma_tx:
610 if (rx)
611 dmaengine_terminate_all(rspi->master->dma_rx);
612 no_dma_rx:
613 if (ret == -EAGAIN) {
614 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
615 dev_driver_string(&rspi->master->dev),
616 dev_name(&rspi->master->dev));
617 }
618 return ret;
619 }
620
621 static void rspi_receive_init(const struct rspi_data *rspi)
622 {
623 u8 spsr;
624
625 spsr = rspi_read8(rspi, RSPI_SPSR);
626 if (spsr & SPSR_SPRF)
627 rspi_read_data(rspi); /* dummy read */
628 if (spsr & SPSR_OVRF)
629 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
630 RSPI_SPSR);
631 }
632
633 static void rspi_rz_receive_init(const struct rspi_data *rspi)
634 {
635 rspi_receive_init(rspi);
636 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
637 rspi_write8(rspi, 0, RSPI_SPBFCR);
638 }
639
640 static void qspi_receive_init(const struct rspi_data *rspi)
641 {
642 u8 spsr;
643
644 spsr = rspi_read8(rspi, RSPI_SPSR);
645 if (spsr & SPSR_SPRF)
646 rspi_read_data(rspi); /* dummy read */
647 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
648 rspi_write8(rspi, 0, QSPI_SPBFCR);
649 }
650
651 static bool __rspi_can_dma(const struct rspi_data *rspi,
652 const struct spi_transfer *xfer)
653 {
654 return xfer->len > rspi->ops->fifo_size;
655 }
656
657 static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi,
658 struct spi_transfer *xfer)
659 {
660 struct rspi_data *rspi = spi_master_get_devdata(master);
661
662 return __rspi_can_dma(rspi, xfer);
663 }
664
665 static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
666 struct spi_transfer *xfer)
667 {
668 if (!rspi->master->can_dma || !__rspi_can_dma(rspi, xfer))
669 return -EAGAIN;
670
671 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
672 return rspi_dma_transfer(rspi, &xfer->tx_sg,
673 xfer->rx_buf ? &xfer->rx_sg : NULL);
674 }
675
676 static int rspi_common_transfer(struct rspi_data *rspi,
677 struct spi_transfer *xfer)
678 {
679 int ret;
680
681 ret = rspi_dma_check_then_transfer(rspi, xfer);
682 if (ret != -EAGAIN)
683 return ret;
684
685 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
686 if (ret < 0)
687 return ret;
688
689 /* Wait for the last transmission */
690 rspi_wait_for_tx_empty(rspi);
691
692 return 0;
693 }
694
695 static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
696 struct spi_transfer *xfer)
697 {
698 struct rspi_data *rspi = spi_master_get_devdata(master);
699 u8 spcr;
700
701 spcr = rspi_read8(rspi, RSPI_SPCR);
702 if (xfer->rx_buf) {
703 rspi_receive_init(rspi);
704 spcr &= ~SPCR_TXMD;
705 } else {
706 spcr |= SPCR_TXMD;
707 }
708 rspi_write8(rspi, spcr, RSPI_SPCR);
709
710 return rspi_common_transfer(rspi, xfer);
711 }
712
713 static int rspi_rz_transfer_one(struct spi_master *master,
714 struct spi_device *spi,
715 struct spi_transfer *xfer)
716 {
717 struct rspi_data *rspi = spi_master_get_devdata(master);
718
719 rspi_rz_receive_init(rspi);
720
721 return rspi_common_transfer(rspi, xfer);
722 }
723
724 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
725 u8 *rx, unsigned int len)
726 {
727 int i, n, ret;
728 int error;
729
730 while (len > 0) {
731 n = qspi_set_send_trigger(rspi, len);
732 qspi_set_receive_trigger(rspi, len);
733 if (n == QSPI_BUFFER_SIZE) {
734 error = rspi_wait_for_tx_empty(rspi);
735 if (error < 0) {
736 dev_err(&rspi->master->dev, "transmit timeout\n");
737 return error;
738 }
739 for (i = 0; i < n; i++)
740 rspi_write_data(rspi, *tx++);
741
742 error = rspi_wait_for_rx_full(rspi);
743 if (error < 0) {
744 dev_err(&rspi->master->dev, "receive timeout\n");
745 return error;
746 }
747 for (i = 0; i < n; i++)
748 *rx++ = rspi_read_data(rspi);
749 } else {
750 ret = rspi_pio_transfer(rspi, tx, rx, n);
751 if (ret < 0)
752 return ret;
753 }
754 len -= n;
755 }
756
757 return 0;
758 }
759
760 static int qspi_transfer_out_in(struct rspi_data *rspi,
761 struct spi_transfer *xfer)
762 {
763 int ret;
764
765 qspi_receive_init(rspi);
766
767 ret = rspi_dma_check_then_transfer(rspi, xfer);
768 if (ret != -EAGAIN)
769 return ret;
770
771 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
772 xfer->rx_buf, xfer->len);
773 }
774
775 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
776 {
777 int ret;
778
779 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
780 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
781 if (ret != -EAGAIN)
782 return ret;
783 }
784
785 ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
786 if (ret < 0)
787 return ret;
788
789 /* Wait for the last transmission */
790 rspi_wait_for_tx_empty(rspi);
791
792 return 0;
793 }
794
795 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
796 {
797 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
798 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
799 if (ret != -EAGAIN)
800 return ret;
801 }
802
803 return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
804 }
805
806 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
807 struct spi_transfer *xfer)
808 {
809 struct rspi_data *rspi = spi_master_get_devdata(master);
810
811 if (spi->mode & SPI_LOOP) {
812 return qspi_transfer_out_in(rspi, xfer);
813 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
814 /* Quad or Dual SPI Write */
815 return qspi_transfer_out(rspi, xfer);
816 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
817 /* Quad or Dual SPI Read */
818 return qspi_transfer_in(rspi, xfer);
819 } else {
820 /* Single SPI Transfer */
821 return qspi_transfer_out_in(rspi, xfer);
822 }
823 }
824
825 static int rspi_setup(struct spi_device *spi)
826 {
827 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
828
829 rspi->max_speed_hz = spi->max_speed_hz;
830
831 rspi->spcmd = SPCMD_SSLKP;
832 if (spi->mode & SPI_CPOL)
833 rspi->spcmd |= SPCMD_CPOL;
834 if (spi->mode & SPI_CPHA)
835 rspi->spcmd |= SPCMD_CPHA;
836
837 /* CMOS output mode and MOSI signal from previous transfer */
838 rspi->sppcr = 0;
839 if (spi->mode & SPI_LOOP)
840 rspi->sppcr |= SPPCR_SPLP;
841
842 set_config_register(rspi, 8);
843
844 return 0;
845 }
846
847 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
848 {
849 if (xfer->tx_buf)
850 switch (xfer->tx_nbits) {
851 case SPI_NBITS_QUAD:
852 return SPCMD_SPIMOD_QUAD;
853 case SPI_NBITS_DUAL:
854 return SPCMD_SPIMOD_DUAL;
855 default:
856 return 0;
857 }
858 if (xfer->rx_buf)
859 switch (xfer->rx_nbits) {
860 case SPI_NBITS_QUAD:
861 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
862 case SPI_NBITS_DUAL:
863 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
864 default:
865 return 0;
866 }
867
868 return 0;
869 }
870
871 static int qspi_setup_sequencer(struct rspi_data *rspi,
872 const struct spi_message *msg)
873 {
874 const struct spi_transfer *xfer;
875 unsigned int i = 0, len = 0;
876 u16 current_mode = 0xffff, mode;
877
878 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
879 mode = qspi_transfer_mode(xfer);
880 if (mode == current_mode) {
881 len += xfer->len;
882 continue;
883 }
884
885 /* Transfer mode change */
886 if (i) {
887 /* Set transfer data length of previous transfer */
888 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
889 }
890
891 if (i >= QSPI_NUM_SPCMD) {
892 dev_err(&msg->spi->dev,
893 "Too many different transfer modes");
894 return -EINVAL;
895 }
896
897 /* Program transfer mode for this transfer */
898 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
899 current_mode = mode;
900 len = xfer->len;
901 i++;
902 }
903 if (i) {
904 /* Set final transfer data length and sequence length */
905 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
906 rspi_write8(rspi, i - 1, RSPI_SPSCR);
907 }
908
909 return 0;
910 }
911
912 static int rspi_prepare_message(struct spi_master *master,
913 struct spi_message *msg)
914 {
915 struct rspi_data *rspi = spi_master_get_devdata(master);
916 int ret;
917
918 if (msg->spi->mode &
919 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
920 /* Setup sequencer for messages with multiple transfer modes */
921 ret = qspi_setup_sequencer(rspi, msg);
922 if (ret < 0)
923 return ret;
924 }
925
926 /* Enable SPI function in master mode */
927 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
928 return 0;
929 }
930
931 static int rspi_unprepare_message(struct spi_master *master,
932 struct spi_message *msg)
933 {
934 struct rspi_data *rspi = spi_master_get_devdata(master);
935
936 /* Disable SPI function */
937 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
938
939 /* Reset sequencer for Single SPI Transfers */
940 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
941 rspi_write8(rspi, 0, RSPI_SPSCR);
942 return 0;
943 }
944
945 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
946 {
947 struct rspi_data *rspi = _sr;
948 u8 spsr;
949 irqreturn_t ret = IRQ_NONE;
950 u8 disable_irq = 0;
951
952 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
953 if (spsr & SPSR_SPRF)
954 disable_irq |= SPCR_SPRIE;
955 if (spsr & SPSR_SPTEF)
956 disable_irq |= SPCR_SPTIE;
957
958 if (disable_irq) {
959 ret = IRQ_HANDLED;
960 rspi_disable_irq(rspi, disable_irq);
961 wake_up(&rspi->wait);
962 }
963
964 return ret;
965 }
966
967 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
968 {
969 struct rspi_data *rspi = _sr;
970 u8 spsr;
971
972 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
973 if (spsr & SPSR_SPRF) {
974 rspi_disable_irq(rspi, SPCR_SPRIE);
975 wake_up(&rspi->wait);
976 return IRQ_HANDLED;
977 }
978
979 return 0;
980 }
981
982 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
983 {
984 struct rspi_data *rspi = _sr;
985 u8 spsr;
986
987 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
988 if (spsr & SPSR_SPTEF) {
989 rspi_disable_irq(rspi, SPCR_SPTIE);
990 wake_up(&rspi->wait);
991 return IRQ_HANDLED;
992 }
993
994 return 0;
995 }
996
997 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
998 enum dma_transfer_direction dir,
999 unsigned int id,
1000 dma_addr_t port_addr)
1001 {
1002 dma_cap_mask_t mask;
1003 struct dma_chan *chan;
1004 struct dma_slave_config cfg;
1005 int ret;
1006
1007 dma_cap_zero(mask);
1008 dma_cap_set(DMA_SLAVE, mask);
1009
1010 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1011 (void *)(unsigned long)id, dev,
1012 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1013 if (!chan) {
1014 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1015 return NULL;
1016 }
1017
1018 memset(&cfg, 0, sizeof(cfg));
1019 cfg.direction = dir;
1020 if (dir == DMA_MEM_TO_DEV) {
1021 cfg.dst_addr = port_addr;
1022 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1023 } else {
1024 cfg.src_addr = port_addr;
1025 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1026 }
1027
1028 ret = dmaengine_slave_config(chan, &cfg);
1029 if (ret) {
1030 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1031 dma_release_channel(chan);
1032 return NULL;
1033 }
1034
1035 return chan;
1036 }
1037
1038 static int rspi_request_dma(struct device *dev, struct spi_master *master,
1039 const struct resource *res)
1040 {
1041 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
1042 unsigned int dma_tx_id, dma_rx_id;
1043
1044 if (dev->of_node) {
1045 /* In the OF case we will get the slave IDs from the DT */
1046 dma_tx_id = 0;
1047 dma_rx_id = 0;
1048 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
1049 dma_tx_id = rspi_pd->dma_tx_id;
1050 dma_rx_id = rspi_pd->dma_rx_id;
1051 } else {
1052 /* The driver assumes no error. */
1053 return 0;
1054 }
1055
1056 master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
1057 res->start + RSPI_SPDR);
1058 if (!master->dma_tx)
1059 return -ENODEV;
1060
1061 master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
1062 res->start + RSPI_SPDR);
1063 if (!master->dma_rx) {
1064 dma_release_channel(master->dma_tx);
1065 master->dma_tx = NULL;
1066 return -ENODEV;
1067 }
1068
1069 master->can_dma = rspi_can_dma;
1070 dev_info(dev, "DMA available");
1071 return 0;
1072 }
1073
1074 static void rspi_release_dma(struct spi_master *master)
1075 {
1076 if (master->dma_tx)
1077 dma_release_channel(master->dma_tx);
1078 if (master->dma_rx)
1079 dma_release_channel(master->dma_rx);
1080 }
1081
1082 static int rspi_remove(struct platform_device *pdev)
1083 {
1084 struct rspi_data *rspi = platform_get_drvdata(pdev);
1085
1086 rspi_release_dma(rspi->master);
1087 pm_runtime_disable(&pdev->dev);
1088
1089 return 0;
1090 }
1091
1092 static const struct spi_ops rspi_ops = {
1093 .set_config_register = rspi_set_config_register,
1094 .transfer_one = rspi_transfer_one,
1095 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1096 .flags = SPI_MASTER_MUST_TX,
1097 .fifo_size = 8,
1098 };
1099
1100 static const struct spi_ops rspi_rz_ops = {
1101 .set_config_register = rspi_rz_set_config_register,
1102 .transfer_one = rspi_rz_transfer_one,
1103 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1104 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1105 .fifo_size = 8, /* 8 for TX, 32 for RX */
1106 };
1107
1108 static const struct spi_ops qspi_ops = {
1109 .set_config_register = qspi_set_config_register,
1110 .transfer_one = qspi_transfer_one,
1111 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1112 SPI_TX_DUAL | SPI_TX_QUAD |
1113 SPI_RX_DUAL | SPI_RX_QUAD,
1114 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1115 .fifo_size = 32,
1116 };
1117
1118 #ifdef CONFIG_OF
1119 static const struct of_device_id rspi_of_match[] = {
1120 /* RSPI on legacy SH */
1121 { .compatible = "renesas,rspi", .data = &rspi_ops },
1122 /* RSPI on RZ/A1H */
1123 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1124 /* QSPI on R-Car Gen2 */
1125 { .compatible = "renesas,qspi", .data = &qspi_ops },
1126 { /* sentinel */ }
1127 };
1128
1129 MODULE_DEVICE_TABLE(of, rspi_of_match);
1130
1131 static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1132 {
1133 u32 num_cs;
1134 int error;
1135
1136 /* Parse DT properties */
1137 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1138 if (error) {
1139 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1140 return error;
1141 }
1142
1143 master->num_chipselect = num_cs;
1144 return 0;
1145 }
1146 #else
1147 #define rspi_of_match NULL
1148 static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1149 {
1150 return -EINVAL;
1151 }
1152 #endif /* CONFIG_OF */
1153
1154 static int rspi_request_irq(struct device *dev, unsigned int irq,
1155 irq_handler_t handler, const char *suffix,
1156 void *dev_id)
1157 {
1158 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
1159 dev_name(dev), suffix);
1160 if (!name)
1161 return -ENOMEM;
1162
1163 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1164 }
1165
1166 static int rspi_probe(struct platform_device *pdev)
1167 {
1168 struct resource *res;
1169 struct spi_master *master;
1170 struct rspi_data *rspi;
1171 int ret;
1172 const struct of_device_id *of_id;
1173 const struct rspi_plat_data *rspi_pd;
1174 const struct spi_ops *ops;
1175
1176 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1177 if (master == NULL) {
1178 dev_err(&pdev->dev, "spi_alloc_master error.\n");
1179 return -ENOMEM;
1180 }
1181
1182 of_id = of_match_device(rspi_of_match, &pdev->dev);
1183 if (of_id) {
1184 ops = of_id->data;
1185 ret = rspi_parse_dt(&pdev->dev, master);
1186 if (ret)
1187 goto error1;
1188 } else {
1189 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1190 rspi_pd = dev_get_platdata(&pdev->dev);
1191 if (rspi_pd && rspi_pd->num_chipselect)
1192 master->num_chipselect = rspi_pd->num_chipselect;
1193 else
1194 master->num_chipselect = 2; /* default */
1195 }
1196
1197 /* ops parameter check */
1198 if (!ops->set_config_register) {
1199 dev_err(&pdev->dev, "there is no set_config_register\n");
1200 ret = -ENODEV;
1201 goto error1;
1202 }
1203
1204 rspi = spi_master_get_devdata(master);
1205 platform_set_drvdata(pdev, rspi);
1206 rspi->ops = ops;
1207 rspi->master = master;
1208
1209 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1210 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1211 if (IS_ERR(rspi->addr)) {
1212 ret = PTR_ERR(rspi->addr);
1213 goto error1;
1214 }
1215
1216 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1217 if (IS_ERR(rspi->clk)) {
1218 dev_err(&pdev->dev, "cannot get clock\n");
1219 ret = PTR_ERR(rspi->clk);
1220 goto error1;
1221 }
1222
1223 pm_runtime_enable(&pdev->dev);
1224
1225 init_waitqueue_head(&rspi->wait);
1226
1227 master->bus_num = pdev->id;
1228 master->setup = rspi_setup;
1229 master->auto_runtime_pm = true;
1230 master->transfer_one = ops->transfer_one;
1231 master->prepare_message = rspi_prepare_message;
1232 master->unprepare_message = rspi_unprepare_message;
1233 master->mode_bits = ops->mode_bits;
1234 master->flags = ops->flags;
1235 master->dev.of_node = pdev->dev.of_node;
1236
1237 ret = platform_get_irq_byname(pdev, "rx");
1238 if (ret < 0) {
1239 ret = platform_get_irq_byname(pdev, "mux");
1240 if (ret < 0)
1241 ret = platform_get_irq(pdev, 0);
1242 if (ret >= 0)
1243 rspi->rx_irq = rspi->tx_irq = ret;
1244 } else {
1245 rspi->rx_irq = ret;
1246 ret = platform_get_irq_byname(pdev, "tx");
1247 if (ret >= 0)
1248 rspi->tx_irq = ret;
1249 }
1250 if (ret < 0) {
1251 dev_err(&pdev->dev, "platform_get_irq error\n");
1252 goto error2;
1253 }
1254
1255 if (rspi->rx_irq == rspi->tx_irq) {
1256 /* Single multiplexed interrupt */
1257 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1258 "mux", rspi);
1259 } else {
1260 /* Multi-interrupt mode, only SPRI and SPTI are used */
1261 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1262 "rx", rspi);
1263 if (!ret)
1264 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1265 rspi_irq_tx, "tx", rspi);
1266 }
1267 if (ret < 0) {
1268 dev_err(&pdev->dev, "request_irq error\n");
1269 goto error2;
1270 }
1271
1272 ret = rspi_request_dma(&pdev->dev, master, res);
1273 if (ret < 0)
1274 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1275
1276 ret = devm_spi_register_master(&pdev->dev, master);
1277 if (ret < 0) {
1278 dev_err(&pdev->dev, "spi_register_master error.\n");
1279 goto error3;
1280 }
1281
1282 dev_info(&pdev->dev, "probed\n");
1283
1284 return 0;
1285
1286 error3:
1287 rspi_release_dma(master);
1288 error2:
1289 pm_runtime_disable(&pdev->dev);
1290 error1:
1291 spi_master_put(master);
1292
1293 return ret;
1294 }
1295
1296 static const struct platform_device_id spi_driver_ids[] = {
1297 { "rspi", (kernel_ulong_t)&rspi_ops },
1298 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1299 { "qspi", (kernel_ulong_t)&qspi_ops },
1300 {},
1301 };
1302
1303 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1304
1305 static struct platform_driver rspi_driver = {
1306 .probe = rspi_probe,
1307 .remove = rspi_remove,
1308 .id_table = spi_driver_ids,
1309 .driver = {
1310 .name = "renesas_spi",
1311 .of_match_table = of_match_ptr(rspi_of_match),
1312 },
1313 };
1314 module_platform_driver(rspi_driver);
1315
1316 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1317 MODULE_LICENSE("GPL v2");
1318 MODULE_AUTHOR("Yoshihiro Shimoda");
1319 MODULE_ALIAS("platform:rspi");
Linux kernel - Deliverables
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