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spi: rspi: Move RSPI-specific setup out of DMA routines
[deliverable/linux.git] / drivers / spi / spi-rspi.c
1 /*
2 * SH RSPI driver
3 *
4 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2014 Glider bvba
6 *
7 * Based on spi-sh.c:
8 * Copyright (C) 2011 Renesas Solutions Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 *
23 */
24
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/sched.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/platform_device.h>
31 #include <linux/io.h>
32 #include <linux/clk.h>
33 #include <linux/dmaengine.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/of_device.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/sh_dma.h>
38 #include <linux/spi/spi.h>
39 #include <linux/spi/rspi.h>
40
41 #define RSPI_SPCR 0x00 /* Control Register */
42 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
43 #define RSPI_SPPCR 0x02 /* Pin Control Register */
44 #define RSPI_SPSR 0x03 /* Status Register */
45 #define RSPI_SPDR 0x04 /* Data Register */
46 #define RSPI_SPSCR 0x08 /* Sequence Control Register */
47 #define RSPI_SPSSR 0x09 /* Sequence Status Register */
48 #define RSPI_SPBR 0x0a /* Bit Rate Register */
49 #define RSPI_SPDCR 0x0b /* Data Control Register */
50 #define RSPI_SPCKD 0x0c /* Clock Delay Register */
51 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
52 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
53 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
54 #define RSPI_SPCMD0 0x10 /* Command Register 0 */
55 #define RSPI_SPCMD1 0x12 /* Command Register 1 */
56 #define RSPI_SPCMD2 0x14 /* Command Register 2 */
57 #define RSPI_SPCMD3 0x16 /* Command Register 3 */
58 #define RSPI_SPCMD4 0x18 /* Command Register 4 */
59 #define RSPI_SPCMD5 0x1a /* Command Register 5 */
60 #define RSPI_SPCMD6 0x1c /* Command Register 6 */
61 #define RSPI_SPCMD7 0x1e /* Command Register 7 */
62 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
63 #define RSPI_NUM_SPCMD 8
64 #define RSPI_RZ_NUM_SPCMD 4
65 #define QSPI_NUM_SPCMD 4
66
67 /* RSPI on RZ only */
68 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */
69 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
70
71 /* QSPI only */
72 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */
73 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
74 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
75 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
76 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
77 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
78 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
79
80 /* SPCR - Control Register */
81 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
82 #define SPCR_SPE 0x40 /* Function Enable */
83 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
84 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
85 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
86 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
87 /* RSPI on SH only */
88 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
89 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
90 /* QSPI on R-Car M2 only */
91 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
92 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
93
94 /* SSLP - Slave Select Polarity Register */
95 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
96 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
97
98 /* SPPCR - Pin Control Register */
99 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
100 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
101 #define SPPCR_SPOM 0x04
102 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
103 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
104
105 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
106 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
107
108 /* SPSR - Status Register */
109 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
110 #define SPSR_TEND 0x40 /* Transmit End */
111 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
112 #define SPSR_PERF 0x08 /* Parity Error Flag */
113 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
114 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
115 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
116
117 /* SPSCR - Sequence Control Register */
118 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
119
120 /* SPSSR - Sequence Status Register */
121 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
122 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
123
124 /* SPDCR - Data Control Register */
125 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
126 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
127 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
128 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
129 #define SPDCR_SPLWORD SPDCR_SPLW1
130 #define SPDCR_SPLBYTE SPDCR_SPLW0
131 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
132 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
133 #define SPDCR_SLSEL1 0x08
134 #define SPDCR_SLSEL0 0x04
135 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
136 #define SPDCR_SPFC1 0x02
137 #define SPDCR_SPFC0 0x01
138 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
139
140 /* SPCKD - Clock Delay Register */
141 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
142
143 /* SSLND - Slave Select Negation Delay Register */
144 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
145
146 /* SPND - Next-Access Delay Register */
147 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
148
149 /* SPCR2 - Control Register 2 */
150 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
151 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
152 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
153 #define SPCR2_SPPE 0x01 /* Parity Enable */
154
155 /* SPCMDn - Command Registers */
156 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
157 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
158 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
159 #define SPCMD_LSBF 0x1000 /* LSB First */
160 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
161 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
162 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
163 #define SPCMD_SPB_16BIT 0x0100
164 #define SPCMD_SPB_20BIT 0x0000
165 #define SPCMD_SPB_24BIT 0x0100
166 #define SPCMD_SPB_32BIT 0x0200
167 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
168 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
169 #define SPCMD_SPIMOD1 0x0040
170 #define SPCMD_SPIMOD0 0x0020
171 #define SPCMD_SPIMOD_SINGLE 0
172 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
173 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
174 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
175 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
176 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
177 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
178 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
179
180 /* SPBFCR - Buffer Control Register */
181 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
182 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
183 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
184 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
185
186 struct rspi_data {
187 void __iomem *addr;
188 u32 max_speed_hz;
189 struct spi_master *master;
190 wait_queue_head_t wait;
191 struct clk *clk;
192 u16 spcmd;
193 u8 spsr;
194 u8 sppcr;
195 int rx_irq, tx_irq;
196 const struct spi_ops *ops;
197
198 unsigned dma_callbacked:1;
199 unsigned byte_access:1;
200 };
201
202 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
203 {
204 iowrite8(data, rspi->addr + offset);
205 }
206
207 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
208 {
209 iowrite16(data, rspi->addr + offset);
210 }
211
212 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
213 {
214 iowrite32(data, rspi->addr + offset);
215 }
216
217 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
218 {
219 return ioread8(rspi->addr + offset);
220 }
221
222 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
223 {
224 return ioread16(rspi->addr + offset);
225 }
226
227 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
228 {
229 if (rspi->byte_access)
230 rspi_write8(rspi, data, RSPI_SPDR);
231 else /* 16 bit */
232 rspi_write16(rspi, data, RSPI_SPDR);
233 }
234
235 static u16 rspi_read_data(const struct rspi_data *rspi)
236 {
237 if (rspi->byte_access)
238 return rspi_read8(rspi, RSPI_SPDR);
239 else /* 16 bit */
240 return rspi_read16(rspi, RSPI_SPDR);
241 }
242
243 /* optional functions */
244 struct spi_ops {
245 int (*set_config_register)(struct rspi_data *rspi, int access_size);
246 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
247 struct spi_transfer *xfer);
248 u16 mode_bits;
249 u16 flags;
250 u16 fifo_size;
251 };
252
253 /*
254 * functions for RSPI on legacy SH
255 */
256 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
257 {
258 int spbr;
259
260 /* Sets output mode, MOSI signal, and (optionally) loopback */
261 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
262
263 /* Sets transfer bit rate */
264 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
265 2 * rspi->max_speed_hz) - 1;
266 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
267
268 /* Disable dummy transmission, set 16-bit word access, 1 frame */
269 rspi_write8(rspi, 0, RSPI_SPDCR);
270 rspi->byte_access = 0;
271
272 /* Sets RSPCK, SSL, next-access delay value */
273 rspi_write8(rspi, 0x00, RSPI_SPCKD);
274 rspi_write8(rspi, 0x00, RSPI_SSLND);
275 rspi_write8(rspi, 0x00, RSPI_SPND);
276
277 /* Sets parity, interrupt mask */
278 rspi_write8(rspi, 0x00, RSPI_SPCR2);
279
280 /* Sets SPCMD */
281 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
282 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
283
284 /* Sets RSPI mode */
285 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
286
287 return 0;
288 }
289
290 /*
291 * functions for RSPI on RZ
292 */
293 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
294 {
295 int spbr;
296
297 /* Sets output mode, MOSI signal, and (optionally) loopback */
298 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
299
300 /* Sets transfer bit rate */
301 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
302 2 * rspi->max_speed_hz) - 1;
303 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
304
305 /* Disable dummy transmission, set byte access */
306 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
307 rspi->byte_access = 1;
308
309 /* Sets RSPCK, SSL, next-access delay value */
310 rspi_write8(rspi, 0x00, RSPI_SPCKD);
311 rspi_write8(rspi, 0x00, RSPI_SSLND);
312 rspi_write8(rspi, 0x00, RSPI_SPND);
313
314 /* Sets SPCMD */
315 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
316 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
317
318 /* Sets RSPI mode */
319 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
320
321 return 0;
322 }
323
324 /*
325 * functions for QSPI
326 */
327 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
328 {
329 int spbr;
330
331 /* Sets output mode, MOSI signal, and (optionally) loopback */
332 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
333
334 /* Sets transfer bit rate */
335 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
336 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
337
338 /* Disable dummy transmission, set byte access */
339 rspi_write8(rspi, 0, RSPI_SPDCR);
340 rspi->byte_access = 1;
341
342 /* Sets RSPCK, SSL, next-access delay value */
343 rspi_write8(rspi, 0x00, RSPI_SPCKD);
344 rspi_write8(rspi, 0x00, RSPI_SSLND);
345 rspi_write8(rspi, 0x00, RSPI_SPND);
346
347 /* Data Length Setting */
348 if (access_size == 8)
349 rspi->spcmd |= SPCMD_SPB_8BIT;
350 else if (access_size == 16)
351 rspi->spcmd |= SPCMD_SPB_16BIT;
352 else
353 rspi->spcmd |= SPCMD_SPB_32BIT;
354
355 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
356
357 /* Resets transfer data length */
358 rspi_write32(rspi, 0, QSPI_SPBMUL0);
359
360 /* Resets transmit and receive buffer */
361 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
362 /* Sets buffer to allow normal operation */
363 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
364
365 /* Sets SPCMD */
366 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
367
368 /* Enables SPI function in master mode */
369 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
370
371 return 0;
372 }
373
374 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
375
376 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
377 {
378 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
379 }
380
381 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
382 {
383 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
384 }
385
386 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
387 u8 enable_bit)
388 {
389 int ret;
390
391 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
392 if (rspi->spsr & wait_mask)
393 return 0;
394
395 rspi_enable_irq(rspi, enable_bit);
396 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
397 if (ret == 0 && !(rspi->spsr & wait_mask))
398 return -ETIMEDOUT;
399
400 return 0;
401 }
402
403 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
404 {
405 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
406 }
407
408 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
409 {
410 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
411 }
412
413 static int rspi_data_out(struct rspi_data *rspi, u8 data)
414 {
415 int error = rspi_wait_for_tx_empty(rspi);
416 if (error < 0) {
417 dev_err(&rspi->master->dev, "transmit timeout\n");
418 return error;
419 }
420 rspi_write_data(rspi, data);
421 return 0;
422 }
423
424 static int rspi_data_in(struct rspi_data *rspi)
425 {
426 int error;
427 u8 data;
428
429 error = rspi_wait_for_rx_full(rspi);
430 if (error < 0) {
431 dev_err(&rspi->master->dev, "receive timeout\n");
432 return error;
433 }
434 data = rspi_read_data(rspi);
435 return data;
436 }
437
438 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
439 unsigned int n)
440 {
441 while (n-- > 0) {
442 if (tx) {
443 int ret = rspi_data_out(rspi, *tx++);
444 if (ret < 0)
445 return ret;
446 }
447 if (rx) {
448 int ret = rspi_data_in(rspi);
449 if (ret < 0)
450 return ret;
451 *rx++ = ret;
452 }
453 }
454
455 return 0;
456 }
457
458 static void rspi_dma_complete(void *arg)
459 {
460 struct rspi_data *rspi = arg;
461
462 rspi->dma_callbacked = 1;
463 wake_up_interruptible(&rspi->wait);
464 }
465
466 static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
467 {
468 struct dma_async_tx_descriptor *desc;
469 int ret;
470
471 desc = dmaengine_prep_slave_sg(rspi->master->dma_tx, t->tx_sg.sgl,
472 t->tx_sg.nents, DMA_TO_DEVICE,
473 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
474 if (!desc)
475 return -EIO;
476
477 /*
478 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
479 * called. So, this driver disables the IRQ while DMA transfer.
480 */
481 disable_irq(rspi->tx_irq);
482
483 rspi_enable_irq(rspi, SPCR_SPTIE);
484 rspi->dma_callbacked = 0;
485
486 desc->callback = rspi_dma_complete;
487 desc->callback_param = rspi;
488 dmaengine_submit(desc);
489 dma_async_issue_pending(rspi->master->dma_tx);
490
491 ret = wait_event_interruptible_timeout(rspi->wait,
492 rspi->dma_callbacked, HZ);
493 if (ret > 0 && rspi->dma_callbacked)
494 ret = 0;
495 else if (!ret)
496 ret = -ETIMEDOUT;
497 rspi_disable_irq(rspi, SPCR_SPTIE);
498
499 enable_irq(rspi->tx_irq);
500 return ret;
501 }
502
503 static void rspi_receive_init(const struct rspi_data *rspi)
504 {
505 u8 spsr;
506
507 spsr = rspi_read8(rspi, RSPI_SPSR);
508 if (spsr & SPSR_SPRF)
509 rspi_read_data(rspi); /* dummy read */
510 if (spsr & SPSR_OVRF)
511 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
512 RSPI_SPSR);
513 }
514
515 static void rspi_rz_receive_init(const struct rspi_data *rspi)
516 {
517 rspi_receive_init(rspi);
518 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
519 rspi_write8(rspi, 0, RSPI_SPBFCR);
520 }
521
522 static void qspi_receive_init(const struct rspi_data *rspi)
523 {
524 u8 spsr;
525
526 spsr = rspi_read8(rspi, RSPI_SPSR);
527 if (spsr & SPSR_SPRF)
528 rspi_read_data(rspi); /* dummy read */
529 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
530 rspi_write8(rspi, 0, QSPI_SPBFCR);
531 }
532
533 static int rspi_send_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
534 {
535 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
536 int ret;
537
538 /* prepare transmit transfer */
539 desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx, t->tx_sg.sgl,
540 t->tx_sg.nents, DMA_TO_DEVICE,
541 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
542 if (!desc_tx)
543 return -EIO;
544
545 /* prepare receive transfer */
546 desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx, t->rx_sg.sgl,
547 t->rx_sg.nents, DMA_FROM_DEVICE,
548 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
549 if (!desc_rx)
550 return -EIO;
551
552 /*
553 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
554 * called. So, this driver disables the IRQ while DMA transfer.
555 */
556 disable_irq(rspi->tx_irq);
557 if (rspi->rx_irq != rspi->tx_irq)
558 disable_irq(rspi->rx_irq);
559
560 rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
561 rspi->dma_callbacked = 0;
562
563 desc_rx->callback = rspi_dma_complete;
564 desc_rx->callback_param = rspi;
565 dmaengine_submit(desc_rx);
566 dma_async_issue_pending(rspi->master->dma_rx);
567
568 desc_tx->callback = NULL; /* No callback */
569 dmaengine_submit(desc_tx);
570 dma_async_issue_pending(rspi->master->dma_tx);
571
572 ret = wait_event_interruptible_timeout(rspi->wait,
573 rspi->dma_callbacked, HZ);
574 if (ret > 0 && rspi->dma_callbacked)
575 ret = 0;
576 else if (!ret)
577 ret = -ETIMEDOUT;
578 rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
579
580 enable_irq(rspi->tx_irq);
581 if (rspi->rx_irq != rspi->tx_irq)
582 enable_irq(rspi->rx_irq);
583
584 return ret;
585 }
586
587 static bool __rspi_can_dma(const struct rspi_data *rspi,
588 const struct spi_transfer *xfer)
589 {
590 return xfer->len > rspi->ops->fifo_size;
591 }
592
593 static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi,
594 struct spi_transfer *xfer)
595 {
596 struct rspi_data *rspi = spi_master_get_devdata(master);
597
598 return __rspi_can_dma(rspi, xfer);
599 }
600
601 static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
602 struct spi_transfer *xfer)
603 {
604 struct rspi_data *rspi = spi_master_get_devdata(master);
605 u8 spcr;
606 int ret;
607
608 spcr = rspi_read8(rspi, RSPI_SPCR);
609 if (xfer->rx_buf) {
610 rspi_receive_init(rspi);
611 spcr &= ~SPCR_TXMD;
612 } else {
613 spcr |= SPCR_TXMD;
614 }
615 rspi_write8(rspi, spcr, RSPI_SPCR);
616
617 if (master->can_dma && __rspi_can_dma(rspi, xfer)) {
618 if (xfer->rx_buf)
619 return rspi_send_receive_dma(rspi, xfer);
620 else
621 return rspi_send_dma(rspi, xfer);
622 }
623
624 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
625 if (ret < 0)
626 return ret;
627
628 /* Wait for the last transmission */
629 rspi_wait_for_tx_empty(rspi);
630
631 return 0;
632 }
633
634 static int rspi_rz_transfer_out_in(struct rspi_data *rspi,
635 struct spi_transfer *xfer)
636 {
637 int ret;
638
639 rspi_rz_receive_init(rspi);
640
641 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
642 if (ret < 0)
643 return ret;
644
645 /* Wait for the last transmission */
646 rspi_wait_for_tx_empty(rspi);
647
648 return 0;
649 }
650
651 static int rspi_rz_transfer_one(struct spi_master *master,
652 struct spi_device *spi,
653 struct spi_transfer *xfer)
654 {
655 struct rspi_data *rspi = spi_master_get_devdata(master);
656
657 return rspi_rz_transfer_out_in(rspi, xfer);
658 }
659
660 static int qspi_transfer_out_in(struct rspi_data *rspi,
661 struct spi_transfer *xfer)
662 {
663 int ret;
664
665 qspi_receive_init(rspi);
666
667 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
668 if (ret < 0)
669 return ret;
670
671 /* Wait for the last transmission */
672 rspi_wait_for_tx_empty(rspi);
673
674 return 0;
675 }
676
677 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
678 {
679 int ret;
680
681 ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
682 if (ret < 0)
683 return ret;
684
685 /* Wait for the last transmission */
686 rspi_wait_for_tx_empty(rspi);
687
688 return 0;
689 }
690
691 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
692 {
693 return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
694 }
695
696 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
697 struct spi_transfer *xfer)
698 {
699 struct rspi_data *rspi = spi_master_get_devdata(master);
700
701 if (spi->mode & SPI_LOOP) {
702 return qspi_transfer_out_in(rspi, xfer);
703 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
704 /* Quad or Dual SPI Write */
705 return qspi_transfer_out(rspi, xfer);
706 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
707 /* Quad or Dual SPI Read */
708 return qspi_transfer_in(rspi, xfer);
709 } else {
710 /* Single SPI Transfer */
711 return qspi_transfer_out_in(rspi, xfer);
712 }
713 }
714
715 static int rspi_setup(struct spi_device *spi)
716 {
717 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
718
719 rspi->max_speed_hz = spi->max_speed_hz;
720
721 rspi->spcmd = SPCMD_SSLKP;
722 if (spi->mode & SPI_CPOL)
723 rspi->spcmd |= SPCMD_CPOL;
724 if (spi->mode & SPI_CPHA)
725 rspi->spcmd |= SPCMD_CPHA;
726
727 /* CMOS output mode and MOSI signal from previous transfer */
728 rspi->sppcr = 0;
729 if (spi->mode & SPI_LOOP)
730 rspi->sppcr |= SPPCR_SPLP;
731
732 set_config_register(rspi, 8);
733
734 return 0;
735 }
736
737 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
738 {
739 if (xfer->tx_buf)
740 switch (xfer->tx_nbits) {
741 case SPI_NBITS_QUAD:
742 return SPCMD_SPIMOD_QUAD;
743 case SPI_NBITS_DUAL:
744 return SPCMD_SPIMOD_DUAL;
745 default:
746 return 0;
747 }
748 if (xfer->rx_buf)
749 switch (xfer->rx_nbits) {
750 case SPI_NBITS_QUAD:
751 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
752 case SPI_NBITS_DUAL:
753 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
754 default:
755 return 0;
756 }
757
758 return 0;
759 }
760
761 static int qspi_setup_sequencer(struct rspi_data *rspi,
762 const struct spi_message *msg)
763 {
764 const struct spi_transfer *xfer;
765 unsigned int i = 0, len = 0;
766 u16 current_mode = 0xffff, mode;
767
768 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
769 mode = qspi_transfer_mode(xfer);
770 if (mode == current_mode) {
771 len += xfer->len;
772 continue;
773 }
774
775 /* Transfer mode change */
776 if (i) {
777 /* Set transfer data length of previous transfer */
778 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
779 }
780
781 if (i >= QSPI_NUM_SPCMD) {
782 dev_err(&msg->spi->dev,
783 "Too many different transfer modes");
784 return -EINVAL;
785 }
786
787 /* Program transfer mode for this transfer */
788 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
789 current_mode = mode;
790 len = xfer->len;
791 i++;
792 }
793 if (i) {
794 /* Set final transfer data length and sequence length */
795 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
796 rspi_write8(rspi, i - 1, RSPI_SPSCR);
797 }
798
799 return 0;
800 }
801
802 static int rspi_prepare_message(struct spi_master *master,
803 struct spi_message *msg)
804 {
805 struct rspi_data *rspi = spi_master_get_devdata(master);
806 int ret;
807
808 if (msg->spi->mode &
809 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
810 /* Setup sequencer for messages with multiple transfer modes */
811 ret = qspi_setup_sequencer(rspi, msg);
812 if (ret < 0)
813 return ret;
814 }
815
816 /* Enable SPI function in master mode */
817 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
818 return 0;
819 }
820
821 static int rspi_unprepare_message(struct spi_master *master,
822 struct spi_message *msg)
823 {
824 struct rspi_data *rspi = spi_master_get_devdata(master);
825
826 /* Disable SPI function */
827 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
828
829 /* Reset sequencer for Single SPI Transfers */
830 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
831 rspi_write8(rspi, 0, RSPI_SPSCR);
832 return 0;
833 }
834
835 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
836 {
837 struct rspi_data *rspi = _sr;
838 u8 spsr;
839 irqreturn_t ret = IRQ_NONE;
840 u8 disable_irq = 0;
841
842 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
843 if (spsr & SPSR_SPRF)
844 disable_irq |= SPCR_SPRIE;
845 if (spsr & SPSR_SPTEF)
846 disable_irq |= SPCR_SPTIE;
847
848 if (disable_irq) {
849 ret = IRQ_HANDLED;
850 rspi_disable_irq(rspi, disable_irq);
851 wake_up(&rspi->wait);
852 }
853
854 return ret;
855 }
856
857 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
858 {
859 struct rspi_data *rspi = _sr;
860 u8 spsr;
861
862 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
863 if (spsr & SPSR_SPRF) {
864 rspi_disable_irq(rspi, SPCR_SPRIE);
865 wake_up(&rspi->wait);
866 return IRQ_HANDLED;
867 }
868
869 return 0;
870 }
871
872 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
873 {
874 struct rspi_data *rspi = _sr;
875 u8 spsr;
876
877 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
878 if (spsr & SPSR_SPTEF) {
879 rspi_disable_irq(rspi, SPCR_SPTIE);
880 wake_up(&rspi->wait);
881 return IRQ_HANDLED;
882 }
883
884 return 0;
885 }
886
887 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
888 enum dma_transfer_direction dir,
889 unsigned int id,
890 dma_addr_t port_addr)
891 {
892 dma_cap_mask_t mask;
893 struct dma_chan *chan;
894 struct dma_slave_config cfg;
895 int ret;
896
897 dma_cap_zero(mask);
898 dma_cap_set(DMA_SLAVE, mask);
899
900 chan = dma_request_channel(mask, shdma_chan_filter,
901 (void *)(unsigned long)id);
902 if (!chan) {
903 dev_warn(dev, "dma_request_channel failed\n");
904 return NULL;
905 }
906
907 memset(&cfg, 0, sizeof(cfg));
908 cfg.slave_id = id;
909 cfg.direction = dir;
910 if (dir == DMA_MEM_TO_DEV)
911 cfg.dst_addr = port_addr;
912 else
913 cfg.src_addr = port_addr;
914
915 ret = dmaengine_slave_config(chan, &cfg);
916 if (ret) {
917 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
918 dma_release_channel(chan);
919 return NULL;
920 }
921
922 return chan;
923 }
924
925 static int rspi_request_dma(struct device *dev, struct spi_master *master,
926 const struct resource *res)
927 {
928 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
929
930 if (!rspi_pd || !rspi_pd->dma_rx_id || !rspi_pd->dma_tx_id)
931 return 0; /* The driver assumes no error. */
932
933 master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM,
934 rspi_pd->dma_rx_id,
935 res->start + RSPI_SPDR);
936 if (!master->dma_rx)
937 return -ENODEV;
938
939 master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV,
940 rspi_pd->dma_tx_id,
941 res->start + RSPI_SPDR);
942 if (!master->dma_tx) {
943 dma_release_channel(master->dma_rx);
944 master->dma_rx = NULL;
945 return -ENODEV;
946 }
947
948 master->can_dma = rspi_can_dma;
949 dev_info(dev, "DMA available");
950 return 0;
951 }
952
953 static void rspi_release_dma(struct rspi_data *rspi)
954 {
955 if (rspi->master->dma_tx)
956 dma_release_channel(rspi->master->dma_tx);
957 if (rspi->master->dma_rx)
958 dma_release_channel(rspi->master->dma_rx);
959 }
960
961 static int rspi_remove(struct platform_device *pdev)
962 {
963 struct rspi_data *rspi = platform_get_drvdata(pdev);
964
965 rspi_release_dma(rspi);
966 pm_runtime_disable(&pdev->dev);
967
968 return 0;
969 }
970
971 static const struct spi_ops rspi_ops = {
972 .set_config_register = rspi_set_config_register,
973 .transfer_one = rspi_transfer_one,
974 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
975 .flags = SPI_MASTER_MUST_TX,
976 .fifo_size = 8,
977 };
978
979 static const struct spi_ops rspi_rz_ops = {
980 .set_config_register = rspi_rz_set_config_register,
981 .transfer_one = rspi_rz_transfer_one,
982 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
983 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
984 .fifo_size = 8, /* 8 for TX, 32 for RX */
985 };
986
987 static const struct spi_ops qspi_ops = {
988 .set_config_register = qspi_set_config_register,
989 .transfer_one = qspi_transfer_one,
990 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
991 SPI_TX_DUAL | SPI_TX_QUAD |
992 SPI_RX_DUAL | SPI_RX_QUAD,
993 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
994 .fifo_size = 32,
995 };
996
997 #ifdef CONFIG_OF
998 static const struct of_device_id rspi_of_match[] = {
999 /* RSPI on legacy SH */
1000 { .compatible = "renesas,rspi", .data = &rspi_ops },
1001 /* RSPI on RZ/A1H */
1002 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1003 /* QSPI on R-Car Gen2 */
1004 { .compatible = "renesas,qspi", .data = &qspi_ops },
1005 { /* sentinel */ }
1006 };
1007
1008 MODULE_DEVICE_TABLE(of, rspi_of_match);
1009
1010 static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1011 {
1012 u32 num_cs;
1013 int error;
1014
1015 /* Parse DT properties */
1016 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1017 if (error) {
1018 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1019 return error;
1020 }
1021
1022 master->num_chipselect = num_cs;
1023 return 0;
1024 }
1025 #else
1026 #define rspi_of_match NULL
1027 static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1028 {
1029 return -EINVAL;
1030 }
1031 #endif /* CONFIG_OF */
1032
1033 static int rspi_request_irq(struct device *dev, unsigned int irq,
1034 irq_handler_t handler, const char *suffix,
1035 void *dev_id)
1036 {
1037 const char *base = dev_name(dev);
1038 size_t len = strlen(base) + strlen(suffix) + 2;
1039 char *name = devm_kzalloc(dev, len, GFP_KERNEL);
1040 if (!name)
1041 return -ENOMEM;
1042 snprintf(name, len, "%s:%s", base, suffix);
1043 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1044 }
1045
1046 static int rspi_probe(struct platform_device *pdev)
1047 {
1048 struct resource *res;
1049 struct spi_master *master;
1050 struct rspi_data *rspi;
1051 int ret;
1052 const struct of_device_id *of_id;
1053 const struct rspi_plat_data *rspi_pd;
1054 const struct spi_ops *ops;
1055
1056 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1057 if (master == NULL) {
1058 dev_err(&pdev->dev, "spi_alloc_master error.\n");
1059 return -ENOMEM;
1060 }
1061
1062 of_id = of_match_device(rspi_of_match, &pdev->dev);
1063 if (of_id) {
1064 ops = of_id->data;
1065 ret = rspi_parse_dt(&pdev->dev, master);
1066 if (ret)
1067 goto error1;
1068 } else {
1069 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1070 rspi_pd = dev_get_platdata(&pdev->dev);
1071 if (rspi_pd && rspi_pd->num_chipselect)
1072 master->num_chipselect = rspi_pd->num_chipselect;
1073 else
1074 master->num_chipselect = 2; /* default */
1075 };
1076
1077 /* ops parameter check */
1078 if (!ops->set_config_register) {
1079 dev_err(&pdev->dev, "there is no set_config_register\n");
1080 ret = -ENODEV;
1081 goto error1;
1082 }
1083
1084 rspi = spi_master_get_devdata(master);
1085 platform_set_drvdata(pdev, rspi);
1086 rspi->ops = ops;
1087 rspi->master = master;
1088
1089 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1090 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1091 if (IS_ERR(rspi->addr)) {
1092 ret = PTR_ERR(rspi->addr);
1093 goto error1;
1094 }
1095
1096 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1097 if (IS_ERR(rspi->clk)) {
1098 dev_err(&pdev->dev, "cannot get clock\n");
1099 ret = PTR_ERR(rspi->clk);
1100 goto error1;
1101 }
1102
1103 pm_runtime_enable(&pdev->dev);
1104
1105 init_waitqueue_head(&rspi->wait);
1106
1107 master->bus_num = pdev->id;
1108 master->setup = rspi_setup;
1109 master->auto_runtime_pm = true;
1110 master->transfer_one = ops->transfer_one;
1111 master->prepare_message = rspi_prepare_message;
1112 master->unprepare_message = rspi_unprepare_message;
1113 master->mode_bits = ops->mode_bits;
1114 master->flags = ops->flags;
1115 master->dev.of_node = pdev->dev.of_node;
1116
1117 ret = platform_get_irq_byname(pdev, "rx");
1118 if (ret < 0) {
1119 ret = platform_get_irq_byname(pdev, "mux");
1120 if (ret < 0)
1121 ret = platform_get_irq(pdev, 0);
1122 if (ret >= 0)
1123 rspi->rx_irq = rspi->tx_irq = ret;
1124 } else {
1125 rspi->rx_irq = ret;
1126 ret = platform_get_irq_byname(pdev, "tx");
1127 if (ret >= 0)
1128 rspi->tx_irq = ret;
1129 }
1130 if (ret < 0) {
1131 dev_err(&pdev->dev, "platform_get_irq error\n");
1132 goto error2;
1133 }
1134
1135 if (rspi->rx_irq == rspi->tx_irq) {
1136 /* Single multiplexed interrupt */
1137 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1138 "mux", rspi);
1139 } else {
1140 /* Multi-interrupt mode, only SPRI and SPTI are used */
1141 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1142 "rx", rspi);
1143 if (!ret)
1144 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1145 rspi_irq_tx, "tx", rspi);
1146 }
1147 if (ret < 0) {
1148 dev_err(&pdev->dev, "request_irq error\n");
1149 goto error2;
1150 }
1151
1152 ret = rspi_request_dma(&pdev->dev, master, res);
1153 if (ret < 0)
1154 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1155
1156 ret = devm_spi_register_master(&pdev->dev, master);
1157 if (ret < 0) {
1158 dev_err(&pdev->dev, "spi_register_master error.\n");
1159 goto error3;
1160 }
1161
1162 dev_info(&pdev->dev, "probed\n");
1163
1164 return 0;
1165
1166 error3:
1167 rspi_release_dma(rspi);
1168 error2:
1169 pm_runtime_disable(&pdev->dev);
1170 error1:
1171 spi_master_put(master);
1172
1173 return ret;
1174 }
1175
1176 static struct platform_device_id spi_driver_ids[] = {
1177 { "rspi", (kernel_ulong_t)&rspi_ops },
1178 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1179 { "qspi", (kernel_ulong_t)&qspi_ops },
1180 {},
1181 };
1182
1183 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1184
1185 static struct platform_driver rspi_driver = {
1186 .probe = rspi_probe,
1187 .remove = rspi_remove,
1188 .id_table = spi_driver_ids,
1189 .driver = {
1190 .name = "renesas_spi",
1191 .owner = THIS_MODULE,
1192 .of_match_table = of_match_ptr(rspi_of_match),
1193 },
1194 };
1195 module_platform_driver(rspi_driver);
1196
1197 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1198 MODULE_LICENSE("GPL v2");
1199 MODULE_AUTHOR("Yoshihiro Shimoda");
1200 MODULE_ALIAS("platform:rspi");
Linux kernel - Deliverables
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