2 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/dmaengine.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/spi/spi.h>
30 #include <linux/gpio.h>
32 #include <linux/of_gpio.h>
34 #include <linux/platform_data/spi-s3c64xx.h>
36 #define MAX_SPI_PORTS 3
37 #define S3C64XX_SPI_QUIRK_POLL (1 << 0)
39 /* Registers and bit-fields */
41 #define S3C64XX_SPI_CH_CFG 0x00
42 #define S3C64XX_SPI_CLK_CFG 0x04
43 #define S3C64XX_SPI_MODE_CFG 0x08
44 #define S3C64XX_SPI_SLAVE_SEL 0x0C
45 #define S3C64XX_SPI_INT_EN 0x10
46 #define S3C64XX_SPI_STATUS 0x14
47 #define S3C64XX_SPI_TX_DATA 0x18
48 #define S3C64XX_SPI_RX_DATA 0x1C
49 #define S3C64XX_SPI_PACKET_CNT 0x20
50 #define S3C64XX_SPI_PENDING_CLR 0x24
51 #define S3C64XX_SPI_SWAP_CFG 0x28
52 #define S3C64XX_SPI_FB_CLK 0x2C
54 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
55 #define S3C64XX_SPI_CH_SW_RST (1<<5)
56 #define S3C64XX_SPI_CH_SLAVE (1<<4)
57 #define S3C64XX_SPI_CPOL_L (1<<3)
58 #define S3C64XX_SPI_CPHA_B (1<<2)
59 #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
60 #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
62 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
63 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
64 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
65 #define S3C64XX_SPI_PSR_MASK 0xff
67 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
68 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
69 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
70 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
71 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
72 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
73 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
74 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
75 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
76 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
77 #define S3C64XX_SPI_MODE_4BURST (1<<0)
79 #define S3C64XX_SPI_SLAVE_AUTO (1<<1)
80 #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
82 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
83 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
84 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
85 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
86 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
87 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
88 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
90 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
91 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
92 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
93 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
94 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
95 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
97 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
99 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
100 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
101 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
102 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
103 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
105 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
106 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
107 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
108 #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
109 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
110 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
111 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
112 #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
114 #define S3C64XX_SPI_FBCLK_MSK (3<<0)
116 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
117 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
118 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
119 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
120 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
123 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
124 #define S3C64XX_SPI_TRAILCNT_OFF 19
126 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
128 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
129 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
131 #define RXBUSY (1<<2)
132 #define TXBUSY (1<<3)
134 struct s3c64xx_spi_dma_data
{
136 enum dma_transfer_direction direction
;
141 * struct s3c64xx_spi_info - SPI Controller hardware info
142 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
143 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
144 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
145 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
146 * @clk_from_cmu: True, if the controller does not include a clock mux and
149 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
150 * differ in some aspects such as the size of the fifo and spi bus clock
151 * setup. Such differences are specified to the driver using this structure
152 * which is provided as driver data to the driver.
154 struct s3c64xx_spi_port_config
{
155 int fifo_lvl_mask
[MAX_SPI_PORTS
];
164 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
165 * @clk: Pointer to the spi clock.
166 * @src_clk: Pointer to the clock used to generate SPI signals.
167 * @master: Pointer to the SPI Protocol master.
168 * @cntrlr_info: Platform specific data for the controller this driver manages.
169 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
170 * @lock: Controller specific lock.
171 * @state: Set of FLAGS to indicate status.
172 * @rx_dmach: Controller's DMA channel for Rx.
173 * @tx_dmach: Controller's DMA channel for Tx.
174 * @sfr_start: BUS address of SPI controller regs.
175 * @regs: Pointer to ioremap'ed controller registers.
177 * @xfer_completion: To indicate completion of xfer task.
178 * @cur_mode: Stores the active configuration of the controller.
179 * @cur_bpw: Stores the active bits per word settings.
180 * @cur_speed: Stores the active xfer clock speed.
182 struct s3c64xx_spi_driver_data
{
186 struct platform_device
*pdev
;
187 struct spi_master
*master
;
188 struct s3c64xx_spi_info
*cntrlr_info
;
189 struct spi_device
*tgl_spi
;
191 unsigned long sfr_start
;
192 struct completion xfer_completion
;
194 unsigned cur_mode
, cur_bpw
;
196 struct s3c64xx_spi_dma_data rx_dma
;
197 struct s3c64xx_spi_dma_data tx_dma
;
198 struct s3c64xx_spi_port_config
*port_conf
;
199 unsigned int port_id
;
203 static void flush_fifo(struct s3c64xx_spi_driver_data
*sdd
)
205 void __iomem
*regs
= sdd
->regs
;
209 writel(0, regs
+ S3C64XX_SPI_PACKET_CNT
);
211 val
= readl(regs
+ S3C64XX_SPI_CH_CFG
);
212 val
&= ~(S3C64XX_SPI_CH_RXCH_ON
| S3C64XX_SPI_CH_TXCH_ON
);
213 writel(val
, regs
+ S3C64XX_SPI_CH_CFG
);
215 val
= readl(regs
+ S3C64XX_SPI_CH_CFG
);
216 val
|= S3C64XX_SPI_CH_SW_RST
;
217 val
&= ~S3C64XX_SPI_CH_HS_EN
;
218 writel(val
, regs
+ S3C64XX_SPI_CH_CFG
);
221 loops
= msecs_to_loops(1);
223 val
= readl(regs
+ S3C64XX_SPI_STATUS
);
224 } while (TX_FIFO_LVL(val
, sdd
) && loops
--);
227 dev_warn(&sdd
->pdev
->dev
, "Timed out flushing TX FIFO\n");
230 loops
= msecs_to_loops(1);
232 val
= readl(regs
+ S3C64XX_SPI_STATUS
);
233 if (RX_FIFO_LVL(val
, sdd
))
234 readl(regs
+ S3C64XX_SPI_RX_DATA
);
240 dev_warn(&sdd
->pdev
->dev
, "Timed out flushing RX FIFO\n");
242 val
= readl(regs
+ S3C64XX_SPI_CH_CFG
);
243 val
&= ~S3C64XX_SPI_CH_SW_RST
;
244 writel(val
, regs
+ S3C64XX_SPI_CH_CFG
);
246 val
= readl(regs
+ S3C64XX_SPI_MODE_CFG
);
247 val
&= ~(S3C64XX_SPI_MODE_TXDMA_ON
| S3C64XX_SPI_MODE_RXDMA_ON
);
248 writel(val
, regs
+ S3C64XX_SPI_MODE_CFG
);
251 static void s3c64xx_spi_dmacb(void *data
)
253 struct s3c64xx_spi_driver_data
*sdd
;
254 struct s3c64xx_spi_dma_data
*dma
= data
;
257 if (dma
->direction
== DMA_DEV_TO_MEM
)
258 sdd
= container_of(data
,
259 struct s3c64xx_spi_driver_data
, rx_dma
);
261 sdd
= container_of(data
,
262 struct s3c64xx_spi_driver_data
, tx_dma
);
264 spin_lock_irqsave(&sdd
->lock
, flags
);
266 if (dma
->direction
== DMA_DEV_TO_MEM
) {
267 sdd
->state
&= ~RXBUSY
;
268 if (!(sdd
->state
& TXBUSY
))
269 complete(&sdd
->xfer_completion
);
271 sdd
->state
&= ~TXBUSY
;
272 if (!(sdd
->state
& RXBUSY
))
273 complete(&sdd
->xfer_completion
);
276 spin_unlock_irqrestore(&sdd
->lock
, flags
);
279 static void prepare_dma(struct s3c64xx_spi_dma_data
*dma
,
280 struct sg_table
*sgt
)
282 struct s3c64xx_spi_driver_data
*sdd
;
283 struct dma_slave_config config
;
284 struct dma_async_tx_descriptor
*desc
;
286 memset(&config
, 0, sizeof(config
));
288 if (dma
->direction
== DMA_DEV_TO_MEM
) {
289 sdd
= container_of((void *)dma
,
290 struct s3c64xx_spi_driver_data
, rx_dma
);
291 config
.direction
= dma
->direction
;
292 config
.src_addr
= sdd
->sfr_start
+ S3C64XX_SPI_RX_DATA
;
293 config
.src_addr_width
= sdd
->cur_bpw
/ 8;
294 config
.src_maxburst
= 1;
295 dmaengine_slave_config(dma
->ch
, &config
);
297 sdd
= container_of((void *)dma
,
298 struct s3c64xx_spi_driver_data
, tx_dma
);
299 config
.direction
= dma
->direction
;
300 config
.dst_addr
= sdd
->sfr_start
+ S3C64XX_SPI_TX_DATA
;
301 config
.dst_addr_width
= sdd
->cur_bpw
/ 8;
302 config
.dst_maxburst
= 1;
303 dmaengine_slave_config(dma
->ch
, &config
);
306 desc
= dmaengine_prep_slave_sg(dma
->ch
, sgt
->sgl
, sgt
->nents
,
307 dma
->direction
, DMA_PREP_INTERRUPT
);
309 desc
->callback
= s3c64xx_spi_dmacb
;
310 desc
->callback_param
= dma
;
312 dmaengine_submit(desc
);
313 dma_async_issue_pending(dma
->ch
);
316 static int s3c64xx_spi_prepare_transfer(struct spi_master
*spi
)
318 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(spi
);
319 dma_filter_fn filter
= sdd
->cntrlr_info
->filter
;
320 struct device
*dev
= &sdd
->pdev
->dev
;
324 if (!is_polling(sdd
)) {
326 dma_cap_set(DMA_SLAVE
, mask
);
328 /* Acquire DMA channels */
329 sdd
->rx_dma
.ch
= dma_request_slave_channel_compat(mask
, filter
,
330 (void *)sdd
->rx_dma
.dmach
, dev
, "rx");
331 if (!sdd
->rx_dma
.ch
) {
332 dev_err(dev
, "Failed to get RX DMA channel\n");
336 spi
->dma_rx
= sdd
->rx_dma
.ch
;
338 sdd
->tx_dma
.ch
= dma_request_slave_channel_compat(mask
, filter
,
339 (void *)sdd
->tx_dma
.dmach
, dev
, "tx");
340 if (!sdd
->tx_dma
.ch
) {
341 dev_err(dev
, "Failed to get TX DMA channel\n");
345 spi
->dma_tx
= sdd
->tx_dma
.ch
;
348 ret
= pm_runtime_get_sync(&sdd
->pdev
->dev
);
350 dev_err(dev
, "Failed to enable device: %d\n", ret
);
357 dma_release_channel(sdd
->tx_dma
.ch
);
359 dma_release_channel(sdd
->rx_dma
.ch
);
364 static int s3c64xx_spi_unprepare_transfer(struct spi_master
*spi
)
366 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(spi
);
368 /* Free DMA channels */
369 if (!is_polling(sdd
)) {
370 dma_release_channel(sdd
->rx_dma
.ch
);
371 dma_release_channel(sdd
->tx_dma
.ch
);
374 pm_runtime_put(&sdd
->pdev
->dev
);
378 static bool s3c64xx_spi_can_dma(struct spi_master
*master
,
379 struct spi_device
*spi
,
380 struct spi_transfer
*xfer
)
382 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
384 return xfer
->len
> (FIFO_LVL_MASK(sdd
) >> 1) + 1;
387 static void enable_datapath(struct s3c64xx_spi_driver_data
*sdd
,
388 struct spi_device
*spi
,
389 struct spi_transfer
*xfer
, int dma_mode
)
391 void __iomem
*regs
= sdd
->regs
;
394 modecfg
= readl(regs
+ S3C64XX_SPI_MODE_CFG
);
395 modecfg
&= ~(S3C64XX_SPI_MODE_TXDMA_ON
| S3C64XX_SPI_MODE_RXDMA_ON
);
397 chcfg
= readl(regs
+ S3C64XX_SPI_CH_CFG
);
398 chcfg
&= ~S3C64XX_SPI_CH_TXCH_ON
;
401 chcfg
&= ~S3C64XX_SPI_CH_RXCH_ON
;
403 /* Always shift in data in FIFO, even if xfer is Tx only,
404 * this helps setting PCKT_CNT value for generating clocks
407 chcfg
|= S3C64XX_SPI_CH_RXCH_ON
;
408 writel(((xfer
->len
* 8 / sdd
->cur_bpw
) & 0xffff)
409 | S3C64XX_SPI_PACKET_CNT_EN
,
410 regs
+ S3C64XX_SPI_PACKET_CNT
);
413 if (xfer
->tx_buf
!= NULL
) {
414 sdd
->state
|= TXBUSY
;
415 chcfg
|= S3C64XX_SPI_CH_TXCH_ON
;
417 modecfg
|= S3C64XX_SPI_MODE_TXDMA_ON
;
418 prepare_dma(&sdd
->tx_dma
, &xfer
->tx_sg
);
420 switch (sdd
->cur_bpw
) {
422 iowrite32_rep(regs
+ S3C64XX_SPI_TX_DATA
,
423 xfer
->tx_buf
, xfer
->len
/ 4);
426 iowrite16_rep(regs
+ S3C64XX_SPI_TX_DATA
,
427 xfer
->tx_buf
, xfer
->len
/ 2);
430 iowrite8_rep(regs
+ S3C64XX_SPI_TX_DATA
,
431 xfer
->tx_buf
, xfer
->len
);
437 if (xfer
->rx_buf
!= NULL
) {
438 sdd
->state
|= RXBUSY
;
440 if (sdd
->port_conf
->high_speed
&& sdd
->cur_speed
>= 30000000UL
441 && !(sdd
->cur_mode
& SPI_CPHA
))
442 chcfg
|= S3C64XX_SPI_CH_HS_EN
;
445 modecfg
|= S3C64XX_SPI_MODE_RXDMA_ON
;
446 chcfg
|= S3C64XX_SPI_CH_RXCH_ON
;
447 writel(((xfer
->len
* 8 / sdd
->cur_bpw
) & 0xffff)
448 | S3C64XX_SPI_PACKET_CNT_EN
,
449 regs
+ S3C64XX_SPI_PACKET_CNT
);
450 prepare_dma(&sdd
->rx_dma
, &xfer
->rx_sg
);
454 writel(modecfg
, regs
+ S3C64XX_SPI_MODE_CFG
);
455 writel(chcfg
, regs
+ S3C64XX_SPI_CH_CFG
);
458 static u32
s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data
*sdd
,
461 void __iomem
*regs
= sdd
->regs
;
462 unsigned long val
= 1;
465 /* max fifo depth available */
466 u32 max_fifo
= (FIFO_LVL_MASK(sdd
) >> 1) + 1;
469 val
= msecs_to_loops(timeout_ms
);
472 status
= readl(regs
+ S3C64XX_SPI_STATUS
);
473 } while (RX_FIFO_LVL(status
, sdd
) < max_fifo
&& --val
);
475 /* return the actual received data length */
476 return RX_FIFO_LVL(status
, sdd
);
479 static int wait_for_dma(struct s3c64xx_spi_driver_data
*sdd
,
480 struct spi_transfer
*xfer
)
482 void __iomem
*regs
= sdd
->regs
;
487 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
488 ms
= xfer
->len
* 8 * 1000 / sdd
->cur_speed
;
489 ms
+= 10; /* some tolerance */
491 val
= msecs_to_jiffies(ms
) + 10;
492 val
= wait_for_completion_timeout(&sdd
->xfer_completion
, val
);
495 * If the previous xfer was completed within timeout, then
496 * proceed further else return -EIO.
497 * DmaTx returns after simply writing data in the FIFO,
498 * w/o waiting for real transmission on the bus to finish.
499 * DmaRx returns only after Dma read data from FIFO which
500 * needs bus transmission to finish, so we don't worry if
501 * Xfer involved Rx(with or without Tx).
503 if (val
&& !xfer
->rx_buf
) {
504 val
= msecs_to_loops(10);
505 status
= readl(regs
+ S3C64XX_SPI_STATUS
);
506 while ((TX_FIFO_LVL(status
, sdd
)
507 || !S3C64XX_SPI_ST_TX_DONE(status
, sdd
))
510 status
= readl(regs
+ S3C64XX_SPI_STATUS
);
515 /* If timed out while checking rx/tx status return error */
522 static int wait_for_pio(struct s3c64xx_spi_driver_data
*sdd
,
523 struct spi_transfer
*xfer
)
525 void __iomem
*regs
= sdd
->regs
;
533 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
534 ms
= xfer
->len
* 8 * 1000 / sdd
->cur_speed
;
535 ms
+= 10; /* some tolerance */
537 val
= msecs_to_loops(ms
);
539 status
= readl(regs
+ S3C64XX_SPI_STATUS
);
540 } while (RX_FIFO_LVL(status
, sdd
) < xfer
->len
&& --val
);
543 /* If it was only Tx */
545 sdd
->state
&= ~TXBUSY
;
550 * If the receive length is bigger than the controller fifo
551 * size, calculate the loops and read the fifo as many times.
552 * loops = length / max fifo size (calculated by using the
554 * For any size less than the fifo size the below code is
555 * executed atleast once.
557 loops
= xfer
->len
/ ((FIFO_LVL_MASK(sdd
) >> 1) + 1);
560 /* wait for data to be received in the fifo */
561 cpy_len
= s3c64xx_spi_wait_for_timeout(sdd
,
564 switch (sdd
->cur_bpw
) {
566 ioread32_rep(regs
+ S3C64XX_SPI_RX_DATA
,
570 ioread16_rep(regs
+ S3C64XX_SPI_RX_DATA
,
574 ioread8_rep(regs
+ S3C64XX_SPI_RX_DATA
,
581 sdd
->state
&= ~RXBUSY
;
586 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data
*sdd
)
588 void __iomem
*regs
= sdd
->regs
;
592 if (sdd
->port_conf
->clk_from_cmu
) {
593 clk_disable_unprepare(sdd
->src_clk
);
595 val
= readl(regs
+ S3C64XX_SPI_CLK_CFG
);
596 val
&= ~S3C64XX_SPI_ENCLK_ENABLE
;
597 writel(val
, regs
+ S3C64XX_SPI_CLK_CFG
);
600 /* Set Polarity and Phase */
601 val
= readl(regs
+ S3C64XX_SPI_CH_CFG
);
602 val
&= ~(S3C64XX_SPI_CH_SLAVE
|
606 if (sdd
->cur_mode
& SPI_CPOL
)
607 val
|= S3C64XX_SPI_CPOL_L
;
609 if (sdd
->cur_mode
& SPI_CPHA
)
610 val
|= S3C64XX_SPI_CPHA_B
;
612 writel(val
, regs
+ S3C64XX_SPI_CH_CFG
);
614 /* Set Channel & DMA Mode */
615 val
= readl(regs
+ S3C64XX_SPI_MODE_CFG
);
616 val
&= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
617 | S3C64XX_SPI_MODE_CH_TSZ_MASK
);
619 switch (sdd
->cur_bpw
) {
621 val
|= S3C64XX_SPI_MODE_BUS_TSZ_WORD
;
622 val
|= S3C64XX_SPI_MODE_CH_TSZ_WORD
;
625 val
|= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD
;
626 val
|= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD
;
629 val
|= S3C64XX_SPI_MODE_BUS_TSZ_BYTE
;
630 val
|= S3C64XX_SPI_MODE_CH_TSZ_BYTE
;
634 writel(val
, regs
+ S3C64XX_SPI_MODE_CFG
);
636 if (sdd
->port_conf
->clk_from_cmu
) {
637 /* Configure Clock */
638 /* There is half-multiplier before the SPI */
639 clk_set_rate(sdd
->src_clk
, sdd
->cur_speed
* 2);
641 clk_prepare_enable(sdd
->src_clk
);
643 /* Configure Clock */
644 val
= readl(regs
+ S3C64XX_SPI_CLK_CFG
);
645 val
&= ~S3C64XX_SPI_PSR_MASK
;
646 val
|= ((clk_get_rate(sdd
->src_clk
) / sdd
->cur_speed
/ 2 - 1)
647 & S3C64XX_SPI_PSR_MASK
);
648 writel(val
, regs
+ S3C64XX_SPI_CLK_CFG
);
651 val
= readl(regs
+ S3C64XX_SPI_CLK_CFG
);
652 val
|= S3C64XX_SPI_ENCLK_ENABLE
;
653 writel(val
, regs
+ S3C64XX_SPI_CLK_CFG
);
657 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
659 static int s3c64xx_spi_prepare_message(struct spi_master
*master
,
660 struct spi_message
*msg
)
662 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
663 struct spi_device
*spi
= msg
->spi
;
664 struct s3c64xx_spi_csinfo
*cs
= spi
->controller_data
;
666 /* If Master's(controller) state differs from that needed by Slave */
667 if (sdd
->cur_speed
!= spi
->max_speed_hz
668 || sdd
->cur_mode
!= spi
->mode
669 || sdd
->cur_bpw
!= spi
->bits_per_word
) {
670 sdd
->cur_bpw
= spi
->bits_per_word
;
671 sdd
->cur_speed
= spi
->max_speed_hz
;
672 sdd
->cur_mode
= spi
->mode
;
673 s3c64xx_spi_config(sdd
);
676 /* Configure feedback delay */
677 writel(cs
->fb_delay
& 0x3, sdd
->regs
+ S3C64XX_SPI_FB_CLK
);
682 static int s3c64xx_spi_transfer_one(struct spi_master
*master
,
683 struct spi_device
*spi
,
684 struct spi_transfer
*xfer
)
686 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
693 reinit_completion(&sdd
->xfer_completion
);
695 /* Only BPW and Speed may change across transfers */
696 bpw
= xfer
->bits_per_word
;
697 speed
= xfer
->speed_hz
? : spi
->max_speed_hz
;
699 if (bpw
!= sdd
->cur_bpw
|| speed
!= sdd
->cur_speed
) {
701 sdd
->cur_speed
= speed
;
702 s3c64xx_spi_config(sdd
);
705 /* Polling method for xfers not bigger than FIFO capacity */
707 if (!is_polling(sdd
) &&
708 (sdd
->rx_dma
.ch
&& sdd
->tx_dma
.ch
&&
709 (xfer
->len
> ((FIFO_LVL_MASK(sdd
) >> 1) + 1))))
712 spin_lock_irqsave(&sdd
->lock
, flags
);
714 /* Pending only which is to be done */
715 sdd
->state
&= ~RXBUSY
;
716 sdd
->state
&= ~TXBUSY
;
718 enable_datapath(sdd
, spi
, xfer
, use_dma
);
720 /* Start the signals */
721 writel(0, sdd
->regs
+ S3C64XX_SPI_SLAVE_SEL
);
723 spin_unlock_irqrestore(&sdd
->lock
, flags
);
726 status
= wait_for_dma(sdd
, xfer
);
728 status
= wait_for_pio(sdd
, xfer
);
731 dev_err(&spi
->dev
, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
732 xfer
->rx_buf
? 1 : 0, xfer
->tx_buf
? 1 : 0,
733 (sdd
->state
& RXBUSY
) ? 'f' : 'p',
734 (sdd
->state
& TXBUSY
) ? 'f' : 'p',
738 if (xfer
->tx_buf
!= NULL
739 && (sdd
->state
& TXBUSY
))
740 dmaengine_terminate_all(sdd
->tx_dma
.ch
);
741 if (xfer
->rx_buf
!= NULL
742 && (sdd
->state
& RXBUSY
))
743 dmaengine_terminate_all(sdd
->rx_dma
.ch
);
752 static struct s3c64xx_spi_csinfo
*s3c64xx_get_slave_ctrldata(
753 struct spi_device
*spi
)
755 struct s3c64xx_spi_csinfo
*cs
;
756 struct device_node
*slave_np
, *data_np
= NULL
;
757 struct s3c64xx_spi_driver_data
*sdd
;
760 sdd
= spi_master_get_devdata(spi
->master
);
761 slave_np
= spi
->dev
.of_node
;
763 dev_err(&spi
->dev
, "device node not found\n");
764 return ERR_PTR(-EINVAL
);
767 data_np
= of_get_child_by_name(slave_np
, "controller-data");
769 dev_err(&spi
->dev
, "child node 'controller-data' not found\n");
770 return ERR_PTR(-EINVAL
);
773 cs
= kzalloc(sizeof(*cs
), GFP_KERNEL
);
775 of_node_put(data_np
);
776 return ERR_PTR(-ENOMEM
);
779 /* The CS line is asserted/deasserted by the gpio pin */
781 cs
->line
= of_get_named_gpio(data_np
, "cs-gpio", 0);
783 if (!gpio_is_valid(cs
->line
)) {
784 dev_err(&spi
->dev
, "chip select gpio is not specified or invalid\n");
786 of_node_put(data_np
);
787 return ERR_PTR(-EINVAL
);
790 of_property_read_u32(data_np
, "samsung,spi-feedback-delay", &fb_delay
);
791 cs
->fb_delay
= fb_delay
;
792 of_node_put(data_np
);
797 * Here we only check the validity of requested configuration
798 * and save the configuration in a local data-structure.
799 * The controller is actually configured only just before we
800 * get a message to transfer.
802 static int s3c64xx_spi_setup(struct spi_device
*spi
)
804 struct s3c64xx_spi_csinfo
*cs
= spi
->controller_data
;
805 struct s3c64xx_spi_driver_data
*sdd
;
806 struct s3c64xx_spi_info
*sci
;
809 sdd
= spi_master_get_devdata(spi
->master
);
810 if (!cs
&& spi
->dev
.of_node
) {
811 cs
= s3c64xx_get_slave_ctrldata(spi
);
812 spi
->controller_data
= cs
;
815 if (IS_ERR_OR_NULL(cs
)) {
816 dev_err(&spi
->dev
, "No CS for SPI(%d)\n", spi
->chip_select
);
820 if (!spi_get_ctldata(spi
)) {
821 /* Request gpio only if cs line is asserted by gpio pins */
823 err
= gpio_request_one(cs
->line
, GPIOF_OUT_INIT_HIGH
,
824 dev_name(&spi
->dev
));
827 "Failed to get /CS gpio [%d]: %d\n",
832 spi
->cs_gpio
= cs
->line
;
835 spi_set_ctldata(spi
, cs
);
838 sci
= sdd
->cntrlr_info
;
840 pm_runtime_get_sync(&sdd
->pdev
->dev
);
842 /* Check if we can provide the requested rate */
843 if (!sdd
->port_conf
->clk_from_cmu
) {
847 speed
= clk_get_rate(sdd
->src_clk
) / 2 / (0 + 1);
849 if (spi
->max_speed_hz
> speed
)
850 spi
->max_speed_hz
= speed
;
852 psr
= clk_get_rate(sdd
->src_clk
) / 2 / spi
->max_speed_hz
- 1;
853 psr
&= S3C64XX_SPI_PSR_MASK
;
854 if (psr
== S3C64XX_SPI_PSR_MASK
)
857 speed
= clk_get_rate(sdd
->src_clk
) / 2 / (psr
+ 1);
858 if (spi
->max_speed_hz
< speed
) {
859 if (psr
+1 < S3C64XX_SPI_PSR_MASK
) {
867 speed
= clk_get_rate(sdd
->src_clk
) / 2 / (psr
+ 1);
868 if (spi
->max_speed_hz
>= speed
) {
869 spi
->max_speed_hz
= speed
;
871 dev_err(&spi
->dev
, "Can't set %dHz transfer speed\n",
878 pm_runtime_put(&sdd
->pdev
->dev
);
879 writel(S3C64XX_SPI_SLAVE_SIG_INACT
, sdd
->regs
+ S3C64XX_SPI_SLAVE_SEL
);
883 pm_runtime_put(&sdd
->pdev
->dev
);
884 /* setup() returns with device de-selected */
885 writel(S3C64XX_SPI_SLAVE_SIG_INACT
, sdd
->regs
+ S3C64XX_SPI_SLAVE_SEL
);
888 spi_set_ctldata(spi
, NULL
);
891 if (spi
->dev
.of_node
)
897 static void s3c64xx_spi_cleanup(struct spi_device
*spi
)
899 struct s3c64xx_spi_csinfo
*cs
= spi_get_ctldata(spi
);
900 struct s3c64xx_spi_driver_data
*sdd
;
902 sdd
= spi_master_get_devdata(spi
->master
);
904 gpio_free(spi
->cs_gpio
);
905 if (spi
->dev
.of_node
)
908 spi_set_ctldata(spi
, NULL
);
911 static irqreturn_t
s3c64xx_spi_irq(int irq
, void *data
)
913 struct s3c64xx_spi_driver_data
*sdd
= data
;
914 struct spi_master
*spi
= sdd
->master
;
915 unsigned int val
, clr
= 0;
917 val
= readl(sdd
->regs
+ S3C64XX_SPI_STATUS
);
919 if (val
& S3C64XX_SPI_ST_RX_OVERRUN_ERR
) {
920 clr
= S3C64XX_SPI_PND_RX_OVERRUN_CLR
;
921 dev_err(&spi
->dev
, "RX overrun\n");
923 if (val
& S3C64XX_SPI_ST_RX_UNDERRUN_ERR
) {
924 clr
|= S3C64XX_SPI_PND_RX_UNDERRUN_CLR
;
925 dev_err(&spi
->dev
, "RX underrun\n");
927 if (val
& S3C64XX_SPI_ST_TX_OVERRUN_ERR
) {
928 clr
|= S3C64XX_SPI_PND_TX_OVERRUN_CLR
;
929 dev_err(&spi
->dev
, "TX overrun\n");
931 if (val
& S3C64XX_SPI_ST_TX_UNDERRUN_ERR
) {
932 clr
|= S3C64XX_SPI_PND_TX_UNDERRUN_CLR
;
933 dev_err(&spi
->dev
, "TX underrun\n");
936 /* Clear the pending irq by setting and then clearing it */
937 writel(clr
, sdd
->regs
+ S3C64XX_SPI_PENDING_CLR
);
938 writel(0, sdd
->regs
+ S3C64XX_SPI_PENDING_CLR
);
943 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data
*sdd
, int channel
)
945 struct s3c64xx_spi_info
*sci
= sdd
->cntrlr_info
;
946 void __iomem
*regs
= sdd
->regs
;
951 writel(S3C64XX_SPI_SLAVE_SIG_INACT
, sdd
->regs
+ S3C64XX_SPI_SLAVE_SEL
);
953 /* Disable Interrupts - we use Polling if not DMA mode */
954 writel(0, regs
+ S3C64XX_SPI_INT_EN
);
956 if (!sdd
->port_conf
->clk_from_cmu
)
957 writel(sci
->src_clk_nr
<< S3C64XX_SPI_CLKSEL_SRCSHFT
,
958 regs
+ S3C64XX_SPI_CLK_CFG
);
959 writel(0, regs
+ S3C64XX_SPI_MODE_CFG
);
960 writel(0, regs
+ S3C64XX_SPI_PACKET_CNT
);
962 /* Clear any irq pending bits, should set and clear the bits */
963 val
= S3C64XX_SPI_PND_RX_OVERRUN_CLR
|
964 S3C64XX_SPI_PND_RX_UNDERRUN_CLR
|
965 S3C64XX_SPI_PND_TX_OVERRUN_CLR
|
966 S3C64XX_SPI_PND_TX_UNDERRUN_CLR
;
967 writel(val
, regs
+ S3C64XX_SPI_PENDING_CLR
);
968 writel(0, regs
+ S3C64XX_SPI_PENDING_CLR
);
970 writel(0, regs
+ S3C64XX_SPI_SWAP_CFG
);
972 val
= readl(regs
+ S3C64XX_SPI_MODE_CFG
);
973 val
&= ~S3C64XX_SPI_MODE_4BURST
;
974 val
&= ~(S3C64XX_SPI_MAX_TRAILCNT
<< S3C64XX_SPI_TRAILCNT_OFF
);
975 val
|= (S3C64XX_SPI_TRAILCNT
<< S3C64XX_SPI_TRAILCNT_OFF
);
976 writel(val
, regs
+ S3C64XX_SPI_MODE_CFG
);
982 static struct s3c64xx_spi_info
*s3c64xx_spi_parse_dt(struct device
*dev
)
984 struct s3c64xx_spi_info
*sci
;
987 sci
= devm_kzalloc(dev
, sizeof(*sci
), GFP_KERNEL
);
989 return ERR_PTR(-ENOMEM
);
991 if (of_property_read_u32(dev
->of_node
, "samsung,spi-src-clk", &temp
)) {
992 dev_warn(dev
, "spi bus clock parent not specified, using clock at index 0 as parent\n");
995 sci
->src_clk_nr
= temp
;
998 if (of_property_read_u32(dev
->of_node
, "num-cs", &temp
)) {
999 dev_warn(dev
, "number of chip select lines not specified, assuming 1 chip select line\n");
1008 static struct s3c64xx_spi_info
*s3c64xx_spi_parse_dt(struct device
*dev
)
1010 return dev_get_platdata(dev
);
1014 static const struct of_device_id s3c64xx_spi_dt_match
[];
1016 static inline struct s3c64xx_spi_port_config
*s3c64xx_spi_get_port_config(
1017 struct platform_device
*pdev
)
1020 if (pdev
->dev
.of_node
) {
1021 const struct of_device_id
*match
;
1022 match
= of_match_node(s3c64xx_spi_dt_match
, pdev
->dev
.of_node
);
1023 return (struct s3c64xx_spi_port_config
*)match
->data
;
1026 return (struct s3c64xx_spi_port_config
*)
1027 platform_get_device_id(pdev
)->driver_data
;
1030 static int s3c64xx_spi_probe(struct platform_device
*pdev
)
1032 struct resource
*mem_res
;
1033 struct resource
*res
;
1034 struct s3c64xx_spi_driver_data
*sdd
;
1035 struct s3c64xx_spi_info
*sci
= dev_get_platdata(&pdev
->dev
);
1036 struct spi_master
*master
;
1040 if (!sci
&& pdev
->dev
.of_node
) {
1041 sci
= s3c64xx_spi_parse_dt(&pdev
->dev
);
1043 return PTR_ERR(sci
);
1047 dev_err(&pdev
->dev
, "platform_data missing!\n");
1051 mem_res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1052 if (mem_res
== NULL
) {
1053 dev_err(&pdev
->dev
, "Unable to get SPI MEM resource\n");
1057 irq
= platform_get_irq(pdev
, 0);
1059 dev_warn(&pdev
->dev
, "Failed to get IRQ: %d\n", irq
);
1063 master
= spi_alloc_master(&pdev
->dev
,
1064 sizeof(struct s3c64xx_spi_driver_data
));
1065 if (master
== NULL
) {
1066 dev_err(&pdev
->dev
, "Unable to allocate SPI Master\n");
1070 platform_set_drvdata(pdev
, master
);
1072 sdd
= spi_master_get_devdata(master
);
1073 sdd
->port_conf
= s3c64xx_spi_get_port_config(pdev
);
1074 sdd
->master
= master
;
1075 sdd
->cntrlr_info
= sci
;
1077 sdd
->sfr_start
= mem_res
->start
;
1078 sdd
->cs_gpio
= true;
1079 if (pdev
->dev
.of_node
) {
1080 if (!of_find_property(pdev
->dev
.of_node
, "cs-gpio", NULL
))
1081 sdd
->cs_gpio
= false;
1083 ret
= of_alias_get_id(pdev
->dev
.of_node
, "spi");
1085 dev_err(&pdev
->dev
, "failed to get alias id, errno %d\n",
1091 sdd
->port_id
= pdev
->id
;
1096 if (!sdd
->pdev
->dev
.of_node
) {
1097 res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
1099 dev_warn(&pdev
->dev
, "Unable to get SPI tx dma resource. Switching to poll mode\n");
1100 sdd
->port_conf
->quirks
= S3C64XX_SPI_QUIRK_POLL
;
1102 sdd
->tx_dma
.dmach
= res
->start
;
1104 res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 1);
1106 dev_warn(&pdev
->dev
, "Unable to get SPI rx dma resource. Switching to poll mode\n");
1107 sdd
->port_conf
->quirks
= S3C64XX_SPI_QUIRK_POLL
;
1109 sdd
->rx_dma
.dmach
= res
->start
;
1112 sdd
->tx_dma
.direction
= DMA_MEM_TO_DEV
;
1113 sdd
->rx_dma
.direction
= DMA_DEV_TO_MEM
;
1115 master
->dev
.of_node
= pdev
->dev
.of_node
;
1116 master
->bus_num
= sdd
->port_id
;
1117 master
->setup
= s3c64xx_spi_setup
;
1118 master
->cleanup
= s3c64xx_spi_cleanup
;
1119 master
->prepare_transfer_hardware
= s3c64xx_spi_prepare_transfer
;
1120 master
->prepare_message
= s3c64xx_spi_prepare_message
;
1121 master
->transfer_one
= s3c64xx_spi_transfer_one
;
1122 master
->unprepare_transfer_hardware
= s3c64xx_spi_unprepare_transfer
;
1123 master
->num_chipselect
= sci
->num_cs
;
1124 master
->dma_alignment
= 8;
1125 master
->bits_per_word_mask
= SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1127 /* the spi->mode bits understood by this driver: */
1128 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1129 master
->auto_runtime_pm
= true;
1130 if (!is_polling(sdd
))
1131 master
->can_dma
= s3c64xx_spi_can_dma
;
1133 sdd
->regs
= devm_ioremap_resource(&pdev
->dev
, mem_res
);
1134 if (IS_ERR(sdd
->regs
)) {
1135 ret
= PTR_ERR(sdd
->regs
);
1139 if (sci
->cfg_gpio
&& sci
->cfg_gpio()) {
1140 dev_err(&pdev
->dev
, "Unable to config gpio\n");
1146 sdd
->clk
= devm_clk_get(&pdev
->dev
, "spi");
1147 if (IS_ERR(sdd
->clk
)) {
1148 dev_err(&pdev
->dev
, "Unable to acquire clock 'spi'\n");
1149 ret
= PTR_ERR(sdd
->clk
);
1153 if (clk_prepare_enable(sdd
->clk
)) {
1154 dev_err(&pdev
->dev
, "Couldn't enable clock 'spi'\n");
1159 sprintf(clk_name
, "spi_busclk%d", sci
->src_clk_nr
);
1160 sdd
->src_clk
= devm_clk_get(&pdev
->dev
, clk_name
);
1161 if (IS_ERR(sdd
->src_clk
)) {
1163 "Unable to acquire clock '%s'\n", clk_name
);
1164 ret
= PTR_ERR(sdd
->src_clk
);
1168 if (clk_prepare_enable(sdd
->src_clk
)) {
1169 dev_err(&pdev
->dev
, "Couldn't enable clock '%s'\n", clk_name
);
1174 /* Setup Deufult Mode */
1175 s3c64xx_spi_hwinit(sdd
, sdd
->port_id
);
1177 spin_lock_init(&sdd
->lock
);
1178 init_completion(&sdd
->xfer_completion
);
1180 ret
= devm_request_irq(&pdev
->dev
, irq
, s3c64xx_spi_irq
, 0,
1181 "spi-s3c64xx", sdd
);
1183 dev_err(&pdev
->dev
, "Failed to request IRQ %d: %d\n",
1188 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN
| S3C64XX_SPI_INT_RX_UNDERRUN_EN
|
1189 S3C64XX_SPI_INT_TX_OVERRUN_EN
| S3C64XX_SPI_INT_TX_UNDERRUN_EN
,
1190 sdd
->regs
+ S3C64XX_SPI_INT_EN
);
1192 pm_runtime_set_active(&pdev
->dev
);
1193 pm_runtime_enable(&pdev
->dev
);
1195 ret
= devm_spi_register_master(&pdev
->dev
, master
);
1197 dev_err(&pdev
->dev
, "cannot register SPI master: %d\n", ret
);
1201 dev_dbg(&pdev
->dev
, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1202 sdd
->port_id
, master
->num_chipselect
);
1203 dev_dbg(&pdev
->dev
, "\tIOmem=[%pR]\tDMA=[Rx-%d, Tx-%d]\n",
1205 sdd
->rx_dma
.dmach
, sdd
->tx_dma
.dmach
);
1210 clk_disable_unprepare(sdd
->src_clk
);
1212 clk_disable_unprepare(sdd
->clk
);
1214 spi_master_put(master
);
1219 static int s3c64xx_spi_remove(struct platform_device
*pdev
)
1221 struct spi_master
*master
= spi_master_get(platform_get_drvdata(pdev
));
1222 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
1224 pm_runtime_disable(&pdev
->dev
);
1226 writel(0, sdd
->regs
+ S3C64XX_SPI_INT_EN
);
1228 clk_disable_unprepare(sdd
->src_clk
);
1230 clk_disable_unprepare(sdd
->clk
);
1235 #ifdef CONFIG_PM_SLEEP
1236 static int s3c64xx_spi_suspend(struct device
*dev
)
1238 struct spi_master
*master
= dev_get_drvdata(dev
);
1239 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
1241 int ret
= spi_master_suspend(master
);
1245 if (!pm_runtime_suspended(dev
)) {
1246 clk_disable_unprepare(sdd
->clk
);
1247 clk_disable_unprepare(sdd
->src_clk
);
1250 sdd
->cur_speed
= 0; /* Output Clock is stopped */
1255 static int s3c64xx_spi_resume(struct device
*dev
)
1257 struct spi_master
*master
= dev_get_drvdata(dev
);
1258 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
1259 struct s3c64xx_spi_info
*sci
= sdd
->cntrlr_info
;
1264 if (!pm_runtime_suspended(dev
)) {
1265 clk_prepare_enable(sdd
->src_clk
);
1266 clk_prepare_enable(sdd
->clk
);
1269 s3c64xx_spi_hwinit(sdd
, sdd
->port_id
);
1271 return spi_master_resume(master
);
1273 #endif /* CONFIG_PM_SLEEP */
1275 #ifdef CONFIG_PM_RUNTIME
1276 static int s3c64xx_spi_runtime_suspend(struct device
*dev
)
1278 struct spi_master
*master
= dev_get_drvdata(dev
);
1279 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
1281 clk_disable_unprepare(sdd
->clk
);
1282 clk_disable_unprepare(sdd
->src_clk
);
1287 static int s3c64xx_spi_runtime_resume(struct device
*dev
)
1289 struct spi_master
*master
= dev_get_drvdata(dev
);
1290 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
1293 ret
= clk_prepare_enable(sdd
->src_clk
);
1297 ret
= clk_prepare_enable(sdd
->clk
);
1299 clk_disable_unprepare(sdd
->src_clk
);
1305 #endif /* CONFIG_PM_RUNTIME */
1307 static const struct dev_pm_ops s3c64xx_spi_pm
= {
1308 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend
, s3c64xx_spi_resume
)
1309 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend
,
1310 s3c64xx_spi_runtime_resume
, NULL
)
1313 static struct s3c64xx_spi_port_config s3c2443_spi_port_config
= {
1314 .fifo_lvl_mask
= { 0x7f },
1315 .rx_lvl_offset
= 13,
1320 static struct s3c64xx_spi_port_config s3c6410_spi_port_config
= {
1321 .fifo_lvl_mask
= { 0x7f, 0x7F },
1322 .rx_lvl_offset
= 13,
1326 static struct s3c64xx_spi_port_config s5p64x0_spi_port_config
= {
1327 .fifo_lvl_mask
= { 0x1ff, 0x7F },
1328 .rx_lvl_offset
= 15,
1332 static struct s3c64xx_spi_port_config s5pc100_spi_port_config
= {
1333 .fifo_lvl_mask
= { 0x7f, 0x7F },
1334 .rx_lvl_offset
= 13,
1339 static struct s3c64xx_spi_port_config s5pv210_spi_port_config
= {
1340 .fifo_lvl_mask
= { 0x1ff, 0x7F },
1341 .rx_lvl_offset
= 15,
1346 static struct s3c64xx_spi_port_config exynos4_spi_port_config
= {
1347 .fifo_lvl_mask
= { 0x1ff, 0x7F, 0x7F },
1348 .rx_lvl_offset
= 15,
1351 .clk_from_cmu
= true,
1354 static struct s3c64xx_spi_port_config exynos5440_spi_port_config
= {
1355 .fifo_lvl_mask
= { 0x1ff },
1356 .rx_lvl_offset
= 15,
1359 .clk_from_cmu
= true,
1360 .quirks
= S3C64XX_SPI_QUIRK_POLL
,
1363 static struct platform_device_id s3c64xx_spi_driver_ids
[] = {
1365 .name
= "s3c2443-spi",
1366 .driver_data
= (kernel_ulong_t
)&s3c2443_spi_port_config
,
1368 .name
= "s3c6410-spi",
1369 .driver_data
= (kernel_ulong_t
)&s3c6410_spi_port_config
,
1371 .name
= "s5p64x0-spi",
1372 .driver_data
= (kernel_ulong_t
)&s5p64x0_spi_port_config
,
1374 .name
= "s5pc100-spi",
1375 .driver_data
= (kernel_ulong_t
)&s5pc100_spi_port_config
,
1377 .name
= "s5pv210-spi",
1378 .driver_data
= (kernel_ulong_t
)&s5pv210_spi_port_config
,
1380 .name
= "exynos4210-spi",
1381 .driver_data
= (kernel_ulong_t
)&exynos4_spi_port_config
,
1386 static const struct of_device_id s3c64xx_spi_dt_match
[] = {
1387 { .compatible
= "samsung,s3c2443-spi",
1388 .data
= (void *)&s3c2443_spi_port_config
,
1390 { .compatible
= "samsung,s3c6410-spi",
1391 .data
= (void *)&s3c6410_spi_port_config
,
1393 { .compatible
= "samsung,s5pc100-spi",
1394 .data
= (void *)&s5pc100_spi_port_config
,
1396 { .compatible
= "samsung,s5pv210-spi",
1397 .data
= (void *)&s5pv210_spi_port_config
,
1399 { .compatible
= "samsung,exynos4210-spi",
1400 .data
= (void *)&exynos4_spi_port_config
,
1402 { .compatible
= "samsung,exynos5440-spi",
1403 .data
= (void *)&exynos5440_spi_port_config
,
1407 MODULE_DEVICE_TABLE(of
, s3c64xx_spi_dt_match
);
1409 static struct platform_driver s3c64xx_spi_driver
= {
1411 .name
= "s3c64xx-spi",
1412 .owner
= THIS_MODULE
,
1413 .pm
= &s3c64xx_spi_pm
,
1414 .of_match_table
= of_match_ptr(s3c64xx_spi_dt_match
),
1416 .probe
= s3c64xx_spi_probe
,
1417 .remove
= s3c64xx_spi_remove
,
1418 .id_table
= s3c64xx_spi_driver_ids
,
1420 MODULE_ALIAS("platform:s3c64xx-spi");
1422 module_platform_driver(s3c64xx_spi_driver
);
1424 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1425 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1426 MODULE_LICENSE("GPL");