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spi/s3c64xx: Add support DMA engine API
[deliverable/linux.git] / drivers / spi / spi-s3c64xx.c
1 /*
2 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/workqueue.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/spi/spi.h>
28
29 #include <mach/dma.h>
30 #include <plat/s3c64xx-spi.h>
31
32 /* Registers and bit-fields */
33
34 #define S3C64XX_SPI_CH_CFG 0x00
35 #define S3C64XX_SPI_CLK_CFG 0x04
36 #define S3C64XX_SPI_MODE_CFG 0x08
37 #define S3C64XX_SPI_SLAVE_SEL 0x0C
38 #define S3C64XX_SPI_INT_EN 0x10
39 #define S3C64XX_SPI_STATUS 0x14
40 #define S3C64XX_SPI_TX_DATA 0x18
41 #define S3C64XX_SPI_RX_DATA 0x1C
42 #define S3C64XX_SPI_PACKET_CNT 0x20
43 #define S3C64XX_SPI_PENDING_CLR 0x24
44 #define S3C64XX_SPI_SWAP_CFG 0x28
45 #define S3C64XX_SPI_FB_CLK 0x2C
46
47 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
48 #define S3C64XX_SPI_CH_SW_RST (1<<5)
49 #define S3C64XX_SPI_CH_SLAVE (1<<4)
50 #define S3C64XX_SPI_CPOL_L (1<<3)
51 #define S3C64XX_SPI_CPHA_B (1<<2)
52 #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
53 #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
54
55 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
56 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
57 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
58 #define S3C64XX_SPI_PSR_MASK 0xff
59
60 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
61 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
62 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
63 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
64 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
65 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
66 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
67 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
68 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
69 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
70 #define S3C64XX_SPI_MODE_4BURST (1<<0)
71
72 #define S3C64XX_SPI_SLAVE_AUTO (1<<1)
73 #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
74
75 #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL)
76
77 #define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \
78 (c)->regs + S3C64XX_SPI_SLAVE_SEL)
79
80 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
81 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
82 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
83 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
84 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
85 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
86 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
87
88 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
89 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
90 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
91 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
92 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
93 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
94
95 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
96
97 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
98 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
99 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
100 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
101 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
102
103 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
104 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
105 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
106 #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
107 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
108 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
109 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
110 #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
111
112 #define S3C64XX_SPI_FBCLK_MSK (3<<0)
113
114 #define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \
115 (((i)->fifo_lvl_mask + 1))) \
116 ? 1 : 0)
117
118 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
119 #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
120 #define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
121
122 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
123 #define S3C64XX_SPI_TRAILCNT_OFF 19
124
125 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
126
127 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
128
129 #define SUSPND (1<<0)
130 #define SPIBUSY (1<<1)
131 #define RXBUSY (1<<2)
132 #define TXBUSY (1<<3)
133
134 /**
135 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
136 * @clk: Pointer to the spi clock.
137 * @src_clk: Pointer to the clock used to generate SPI signals.
138 * @master: Pointer to the SPI Protocol master.
139 * @workqueue: Work queue for the SPI xfer requests.
140 * @cntrlr_info: Platform specific data for the controller this driver manages.
141 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
142 * @work: Work
143 * @queue: To log SPI xfer requests.
144 * @lock: Controller specific lock.
145 * @state: Set of FLAGS to indicate status.
146 * @rx_dmach: Controller's DMA channel for Rx.
147 * @tx_dmach: Controller's DMA channel for Tx.
148 * @sfr_start: BUS address of SPI controller regs.
149 * @regs: Pointer to ioremap'ed controller registers.
150 * @xfer_completion: To indicate completion of xfer task.
151 * @cur_mode: Stores the active configuration of the controller.
152 * @cur_bpw: Stores the active bits per word settings.
153 * @cur_speed: Stores the active xfer clock speed.
154 */
155 struct s3c64xx_spi_driver_data {
156 void __iomem *regs;
157 struct clk *clk;
158 struct clk *src_clk;
159 struct platform_device *pdev;
160 struct spi_master *master;
161 struct workqueue_struct *workqueue;
162 struct s3c64xx_spi_info *cntrlr_info;
163 struct spi_device *tgl_spi;
164 struct work_struct work;
165 struct list_head queue;
166 spinlock_t lock;
167 enum dma_ch rx_dmach;
168 enum dma_ch tx_dmach;
169 unsigned long sfr_start;
170 struct completion xfer_completion;
171 unsigned state;
172 unsigned cur_mode, cur_bpw;
173 unsigned cur_speed;
174 unsigned rx_ch;
175 unsigned tx_ch;
176 struct samsung_dma_ops *ops;
177 };
178
179 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
180 .name = "samsung-spi-dma",
181 };
182
183 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
184 {
185 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
186 void __iomem *regs = sdd->regs;
187 unsigned long loops;
188 u32 val;
189
190 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
191
192 val = readl(regs + S3C64XX_SPI_CH_CFG);
193 val |= S3C64XX_SPI_CH_SW_RST;
194 val &= ~S3C64XX_SPI_CH_HS_EN;
195 writel(val, regs + S3C64XX_SPI_CH_CFG);
196
197 /* Flush TxFIFO*/
198 loops = msecs_to_loops(1);
199 do {
200 val = readl(regs + S3C64XX_SPI_STATUS);
201 } while (TX_FIFO_LVL(val, sci) && loops--);
202
203 if (loops == 0)
204 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
205
206 /* Flush RxFIFO*/
207 loops = msecs_to_loops(1);
208 do {
209 val = readl(regs + S3C64XX_SPI_STATUS);
210 if (RX_FIFO_LVL(val, sci))
211 readl(regs + S3C64XX_SPI_RX_DATA);
212 else
213 break;
214 } while (loops--);
215
216 if (loops == 0)
217 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
218
219 val = readl(regs + S3C64XX_SPI_CH_CFG);
220 val &= ~S3C64XX_SPI_CH_SW_RST;
221 writel(val, regs + S3C64XX_SPI_CH_CFG);
222
223 val = readl(regs + S3C64XX_SPI_MODE_CFG);
224 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
225 writel(val, regs + S3C64XX_SPI_MODE_CFG);
226
227 val = readl(regs + S3C64XX_SPI_CH_CFG);
228 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
229 writel(val, regs + S3C64XX_SPI_CH_CFG);
230 }
231
232 static void s3c64xx_spi_dma_rxcb(void *data)
233 {
234 struct s3c64xx_spi_driver_data *sdd
235 = (struct s3c64xx_spi_driver_data *)data;
236 unsigned long flags;
237
238 spin_lock_irqsave(&sdd->lock, flags);
239
240 sdd->state &= ~RXBUSY;
241 /* If the other done */
242 if (!(sdd->state & TXBUSY))
243 complete(&sdd->xfer_completion);
244
245 spin_unlock_irqrestore(&sdd->lock, flags);
246 }
247
248 static void s3c64xx_spi_dma_txcb(void *data)
249 {
250 struct s3c64xx_spi_driver_data *sdd
251 = (struct s3c64xx_spi_driver_data *)data;
252 unsigned long flags;
253
254 spin_lock_irqsave(&sdd->lock, flags);
255
256 sdd->state &= ~TXBUSY;
257 /* If the other done */
258 if (!(sdd->state & RXBUSY))
259 complete(&sdd->xfer_completion);
260
261 spin_unlock_irqrestore(&sdd->lock, flags);
262 }
263
264 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
265 struct spi_device *spi,
266 struct spi_transfer *xfer, int dma_mode)
267 {
268 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
269 void __iomem *regs = sdd->regs;
270 u32 modecfg, chcfg;
271 struct samsung_dma_prep_info info;
272
273 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
274 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
275
276 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
277 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
278
279 if (dma_mode) {
280 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
281 } else {
282 /* Always shift in data in FIFO, even if xfer is Tx only,
283 * this helps setting PCKT_CNT value for generating clocks
284 * as exactly needed.
285 */
286 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
287 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
288 | S3C64XX_SPI_PACKET_CNT_EN,
289 regs + S3C64XX_SPI_PACKET_CNT);
290 }
291
292 if (xfer->tx_buf != NULL) {
293 sdd->state |= TXBUSY;
294 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
295 if (dma_mode) {
296 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
297 info.cap = DMA_SLAVE;
298 info.direction = DMA_TO_DEVICE;
299 info.buf = xfer->tx_dma;
300 info.len = xfer->len;
301 info.fp = s3c64xx_spi_dma_txcb;
302 info.fp_param = sdd;
303 sdd->ops->prepare(sdd->tx_ch, &info);
304 sdd->ops->trigger(sdd->tx_ch);
305 } else {
306 switch (sdd->cur_bpw) {
307 case 32:
308 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
309 xfer->tx_buf, xfer->len / 4);
310 break;
311 case 16:
312 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
313 xfer->tx_buf, xfer->len / 2);
314 break;
315 default:
316 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
317 xfer->tx_buf, xfer->len);
318 break;
319 }
320 }
321 }
322
323 if (xfer->rx_buf != NULL) {
324 sdd->state |= RXBUSY;
325
326 if (sci->high_speed && sdd->cur_speed >= 30000000UL
327 && !(sdd->cur_mode & SPI_CPHA))
328 chcfg |= S3C64XX_SPI_CH_HS_EN;
329
330 if (dma_mode) {
331 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
332 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
333 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
334 | S3C64XX_SPI_PACKET_CNT_EN,
335 regs + S3C64XX_SPI_PACKET_CNT);
336 info.cap = DMA_SLAVE;
337 info.direction = DMA_FROM_DEVICE;
338 info.buf = xfer->rx_dma;
339 info.len = xfer->len;
340 info.fp = s3c64xx_spi_dma_rxcb;
341 info.fp_param = sdd;
342 sdd->ops->prepare(sdd->rx_ch, &info);
343 sdd->ops->trigger(sdd->rx_ch);
344 }
345 }
346
347 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
348 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
349 }
350
351 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
352 struct spi_device *spi)
353 {
354 struct s3c64xx_spi_csinfo *cs;
355
356 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
357 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
358 /* Deselect the last toggled device */
359 cs = sdd->tgl_spi->controller_data;
360 cs->set_level(cs->line,
361 spi->mode & SPI_CS_HIGH ? 0 : 1);
362 }
363 sdd->tgl_spi = NULL;
364 }
365
366 cs = spi->controller_data;
367 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
368 }
369
370 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
371 struct spi_transfer *xfer, int dma_mode)
372 {
373 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
374 void __iomem *regs = sdd->regs;
375 unsigned long val;
376 int ms;
377
378 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
379 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
380 ms += 10; /* some tolerance */
381
382 if (dma_mode) {
383 val = msecs_to_jiffies(ms) + 10;
384 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
385 } else {
386 u32 status;
387 val = msecs_to_loops(ms);
388 do {
389 status = readl(regs + S3C64XX_SPI_STATUS);
390 } while (RX_FIFO_LVL(status, sci) < xfer->len && --val);
391 }
392
393 if (!val)
394 return -EIO;
395
396 if (dma_mode) {
397 u32 status;
398
399 /*
400 * DmaTx returns after simply writing data in the FIFO,
401 * w/o waiting for real transmission on the bus to finish.
402 * DmaRx returns only after Dma read data from FIFO which
403 * needs bus transmission to finish, so we don't worry if
404 * Xfer involved Rx(with or without Tx).
405 */
406 if (xfer->rx_buf == NULL) {
407 val = msecs_to_loops(10);
408 status = readl(regs + S3C64XX_SPI_STATUS);
409 while ((TX_FIFO_LVL(status, sci)
410 || !S3C64XX_SPI_ST_TX_DONE(status, sci))
411 && --val) {
412 cpu_relax();
413 status = readl(regs + S3C64XX_SPI_STATUS);
414 }
415
416 if (!val)
417 return -EIO;
418 }
419 } else {
420 /* If it was only Tx */
421 if (xfer->rx_buf == NULL) {
422 sdd->state &= ~TXBUSY;
423 return 0;
424 }
425
426 switch (sdd->cur_bpw) {
427 case 32:
428 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
429 xfer->rx_buf, xfer->len / 4);
430 break;
431 case 16:
432 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
433 xfer->rx_buf, xfer->len / 2);
434 break;
435 default:
436 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
437 xfer->rx_buf, xfer->len);
438 break;
439 }
440 sdd->state &= ~RXBUSY;
441 }
442
443 return 0;
444 }
445
446 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
447 struct spi_device *spi)
448 {
449 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
450
451 if (sdd->tgl_spi == spi)
452 sdd->tgl_spi = NULL;
453
454 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
455 }
456
457 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
458 {
459 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
460 void __iomem *regs = sdd->regs;
461 u32 val;
462
463 /* Disable Clock */
464 if (sci->clk_from_cmu) {
465 clk_disable(sdd->src_clk);
466 } else {
467 val = readl(regs + S3C64XX_SPI_CLK_CFG);
468 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
469 writel(val, regs + S3C64XX_SPI_CLK_CFG);
470 }
471
472 /* Set Polarity and Phase */
473 val = readl(regs + S3C64XX_SPI_CH_CFG);
474 val &= ~(S3C64XX_SPI_CH_SLAVE |
475 S3C64XX_SPI_CPOL_L |
476 S3C64XX_SPI_CPHA_B);
477
478 if (sdd->cur_mode & SPI_CPOL)
479 val |= S3C64XX_SPI_CPOL_L;
480
481 if (sdd->cur_mode & SPI_CPHA)
482 val |= S3C64XX_SPI_CPHA_B;
483
484 writel(val, regs + S3C64XX_SPI_CH_CFG);
485
486 /* Set Channel & DMA Mode */
487 val = readl(regs + S3C64XX_SPI_MODE_CFG);
488 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
489 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
490
491 switch (sdd->cur_bpw) {
492 case 32:
493 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
494 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
495 break;
496 case 16:
497 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
498 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
499 break;
500 default:
501 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
502 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
503 break;
504 }
505
506 writel(val, regs + S3C64XX_SPI_MODE_CFG);
507
508 if (sci->clk_from_cmu) {
509 /* Configure Clock */
510 /* There is half-multiplier before the SPI */
511 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
512 /* Enable Clock */
513 clk_enable(sdd->src_clk);
514 } else {
515 /* Configure Clock */
516 val = readl(regs + S3C64XX_SPI_CLK_CFG);
517 val &= ~S3C64XX_SPI_PSR_MASK;
518 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
519 & S3C64XX_SPI_PSR_MASK);
520 writel(val, regs + S3C64XX_SPI_CLK_CFG);
521
522 /* Enable Clock */
523 val = readl(regs + S3C64XX_SPI_CLK_CFG);
524 val |= S3C64XX_SPI_ENCLK_ENABLE;
525 writel(val, regs + S3C64XX_SPI_CLK_CFG);
526 }
527 }
528
529 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
530
531 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
532 struct spi_message *msg)
533 {
534 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
535 struct device *dev = &sdd->pdev->dev;
536 struct spi_transfer *xfer;
537
538 if (msg->is_dma_mapped)
539 return 0;
540
541 /* First mark all xfer unmapped */
542 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
543 xfer->rx_dma = XFER_DMAADDR_INVALID;
544 xfer->tx_dma = XFER_DMAADDR_INVALID;
545 }
546
547 /* Map until end or first fail */
548 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
549
550 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
551 continue;
552
553 if (xfer->tx_buf != NULL) {
554 xfer->tx_dma = dma_map_single(dev,
555 (void *)xfer->tx_buf, xfer->len,
556 DMA_TO_DEVICE);
557 if (dma_mapping_error(dev, xfer->tx_dma)) {
558 dev_err(dev, "dma_map_single Tx failed\n");
559 xfer->tx_dma = XFER_DMAADDR_INVALID;
560 return -ENOMEM;
561 }
562 }
563
564 if (xfer->rx_buf != NULL) {
565 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
566 xfer->len, DMA_FROM_DEVICE);
567 if (dma_mapping_error(dev, xfer->rx_dma)) {
568 dev_err(dev, "dma_map_single Rx failed\n");
569 dma_unmap_single(dev, xfer->tx_dma,
570 xfer->len, DMA_TO_DEVICE);
571 xfer->tx_dma = XFER_DMAADDR_INVALID;
572 xfer->rx_dma = XFER_DMAADDR_INVALID;
573 return -ENOMEM;
574 }
575 }
576 }
577
578 return 0;
579 }
580
581 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
582 struct spi_message *msg)
583 {
584 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
585 struct device *dev = &sdd->pdev->dev;
586 struct spi_transfer *xfer;
587
588 if (msg->is_dma_mapped)
589 return;
590
591 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
592
593 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
594 continue;
595
596 if (xfer->rx_buf != NULL
597 && xfer->rx_dma != XFER_DMAADDR_INVALID)
598 dma_unmap_single(dev, xfer->rx_dma,
599 xfer->len, DMA_FROM_DEVICE);
600
601 if (xfer->tx_buf != NULL
602 && xfer->tx_dma != XFER_DMAADDR_INVALID)
603 dma_unmap_single(dev, xfer->tx_dma,
604 xfer->len, DMA_TO_DEVICE);
605 }
606 }
607
608 static void handle_msg(struct s3c64xx_spi_driver_data *sdd,
609 struct spi_message *msg)
610 {
611 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
612 struct spi_device *spi = msg->spi;
613 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
614 struct spi_transfer *xfer;
615 int status = 0, cs_toggle = 0;
616 u32 speed;
617 u8 bpw;
618
619 /* If Master's(controller) state differs from that needed by Slave */
620 if (sdd->cur_speed != spi->max_speed_hz
621 || sdd->cur_mode != spi->mode
622 || sdd->cur_bpw != spi->bits_per_word) {
623 sdd->cur_bpw = spi->bits_per_word;
624 sdd->cur_speed = spi->max_speed_hz;
625 sdd->cur_mode = spi->mode;
626 s3c64xx_spi_config(sdd);
627 }
628
629 /* Map all the transfers if needed */
630 if (s3c64xx_spi_map_mssg(sdd, msg)) {
631 dev_err(&spi->dev,
632 "Xfer: Unable to map message buffers!\n");
633 status = -ENOMEM;
634 goto out;
635 }
636
637 /* Configure feedback delay */
638 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
639
640 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
641
642 unsigned long flags;
643 int use_dma;
644
645 INIT_COMPLETION(sdd->xfer_completion);
646
647 /* Only BPW and Speed may change across transfers */
648 bpw = xfer->bits_per_word ? : spi->bits_per_word;
649 speed = xfer->speed_hz ? : spi->max_speed_hz;
650
651 if (xfer->len % (bpw / 8)) {
652 dev_err(&spi->dev,
653 "Xfer length(%u) not a multiple of word size(%u)\n",
654 xfer->len, bpw / 8);
655 status = -EIO;
656 goto out;
657 }
658
659 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
660 sdd->cur_bpw = bpw;
661 sdd->cur_speed = speed;
662 s3c64xx_spi_config(sdd);
663 }
664
665 /* Polling method for xfers not bigger than FIFO capacity */
666 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
667 use_dma = 0;
668 else
669 use_dma = 1;
670
671 spin_lock_irqsave(&sdd->lock, flags);
672
673 /* Pending only which is to be done */
674 sdd->state &= ~RXBUSY;
675 sdd->state &= ~TXBUSY;
676
677 enable_datapath(sdd, spi, xfer, use_dma);
678
679 /* Slave Select */
680 enable_cs(sdd, spi);
681
682 /* Start the signals */
683 S3C64XX_SPI_ACT(sdd);
684
685 spin_unlock_irqrestore(&sdd->lock, flags);
686
687 status = wait_for_xfer(sdd, xfer, use_dma);
688
689 /* Quiese the signals */
690 S3C64XX_SPI_DEACT(sdd);
691
692 if (status) {
693 dev_err(&spi->dev, "I/O Error: "
694 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
695 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
696 (sdd->state & RXBUSY) ? 'f' : 'p',
697 (sdd->state & TXBUSY) ? 'f' : 'p',
698 xfer->len);
699
700 if (use_dma) {
701 if (xfer->tx_buf != NULL
702 && (sdd->state & TXBUSY))
703 sdd->ops->stop(sdd->tx_ch);
704 if (xfer->rx_buf != NULL
705 && (sdd->state & RXBUSY))
706 sdd->ops->stop(sdd->rx_ch);
707 }
708
709 goto out;
710 }
711
712 if (xfer->delay_usecs)
713 udelay(xfer->delay_usecs);
714
715 if (xfer->cs_change) {
716 /* Hint that the next mssg is gonna be
717 for the same device */
718 if (list_is_last(&xfer->transfer_list,
719 &msg->transfers))
720 cs_toggle = 1;
721 else
722 disable_cs(sdd, spi);
723 }
724
725 msg->actual_length += xfer->len;
726
727 flush_fifo(sdd);
728 }
729
730 out:
731 if (!cs_toggle || status)
732 disable_cs(sdd, spi);
733 else
734 sdd->tgl_spi = spi;
735
736 s3c64xx_spi_unmap_mssg(sdd, msg);
737
738 msg->status = status;
739
740 if (msg->complete)
741 msg->complete(msg->context);
742 }
743
744 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
745 {
746
747 struct samsung_dma_info info;
748 sdd->ops = samsung_dma_get_ops();
749
750 info.cap = DMA_SLAVE;
751 info.client = &s3c64xx_spi_dma_client;
752 info.direction = DMA_FROM_DEVICE;
753 info.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
754 info.width = sdd->cur_bpw / 8;
755 sdd->rx_ch = sdd->ops->request(sdd->rx_dmach, &info);
756 info.direction = DMA_TO_DEVICE;
757 info.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
758 sdd->tx_ch = sdd->ops->request(sdd->tx_dmach, &info);
759
760 return 1;
761 }
762
763 static void s3c64xx_spi_work(struct work_struct *work)
764 {
765 struct s3c64xx_spi_driver_data *sdd = container_of(work,
766 struct s3c64xx_spi_driver_data, work);
767 unsigned long flags;
768
769 /* Acquire DMA channels */
770 while (!acquire_dma(sdd))
771 msleep(10);
772
773 spin_lock_irqsave(&sdd->lock, flags);
774
775 while (!list_empty(&sdd->queue)
776 && !(sdd->state & SUSPND)) {
777
778 struct spi_message *msg;
779
780 msg = container_of(sdd->queue.next, struct spi_message, queue);
781
782 list_del_init(&msg->queue);
783
784 /* Set Xfer busy flag */
785 sdd->state |= SPIBUSY;
786
787 spin_unlock_irqrestore(&sdd->lock, flags);
788
789 handle_msg(sdd, msg);
790
791 spin_lock_irqsave(&sdd->lock, flags);
792
793 sdd->state &= ~SPIBUSY;
794 }
795
796 spin_unlock_irqrestore(&sdd->lock, flags);
797
798 /* Free DMA channels */
799 sdd->ops->release(sdd->rx_ch, &s3c64xx_spi_dma_client);
800 sdd->ops->release(sdd->tx_ch, &s3c64xx_spi_dma_client);
801 }
802
803 static int s3c64xx_spi_transfer(struct spi_device *spi,
804 struct spi_message *msg)
805 {
806 struct s3c64xx_spi_driver_data *sdd;
807 unsigned long flags;
808
809 sdd = spi_master_get_devdata(spi->master);
810
811 spin_lock_irqsave(&sdd->lock, flags);
812
813 if (sdd->state & SUSPND) {
814 spin_unlock_irqrestore(&sdd->lock, flags);
815 return -ESHUTDOWN;
816 }
817
818 msg->status = -EINPROGRESS;
819 msg->actual_length = 0;
820
821 list_add_tail(&msg->queue, &sdd->queue);
822
823 queue_work(sdd->workqueue, &sdd->work);
824
825 spin_unlock_irqrestore(&sdd->lock, flags);
826
827 return 0;
828 }
829
830 /*
831 * Here we only check the validity of requested configuration
832 * and save the configuration in a local data-structure.
833 * The controller is actually configured only just before we
834 * get a message to transfer.
835 */
836 static int s3c64xx_spi_setup(struct spi_device *spi)
837 {
838 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
839 struct s3c64xx_spi_driver_data *sdd;
840 struct s3c64xx_spi_info *sci;
841 struct spi_message *msg;
842 unsigned long flags;
843 int err = 0;
844
845 if (cs == NULL || cs->set_level == NULL) {
846 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
847 return -ENODEV;
848 }
849
850 sdd = spi_master_get_devdata(spi->master);
851 sci = sdd->cntrlr_info;
852
853 spin_lock_irqsave(&sdd->lock, flags);
854
855 list_for_each_entry(msg, &sdd->queue, queue) {
856 /* Is some mssg is already queued for this device */
857 if (msg->spi == spi) {
858 dev_err(&spi->dev,
859 "setup: attempt while mssg in queue!\n");
860 spin_unlock_irqrestore(&sdd->lock, flags);
861 return -EBUSY;
862 }
863 }
864
865 if (sdd->state & SUSPND) {
866 spin_unlock_irqrestore(&sdd->lock, flags);
867 dev_err(&spi->dev,
868 "setup: SPI-%d not active!\n", spi->master->bus_num);
869 return -ESHUTDOWN;
870 }
871
872 spin_unlock_irqrestore(&sdd->lock, flags);
873
874 if (spi->bits_per_word != 8
875 && spi->bits_per_word != 16
876 && spi->bits_per_word != 32) {
877 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
878 spi->bits_per_word);
879 err = -EINVAL;
880 goto setup_exit;
881 }
882
883 /* Check if we can provide the requested rate */
884 if (!sci->clk_from_cmu) {
885 u32 psr, speed;
886
887 /* Max possible */
888 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
889
890 if (spi->max_speed_hz > speed)
891 spi->max_speed_hz = speed;
892
893 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
894 psr &= S3C64XX_SPI_PSR_MASK;
895 if (psr == S3C64XX_SPI_PSR_MASK)
896 psr--;
897
898 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
899 if (spi->max_speed_hz < speed) {
900 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
901 psr++;
902 } else {
903 err = -EINVAL;
904 goto setup_exit;
905 }
906 }
907
908 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
909 if (spi->max_speed_hz >= speed)
910 spi->max_speed_hz = speed;
911 else
912 err = -EINVAL;
913 }
914
915 setup_exit:
916
917 /* setup() returns with device de-selected */
918 disable_cs(sdd, spi);
919
920 return err;
921 }
922
923 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
924 {
925 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
926 void __iomem *regs = sdd->regs;
927 unsigned int val;
928
929 sdd->cur_speed = 0;
930
931 S3C64XX_SPI_DEACT(sdd);
932
933 /* Disable Interrupts - we use Polling if not DMA mode */
934 writel(0, regs + S3C64XX_SPI_INT_EN);
935
936 if (!sci->clk_from_cmu)
937 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
938 regs + S3C64XX_SPI_CLK_CFG);
939 writel(0, regs + S3C64XX_SPI_MODE_CFG);
940 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
941
942 /* Clear any irq pending bits */
943 writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
944 regs + S3C64XX_SPI_PENDING_CLR);
945
946 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
947
948 val = readl(regs + S3C64XX_SPI_MODE_CFG);
949 val &= ~S3C64XX_SPI_MODE_4BURST;
950 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
951 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
952 writel(val, regs + S3C64XX_SPI_MODE_CFG);
953
954 flush_fifo(sdd);
955 }
956
957 static int __init s3c64xx_spi_probe(struct platform_device *pdev)
958 {
959 struct resource *mem_res, *dmatx_res, *dmarx_res;
960 struct s3c64xx_spi_driver_data *sdd;
961 struct s3c64xx_spi_info *sci;
962 struct spi_master *master;
963 int ret;
964
965 if (pdev->id < 0) {
966 dev_err(&pdev->dev,
967 "Invalid platform device id-%d\n", pdev->id);
968 return -ENODEV;
969 }
970
971 if (pdev->dev.platform_data == NULL) {
972 dev_err(&pdev->dev, "platform_data missing!\n");
973 return -ENODEV;
974 }
975
976 sci = pdev->dev.platform_data;
977 if (!sci->src_clk_name) {
978 dev_err(&pdev->dev,
979 "Board init must call s3c64xx_spi_set_info()\n");
980 return -EINVAL;
981 }
982
983 /* Check for availability of necessary resource */
984
985 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
986 if (dmatx_res == NULL) {
987 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");
988 return -ENXIO;
989 }
990
991 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
992 if (dmarx_res == NULL) {
993 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");
994 return -ENXIO;
995 }
996
997 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
998 if (mem_res == NULL) {
999 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1000 return -ENXIO;
1001 }
1002
1003 master = spi_alloc_master(&pdev->dev,
1004 sizeof(struct s3c64xx_spi_driver_data));
1005 if (master == NULL) {
1006 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1007 return -ENOMEM;
1008 }
1009
1010 platform_set_drvdata(pdev, master);
1011
1012 sdd = spi_master_get_devdata(master);
1013 sdd->master = master;
1014 sdd->cntrlr_info = sci;
1015 sdd->pdev = pdev;
1016 sdd->sfr_start = mem_res->start;
1017 sdd->tx_dmach = dmatx_res->start;
1018 sdd->rx_dmach = dmarx_res->start;
1019
1020 sdd->cur_bpw = 8;
1021
1022 master->bus_num = pdev->id;
1023 master->setup = s3c64xx_spi_setup;
1024 master->transfer = s3c64xx_spi_transfer;
1025 master->num_chipselect = sci->num_cs;
1026 master->dma_alignment = 8;
1027 /* the spi->mode bits understood by this driver: */
1028 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1029
1030 if (request_mem_region(mem_res->start,
1031 resource_size(mem_res), pdev->name) == NULL) {
1032 dev_err(&pdev->dev, "Req mem region failed\n");
1033 ret = -ENXIO;
1034 goto err0;
1035 }
1036
1037 sdd->regs = ioremap(mem_res->start, resource_size(mem_res));
1038 if (sdd->regs == NULL) {
1039 dev_err(&pdev->dev, "Unable to remap IO\n");
1040 ret = -ENXIO;
1041 goto err1;
1042 }
1043
1044 if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) {
1045 dev_err(&pdev->dev, "Unable to config gpio\n");
1046 ret = -EBUSY;
1047 goto err2;
1048 }
1049
1050 /* Setup clocks */
1051 sdd->clk = clk_get(&pdev->dev, "spi");
1052 if (IS_ERR(sdd->clk)) {
1053 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1054 ret = PTR_ERR(sdd->clk);
1055 goto err3;
1056 }
1057
1058 if (clk_enable(sdd->clk)) {
1059 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1060 ret = -EBUSY;
1061 goto err4;
1062 }
1063
1064 sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name);
1065 if (IS_ERR(sdd->src_clk)) {
1066 dev_err(&pdev->dev,
1067 "Unable to acquire clock '%s'\n", sci->src_clk_name);
1068 ret = PTR_ERR(sdd->src_clk);
1069 goto err5;
1070 }
1071
1072 if (clk_enable(sdd->src_clk)) {
1073 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n",
1074 sci->src_clk_name);
1075 ret = -EBUSY;
1076 goto err6;
1077 }
1078
1079 sdd->workqueue = create_singlethread_workqueue(
1080 dev_name(master->dev.parent));
1081 if (sdd->workqueue == NULL) {
1082 dev_err(&pdev->dev, "Unable to create workqueue\n");
1083 ret = -ENOMEM;
1084 goto err7;
1085 }
1086
1087 /* Setup Deufult Mode */
1088 s3c64xx_spi_hwinit(sdd, pdev->id);
1089
1090 spin_lock_init(&sdd->lock);
1091 init_completion(&sdd->xfer_completion);
1092 INIT_WORK(&sdd->work, s3c64xx_spi_work);
1093 INIT_LIST_HEAD(&sdd->queue);
1094
1095 if (spi_register_master(master)) {
1096 dev_err(&pdev->dev, "cannot register SPI master\n");
1097 ret = -EBUSY;
1098 goto err8;
1099 }
1100
1101 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
1102 "with %d Slaves attached\n",
1103 pdev->id, master->num_chipselect);
1104 dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1105 mem_res->end, mem_res->start,
1106 sdd->rx_dmach, sdd->tx_dmach);
1107
1108 return 0;
1109
1110 err8:
1111 destroy_workqueue(sdd->workqueue);
1112 err7:
1113 clk_disable(sdd->src_clk);
1114 err6:
1115 clk_put(sdd->src_clk);
1116 err5:
1117 clk_disable(sdd->clk);
1118 err4:
1119 clk_put(sdd->clk);
1120 err3:
1121 err2:
1122 iounmap((void *) sdd->regs);
1123 err1:
1124 release_mem_region(mem_res->start, resource_size(mem_res));
1125 err0:
1126 platform_set_drvdata(pdev, NULL);
1127 spi_master_put(master);
1128
1129 return ret;
1130 }
1131
1132 static int s3c64xx_spi_remove(struct platform_device *pdev)
1133 {
1134 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1135 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1136 struct resource *mem_res;
1137 unsigned long flags;
1138
1139 spin_lock_irqsave(&sdd->lock, flags);
1140 sdd->state |= SUSPND;
1141 spin_unlock_irqrestore(&sdd->lock, flags);
1142
1143 while (sdd->state & SPIBUSY)
1144 msleep(10);
1145
1146 spi_unregister_master(master);
1147
1148 destroy_workqueue(sdd->workqueue);
1149
1150 clk_disable(sdd->src_clk);
1151 clk_put(sdd->src_clk);
1152
1153 clk_disable(sdd->clk);
1154 clk_put(sdd->clk);
1155
1156 iounmap((void *) sdd->regs);
1157
1158 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1159 if (mem_res != NULL)
1160 release_mem_region(mem_res->start, resource_size(mem_res));
1161
1162 platform_set_drvdata(pdev, NULL);
1163 spi_master_put(master);
1164
1165 return 0;
1166 }
1167
1168 #ifdef CONFIG_PM
1169 static int s3c64xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1170 {
1171 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1172 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1173 unsigned long flags;
1174
1175 spin_lock_irqsave(&sdd->lock, flags);
1176 sdd->state |= SUSPND;
1177 spin_unlock_irqrestore(&sdd->lock, flags);
1178
1179 while (sdd->state & SPIBUSY)
1180 msleep(10);
1181
1182 /* Disable the clock */
1183 clk_disable(sdd->src_clk);
1184 clk_disable(sdd->clk);
1185
1186 sdd->cur_speed = 0; /* Output Clock is stopped */
1187
1188 return 0;
1189 }
1190
1191 static int s3c64xx_spi_resume(struct platform_device *pdev)
1192 {
1193 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1194 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1195 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1196 unsigned long flags;
1197
1198 sci->cfg_gpio(pdev);
1199
1200 /* Enable the clock */
1201 clk_enable(sdd->src_clk);
1202 clk_enable(sdd->clk);
1203
1204 s3c64xx_spi_hwinit(sdd, pdev->id);
1205
1206 spin_lock_irqsave(&sdd->lock, flags);
1207 sdd->state &= ~SUSPND;
1208 spin_unlock_irqrestore(&sdd->lock, flags);
1209
1210 return 0;
1211 }
1212 #else
1213 #define s3c64xx_spi_suspend NULL
1214 #define s3c64xx_spi_resume NULL
1215 #endif /* CONFIG_PM */
1216
1217 static struct platform_driver s3c64xx_spi_driver = {
1218 .driver = {
1219 .name = "s3c64xx-spi",
1220 .owner = THIS_MODULE,
1221 },
1222 .remove = s3c64xx_spi_remove,
1223 .suspend = s3c64xx_spi_suspend,
1224 .resume = s3c64xx_spi_resume,
1225 };
1226 MODULE_ALIAS("platform:s3c64xx-spi");
1227
1228 static int __init s3c64xx_spi_init(void)
1229 {
1230 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1231 }
1232 subsys_initcall(s3c64xx_spi_init);
1233
1234 static void __exit s3c64xx_spi_exit(void)
1235 {
1236 platform_driver_unregister(&s3c64xx_spi_driver);
1237 }
1238 module_exit(s3c64xx_spi_exit);
1239
1240 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1241 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1242 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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