drivers/spi/spi-sh-hspi.c

   1 /*
   2  * SuperH HSPI bus driver
   3  *
   4  * Copyright (C) 2011  Kuninori Morimoto
   5  *
   6  * Based on spi-sh.c:
   7  * Based on pxa2xx_spi.c:
   8  * Copyright (C) 2011 Renesas Solutions Corp.
   9  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; version 2 of the License.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  23  *
  24  */
  25
  26 #include <linux/clk.h>
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/timer.h>
  30 #include <linux/delay.h>
  31 #include <linux/list.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/io.h>
  36 #include <linux/spi/spi.h>
  37 #include <linux/spi/sh_hspi.h>
  38
  39 #define SPCR    0x00
  40 #define SPSR    0x04
  41 #define SPSCR   0x08
  42 #define SPTBR   0x0C
  43 #define SPRBR   0x10
  44 #define SPCR2   0x14
  45
  46 /* SPSR */
  47 #define RXFL    (1 << 2)
  48
  49 struct hspi_priv {
  50         void __iomem *addr;
  51         struct spi_master *master;
  52         struct device *dev;
  53         struct clk *clk;
  54 };
  55
  56 /*
  57  *              basic function
  58  */
  59 static void hspi_write(struct hspi_priv *hspi, int reg, u32 val)
  60 {
  61         iowrite32(val, hspi->addr + reg);
  62 }
  63
  64 static u32 hspi_read(struct hspi_priv *hspi, int reg)
  65 {
  66         return ioread32(hspi->addr + reg);
  67 }
  68
  69 static void hspi_bit_set(struct hspi_priv *hspi, int reg, u32 mask, u32 set)
  70 {
  71         u32 val = hspi_read(hspi, reg);
  72
  73         val &= ~mask;
  74         val |= set & mask;
  75
  76         hspi_write(hspi, reg, val);
  77 }
  78
  79 /*
  80  *              transfer function
  81  */
  82 static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
  83 {
  84         int t = 256;
  85
  86         while (t--) {
  87                 if ((mask & hspi_read(hspi, SPSR)) == val)
  88                         return 0;
  89
  90                 udelay(10);
  91         }
  92
  93         dev_err(hspi->dev, "timeout\n");
  94         return -ETIMEDOUT;
  95 }
  96
  97 /*
  98  *              spi master function
  99  */
 100
 101 #define hspi_hw_cs_enable(hspi)         hspi_hw_cs_ctrl(hspi, 0)
 102 #define hspi_hw_cs_disable(hspi)        hspi_hw_cs_ctrl(hspi, 1)
 103 static void hspi_hw_cs_ctrl(struct hspi_priv *hspi, int hi)
 104 {
 105         hspi_bit_set(hspi, SPSCR, (1 << 6), (hi) << 6);
 106 }
 107
 108 static void hspi_hw_setup(struct hspi_priv *hspi,
 109                           struct spi_message *msg,
 110                           struct spi_transfer *t)
 111 {
 112         struct spi_device *spi = msg->spi;
 113         struct device *dev = hspi->dev;
 114         u32 spcr, idiv_clk;
 115         u32 rate, best_rate, min, tmp;
 116
 117         /*
 118          * find best IDIV/CLKCx settings
 119          */
 120         min = ~0;
 121         best_rate = 0;
 122         spcr = 0;
 123         for (idiv_clk = 0x00; idiv_clk <= 0x3F; idiv_clk++) {
 124                 rate = clk_get_rate(hspi->clk);
 125
 126                 /* IDIV calculation */
 127                 if (idiv_clk & (1 << 5))
 128                         rate /= 128;
 129                 else
 130                         rate /= 16;
 131
 132                 /* CLKCx calculation */
 133                 rate /= (((idiv_clk & 0x1F) + 1) * 2);
 134
 135                 /* save best settings */
 136                 tmp = abs(t->speed_hz - rate);
 137                 if (tmp < min) {
 138                         min = tmp;
 139                         spcr = idiv_clk;
 140                         best_rate = rate;
 141                 }
 142         }
 143
 144         if (spi->mode & SPI_CPHA)
 145                 spcr |= 1 << 7;
 146         if (spi->mode & SPI_CPOL)
 147                 spcr |= 1 << 6;
 148
 149         dev_dbg(dev, "speed %d/%d\n", t->speed_hz, best_rate);
 150
 151         hspi_write(hspi, SPCR, spcr);
 152         hspi_write(hspi, SPSR, 0x0);
 153         hspi_write(hspi, SPSCR, 0x21);  /* master mode / CS control */
 154 }
 155
 156 static int hspi_transfer_one_message(struct spi_master *master,
 157                                      struct spi_message *msg)
 158 {
 159         struct hspi_priv *hspi = spi_master_get_devdata(master);
 160         struct spi_transfer *t;
 161         u32 tx;
 162         u32 rx;
 163         int ret, i;
 164         unsigned int cs_change;
 165         const int nsecs = 50;
 166
 167         dev_dbg(hspi->dev, "%s\n", __func__);
 168
 169         cs_change = 1;
 170         ret = 0;
 171         list_for_each_entry(t, &msg->transfers, transfer_list) {
 172
 173                 if (cs_change) {
 174                         hspi_hw_setup(hspi, msg, t);
 175                         hspi_hw_cs_enable(hspi);
 176                         ndelay(nsecs);
 177                 }
 178                 cs_change = t->cs_change;
 179
 180                 for (i = 0; i < t->len; i++) {
 181
 182                         /* wait remains */
 183                         ret = hspi_status_check_timeout(hspi, 0x1, 0);
 184                         if (ret < 0)
 185                                 break;
 186
 187                         tx = 0;
 188                         if (t->tx_buf)
 189                                 tx = (u32)((u8 *)t->tx_buf)[i];
 190
 191                         hspi_write(hspi, SPTBR, tx);
 192
 193                         /* wait receive */
 194                         ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
 195                         if (ret < 0)
 196                                 break;
 197
 198                         rx = hspi_read(hspi, SPRBR);
 199                         if (t->rx_buf)
 200                                 ((u8 *)t->rx_buf)[i] = (u8)rx;
 201
 202                 }
 203
 204                 msg->actual_length += t->len;
 205
 206                 if (t->delay_usecs)
 207                         udelay(t->delay_usecs);
 208
 209                 if (cs_change) {
 210                         ndelay(nsecs);
 211                         hspi_hw_cs_disable(hspi);
 212                         ndelay(nsecs);
 213                 }
 214         }
 215
 216         msg->status = ret;
 217         if (!cs_change) {
 218                 ndelay(nsecs);
 219                 hspi_hw_cs_disable(hspi);
 220         }
 221         spi_finalize_current_message(master);
 222
 223         return ret;
 224 }
 225
 226 static int hspi_probe(struct platform_device *pdev)
 227 {
 228         struct resource *res;
 229         struct spi_master *master;
 230         struct hspi_priv *hspi;
 231         struct clk *clk;
 232         int ret;
 233
 234         /* get base addr */
 235         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 236         if (!res) {
 237                 dev_err(&pdev->dev, "invalid resource\n");
 238                 return -EINVAL;
 239         }
 240
 241         master = spi_alloc_master(&pdev->dev, sizeof(*hspi));
 242         if (!master) {
 243                 dev_err(&pdev->dev, "spi_alloc_master error.\n");
 244                 return -ENOMEM;
 245         }
 246
 247         clk = clk_get(&pdev->dev, NULL);
 248         if (IS_ERR(clk)) {
 249                 dev_err(&pdev->dev, "couldn't get clock\n");
 250                 ret = -EINVAL;
 251                 goto error0;
 252         }
 253
 254         hspi = spi_master_get_devdata(master);
 255         platform_set_drvdata(pdev, hspi);
 256
 257         /* init hspi */
 258         hspi->master    = master;
 259         hspi->dev       = &pdev->dev;
 260         hspi->clk       = clk;
 261         hspi->addr      = devm_ioremap(hspi->dev,
 262                                        res->start, resource_size(res));
 263         if (!hspi->addr) {
 264                 dev_err(&pdev->dev, "ioremap error.\n");
 265                 ret = -ENOMEM;
 266                 goto error1;
 267         }
 268
 269         pm_runtime_enable(&pdev->dev);
 270
 271         master->bus_num         = pdev->id;
 272         master->mode_bits       = SPI_CPOL | SPI_CPHA;
 273         master->dev.of_node     = pdev->dev.of_node;
 274         master->auto_runtime_pm = true;
 275         master->transfer_one_message            = hspi_transfer_one_message;
 276         master->bits_per_word_mask = SPI_BPW_MASK(8);
 277
 278         ret = devm_spi_register_master(&pdev->dev, master);
 279         if (ret < 0) {
 280                 dev_err(&pdev->dev, "spi_register_master error.\n");
 281                 goto error2;
 282         }
 283
 284         return 0;
 285
 286  error2:
 287         pm_runtime_disable(&pdev->dev);
 288  error1:
 289         clk_put(clk);
 290  error0:
 291         spi_master_put(master);
 292
 293         return ret;
 294 }
 295
 296 static int hspi_remove(struct platform_device *pdev)
 297 {
 298         struct hspi_priv *hspi = platform_get_drvdata(pdev);
 299
 300         pm_runtime_disable(&pdev->dev);
 301
 302         clk_put(hspi->clk);
 303
 304         return 0;
 305 }
 306
 307 static const struct of_device_id hspi_of_match[] = {
 308         { .compatible = "renesas,hspi", },
 309         { /* sentinel */ }
 310 };
 311 MODULE_DEVICE_TABLE(of, hspi_of_match);
 312
 313 static struct platform_driver hspi_driver = {
 314         .probe = hspi_probe,
 315         .remove = hspi_remove,
 316         .driver = {
 317                 .name = "sh-hspi",
 318                 .owner = THIS_MODULE,
 319                 .of_match_table = hspi_of_match,
 320         },
 321 };
 322 module_platform_driver(hspi_driver);
 323
 324 MODULE_DESCRIPTION("SuperH HSPI bus driver");
 325 MODULE_LICENSE("GPL");
 326 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
 327 MODULE_ALIAS("platform:sh-hspi");