2 * SuperH MSIOF SPI Master Interface
4 * Copyright (c) 2009 Magnus Damm
5 * Copyright (C) 2014 Glider bvba
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
13 #include <linux/bitmap.h>
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/dmaengine.h>
19 #include <linux/err.h>
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/sh_dma.h>
31 #include <linux/spi/sh_msiof.h>
32 #include <linux/spi/spi.h>
34 #include <asm/unaligned.h>
37 struct sh_msiof_chipdata
{
43 struct sh_msiof_spi_priv
{
44 struct spi_master
*master
;
45 void __iomem
*mapbase
;
47 struct platform_device
*pdev
;
48 struct sh_msiof_spi_info
*info
;
49 struct completion done
;
50 unsigned int tx_fifo_size
;
51 unsigned int rx_fifo_size
;
54 dma_addr_t tx_dma_addr
;
55 dma_addr_t rx_dma_addr
;
58 #define TMDR1 0x00 /* Transmit Mode Register 1 */
59 #define TMDR2 0x04 /* Transmit Mode Register 2 */
60 #define TMDR3 0x08 /* Transmit Mode Register 3 */
61 #define RMDR1 0x10 /* Receive Mode Register 1 */
62 #define RMDR2 0x14 /* Receive Mode Register 2 */
63 #define RMDR3 0x18 /* Receive Mode Register 3 */
64 #define TSCR 0x20 /* Transmit Clock Select Register */
65 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
66 #define CTR 0x28 /* Control Register */
67 #define FCTR 0x30 /* FIFO Control Register */
68 #define STR 0x40 /* Status Register */
69 #define IER 0x44 /* Interrupt Enable Register */
70 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
71 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
72 #define TFDR 0x50 /* Transmit FIFO Data Register */
73 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
74 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
75 #define RFDR 0x60 /* Receive FIFO Data Register */
78 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
79 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
80 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
81 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
82 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
83 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
84 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
85 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
86 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
87 #define MDR1_FLD_SHIFT 2
88 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
90 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
93 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
94 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
95 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
98 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
99 #define SCR_BRPS(i) (((i) - 1) << 8)
100 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
101 #define SCR_BRDV_DIV_2 0x0000
102 #define SCR_BRDV_DIV_4 0x0001
103 #define SCR_BRDV_DIV_8 0x0002
104 #define SCR_BRDV_DIV_16 0x0003
105 #define SCR_BRDV_DIV_32 0x0004
106 #define SCR_BRDV_DIV_1 0x0007
109 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
110 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
111 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
112 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
113 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
114 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
115 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
116 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
117 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
118 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
119 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
120 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
121 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
122 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
123 #define CTR_TXE 0x00000200 /* Transmit Enable */
124 #define CTR_RXE 0x00000100 /* Receive Enable */
127 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
128 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
129 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
130 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
131 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
132 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
133 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
134 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
135 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
136 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
137 #define FCTR_TFUA_SHIFT 20
138 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
139 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
140 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
141 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
142 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
143 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
144 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
145 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
146 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
147 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
148 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
149 #define FCTR_RFUA_SHIFT 4
150 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
153 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
154 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
155 #define STR_TEOF 0x00800000 /* Frame Transmission End */
156 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
157 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
158 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
159 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
160 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
161 #define STR_REOF 0x00000080 /* Frame Reception End */
162 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
163 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
164 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
167 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
168 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
169 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
170 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
171 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
172 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
173 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
174 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
175 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
176 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
177 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
178 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
179 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
180 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
183 static u32
sh_msiof_read(struct sh_msiof_spi_priv
*p
, int reg_offs
)
188 return ioread16(p
->mapbase
+ reg_offs
);
190 return ioread32(p
->mapbase
+ reg_offs
);
194 static void sh_msiof_write(struct sh_msiof_spi_priv
*p
, int reg_offs
,
200 iowrite16(value
, p
->mapbase
+ reg_offs
);
203 iowrite32(value
, p
->mapbase
+ reg_offs
);
208 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv
*p
,
211 u32 mask
= clr
| set
;
215 data
= sh_msiof_read(p
, CTR
);
218 sh_msiof_write(p
, CTR
, data
);
220 for (k
= 100; k
> 0; k
--) {
221 if ((sh_msiof_read(p
, CTR
) & mask
) == set
)
227 return k
> 0 ? 0 : -ETIMEDOUT
;
230 static irqreturn_t
sh_msiof_spi_irq(int irq
, void *data
)
232 struct sh_msiof_spi_priv
*p
= data
;
234 /* just disable the interrupt and wake up */
235 sh_msiof_write(p
, IER
, 0);
244 } const sh_msiof_spi_div_table
[] = {
245 { 1, SCR_BRDV_DIV_1
},
246 { 2, SCR_BRDV_DIV_2
},
247 { 4, SCR_BRDV_DIV_4
},
248 { 8, SCR_BRDV_DIV_8
},
249 { 16, SCR_BRDV_DIV_16
},
250 { 32, SCR_BRDV_DIV_32
},
253 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv
*p
,
254 unsigned long parent_rate
, u32 spi_hz
)
256 unsigned long div
= 1024;
260 if (!WARN_ON(!spi_hz
|| !parent_rate
))
261 div
= DIV_ROUND_UP(parent_rate
, spi_hz
);
263 for (k
= 0; k
< ARRAY_SIZE(sh_msiof_spi_div_table
); k
++) {
264 brps
= DIV_ROUND_UP(div
, sh_msiof_spi_div_table
[k
].div
);
265 if (brps
<= 32) /* max of brdv is 32 */
269 k
= min_t(int, k
, ARRAY_SIZE(sh_msiof_spi_div_table
) - 1);
271 scr
= sh_msiof_spi_div_table
[k
].brdv
| SCR_BRPS(brps
);
272 sh_msiof_write(p
, TSCR
, scr
);
273 if (!(p
->master
->flags
& SPI_MASTER_MUST_TX
))
274 sh_msiof_write(p
, RSCR
, scr
);
277 static u32
sh_msiof_get_delay_bit(u32 dtdl_or_syncdl
)
280 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
284 * b'011 (SYNCDL only) : 300
288 if (dtdl_or_syncdl
% 100)
289 return dtdl_or_syncdl
/ 100 + 5;
291 return dtdl_or_syncdl
/ 100;
294 static u32
sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv
*p
)
301 /* check if DTDL and SYNCDL is allowed value */
302 if (p
->info
->dtdl
> 200 || p
->info
->syncdl
> 300) {
303 dev_warn(&p
->pdev
->dev
, "DTDL or SYNCDL is too large\n");
307 /* check if the sum of DTDL and SYNCDL becomes an integer value */
308 if ((p
->info
->dtdl
+ p
->info
->syncdl
) % 100) {
309 dev_warn(&p
->pdev
->dev
, "the sum of DTDL/SYNCDL is not good\n");
313 val
= sh_msiof_get_delay_bit(p
->info
->dtdl
) << MDR1_DTDL_SHIFT
;
314 val
|= sh_msiof_get_delay_bit(p
->info
->syncdl
) << MDR1_SYNCDL_SHIFT
;
319 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv
*p
,
321 u32 tx_hi_z
, u32 lsb_first
, u32 cs_high
)
327 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
333 tmp
= MDR1_SYNCMD_SPI
| 1 << MDR1_FLD_SHIFT
| MDR1_XXSTP
;
334 tmp
|= !cs_high
<< MDR1_SYNCAC_SHIFT
;
335 tmp
|= lsb_first
<< MDR1_BITLSB_SHIFT
;
336 tmp
|= sh_msiof_spi_get_dtdl_and_syncdl(p
);
337 sh_msiof_write(p
, TMDR1
, tmp
| MDR1_TRMD
| TMDR1_PCON
);
338 if (p
->master
->flags
& SPI_MASTER_MUST_TX
) {
339 /* These bits are reserved if RX needs TX */
342 sh_msiof_write(p
, RMDR1
, tmp
);
345 tmp
|= CTR_TSCKIZ_SCK
| cpol
<< CTR_TSCKIZ_POL_SHIFT
;
346 tmp
|= CTR_RSCKIZ_SCK
| cpol
<< CTR_RSCKIZ_POL_SHIFT
;
350 tmp
|= edge
<< CTR_TEDG_SHIFT
;
351 tmp
|= edge
<< CTR_REDG_SHIFT
;
352 tmp
|= tx_hi_z
? CTR_TXDIZ_HIZ
: CTR_TXDIZ_LOW
;
353 sh_msiof_write(p
, CTR
, tmp
);
356 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv
*p
,
357 const void *tx_buf
, void *rx_buf
,
360 u32 dr2
= MDR2_BITLEN1(bits
) | MDR2_WDLEN1(words
);
362 if (tx_buf
|| (p
->master
->flags
& SPI_MASTER_MUST_TX
))
363 sh_msiof_write(p
, TMDR2
, dr2
);
365 sh_msiof_write(p
, TMDR2
, dr2
| MDR2_GRPMASK1
);
368 sh_msiof_write(p
, RMDR2
, dr2
);
371 static void sh_msiof_reset_str(struct sh_msiof_spi_priv
*p
)
373 sh_msiof_write(p
, STR
, sh_msiof_read(p
, STR
));
376 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv
*p
,
377 const void *tx_buf
, int words
, int fs
)
379 const u8
*buf_8
= tx_buf
;
382 for (k
= 0; k
< words
; k
++)
383 sh_msiof_write(p
, TFDR
, buf_8
[k
] << fs
);
386 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv
*p
,
387 const void *tx_buf
, int words
, int fs
)
389 const u16
*buf_16
= tx_buf
;
392 for (k
= 0; k
< words
; k
++)
393 sh_msiof_write(p
, TFDR
, buf_16
[k
] << fs
);
396 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv
*p
,
397 const void *tx_buf
, int words
, int fs
)
399 const u16
*buf_16
= tx_buf
;
402 for (k
= 0; k
< words
; k
++)
403 sh_msiof_write(p
, TFDR
, get_unaligned(&buf_16
[k
]) << fs
);
406 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv
*p
,
407 const void *tx_buf
, int words
, int fs
)
409 const u32
*buf_32
= tx_buf
;
412 for (k
= 0; k
< words
; k
++)
413 sh_msiof_write(p
, TFDR
, buf_32
[k
] << fs
);
416 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv
*p
,
417 const void *tx_buf
, int words
, int fs
)
419 const u32
*buf_32
= tx_buf
;
422 for (k
= 0; k
< words
; k
++)
423 sh_msiof_write(p
, TFDR
, get_unaligned(&buf_32
[k
]) << fs
);
426 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv
*p
,
427 const void *tx_buf
, int words
, int fs
)
429 const u32
*buf_32
= tx_buf
;
432 for (k
= 0; k
< words
; k
++)
433 sh_msiof_write(p
, TFDR
, swab32(buf_32
[k
] << fs
));
436 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv
*p
,
437 const void *tx_buf
, int words
, int fs
)
439 const u32
*buf_32
= tx_buf
;
442 for (k
= 0; k
< words
; k
++)
443 sh_msiof_write(p
, TFDR
, swab32(get_unaligned(&buf_32
[k
]) << fs
));
446 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv
*p
,
447 void *rx_buf
, int words
, int fs
)
452 for (k
= 0; k
< words
; k
++)
453 buf_8
[k
] = sh_msiof_read(p
, RFDR
) >> fs
;
456 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv
*p
,
457 void *rx_buf
, int words
, int fs
)
459 u16
*buf_16
= rx_buf
;
462 for (k
= 0; k
< words
; k
++)
463 buf_16
[k
] = sh_msiof_read(p
, RFDR
) >> fs
;
466 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv
*p
,
467 void *rx_buf
, int words
, int fs
)
469 u16
*buf_16
= rx_buf
;
472 for (k
= 0; k
< words
; k
++)
473 put_unaligned(sh_msiof_read(p
, RFDR
) >> fs
, &buf_16
[k
]);
476 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv
*p
,
477 void *rx_buf
, int words
, int fs
)
479 u32
*buf_32
= rx_buf
;
482 for (k
= 0; k
< words
; k
++)
483 buf_32
[k
] = sh_msiof_read(p
, RFDR
) >> fs
;
486 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv
*p
,
487 void *rx_buf
, int words
, int fs
)
489 u32
*buf_32
= rx_buf
;
492 for (k
= 0; k
< words
; k
++)
493 put_unaligned(sh_msiof_read(p
, RFDR
) >> fs
, &buf_32
[k
]);
496 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv
*p
,
497 void *rx_buf
, int words
, int fs
)
499 u32
*buf_32
= rx_buf
;
502 for (k
= 0; k
< words
; k
++)
503 buf_32
[k
] = swab32(sh_msiof_read(p
, RFDR
) >> fs
);
506 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv
*p
,
507 void *rx_buf
, int words
, int fs
)
509 u32
*buf_32
= rx_buf
;
512 for (k
= 0; k
< words
; k
++)
513 put_unaligned(swab32(sh_msiof_read(p
, RFDR
) >> fs
), &buf_32
[k
]);
516 static int sh_msiof_spi_setup(struct spi_device
*spi
)
518 struct device_node
*np
= spi
->master
->dev
.of_node
;
519 struct sh_msiof_spi_priv
*p
= spi_master_get_devdata(spi
->master
);
521 pm_runtime_get_sync(&p
->pdev
->dev
);
525 * Use spi->controller_data for CS (same strategy as spi_gpio),
526 * if any. otherwise let HW control CS
528 spi
->cs_gpio
= (uintptr_t)spi
->controller_data
;
531 /* Configure pins before deasserting CS */
532 sh_msiof_spi_set_pin_regs(p
, !!(spi
->mode
& SPI_CPOL
),
533 !!(spi
->mode
& SPI_CPHA
),
534 !!(spi
->mode
& SPI_3WIRE
),
535 !!(spi
->mode
& SPI_LSB_FIRST
),
536 !!(spi
->mode
& SPI_CS_HIGH
));
538 if (spi
->cs_gpio
>= 0)
539 gpio_set_value(spi
->cs_gpio
, !(spi
->mode
& SPI_CS_HIGH
));
542 pm_runtime_put(&p
->pdev
->dev
);
547 static int sh_msiof_prepare_message(struct spi_master
*master
,
548 struct spi_message
*msg
)
550 struct sh_msiof_spi_priv
*p
= spi_master_get_devdata(master
);
551 const struct spi_device
*spi
= msg
->spi
;
553 /* Configure pins before asserting CS */
554 sh_msiof_spi_set_pin_regs(p
, !!(spi
->mode
& SPI_CPOL
),
555 !!(spi
->mode
& SPI_CPHA
),
556 !!(spi
->mode
& SPI_3WIRE
),
557 !!(spi
->mode
& SPI_LSB_FIRST
),
558 !!(spi
->mode
& SPI_CS_HIGH
));
562 static int sh_msiof_spi_start(struct sh_msiof_spi_priv
*p
, void *rx_buf
)
566 /* setup clock and rx/tx signals */
567 ret
= sh_msiof_modify_ctr_wait(p
, 0, CTR_TSCKE
);
569 ret
= sh_msiof_modify_ctr_wait(p
, 0, CTR_RXE
);
571 ret
= sh_msiof_modify_ctr_wait(p
, 0, CTR_TXE
);
573 /* start by setting frame bit */
575 ret
= sh_msiof_modify_ctr_wait(p
, 0, CTR_TFSE
);
580 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv
*p
, void *rx_buf
)
584 /* shut down frame, rx/tx and clock signals */
585 ret
= sh_msiof_modify_ctr_wait(p
, CTR_TFSE
, 0);
587 ret
= sh_msiof_modify_ctr_wait(p
, CTR_TXE
, 0);
589 ret
= sh_msiof_modify_ctr_wait(p
, CTR_RXE
, 0);
591 ret
= sh_msiof_modify_ctr_wait(p
, CTR_TSCKE
, 0);
596 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv
*p
,
597 void (*tx_fifo
)(struct sh_msiof_spi_priv
*,
598 const void *, int, int),
599 void (*rx_fifo
)(struct sh_msiof_spi_priv
*,
601 const void *tx_buf
, void *rx_buf
,
607 /* limit maximum word transfer to rx/tx fifo size */
609 words
= min_t(int, words
, p
->tx_fifo_size
);
611 words
= min_t(int, words
, p
->rx_fifo_size
);
613 /* the fifo contents need shifting */
614 fifo_shift
= 32 - bits
;
616 /* default FIFO watermarks for PIO */
617 sh_msiof_write(p
, FCTR
, 0);
619 /* setup msiof transfer mode registers */
620 sh_msiof_spi_set_mode_regs(p
, tx_buf
, rx_buf
, bits
, words
);
621 sh_msiof_write(p
, IER
, IER_TEOFE
| IER_REOFE
);
625 tx_fifo(p
, tx_buf
, words
, fifo_shift
);
627 reinit_completion(&p
->done
);
629 ret
= sh_msiof_spi_start(p
, rx_buf
);
631 dev_err(&p
->pdev
->dev
, "failed to start hardware\n");
635 /* wait for tx fifo to be emptied / rx fifo to be filled */
636 if (!wait_for_completion_timeout(&p
->done
, HZ
)) {
637 dev_err(&p
->pdev
->dev
, "PIO timeout\n");
644 rx_fifo(p
, rx_buf
, words
, fifo_shift
);
646 /* clear status bits */
647 sh_msiof_reset_str(p
);
649 ret
= sh_msiof_spi_stop(p
, rx_buf
);
651 dev_err(&p
->pdev
->dev
, "failed to shut down hardware\n");
658 sh_msiof_reset_str(p
);
659 sh_msiof_spi_stop(p
, rx_buf
);
661 sh_msiof_write(p
, IER
, 0);
665 static void sh_msiof_dma_complete(void *arg
)
667 struct sh_msiof_spi_priv
*p
= arg
;
669 sh_msiof_write(p
, IER
, 0);
673 static int sh_msiof_dma_once(struct sh_msiof_spi_priv
*p
, const void *tx
,
674 void *rx
, unsigned int len
)
677 struct dma_async_tx_descriptor
*desc_tx
= NULL
, *desc_rx
= NULL
;
681 /* First prepare and submit the DMA request(s), as this may fail */
683 ier_bits
|= IER_RDREQE
| IER_RDMAE
;
684 desc_rx
= dmaengine_prep_slave_single(p
->master
->dma_rx
,
685 p
->rx_dma_addr
, len
, DMA_FROM_DEVICE
,
686 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
690 desc_rx
->callback
= sh_msiof_dma_complete
;
691 desc_rx
->callback_param
= p
;
692 cookie
= dmaengine_submit(desc_rx
);
693 if (dma_submit_error(cookie
))
698 ier_bits
|= IER_TDREQE
| IER_TDMAE
;
699 dma_sync_single_for_device(p
->master
->dma_tx
->device
->dev
,
700 p
->tx_dma_addr
, len
, DMA_TO_DEVICE
);
701 desc_tx
= dmaengine_prep_slave_single(p
->master
->dma_tx
,
702 p
->tx_dma_addr
, len
, DMA_TO_DEVICE
,
703 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
711 desc_tx
->callback
= NULL
;
713 desc_tx
->callback
= sh_msiof_dma_complete
;
714 desc_tx
->callback_param
= p
;
716 cookie
= dmaengine_submit(desc_tx
);
717 if (dma_submit_error(cookie
)) {
723 /* 1 stage FIFO watermarks for DMA */
724 sh_msiof_write(p
, FCTR
, FCTR_TFWM_1
| FCTR_RFWM_1
);
726 /* setup msiof transfer mode registers (32-bit words) */
727 sh_msiof_spi_set_mode_regs(p
, tx
, rx
, 32, len
/ 4);
729 sh_msiof_write(p
, IER
, ier_bits
);
731 reinit_completion(&p
->done
);
735 dma_async_issue_pending(p
->master
->dma_rx
);
737 dma_async_issue_pending(p
->master
->dma_tx
);
739 ret
= sh_msiof_spi_start(p
, rx
);
741 dev_err(&p
->pdev
->dev
, "failed to start hardware\n");
745 /* wait for tx fifo to be emptied / rx fifo to be filled */
746 if (!wait_for_completion_timeout(&p
->done
, HZ
)) {
747 dev_err(&p
->pdev
->dev
, "DMA timeout\n");
752 /* clear status bits */
753 sh_msiof_reset_str(p
);
755 ret
= sh_msiof_spi_stop(p
, rx
);
757 dev_err(&p
->pdev
->dev
, "failed to shut down hardware\n");
762 dma_sync_single_for_cpu(p
->master
->dma_rx
->device
->dev
,
769 sh_msiof_reset_str(p
);
770 sh_msiof_spi_stop(p
, rx
);
773 dmaengine_terminate_all(p
->master
->dma_tx
);
776 dmaengine_terminate_all(p
->master
->dma_rx
);
777 sh_msiof_write(p
, IER
, 0);
781 static void copy_bswap32(u32
*dst
, const u32
*src
, unsigned int words
)
783 /* src or dst can be unaligned, but not both */
784 if ((unsigned long)src
& 3) {
786 *dst
++ = swab32(get_unaligned(src
));
789 } else if ((unsigned long)dst
& 3) {
791 put_unaligned(swab32(*src
++), dst
);
796 *dst
++ = swab32(*src
++);
800 static void copy_wswap32(u32
*dst
, const u32
*src
, unsigned int words
)
802 /* src or dst can be unaligned, but not both */
803 if ((unsigned long)src
& 3) {
805 *dst
++ = swahw32(get_unaligned(src
));
808 } else if ((unsigned long)dst
& 3) {
810 put_unaligned(swahw32(*src
++), dst
);
815 *dst
++ = swahw32(*src
++);
819 static void copy_plain32(u32
*dst
, const u32
*src
, unsigned int words
)
821 memcpy(dst
, src
, words
* 4);
824 static int sh_msiof_transfer_one(struct spi_master
*master
,
825 struct spi_device
*spi
,
826 struct spi_transfer
*t
)
828 struct sh_msiof_spi_priv
*p
= spi_master_get_devdata(master
);
829 void (*copy32
)(u32
*, const u32
*, unsigned int);
830 void (*tx_fifo
)(struct sh_msiof_spi_priv
*, const void *, int, int);
831 void (*rx_fifo
)(struct sh_msiof_spi_priv
*, void *, int, int);
832 const void *tx_buf
= t
->tx_buf
;
833 void *rx_buf
= t
->rx_buf
;
834 unsigned int len
= t
->len
;
835 unsigned int bits
= t
->bits_per_word
;
836 unsigned int bytes_per_word
;
842 /* setup clocks (clock already enabled in chipselect()) */
843 sh_msiof_spi_set_clk_regs(p
, clk_get_rate(p
->clk
), t
->speed_hz
);
845 while (master
->dma_tx
&& len
> 15) {
847 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
848 * words, with byte resp. word swapping.
853 l
= min(len
, p
->tx_fifo_size
* 4);
855 l
= min(len
, p
->rx_fifo_size
* 4);
860 copy32
= copy_bswap32
;
861 } else if (bits
<= 16) {
864 copy32
= copy_wswap32
;
866 copy32
= copy_plain32
;
870 copy32(p
->tx_dma_page
, tx_buf
, l
/ 4);
872 ret
= sh_msiof_dma_once(p
, tx_buf
, rx_buf
, l
);
873 if (ret
== -EAGAIN
) {
874 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
875 dev_driver_string(&p
->pdev
->dev
),
876 dev_name(&p
->pdev
->dev
));
883 copy32(rx_buf
, p
->rx_dma_page
, l
/ 4);
894 if (bits
<= 8 && len
> 15 && !(len
& 3)) {
901 /* setup bytes per word and fifo read/write functions */
904 tx_fifo
= sh_msiof_spi_write_fifo_8
;
905 rx_fifo
= sh_msiof_spi_read_fifo_8
;
906 } else if (bits
<= 16) {
908 if ((unsigned long)tx_buf
& 0x01)
909 tx_fifo
= sh_msiof_spi_write_fifo_16u
;
911 tx_fifo
= sh_msiof_spi_write_fifo_16
;
913 if ((unsigned long)rx_buf
& 0x01)
914 rx_fifo
= sh_msiof_spi_read_fifo_16u
;
916 rx_fifo
= sh_msiof_spi_read_fifo_16
;
919 if ((unsigned long)tx_buf
& 0x03)
920 tx_fifo
= sh_msiof_spi_write_fifo_s32u
;
922 tx_fifo
= sh_msiof_spi_write_fifo_s32
;
924 if ((unsigned long)rx_buf
& 0x03)
925 rx_fifo
= sh_msiof_spi_read_fifo_s32u
;
927 rx_fifo
= sh_msiof_spi_read_fifo_s32
;
930 if ((unsigned long)tx_buf
& 0x03)
931 tx_fifo
= sh_msiof_spi_write_fifo_32u
;
933 tx_fifo
= sh_msiof_spi_write_fifo_32
;
935 if ((unsigned long)rx_buf
& 0x03)
936 rx_fifo
= sh_msiof_spi_read_fifo_32u
;
938 rx_fifo
= sh_msiof_spi_read_fifo_32
;
941 /* transfer in fifo sized chunks */
942 words
= len
/ bytes_per_word
;
945 n
= sh_msiof_spi_txrx_once(p
, tx_fifo
, rx_fifo
, tx_buf
, rx_buf
,
951 tx_buf
+= n
* bytes_per_word
;
953 rx_buf
+= n
* bytes_per_word
;
960 static const struct sh_msiof_chipdata sh_data
= {
966 static const struct sh_msiof_chipdata r8a779x_data
= {
969 .master_flags
= SPI_MASTER_MUST_TX
,
972 static const struct of_device_id sh_msiof_match
[] = {
973 { .compatible
= "renesas,sh-msiof", .data
= &sh_data
},
974 { .compatible
= "renesas,sh-mobile-msiof", .data
= &sh_data
},
975 { .compatible
= "renesas,msiof-r8a7790", .data
= &r8a779x_data
},
976 { .compatible
= "renesas,msiof-r8a7791", .data
= &r8a779x_data
},
977 { .compatible
= "renesas,msiof-r8a7792", .data
= &r8a779x_data
},
978 { .compatible
= "renesas,msiof-r8a7793", .data
= &r8a779x_data
},
979 { .compatible
= "renesas,msiof-r8a7794", .data
= &r8a779x_data
},
982 MODULE_DEVICE_TABLE(of
, sh_msiof_match
);
985 static struct sh_msiof_spi_info
*sh_msiof_spi_parse_dt(struct device
*dev
)
987 struct sh_msiof_spi_info
*info
;
988 struct device_node
*np
= dev
->of_node
;
991 info
= devm_kzalloc(dev
, sizeof(struct sh_msiof_spi_info
), GFP_KERNEL
);
995 /* Parse the MSIOF properties */
996 of_property_read_u32(np
, "num-cs", &num_cs
);
997 of_property_read_u32(np
, "renesas,tx-fifo-size",
998 &info
->tx_fifo_override
);
999 of_property_read_u32(np
, "renesas,rx-fifo-size",
1000 &info
->rx_fifo_override
);
1001 of_property_read_u32(np
, "renesas,dtdl", &info
->dtdl
);
1002 of_property_read_u32(np
, "renesas,syncdl", &info
->syncdl
);
1004 info
->num_chipselect
= num_cs
;
1009 static struct sh_msiof_spi_info
*sh_msiof_spi_parse_dt(struct device
*dev
)
1015 static struct dma_chan
*sh_msiof_request_dma_chan(struct device
*dev
,
1016 enum dma_transfer_direction dir
, unsigned int id
, dma_addr_t port_addr
)
1018 dma_cap_mask_t mask
;
1019 struct dma_chan
*chan
;
1020 struct dma_slave_config cfg
;
1024 dma_cap_set(DMA_SLAVE
, mask
);
1026 chan
= dma_request_slave_channel_compat(mask
, shdma_chan_filter
,
1027 (void *)(unsigned long)id
, dev
,
1028 dir
== DMA_MEM_TO_DEV
? "tx" : "rx");
1030 dev_warn(dev
, "dma_request_slave_channel_compat failed\n");
1034 memset(&cfg
, 0, sizeof(cfg
));
1035 cfg
.direction
= dir
;
1036 if (dir
== DMA_MEM_TO_DEV
) {
1037 cfg
.dst_addr
= port_addr
;
1038 cfg
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1040 cfg
.src_addr
= port_addr
;
1041 cfg
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1044 ret
= dmaengine_slave_config(chan
, &cfg
);
1046 dev_warn(dev
, "dmaengine_slave_config failed %d\n", ret
);
1047 dma_release_channel(chan
);
1054 static int sh_msiof_request_dma(struct sh_msiof_spi_priv
*p
)
1056 struct platform_device
*pdev
= p
->pdev
;
1057 struct device
*dev
= &pdev
->dev
;
1058 const struct sh_msiof_spi_info
*info
= dev_get_platdata(dev
);
1059 unsigned int dma_tx_id
, dma_rx_id
;
1060 const struct resource
*res
;
1061 struct spi_master
*master
;
1062 struct device
*tx_dev
, *rx_dev
;
1065 /* In the OF case we will get the slave IDs from the DT */
1068 } else if (info
&& info
->dma_tx_id
&& info
->dma_rx_id
) {
1069 dma_tx_id
= info
->dma_tx_id
;
1070 dma_rx_id
= info
->dma_rx_id
;
1072 /* The driver assumes no error */
1076 /* The DMA engine uses the second register set, if present */
1077 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1079 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1082 master
->dma_tx
= sh_msiof_request_dma_chan(dev
, DMA_MEM_TO_DEV
,
1085 if (!master
->dma_tx
)
1088 master
->dma_rx
= sh_msiof_request_dma_chan(dev
, DMA_DEV_TO_MEM
,
1091 if (!master
->dma_rx
)
1094 p
->tx_dma_page
= (void *)__get_free_page(GFP_KERNEL
| GFP_DMA
);
1095 if (!p
->tx_dma_page
)
1098 p
->rx_dma_page
= (void *)__get_free_page(GFP_KERNEL
| GFP_DMA
);
1099 if (!p
->rx_dma_page
)
1102 tx_dev
= master
->dma_tx
->device
->dev
;
1103 p
->tx_dma_addr
= dma_map_single(tx_dev
, p
->tx_dma_page
, PAGE_SIZE
,
1105 if (dma_mapping_error(tx_dev
, p
->tx_dma_addr
))
1108 rx_dev
= master
->dma_rx
->device
->dev
;
1109 p
->rx_dma_addr
= dma_map_single(rx_dev
, p
->rx_dma_page
, PAGE_SIZE
,
1111 if (dma_mapping_error(rx_dev
, p
->rx_dma_addr
))
1114 dev_info(dev
, "DMA available");
1118 dma_unmap_single(tx_dev
, p
->tx_dma_addr
, PAGE_SIZE
, DMA_TO_DEVICE
);
1120 free_page((unsigned long)p
->rx_dma_page
);
1122 free_page((unsigned long)p
->tx_dma_page
);
1124 dma_release_channel(master
->dma_rx
);
1126 dma_release_channel(master
->dma_tx
);
1127 master
->dma_tx
= NULL
;
1131 static void sh_msiof_release_dma(struct sh_msiof_spi_priv
*p
)
1133 struct spi_master
*master
= p
->master
;
1136 if (!master
->dma_tx
)
1139 dev
= &p
->pdev
->dev
;
1140 dma_unmap_single(master
->dma_rx
->device
->dev
, p
->rx_dma_addr
,
1141 PAGE_SIZE
, DMA_FROM_DEVICE
);
1142 dma_unmap_single(master
->dma_tx
->device
->dev
, p
->tx_dma_addr
,
1143 PAGE_SIZE
, DMA_TO_DEVICE
);
1144 free_page((unsigned long)p
->rx_dma_page
);
1145 free_page((unsigned long)p
->tx_dma_page
);
1146 dma_release_channel(master
->dma_rx
);
1147 dma_release_channel(master
->dma_tx
);
1150 static int sh_msiof_spi_probe(struct platform_device
*pdev
)
1153 struct spi_master
*master
;
1154 const struct sh_msiof_chipdata
*chipdata
;
1155 const struct of_device_id
*of_id
;
1156 struct sh_msiof_spi_priv
*p
;
1160 master
= spi_alloc_master(&pdev
->dev
, sizeof(struct sh_msiof_spi_priv
));
1161 if (master
== NULL
) {
1162 dev_err(&pdev
->dev
, "failed to allocate spi master\n");
1166 p
= spi_master_get_devdata(master
);
1168 platform_set_drvdata(pdev
, p
);
1171 of_id
= of_match_device(sh_msiof_match
, &pdev
->dev
);
1173 chipdata
= of_id
->data
;
1174 p
->info
= sh_msiof_spi_parse_dt(&pdev
->dev
);
1176 chipdata
= (const void *)pdev
->id_entry
->driver_data
;
1177 p
->info
= dev_get_platdata(&pdev
->dev
);
1181 dev_err(&pdev
->dev
, "failed to obtain device info\n");
1186 init_completion(&p
->done
);
1188 p
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1189 if (IS_ERR(p
->clk
)) {
1190 dev_err(&pdev
->dev
, "cannot get clock\n");
1191 ret
= PTR_ERR(p
->clk
);
1195 i
= platform_get_irq(pdev
, 0);
1197 dev_err(&pdev
->dev
, "cannot get platform IRQ\n");
1202 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1203 p
->mapbase
= devm_ioremap_resource(&pdev
->dev
, r
);
1204 if (IS_ERR(p
->mapbase
)) {
1205 ret
= PTR_ERR(p
->mapbase
);
1209 ret
= devm_request_irq(&pdev
->dev
, i
, sh_msiof_spi_irq
, 0,
1210 dev_name(&pdev
->dev
), p
);
1212 dev_err(&pdev
->dev
, "unable to request irq\n");
1217 pm_runtime_enable(&pdev
->dev
);
1219 /* Platform data may override FIFO sizes */
1220 p
->tx_fifo_size
= chipdata
->tx_fifo_size
;
1221 p
->rx_fifo_size
= chipdata
->rx_fifo_size
;
1222 if (p
->info
->tx_fifo_override
)
1223 p
->tx_fifo_size
= p
->info
->tx_fifo_override
;
1224 if (p
->info
->rx_fifo_override
)
1225 p
->rx_fifo_size
= p
->info
->rx_fifo_override
;
1227 /* init master code */
1228 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1229 master
->mode_bits
|= SPI_LSB_FIRST
| SPI_3WIRE
;
1230 master
->flags
= chipdata
->master_flags
;
1231 master
->bus_num
= pdev
->id
;
1232 master
->dev
.of_node
= pdev
->dev
.of_node
;
1233 master
->num_chipselect
= p
->info
->num_chipselect
;
1234 master
->setup
= sh_msiof_spi_setup
;
1235 master
->prepare_message
= sh_msiof_prepare_message
;
1236 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(8, 32);
1237 master
->auto_runtime_pm
= true;
1238 master
->transfer_one
= sh_msiof_transfer_one
;
1240 ret
= sh_msiof_request_dma(p
);
1242 dev_warn(&pdev
->dev
, "DMA not available, using PIO\n");
1244 ret
= devm_spi_register_master(&pdev
->dev
, master
);
1246 dev_err(&pdev
->dev
, "spi_register_master error.\n");
1253 sh_msiof_release_dma(p
);
1254 pm_runtime_disable(&pdev
->dev
);
1256 spi_master_put(master
);
1260 static int sh_msiof_spi_remove(struct platform_device
*pdev
)
1262 struct sh_msiof_spi_priv
*p
= platform_get_drvdata(pdev
);
1264 sh_msiof_release_dma(p
);
1265 pm_runtime_disable(&pdev
->dev
);
1269 static const struct platform_device_id spi_driver_ids
[] = {
1270 { "spi_sh_msiof", (kernel_ulong_t
)&sh_data
},
1273 MODULE_DEVICE_TABLE(platform
, spi_driver_ids
);
1275 static struct platform_driver sh_msiof_spi_drv
= {
1276 .probe
= sh_msiof_spi_probe
,
1277 .remove
= sh_msiof_spi_remove
,
1278 .id_table
= spi_driver_ids
,
1280 .name
= "spi_sh_msiof",
1281 .of_match_table
= of_match_ptr(sh_msiof_match
),
1284 module_platform_driver(sh_msiof_spi_drv
);
1286 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1287 MODULE_AUTHOR("Magnus Damm");
1288 MODULE_LICENSE("GPL v2");
1289 MODULE_ALIAS("platform:spi_sh_msiof");