2 * SPI bus driver for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
16 #include <linux/bitops.h>
17 #include <linux/err.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_gpio.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/spi_bitbang.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-direction.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/sirfsoc_dma.h>
27 #define DRIVER_NAME "sirfsoc_spi"
29 #define SIRFSOC_SPI_CTRL 0x0000
30 #define SIRFSOC_SPI_CMD 0x0004
31 #define SIRFSOC_SPI_TX_RX_EN 0x0008
32 #define SIRFSOC_SPI_INT_EN 0x000C
33 #define SIRFSOC_SPI_INT_STATUS 0x0010
34 #define SIRFSOC_SPI_TX_DMA_IO_CTRL 0x0100
35 #define SIRFSOC_SPI_TX_DMA_IO_LEN 0x0104
36 #define SIRFSOC_SPI_TXFIFO_CTRL 0x0108
37 #define SIRFSOC_SPI_TXFIFO_LEVEL_CHK 0x010C
38 #define SIRFSOC_SPI_TXFIFO_OP 0x0110
39 #define SIRFSOC_SPI_TXFIFO_STATUS 0x0114
40 #define SIRFSOC_SPI_TXFIFO_DATA 0x0118
41 #define SIRFSOC_SPI_RX_DMA_IO_CTRL 0x0120
42 #define SIRFSOC_SPI_RX_DMA_IO_LEN 0x0124
43 #define SIRFSOC_SPI_RXFIFO_CTRL 0x0128
44 #define SIRFSOC_SPI_RXFIFO_LEVEL_CHK 0x012C
45 #define SIRFSOC_SPI_RXFIFO_OP 0x0130
46 #define SIRFSOC_SPI_RXFIFO_STATUS 0x0134
47 #define SIRFSOC_SPI_RXFIFO_DATA 0x0138
48 #define SIRFSOC_SPI_DUMMY_DELAY_CTL 0x0144
50 /* SPI CTRL register defines */
51 #define SIRFSOC_SPI_SLV_MODE BIT(16)
52 #define SIRFSOC_SPI_CMD_MODE BIT(17)
53 #define SIRFSOC_SPI_CS_IO_OUT BIT(18)
54 #define SIRFSOC_SPI_CS_IO_MODE BIT(19)
55 #define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20)
56 #define SIRFSOC_SPI_CS_IDLE_STAT BIT(21)
57 #define SIRFSOC_SPI_TRAN_MSB BIT(22)
58 #define SIRFSOC_SPI_DRV_POS_EDGE BIT(23)
59 #define SIRFSOC_SPI_CS_HOLD_TIME BIT(24)
60 #define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25)
61 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26)
62 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26)
63 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26)
64 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26)
65 #define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28)
66 #define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30)
67 #define SIRFSOC_SPI_MUL_DAT_MODE BIT(31)
69 /* Interrupt Enable */
70 #define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0)
71 #define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1)
72 #define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2)
73 #define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3)
74 #define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4)
75 #define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5)
76 #define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6)
77 #define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
78 #define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8)
79 #define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9)
80 #define SIRFSOC_SPI_FRM_END_INT_EN BIT(10)
82 #define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF
84 /* Interrupt status */
85 #define SIRFSOC_SPI_RX_DONE BIT(0)
86 #define SIRFSOC_SPI_TX_DONE BIT(1)
87 #define SIRFSOC_SPI_RX_OFLOW BIT(2)
88 #define SIRFSOC_SPI_TX_UFLOW BIT(3)
89 #define SIRFSOC_SPI_RX_FIFO_FULL BIT(6)
90 #define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7)
91 #define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8)
92 #define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9)
93 #define SIRFSOC_SPI_FRM_END BIT(10)
96 #define SIRFSOC_SPI_RX_EN BIT(0)
97 #define SIRFSOC_SPI_TX_EN BIT(1)
98 #define SIRFSOC_SPI_CMD_TX_EN BIT(2)
100 #define SIRFSOC_SPI_IO_MODE_SEL BIT(0)
101 #define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2)
104 #define SIRFSOC_SPI_FIFO_RESET BIT(0)
105 #define SIRFSOC_SPI_FIFO_START BIT(1)
108 #define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0)
109 #define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0)
110 #define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0)
113 #define SIRFSOC_SPI_FIFO_LEVEL_MASK 0xFF
114 #define SIRFSOC_SPI_FIFO_FULL BIT(8)
115 #define SIRFSOC_SPI_FIFO_EMPTY BIT(9)
117 /* 256 bytes rx/tx FIFO */
118 #define SIRFSOC_SPI_FIFO_SIZE 256
119 #define SIRFSOC_SPI_DAT_FRM_LEN_MAX (64 * 1024)
121 #define SIRFSOC_SPI_FIFO_SC(x) ((x) & 0x3F)
122 #define SIRFSOC_SPI_FIFO_LC(x) (((x) & 0x3F) << 10)
123 #define SIRFSOC_SPI_FIFO_HC(x) (((x) & 0x3F) << 20)
124 #define SIRFSOC_SPI_FIFO_THD(x) (((x) & 0xFF) << 2)
127 * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
128 * due to the limitation of dma controller
131 #define ALIGNED(x) (!((u32)x & 0x3))
132 #define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
133 ALIGNED(x->len * sspi->word_width) && (x->len * sspi->word_width < \
137 struct spi_bitbang bitbang
;
138 struct completion rx_done
;
139 struct completion tx_done
;
142 u32 ctrl_freq
; /* SPI controller clock speed */
145 /* rx & tx bufs from the spi_transfer */
149 /* place received word into rx buffer */
150 void (*rx_word
) (struct sirfsoc_spi
*);
151 /* get word from tx buffer for sending */
152 void (*tx_word
) (struct sirfsoc_spi
*);
154 /* number of words left to be tranmitted/received */
155 unsigned int left_tx_cnt
;
156 unsigned int left_rx_cnt
;
158 /* rx & tx DMA channels */
159 struct dma_chan
*rx_chan
;
160 struct dma_chan
*tx_chan
;
161 dma_addr_t src_start
;
162 dma_addr_t dst_start
;
164 int word_width
; /* in bytes */
169 static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi
*sspi
)
174 data
= readl(sspi
->base
+ SIRFSOC_SPI_RXFIFO_DATA
);
184 static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi
*sspi
)
187 const u8
*tx
= sspi
->tx
;
194 writel(data
, sspi
->base
+ SIRFSOC_SPI_TXFIFO_DATA
);
198 static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi
*sspi
)
203 data
= readl(sspi
->base
+ SIRFSOC_SPI_RXFIFO_DATA
);
213 static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi
*sspi
)
216 const u16
*tx
= sspi
->tx
;
223 writel(data
, sspi
->base
+ SIRFSOC_SPI_TXFIFO_DATA
);
227 static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi
*sspi
)
232 data
= readl(sspi
->base
+ SIRFSOC_SPI_RXFIFO_DATA
);
243 static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi
*sspi
)
246 const u32
*tx
= sspi
->tx
;
253 writel(data
, sspi
->base
+ SIRFSOC_SPI_TXFIFO_DATA
);
257 static irqreturn_t
spi_sirfsoc_irq(int irq
, void *dev_id
)
259 struct sirfsoc_spi
*sspi
= dev_id
;
260 u32 spi_stat
= readl(sspi
->base
+ SIRFSOC_SPI_INT_STATUS
);
262 writel(spi_stat
, sspi
->base
+ SIRFSOC_SPI_INT_STATUS
);
264 /* Error Conditions */
265 if (spi_stat
& SIRFSOC_SPI_RX_OFLOW
||
266 spi_stat
& SIRFSOC_SPI_TX_UFLOW
) {
267 complete(&sspi
->rx_done
);
268 writel(0x0, sspi
->base
+ SIRFSOC_SPI_INT_EN
);
271 if (spi_stat
& (SIRFSOC_SPI_FRM_END
272 | SIRFSOC_SPI_RXFIFO_THD_REACH
))
273 while (!((readl(sspi
->base
+ SIRFSOC_SPI_RXFIFO_STATUS
)
274 & SIRFSOC_SPI_FIFO_EMPTY
)) &&
278 if (spi_stat
& (SIRFSOC_SPI_FIFO_EMPTY
279 | SIRFSOC_SPI_TXFIFO_THD_REACH
))
280 while (!((readl(sspi
->base
+ SIRFSOC_SPI_TXFIFO_STATUS
)
281 & SIRFSOC_SPI_FIFO_FULL
)) &&
285 /* Received all words */
286 if ((sspi
->left_rx_cnt
== 0) && (sspi
->left_tx_cnt
== 0)) {
287 complete(&sspi
->rx_done
);
288 writel(0x0, sspi
->base
+ SIRFSOC_SPI_INT_EN
);
293 static void spi_sirfsoc_dma_fini_callback(void *data
)
295 struct completion
*dma_complete
= data
;
297 complete(dma_complete
);
300 static int spi_sirfsoc_transfer(struct spi_device
*spi
, struct spi_transfer
*t
)
302 struct sirfsoc_spi
*sspi
;
303 int timeout
= t
->len
* 10;
304 sspi
= spi_master_get_devdata(spi
->master
);
306 sspi
->tx
= t
->tx_buf
? t
->tx_buf
: sspi
->dummypage
;
307 sspi
->rx
= t
->rx_buf
? t
->rx_buf
: sspi
->dummypage
;
308 sspi
->left_tx_cnt
= sspi
->left_rx_cnt
= t
->len
;
309 INIT_COMPLETION(sspi
->rx_done
);
310 INIT_COMPLETION(sspi
->tx_done
);
312 writel(SIRFSOC_SPI_INT_MASK_ALL
, sspi
->base
+ SIRFSOC_SPI_INT_STATUS
);
315 writel(readl(sspi
->base
+ SIRFSOC_SPI_CTRL
) |
316 SIRFSOC_SPI_ENA_AUTO_CLR
,
317 sspi
->base
+ SIRFSOC_SPI_CTRL
);
318 writel(0, sspi
->base
+ SIRFSOC_SPI_TX_DMA_IO_LEN
);
319 writel(0, sspi
->base
+ SIRFSOC_SPI_RX_DMA_IO_LEN
);
320 } else if ((t
->len
> 1) && (t
->len
< SIRFSOC_SPI_DAT_FRM_LEN_MAX
)) {
321 writel(readl(sspi
->base
+ SIRFSOC_SPI_CTRL
) |
322 SIRFSOC_SPI_MUL_DAT_MODE
|
323 SIRFSOC_SPI_ENA_AUTO_CLR
,
324 sspi
->base
+ SIRFSOC_SPI_CTRL
);
325 writel(t
->len
- 1, sspi
->base
+ SIRFSOC_SPI_TX_DMA_IO_LEN
);
326 writel(t
->len
- 1, sspi
->base
+ SIRFSOC_SPI_RX_DMA_IO_LEN
);
328 writel(readl(sspi
->base
+ SIRFSOC_SPI_CTRL
),
329 sspi
->base
+ SIRFSOC_SPI_CTRL
);
330 writel(0, sspi
->base
+ SIRFSOC_SPI_TX_DMA_IO_LEN
);
331 writel(0, sspi
->base
+ SIRFSOC_SPI_RX_DMA_IO_LEN
);
334 writel(SIRFSOC_SPI_FIFO_RESET
, sspi
->base
+ SIRFSOC_SPI_RXFIFO_OP
);
335 writel(SIRFSOC_SPI_FIFO_RESET
, sspi
->base
+ SIRFSOC_SPI_TXFIFO_OP
);
336 writel(SIRFSOC_SPI_FIFO_START
, sspi
->base
+ SIRFSOC_SPI_RXFIFO_OP
);
337 writel(SIRFSOC_SPI_FIFO_START
, sspi
->base
+ SIRFSOC_SPI_TXFIFO_OP
);
339 if (IS_DMA_VALID(t
)) {
340 struct dma_async_tx_descriptor
*rx_desc
, *tx_desc
;
341 unsigned int size
= t
->len
* sspi
->word_width
;
343 sspi
->dst_start
= dma_map_single(&spi
->dev
, sspi
->rx
, t
->len
, DMA_FROM_DEVICE
);
344 rx_desc
= dmaengine_prep_slave_single(sspi
->rx_chan
,
345 sspi
->dst_start
, size
, DMA_DEV_TO_MEM
,
346 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
347 rx_desc
->callback
= spi_sirfsoc_dma_fini_callback
;
348 rx_desc
->callback_param
= &sspi
->rx_done
;
350 sspi
->src_start
= dma_map_single(&spi
->dev
, (void *)sspi
->tx
, t
->len
, DMA_TO_DEVICE
);
351 tx_desc
= dmaengine_prep_slave_single(sspi
->tx_chan
,
352 sspi
->src_start
, size
, DMA_MEM_TO_DEV
,
353 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
354 tx_desc
->callback
= spi_sirfsoc_dma_fini_callback
;
355 tx_desc
->callback_param
= &sspi
->tx_done
;
357 dmaengine_submit(tx_desc
);
358 dmaengine_submit(rx_desc
);
359 dma_async_issue_pending(sspi
->tx_chan
);
360 dma_async_issue_pending(sspi
->rx_chan
);
362 /* Send the first word to trigger the whole tx/rx process */
365 writel(SIRFSOC_SPI_RX_OFLOW_INT_EN
| SIRFSOC_SPI_TX_UFLOW_INT_EN
|
366 SIRFSOC_SPI_RXFIFO_THD_INT_EN
| SIRFSOC_SPI_TXFIFO_THD_INT_EN
|
367 SIRFSOC_SPI_FRM_END_INT_EN
| SIRFSOC_SPI_RXFIFO_FULL_INT_EN
|
368 SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN
, sspi
->base
+ SIRFSOC_SPI_INT_EN
);
371 writel(SIRFSOC_SPI_RX_EN
| SIRFSOC_SPI_TX_EN
, sspi
->base
+ SIRFSOC_SPI_TX_RX_EN
);
373 if (!IS_DMA_VALID(t
)) { /* for PIO */
374 if (wait_for_completion_timeout(&sspi
->rx_done
, timeout
) == 0)
375 dev_err(&spi
->dev
, "transfer timeout\n");
376 } else if (wait_for_completion_timeout(&sspi
->rx_done
, timeout
) == 0) {
377 dev_err(&spi
->dev
, "transfer timeout\n");
378 dmaengine_terminate_all(sspi
->rx_chan
);
380 sspi
->left_rx_cnt
= 0;
383 * we only wait tx-done event if transferring by DMA. for PIO,
384 * we get rx data by writing tx data, so if rx is done, tx has
387 if (IS_DMA_VALID(t
)) {
388 if (wait_for_completion_timeout(&sspi
->tx_done
, timeout
) == 0) {
389 dev_err(&spi
->dev
, "transfer timeout\n");
390 dmaengine_terminate_all(sspi
->tx_chan
);
394 if (IS_DMA_VALID(t
)) {
395 dma_unmap_single(&spi
->dev
, sspi
->src_start
, t
->len
, DMA_TO_DEVICE
);
396 dma_unmap_single(&spi
->dev
, sspi
->dst_start
, t
->len
, DMA_FROM_DEVICE
);
399 /* TX, RX FIFO stop */
400 writel(0, sspi
->base
+ SIRFSOC_SPI_RXFIFO_OP
);
401 writel(0, sspi
->base
+ SIRFSOC_SPI_TXFIFO_OP
);
402 writel(0, sspi
->base
+ SIRFSOC_SPI_TX_RX_EN
);
403 writel(0, sspi
->base
+ SIRFSOC_SPI_INT_EN
);
405 return t
->len
- sspi
->left_rx_cnt
;
408 static void spi_sirfsoc_chipselect(struct spi_device
*spi
, int value
)
410 struct sirfsoc_spi
*sspi
= spi_master_get_devdata(spi
->master
);
412 if (sspi
->chipselect
[spi
->chip_select
] == 0) {
413 u32 regval
= readl(sspi
->base
+ SIRFSOC_SPI_CTRL
);
415 case BITBANG_CS_ACTIVE
:
416 if (spi
->mode
& SPI_CS_HIGH
)
417 regval
|= SIRFSOC_SPI_CS_IO_OUT
;
419 regval
&= ~SIRFSOC_SPI_CS_IO_OUT
;
421 case BITBANG_CS_INACTIVE
:
422 if (spi
->mode
& SPI_CS_HIGH
)
423 regval
&= ~SIRFSOC_SPI_CS_IO_OUT
;
425 regval
|= SIRFSOC_SPI_CS_IO_OUT
;
428 writel(regval
, sspi
->base
+ SIRFSOC_SPI_CTRL
);
430 int gpio
= sspi
->chipselect
[spi
->chip_select
];
431 gpio_direction_output(gpio
, spi
->mode
& SPI_CS_HIGH
? 0 : 1);
436 spi_sirfsoc_setup_transfer(struct spi_device
*spi
, struct spi_transfer
*t
)
438 struct sirfsoc_spi
*sspi
;
439 u8 bits_per_word
= 0;
442 u32 txfifo_ctrl
, rxfifo_ctrl
;
443 u32 fifo_size
= SIRFSOC_SPI_FIFO_SIZE
/ 4;
445 sspi
= spi_master_get_devdata(spi
->master
);
447 bits_per_word
= (t
) ? t
->bits_per_word
: spi
->bits_per_word
;
448 hz
= t
&& t
->speed_hz
? t
->speed_hz
: spi
->max_speed_hz
;
450 regval
= (sspi
->ctrl_freq
/ (2 * hz
)) - 1;
451 if (regval
> 0xFFFF || regval
< 0) {
452 dev_err(&spi
->dev
, "Speed %d not supported\n", hz
);
456 switch (bits_per_word
) {
458 regval
|= SIRFSOC_SPI_TRAN_DAT_FORMAT_8
;
459 sspi
->rx_word
= spi_sirfsoc_rx_word_u8
;
460 sspi
->tx_word
= spi_sirfsoc_tx_word_u8
;
461 txfifo_ctrl
= SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE
/ 2) |
462 SIRFSOC_SPI_FIFO_WIDTH_BYTE
;
463 rxfifo_ctrl
= SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE
/ 2) |
464 SIRFSOC_SPI_FIFO_WIDTH_BYTE
;
465 sspi
->word_width
= 1;
469 regval
|= (bits_per_word
== 12) ? SIRFSOC_SPI_TRAN_DAT_FORMAT_12
:
470 SIRFSOC_SPI_TRAN_DAT_FORMAT_16
;
471 sspi
->rx_word
= spi_sirfsoc_rx_word_u16
;
472 sspi
->tx_word
= spi_sirfsoc_tx_word_u16
;
473 txfifo_ctrl
= SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE
/ 2) |
474 SIRFSOC_SPI_FIFO_WIDTH_WORD
;
475 rxfifo_ctrl
= SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE
/ 2) |
476 SIRFSOC_SPI_FIFO_WIDTH_WORD
;
477 sspi
->word_width
= 2;
480 regval
|= SIRFSOC_SPI_TRAN_DAT_FORMAT_32
;
481 sspi
->rx_word
= spi_sirfsoc_rx_word_u32
;
482 sspi
->tx_word
= spi_sirfsoc_tx_word_u32
;
483 txfifo_ctrl
= SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE
/ 2) |
484 SIRFSOC_SPI_FIFO_WIDTH_DWORD
;
485 rxfifo_ctrl
= SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE
/ 2) |
486 SIRFSOC_SPI_FIFO_WIDTH_DWORD
;
487 sspi
->word_width
= 4;
493 if (!(spi
->mode
& SPI_CS_HIGH
))
494 regval
|= SIRFSOC_SPI_CS_IDLE_STAT
;
495 if (!(spi
->mode
& SPI_LSB_FIRST
))
496 regval
|= SIRFSOC_SPI_TRAN_MSB
;
497 if (spi
->mode
& SPI_CPOL
)
498 regval
|= SIRFSOC_SPI_CLK_IDLE_STAT
;
501 * Data should be driven at least 1/2 cycle before the fetch edge to make
502 * sure that data gets stable at the fetch edge.
504 if (((spi
->mode
& SPI_CPOL
) && (spi
->mode
& SPI_CPHA
)) ||
505 (!(spi
->mode
& SPI_CPOL
) && !(spi
->mode
& SPI_CPHA
)))
506 regval
&= ~SIRFSOC_SPI_DRV_POS_EDGE
;
508 regval
|= SIRFSOC_SPI_DRV_POS_EDGE
;
510 writel(SIRFSOC_SPI_FIFO_SC(fifo_size
- 2) |
511 SIRFSOC_SPI_FIFO_LC(fifo_size
/ 2) |
512 SIRFSOC_SPI_FIFO_HC(2),
513 sspi
->base
+ SIRFSOC_SPI_TXFIFO_LEVEL_CHK
);
514 writel(SIRFSOC_SPI_FIFO_SC(2) |
515 SIRFSOC_SPI_FIFO_LC(fifo_size
/ 2) |
516 SIRFSOC_SPI_FIFO_HC(fifo_size
- 2),
517 sspi
->base
+ SIRFSOC_SPI_RXFIFO_LEVEL_CHK
);
518 writel(txfifo_ctrl
, sspi
->base
+ SIRFSOC_SPI_TXFIFO_CTRL
);
519 writel(rxfifo_ctrl
, sspi
->base
+ SIRFSOC_SPI_RXFIFO_CTRL
);
521 writel(regval
, sspi
->base
+ SIRFSOC_SPI_CTRL
);
523 if (IS_DMA_VALID(t
)) {
524 /* Enable DMA mode for RX, TX */
525 writel(0, sspi
->base
+ SIRFSOC_SPI_TX_DMA_IO_CTRL
);
526 writel(SIRFSOC_SPI_RX_DMA_FLUSH
, sspi
->base
+ SIRFSOC_SPI_RX_DMA_IO_CTRL
);
528 /* Enable IO mode for RX, TX */
529 writel(SIRFSOC_SPI_IO_MODE_SEL
, sspi
->base
+ SIRFSOC_SPI_TX_DMA_IO_CTRL
);
530 writel(SIRFSOC_SPI_IO_MODE_SEL
, sspi
->base
+ SIRFSOC_SPI_RX_DMA_IO_CTRL
);
536 static int spi_sirfsoc_setup(struct spi_device
*spi
)
538 struct sirfsoc_spi
*sspi
;
540 if (!spi
->max_speed_hz
)
543 sspi
= spi_master_get_devdata(spi
->master
);
545 if (!spi
->bits_per_word
)
546 spi
->bits_per_word
= 8;
548 return spi_sirfsoc_setup_transfer(spi
, NULL
);
551 static int spi_sirfsoc_probe(struct platform_device
*pdev
)
553 struct sirfsoc_spi
*sspi
;
554 struct spi_master
*master
;
555 struct resource
*mem_res
;
556 int num_cs
, cs_gpio
, irq
;
557 u32 rx_dma_ch
, tx_dma_ch
;
558 dma_cap_mask_t dma_cap_mask
;
562 ret
= of_property_read_u32(pdev
->dev
.of_node
,
563 "sirf,spi-num-chipselects", &num_cs
);
565 dev_err(&pdev
->dev
, "Unable to get chip select number\n");
569 ret
= of_property_read_u32(pdev
->dev
.of_node
,
570 "sirf,spi-dma-rx-channel", &rx_dma_ch
);
572 dev_err(&pdev
->dev
, "Unable to get rx dma channel\n");
576 ret
= of_property_read_u32(pdev
->dev
.of_node
,
577 "sirf,spi-dma-tx-channel", &tx_dma_ch
);
579 dev_err(&pdev
->dev
, "Unable to get tx dma channel\n");
583 master
= spi_alloc_master(&pdev
->dev
, sizeof(*sspi
) + sizeof(int) * num_cs
);
585 dev_err(&pdev
->dev
, "Unable to allocate SPI master\n");
588 platform_set_drvdata(pdev
, master
);
589 sspi
= spi_master_get_devdata(master
);
591 master
->num_chipselect
= num_cs
;
593 for (i
= 0; i
< master
->num_chipselect
; i
++) {
594 cs_gpio
= of_get_named_gpio(pdev
->dev
.of_node
, "cs-gpios", i
);
596 dev_err(&pdev
->dev
, "can't get cs gpio from DT\n");
601 sspi
->chipselect
[i
] = cs_gpio
;
603 continue; /* use cs from spi controller */
605 ret
= gpio_request(cs_gpio
, DRIVER_NAME
);
609 if (sspi
->chipselect
[i
] > 0)
610 gpio_free(sspi
->chipselect
[i
]);
612 dev_err(&pdev
->dev
, "fail to request cs gpios\n");
617 mem_res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
618 sspi
->base
= devm_ioremap_resource(&pdev
->dev
, mem_res
);
619 if (IS_ERR(sspi
->base
)) {
620 ret
= PTR_ERR(sspi
->base
);
624 irq
= platform_get_irq(pdev
, 0);
629 ret
= devm_request_irq(&pdev
->dev
, irq
, spi_sirfsoc_irq
, 0,
634 sspi
->bitbang
.master
= spi_master_get(master
);
635 sspi
->bitbang
.chipselect
= spi_sirfsoc_chipselect
;
636 sspi
->bitbang
.setup_transfer
= spi_sirfsoc_setup_transfer
;
637 sspi
->bitbang
.txrx_bufs
= spi_sirfsoc_transfer
;
638 sspi
->bitbang
.master
->setup
= spi_sirfsoc_setup
;
639 master
->bus_num
= pdev
->id
;
640 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_LSB_FIRST
| SPI_CS_HIGH
;
641 master
->bits_per_word_mask
= SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
642 SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
643 sspi
->bitbang
.master
->dev
.of_node
= pdev
->dev
.of_node
;
645 /* request DMA channels */
646 dma_cap_zero(dma_cap_mask
);
647 dma_cap_set(DMA_INTERLEAVE
, dma_cap_mask
);
649 sspi
->rx_chan
= dma_request_channel(dma_cap_mask
, (dma_filter_fn
)sirfsoc_dma_filter_id
,
651 if (!sspi
->rx_chan
) {
652 dev_err(&pdev
->dev
, "can not allocate rx dma channel\n");
655 sspi
->tx_chan
= dma_request_channel(dma_cap_mask
, (dma_filter_fn
)sirfsoc_dma_filter_id
,
657 if (!sspi
->tx_chan
) {
658 dev_err(&pdev
->dev
, "can not allocate tx dma channel\n");
662 sspi
->clk
= clk_get(&pdev
->dev
, NULL
);
663 if (IS_ERR(sspi
->clk
)) {
664 ret
= PTR_ERR(sspi
->clk
);
667 clk_prepare_enable(sspi
->clk
);
668 sspi
->ctrl_freq
= clk_get_rate(sspi
->clk
);
670 init_completion(&sspi
->rx_done
);
671 init_completion(&sspi
->tx_done
);
673 writel(SIRFSOC_SPI_FIFO_RESET
, sspi
->base
+ SIRFSOC_SPI_RXFIFO_OP
);
674 writel(SIRFSOC_SPI_FIFO_RESET
, sspi
->base
+ SIRFSOC_SPI_TXFIFO_OP
);
675 writel(SIRFSOC_SPI_FIFO_START
, sspi
->base
+ SIRFSOC_SPI_RXFIFO_OP
);
676 writel(SIRFSOC_SPI_FIFO_START
, sspi
->base
+ SIRFSOC_SPI_TXFIFO_OP
);
677 /* We are not using dummy delay between command and data */
678 writel(0, sspi
->base
+ SIRFSOC_SPI_DUMMY_DELAY_CTL
);
680 sspi
->dummypage
= kmalloc(2 * PAGE_SIZE
, GFP_KERNEL
);
681 if (!sspi
->dummypage
)
684 ret
= spi_bitbang_start(&sspi
->bitbang
);
688 dev_info(&pdev
->dev
, "registerred, bus number = %d\n", master
->bus_num
);
692 kfree(sspi
->dummypage
);
694 clk_disable_unprepare(sspi
->clk
);
697 dma_release_channel(sspi
->tx_chan
);
699 dma_release_channel(sspi
->rx_chan
);
701 spi_master_put(master
);
706 static int spi_sirfsoc_remove(struct platform_device
*pdev
)
708 struct spi_master
*master
;
709 struct sirfsoc_spi
*sspi
;
712 master
= platform_get_drvdata(pdev
);
713 sspi
= spi_master_get_devdata(master
);
715 spi_bitbang_stop(&sspi
->bitbang
);
716 for (i
= 0; i
< master
->num_chipselect
; i
++) {
717 if (sspi
->chipselect
[i
] > 0)
718 gpio_free(sspi
->chipselect
[i
]);
720 kfree(sspi
->dummypage
);
721 clk_disable_unprepare(sspi
->clk
);
723 dma_release_channel(sspi
->rx_chan
);
724 dma_release_channel(sspi
->tx_chan
);
725 spi_master_put(master
);
730 static int spi_sirfsoc_suspend(struct device
*dev
)
732 struct platform_device
*pdev
= to_platform_device(dev
);
733 struct spi_master
*master
= platform_get_drvdata(pdev
);
734 struct sirfsoc_spi
*sspi
= spi_master_get_devdata(master
);
736 clk_disable(sspi
->clk
);
740 static int spi_sirfsoc_resume(struct device
*dev
)
742 struct platform_device
*pdev
= to_platform_device(dev
);
743 struct spi_master
*master
= platform_get_drvdata(pdev
);
744 struct sirfsoc_spi
*sspi
= spi_master_get_devdata(master
);
746 clk_enable(sspi
->clk
);
747 writel(SIRFSOC_SPI_FIFO_RESET
, sspi
->base
+ SIRFSOC_SPI_RXFIFO_OP
);
748 writel(SIRFSOC_SPI_FIFO_RESET
, sspi
->base
+ SIRFSOC_SPI_TXFIFO_OP
);
749 writel(SIRFSOC_SPI_FIFO_START
, sspi
->base
+ SIRFSOC_SPI_RXFIFO_OP
);
750 writel(SIRFSOC_SPI_FIFO_START
, sspi
->base
+ SIRFSOC_SPI_TXFIFO_OP
);
755 static const struct dev_pm_ops spi_sirfsoc_pm_ops
= {
756 .suspend
= spi_sirfsoc_suspend
,
757 .resume
= spi_sirfsoc_resume
,
761 static const struct of_device_id spi_sirfsoc_of_match
[] = {
762 { .compatible
= "sirf,prima2-spi", },
763 { .compatible
= "sirf,marco-spi", },
766 MODULE_DEVICE_TABLE(of
, spi_sirfsoc_of_match
);
768 static struct platform_driver spi_sirfsoc_driver
= {
771 .owner
= THIS_MODULE
,
773 .pm
= &spi_sirfsoc_pm_ops
,
775 .of_match_table
= spi_sirfsoc_of_match
,
777 .probe
= spi_sirfsoc_probe
,
778 .remove
= spi_sirfsoc_remove
,
780 module_platform_driver(spi_sirfsoc_driver
);
782 MODULE_DESCRIPTION("SiRF SoC SPI master driver");
783 MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
784 "Barry Song <Baohua.Song@csr.com>");
785 MODULE_LICENSE("GPL v2");