2 * Copyright (c) 2008-2014 STMicroelectronics Limited
4 * Author: Angus Clark <Angus.Clark@st.com>
5 * Patrice Chotard <patrice.chotard@st.com>
6 * Lee Jones <lee.jones@linaro.org>
8 * SPI master mode controller driver, used in STMicroelectronics devices.
10 * May be copied or modified under the terms of the GNU General Public
11 * License Version 2.0 only. See linux/COPYING for more information.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/platform_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/of_irq.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/spi_bitbang.h>
30 #define SSC_TBUF 0x004
31 #define SSC_RBUF 0x008
37 #define SSC_CTL_DATA_WIDTH_9 0x8
38 #define SSC_CTL_DATA_WIDTH_MSK 0xf
39 #define SSC_CTL_BM 0xf
40 #define SSC_CTL_HB BIT(4)
41 #define SSC_CTL_PH BIT(5)
42 #define SSC_CTL_PO BIT(6)
43 #define SSC_CTL_SR BIT(7)
44 #define SSC_CTL_MS BIT(8)
45 #define SSC_CTL_EN BIT(9)
46 #define SSC_CTL_LPB BIT(10)
47 #define SSC_CTL_EN_TX_FIFO BIT(11)
48 #define SSC_CTL_EN_RX_FIFO BIT(12)
49 #define SSC_CTL_EN_CLST_RX BIT(13)
51 /* SSC Interrupt Enable */
52 #define SSC_IEN_TEEN BIT(2)
57 /* SSC SPI Controller */
62 /* SSC SPI current transaction */
66 unsigned int words_remaining
;
68 struct completion done
;
71 /* Load the TX FIFO */
72 static void ssc_write_tx_fifo(struct spi_st
*spi_st
)
74 unsigned int count
, i
;
77 if (spi_st
->words_remaining
> FIFO_SIZE
)
80 count
= spi_st
->words_remaining
;
82 for (i
= 0; i
< count
; i
++) {
84 if (spi_st
->bytes_per_word
== 1) {
85 word
= *spi_st
->tx_ptr
++;
87 word
= *spi_st
->tx_ptr
++;
88 word
= *spi_st
->tx_ptr
++ | (word
<< 8);
91 writel_relaxed(word
, spi_st
->base
+ SSC_TBUF
);
95 /* Read the RX FIFO */
96 static void ssc_read_rx_fifo(struct spi_st
*spi_st
)
98 unsigned int count
, i
;
101 if (spi_st
->words_remaining
> FIFO_SIZE
)
104 count
= spi_st
->words_remaining
;
106 for (i
= 0; i
< count
; i
++) {
107 word
= readl_relaxed(spi_st
->base
+ SSC_RBUF
);
109 if (spi_st
->rx_ptr
) {
110 if (spi_st
->bytes_per_word
== 1) {
111 *spi_st
->rx_ptr
++ = (uint8_t)word
;
113 *spi_st
->rx_ptr
++ = (word
>> 8);
114 *spi_st
->rx_ptr
++ = word
& 0xff;
118 spi_st
->words_remaining
-= count
;
121 static int spi_st_transfer_one(struct spi_master
*master
,
122 struct spi_device
*spi
, struct spi_transfer
*t
)
124 struct spi_st
*spi_st
= spi_master_get_devdata(master
);
128 spi_st
->tx_ptr
= t
->tx_buf
;
129 spi_st
->rx_ptr
= t
->rx_buf
;
131 if (spi
->bits_per_word
> 8) {
133 * Anything greater than 8 bits-per-word requires 2
134 * bytes-per-word in the RX/TX buffers
136 spi_st
->bytes_per_word
= 2;
137 spi_st
->words_remaining
= t
->len
/ 2;
139 } else if (spi
->bits_per_word
== 8 && !(t
->len
& 0x1)) {
141 * If transfer is even-length, and 8 bits-per-word, then
142 * implement as half-length 16 bits-per-word transfer
144 spi_st
->bytes_per_word
= 2;
145 spi_st
->words_remaining
= t
->len
/ 2;
147 /* Set SSC_CTL to 16 bits-per-word */
148 ctl
= readl_relaxed(spi_st
->base
+ SSC_CTL
);
149 writel_relaxed((ctl
| 0xf), spi_st
->base
+ SSC_CTL
);
151 readl_relaxed(spi_st
->base
+ SSC_RBUF
);
154 spi_st
->bytes_per_word
= 1;
155 spi_st
->words_remaining
= t
->len
;
158 reinit_completion(&spi_st
->done
);
160 /* Start transfer by writing to the TX FIFO */
161 ssc_write_tx_fifo(spi_st
);
162 writel_relaxed(SSC_IEN_TEEN
, spi_st
->base
+ SSC_IEN
);
164 /* Wait for transfer to complete */
165 wait_for_completion(&spi_st
->done
);
167 /* Restore SSC_CTL if necessary */
169 writel_relaxed(ctl
, spi_st
->base
+ SSC_CTL
);
171 spi_finalize_current_transfer(spi
->master
);
176 static void spi_st_cleanup(struct spi_device
*spi
)
178 int cs
= spi
->cs_gpio
;
180 if (gpio_is_valid(cs
))
181 devm_gpio_free(&spi
->dev
, cs
);
184 /* the spi->mode bits understood by this driver: */
185 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH)
186 static int spi_st_setup(struct spi_device
*spi
)
188 struct spi_st
*spi_st
= spi_master_get_devdata(spi
->master
);
189 u32 spi_st_clk
, sscbrg
, var
;
190 u32 hz
= spi
->max_speed_hz
;
191 int cs
= spi
->cs_gpio
;
195 dev_err(&spi
->dev
, "max_speed_hz unspecified\n");
199 if (!gpio_is_valid(cs
)) {
200 dev_err(&spi
->dev
, "%d is not a valid gpio\n", cs
);
204 if (devm_gpio_request(&spi
->dev
, cs
, dev_name(&spi
->dev
))) {
205 dev_err(&spi
->dev
, "could not request gpio:%d\n", cs
);
209 ret
= gpio_direction_output(cs
, spi
->mode
& SPI_CS_HIGH
);
213 spi_st_clk
= clk_get_rate(spi_st
->clk
);
216 sscbrg
= spi_st_clk
/ (2 * hz
);
217 if (sscbrg
< 0x07 || sscbrg
> BIT(16)) {
219 "baudrate %d outside valid range %d\n", sscbrg
, hz
);
223 spi_st
->baud
= spi_st_clk
/ (2 * sscbrg
);
224 if (sscbrg
== BIT(16)) /* 16-bit counter wraps */
227 writel_relaxed(sscbrg
, spi_st
->base
+ SSC_BRG
);
230 "setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
231 hz
, spi_st
->baud
, sscbrg
);
233 /* Set SSC_CTL and enable SSC */
234 var
= readl_relaxed(spi_st
->base
+ SSC_CTL
);
237 if (spi
->mode
& SPI_CPOL
)
242 if (spi
->mode
& SPI_CPHA
)
247 if ((spi
->mode
& SPI_LSB_FIRST
) == 0)
252 if (spi
->mode
& SPI_LOOP
)
257 var
&= ~SSC_CTL_DATA_WIDTH_MSK
;
258 var
|= (spi
->bits_per_word
- 1);
260 var
|= SSC_CTL_EN_TX_FIFO
| SSC_CTL_EN_RX_FIFO
;
263 writel_relaxed(var
, spi_st
->base
+ SSC_CTL
);
265 /* Clear the status register */
266 readl_relaxed(spi_st
->base
+ SSC_RBUF
);
271 /* Interrupt fired when TX shift register becomes empty */
272 static irqreturn_t
spi_st_irq(int irq
, void *dev_id
)
274 struct spi_st
*spi_st
= (struct spi_st
*)dev_id
;
277 ssc_read_rx_fifo(spi_st
);
280 if (spi_st
->words_remaining
) {
281 ssc_write_tx_fifo(spi_st
);
284 writel_relaxed(0x0, spi_st
->base
+ SSC_IEN
);
286 * read SSC_IEN to ensure that this bit is set
287 * before re-enabling interrupt
289 readl(spi_st
->base
+ SSC_IEN
);
290 complete(&spi_st
->done
);
296 static int spi_st_probe(struct platform_device
*pdev
)
298 struct device_node
*np
= pdev
->dev
.of_node
;
299 struct spi_master
*master
;
300 struct resource
*res
;
301 struct spi_st
*spi_st
;
305 master
= spi_alloc_master(&pdev
->dev
, sizeof(*spi_st
));
309 master
->dev
.of_node
= np
;
310 master
->mode_bits
= MODEBITS
;
311 master
->setup
= spi_st_setup
;
312 master
->cleanup
= spi_st_cleanup
;
313 master
->transfer_one
= spi_st_transfer_one
;
314 master
->bits_per_word_mask
= SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
315 master
->auto_runtime_pm
= true;
316 master
->bus_num
= pdev
->id
;
317 spi_st
= spi_master_get_devdata(master
);
319 spi_st
->clk
= devm_clk_get(&pdev
->dev
, "ssc");
320 if (IS_ERR(spi_st
->clk
)) {
321 dev_err(&pdev
->dev
, "Unable to request clock\n");
322 ret
= PTR_ERR(spi_st
->clk
);
326 ret
= clk_prepare_enable(spi_st
->clk
);
330 init_completion(&spi_st
->done
);
333 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
334 spi_st
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
335 if (IS_ERR(spi_st
->base
)) {
336 ret
= PTR_ERR(spi_st
->base
);
340 /* Disable I2C and Reset SSC */
341 writel_relaxed(0x0, spi_st
->base
+ SSC_I2C
);
342 var
= readw_relaxed(spi_st
->base
+ SSC_CTL
);
344 writel_relaxed(var
, spi_st
->base
+ SSC_CTL
);
347 var
= readl_relaxed(spi_st
->base
+ SSC_CTL
);
349 writel_relaxed(var
, spi_st
->base
+ SSC_CTL
);
351 /* Set SSC into slave mode before reconfiguring PIO pins */
352 var
= readl_relaxed(spi_st
->base
+ SSC_CTL
);
354 writel_relaxed(var
, spi_st
->base
+ SSC_CTL
);
356 irq
= irq_of_parse_and_map(np
, 0);
358 dev_err(&pdev
->dev
, "IRQ missing or invalid\n");
363 ret
= devm_request_irq(&pdev
->dev
, irq
, spi_st_irq
, 0,
366 dev_err(&pdev
->dev
, "Failed to request irq %d\n", irq
);
370 /* by default the device is on */
371 pm_runtime_set_active(&pdev
->dev
);
372 pm_runtime_enable(&pdev
->dev
);
374 platform_set_drvdata(pdev
, master
);
376 ret
= devm_spi_register_master(&pdev
->dev
, master
);
378 dev_err(&pdev
->dev
, "Failed to register master\n");
385 clk_disable_unprepare(spi_st
->clk
);
387 spi_master_put(master
);
391 static int spi_st_remove(struct platform_device
*pdev
)
393 struct spi_master
*master
= platform_get_drvdata(pdev
);
394 struct spi_st
*spi_st
= spi_master_get_devdata(master
);
396 clk_disable_unprepare(spi_st
->clk
);
398 pinctrl_pm_select_sleep_state(&pdev
->dev
);
404 static int spi_st_runtime_suspend(struct device
*dev
)
406 struct spi_master
*master
= dev_get_drvdata(dev
);
407 struct spi_st
*spi_st
= spi_master_get_devdata(master
);
409 writel_relaxed(0, spi_st
->base
+ SSC_IEN
);
410 pinctrl_pm_select_sleep_state(dev
);
412 clk_disable_unprepare(spi_st
->clk
);
417 static int spi_st_runtime_resume(struct device
*dev
)
419 struct spi_master
*master
= dev_get_drvdata(dev
);
420 struct spi_st
*spi_st
= spi_master_get_devdata(master
);
423 ret
= clk_prepare_enable(spi_st
->clk
);
424 pinctrl_pm_select_default_state(dev
);
430 #ifdef CONFIG_PM_SLEEP
431 static int spi_st_suspend(struct device
*dev
)
433 struct spi_master
*master
= dev_get_drvdata(dev
);
436 ret
= spi_master_suspend(master
);
440 return pm_runtime_force_suspend(dev
);
443 static int spi_st_resume(struct device
*dev
)
445 struct spi_master
*master
= dev_get_drvdata(dev
);
448 ret
= spi_master_resume(master
);
452 return pm_runtime_force_resume(dev
);
456 static const struct dev_pm_ops spi_st_pm
= {
457 SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend
, spi_st_resume
)
458 SET_RUNTIME_PM_OPS(spi_st_runtime_suspend
, spi_st_runtime_resume
, NULL
)
461 static const struct of_device_id stm_spi_match
[] = {
462 { .compatible
= "st,comms-ssc4-spi", },
465 MODULE_DEVICE_TABLE(of
, stm_spi_match
);
467 static struct platform_driver spi_st_driver
= {
471 .of_match_table
= of_match_ptr(stm_spi_match
),
473 .probe
= spi_st_probe
,
474 .remove
= spi_st_remove
,
476 module_platform_driver(spi_st_driver
);
478 MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
479 MODULE_DESCRIPTION("STM SSC SPI driver");
480 MODULE_LICENSE("GPL v2");