2 * Driver for Nvidia TEGRA spi controller.
4 * Copyright (C) 2010 Google, Inc.
7 * Erik Gilling <konkers@android.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/err.h>
24 #include <linux/platform_device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/dmapool.h>
28 #include <linux/clk.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
32 #include <linux/spi/spi.h>
33 #include <linux/dmaengine.h>
37 #define SLINK_COMMAND 0x000
38 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
39 #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
40 #define SLINK_BOTH_EN (1 << 10)
41 #define SLINK_CS_SW (1 << 11)
42 #define SLINK_CS_VALUE (1 << 12)
43 #define SLINK_CS_POLARITY (1 << 13)
44 #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
45 #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
46 #define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
47 #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
48 #define SLINK_IDLE_SDA_MASK (3 << 16)
49 #define SLINK_CS_POLARITY1 (1 << 20)
50 #define SLINK_CK_SDA (1 << 21)
51 #define SLINK_CS_POLARITY2 (1 << 22)
52 #define SLINK_CS_POLARITY3 (1 << 23)
53 #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
54 #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
55 #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
56 #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
57 #define SLINK_IDLE_SCLK_MASK (3 << 24)
58 #define SLINK_M_S (1 << 28)
59 #define SLINK_WAIT (1 << 29)
60 #define SLINK_GO (1 << 30)
61 #define SLINK_ENB (1 << 31)
63 #define SLINK_COMMAND2 0x004
64 #define SLINK_LSBFE (1 << 0)
65 #define SLINK_SSOE (1 << 1)
66 #define SLINK_SPIE (1 << 4)
67 #define SLINK_BIDIROE (1 << 6)
68 #define SLINK_MODFEN (1 << 7)
69 #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
70 #define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
71 #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
72 #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
73 #define SLINK_FIFO_REFILLS_0 (0 << 22)
74 #define SLINK_FIFO_REFILLS_1 (1 << 22)
75 #define SLINK_FIFO_REFILLS_2 (2 << 22)
76 #define SLINK_FIFO_REFILLS_3 (3 << 22)
77 #define SLINK_FIFO_REFILLS_MASK (3 << 22)
78 #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
79 #define SLINK_SPC0 (1 << 29)
80 #define SLINK_TXEN (1 << 30)
81 #define SLINK_RXEN (1 << 31)
83 #define SLINK_STATUS 0x008
84 #define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
85 #define SLINK_WORD(val) (((val) >> 5) & 0x1f)
86 #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
87 #define SLINK_MODF (1 << 16)
88 #define SLINK_RX_UNF (1 << 18)
89 #define SLINK_TX_OVF (1 << 19)
90 #define SLINK_TX_FULL (1 << 20)
91 #define SLINK_TX_EMPTY (1 << 21)
92 #define SLINK_RX_FULL (1 << 22)
93 #define SLINK_RX_EMPTY (1 << 23)
94 #define SLINK_TX_UNF (1 << 24)
95 #define SLINK_RX_OVF (1 << 25)
96 #define SLINK_TX_FLUSH (1 << 26)
97 #define SLINK_RX_FLUSH (1 << 27)
98 #define SLINK_SCLK (1 << 28)
99 #define SLINK_ERR (1 << 29)
100 #define SLINK_RDY (1 << 30)
101 #define SLINK_BSY (1 << 31)
103 #define SLINK_MAS_DATA 0x010
104 #define SLINK_SLAVE_DATA 0x014
106 #define SLINK_DMA_CTL 0x018
107 #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
108 #define SLINK_TX_TRIG_1 (0 << 16)
109 #define SLINK_TX_TRIG_4 (1 << 16)
110 #define SLINK_TX_TRIG_8 (2 << 16)
111 #define SLINK_TX_TRIG_16 (3 << 16)
112 #define SLINK_TX_TRIG_MASK (3 << 16)
113 #define SLINK_RX_TRIG_1 (0 << 18)
114 #define SLINK_RX_TRIG_4 (1 << 18)
115 #define SLINK_RX_TRIG_8 (2 << 18)
116 #define SLINK_RX_TRIG_16 (3 << 18)
117 #define SLINK_RX_TRIG_MASK (3 << 18)
118 #define SLINK_PACKED (1 << 20)
119 #define SLINK_PACK_SIZE_4 (0 << 21)
120 #define SLINK_PACK_SIZE_8 (1 << 21)
121 #define SLINK_PACK_SIZE_16 (2 << 21)
122 #define SLINK_PACK_SIZE_32 (3 << 21)
123 #define SLINK_PACK_SIZE_MASK (3 << 21)
124 #define SLINK_IE_TXC (1 << 26)
125 #define SLINK_IE_RXC (1 << 27)
126 #define SLINK_DMA_EN (1 << 31)
128 #define SLINK_STATUS2 0x01c
129 #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
130 #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f) >> 16)
132 #define SLINK_TX_FIFO 0x100
133 #define SLINK_RX_FIFO 0x180
135 static const unsigned long spi_tegra_req_sels
[] = {
136 TEGRA_DMA_REQ_SEL_SL2B1
,
137 TEGRA_DMA_REQ_SEL_SL2B2
,
138 TEGRA_DMA_REQ_SEL_SL2B3
,
139 TEGRA_DMA_REQ_SEL_SL2B4
,
144 struct spi_tegra_data
{
145 struct spi_master
*master
;
146 struct platform_device
*pdev
;
155 struct list_head queue
;
156 struct spi_transfer
*cur
;
159 unsigned cur_bytes_per_word
;
161 /* The tegra spi controller has a bug which causes the first word
162 * in PIO transactions to be garbage. Since packed DMA transactions
163 * require transfers to be 4 byte aligned we need a bounce buffer
164 * for the generic case.
167 #if defined(CONFIG_TEGRA_SYSTEM_DMA)
168 struct tegra_dma_req rx_dma_req
;
169 struct tegra_dma_channel
*rx_dma
;
171 struct dma_chan
*rx_dma
;
172 struct dma_slave_config sconfig
;
173 struct dma_async_tx_descriptor
*rx_dma_desc
;
174 dma_cookie_t rx_cookie
;
177 dma_addr_t rx_bb_phys
;
180 #if !defined(CONFIG_TEGRA_SYSTEM_DMA)
181 static void tegra_spi_rx_dma_complete(void *args
);
184 static inline unsigned long spi_tegra_readl(struct spi_tegra_data
*tspi
,
187 return readl(tspi
->base
+ reg
);
190 static inline void spi_tegra_writel(struct spi_tegra_data
*tspi
,
194 writel(val
, tspi
->base
+ reg
);
197 static void spi_tegra_go(struct spi_tegra_data
*tspi
)
203 val
= spi_tegra_readl(tspi
, SLINK_DMA_CTL
);
204 val
&= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN
;
205 val
|= SLINK_DMA_BLOCK_SIZE(tspi
->dma_req_len
/ 4 - 1);
206 spi_tegra_writel(tspi
, val
, SLINK_DMA_CTL
);
207 #if defined(CONFIG_TEGRA_SYSTEM_DMA)
208 tspi
->rx_dma_req
.size
= tspi
->dma_req_len
;
209 tegra_dma_enqueue_req(tspi
->rx_dma
, &tspi
->rx_dma_req
);
211 tspi
->rx_dma_desc
= dmaengine_prep_slave_single(tspi
->rx_dma
,
212 tspi
->rx_bb_phys
, tspi
->dma_req_len
,
213 DMA_DEV_TO_MEM
, DMA_PREP_INTERRUPT
);
214 if (!tspi
->rx_dma_desc
) {
215 dev_err(&tspi
->pdev
->dev
, "dmaengine slave prep failed\n");
218 tspi
->rx_dma_desc
->callback
= tegra_spi_rx_dma_complete
;
219 tspi
->rx_dma_desc
->callback_param
= tspi
;
220 tspi
->rx_cookie
= dmaengine_submit(tspi
->rx_dma_desc
);
221 dma_async_issue_pending(tspi
->rx_dma
);
225 spi_tegra_writel(tspi
, val
, SLINK_DMA_CTL
);
228 static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data
*tspi
,
229 struct spi_transfer
*t
)
231 unsigned len
= min(t
->len
- tspi
->cur_pos
, BB_LEN
*
232 tspi
->cur_bytes_per_word
);
233 u8
*tx_buf
= (u8
*)t
->tx_buf
+ tspi
->cur_pos
;
237 val
= spi_tegra_readl(tspi
, SLINK_COMMAND
);
238 val
&= ~SLINK_WORD_SIZE(~0);
239 val
|= SLINK_WORD_SIZE(len
/ tspi
->cur_bytes_per_word
- 1);
240 spi_tegra_writel(tspi
, val
, SLINK_COMMAND
);
242 for (i
= 0; i
< len
; i
+= tspi
->cur_bytes_per_word
) {
244 for (j
= 0; j
< tspi
->cur_bytes_per_word
; j
++)
245 val
|= tx_buf
[i
+ j
] << j
* 8;
247 spi_tegra_writel(tspi
, val
, SLINK_TX_FIFO
);
250 tspi
->dma_req_len
= len
/ tspi
->cur_bytes_per_word
* 4;
255 static unsigned spi_tegra_drain_rx_fifo(struct spi_tegra_data
*tspi
,
256 struct spi_transfer
*t
)
258 unsigned len
= tspi
->cur_len
;
259 u8
*rx_buf
= (u8
*)t
->rx_buf
+ tspi
->cur_pos
;
263 for (i
= 0; i
< len
; i
+= tspi
->cur_bytes_per_word
) {
264 val
= tspi
->rx_bb
[i
/ tspi
->cur_bytes_per_word
];
265 for (j
= 0; j
< tspi
->cur_bytes_per_word
; j
++)
266 rx_buf
[i
+ j
] = (val
>> (j
* 8)) & 0xff;
272 static void spi_tegra_start_transfer(struct spi_device
*spi
,
273 struct spi_transfer
*t
)
275 struct spi_tegra_data
*tspi
= spi_master_get_devdata(spi
->master
);
280 speed
= t
->speed_hz
? t
->speed_hz
: spi
->max_speed_hz
;
281 bits_per_word
= t
->bits_per_word
? t
->bits_per_word
:
284 tspi
->cur_bytes_per_word
= (bits_per_word
- 1) / 8 + 1;
286 if (speed
!= tspi
->cur_speed
)
287 clk_set_rate(tspi
->clk
, speed
);
289 if (tspi
->cur_speed
== 0)
290 clk_prepare_enable(tspi
->clk
);
292 tspi
->cur_speed
= speed
;
294 val
= spi_tegra_readl(tspi
, SLINK_COMMAND2
);
295 val
&= ~SLINK_SS_EN_CS(~0) | SLINK_RXEN
| SLINK_TXEN
;
300 val
|= SLINK_SS_EN_CS(spi
->chip_select
);
302 spi_tegra_writel(tspi
, val
, SLINK_COMMAND2
);
304 val
= spi_tegra_readl(tspi
, SLINK_COMMAND
);
305 val
&= ~SLINK_BIT_LENGTH(~0);
306 val
|= SLINK_BIT_LENGTH(bits_per_word
- 1);
308 /* FIXME: should probably control CS manually so that we can be sure
309 * it does not go low between transfer and to support delay_usecs
312 val
&= ~SLINK_IDLE_SCLK_MASK
& ~SLINK_CK_SDA
& ~SLINK_CS_SW
;
314 if (spi
->mode
& SPI_CPHA
)
317 if (spi
->mode
& SPI_CPOL
)
318 val
|= SLINK_IDLE_SCLK_DRIVE_HIGH
;
320 val
|= SLINK_IDLE_SCLK_DRIVE_LOW
;
324 spi_tegra_writel(tspi
, val
, SLINK_COMMAND
);
326 spi_tegra_writel(tspi
, SLINK_RX_FLUSH
| SLINK_TX_FLUSH
, SLINK_STATUS
);
330 tspi
->cur_len
= spi_tegra_fill_tx_fifo(tspi
, t
);
335 static void spi_tegra_start_message(struct spi_device
*spi
,
336 struct spi_message
*m
)
338 struct spi_transfer
*t
;
340 m
->actual_length
= 0;
343 t
= list_first_entry(&m
->transfers
, struct spi_transfer
, transfer_list
);
344 spi_tegra_start_transfer(spi
, t
);
347 static void handle_spi_rx_dma_complete(struct spi_tegra_data
*tspi
)
350 struct spi_message
*m
;
351 struct spi_device
*spi
;
355 /* the SPI controller may come back with both the BSY and RDY bits
356 * set. In this case we need to wait for the BSY bit to clear so
357 * that we are sure the DMA is finished. 1000 reads was empirically
358 * determined to be long enough.
360 while (timeout
++ < 1000) {
361 if (!(spi_tegra_readl(tspi
, SLINK_STATUS
) & SLINK_BSY
))
365 spin_lock_irqsave(&tspi
->lock
, flags
);
367 val
= spi_tegra_readl(tspi
, SLINK_STATUS
);
369 spi_tegra_writel(tspi
, val
, SLINK_STATUS
);
371 m
= list_first_entry(&tspi
->queue
, struct spi_message
, queue
);
378 tspi
->cur_pos
+= spi_tegra_drain_rx_fifo(tspi
, tspi
->cur
);
379 m
->actual_length
+= tspi
->cur_pos
;
381 if (tspi
->cur_pos
< tspi
->cur
->len
) {
382 tspi
->cur_len
= spi_tegra_fill_tx_fifo(tspi
, tspi
->cur
);
384 } else if (!list_is_last(&tspi
->cur
->transfer_list
,
386 tspi
->cur
= list_first_entry(&tspi
->cur
->transfer_list
,
389 spi_tegra_start_transfer(spi
, tspi
->cur
);
393 m
->complete(m
->context
);
395 if (!list_empty(&tspi
->queue
)) {
396 m
= list_first_entry(&tspi
->queue
, struct spi_message
,
399 spi_tegra_start_message(spi
, m
);
401 clk_disable_unprepare(tspi
->clk
);
406 spin_unlock_irqrestore(&tspi
->lock
, flags
);
408 #if defined(CONFIG_TEGRA_SYSTEM_DMA)
409 static void tegra_spi_rx_dma_complete(struct tegra_dma_req
*req
)
411 struct spi_tegra_data
*tspi
= req
->dev
;
412 handle_spi_rx_dma_complete(tspi
);
415 static void tegra_spi_rx_dma_complete(void *args
)
417 struct spi_tegra_data
*tspi
= args
;
418 handle_spi_rx_dma_complete(tspi
);
422 static int spi_tegra_setup(struct spi_device
*spi
)
424 struct spi_tegra_data
*tspi
= spi_master_get_devdata(spi
->master
);
425 unsigned long cs_bit
;
429 dev_dbg(&spi
->dev
, "setup %d bpw, %scpol, %scpha, %dHz\n",
431 spi
->mode
& SPI_CPOL
? "" : "~",
432 spi
->mode
& SPI_CPHA
? "" : "~",
436 switch (spi
->chip_select
) {
438 cs_bit
= SLINK_CS_POLARITY
;
442 cs_bit
= SLINK_CS_POLARITY1
;
446 cs_bit
= SLINK_CS_POLARITY2
;
450 cs_bit
= SLINK_CS_POLARITY3
;
457 spin_lock_irqsave(&tspi
->lock
, flags
);
459 val
= spi_tegra_readl(tspi
, SLINK_COMMAND
);
460 if (spi
->mode
& SPI_CS_HIGH
)
464 spi_tegra_writel(tspi
, val
, SLINK_COMMAND
);
466 spin_unlock_irqrestore(&tspi
->lock
, flags
);
471 static int spi_tegra_transfer(struct spi_device
*spi
, struct spi_message
*m
)
473 struct spi_tegra_data
*tspi
= spi_master_get_devdata(spi
->master
);
474 struct spi_transfer
*t
;
478 if (list_empty(&m
->transfers
) || !m
->complete
)
481 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
482 if (t
->bits_per_word
< 0 || t
->bits_per_word
> 32)
488 if (!t
->rx_buf
&& !t
->tx_buf
)
494 spin_lock_irqsave(&tspi
->lock
, flags
);
495 was_empty
= list_empty(&tspi
->queue
);
496 list_add_tail(&m
->queue
, &tspi
->queue
);
499 spi_tegra_start_message(spi
, m
);
501 spin_unlock_irqrestore(&tspi
->lock
, flags
);
506 static int __devinit
spi_tegra_probe(struct platform_device
*pdev
)
508 struct spi_master
*master
;
509 struct spi_tegra_data
*tspi
;
512 #if !defined(CONFIG_TEGRA_SYSTEM_DMA)
516 master
= spi_alloc_master(&pdev
->dev
, sizeof *tspi
);
517 if (master
== NULL
) {
518 dev_err(&pdev
->dev
, "master allocation failed\n");
522 /* the spi->mode bits understood by this driver: */
523 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
525 master
->bus_num
= pdev
->id
;
527 master
->setup
= spi_tegra_setup
;
528 master
->transfer
= spi_tegra_transfer
;
529 master
->num_chipselect
= 4;
531 dev_set_drvdata(&pdev
->dev
, master
);
532 tspi
= spi_master_get_devdata(master
);
533 tspi
->master
= master
;
535 spin_lock_init(&tspi
->lock
);
537 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
543 if (!request_mem_region(r
->start
, resource_size(r
),
544 dev_name(&pdev
->dev
))) {
549 tspi
->phys
= r
->start
;
550 tspi
->base
= ioremap(r
->start
, resource_size(r
));
552 dev_err(&pdev
->dev
, "can't ioremap iomem\n");
557 tspi
->clk
= clk_get(&pdev
->dev
, NULL
);
558 if (IS_ERR(tspi
->clk
)) {
559 dev_err(&pdev
->dev
, "can not get clock\n");
560 ret
= PTR_ERR(tspi
->clk
);
564 INIT_LIST_HEAD(&tspi
->queue
);
566 #if defined(CONFIG_TEGRA_SYSTEM_DMA)
567 tspi
->rx_dma
= tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT
);
569 dev_err(&pdev
->dev
, "can not allocate rx dma channel\n");
575 dma_cap_set(DMA_SLAVE
, mask
);
576 tspi
->rx_dma
= dma_request_channel(mask
, NULL
, NULL
);
578 dev_err(&pdev
->dev
, "can not allocate rx dma channel\n");
585 tspi
->rx_bb
= dma_alloc_coherent(&pdev
->dev
, sizeof(u32
) * BB_LEN
,
586 &tspi
->rx_bb_phys
, GFP_KERNEL
);
588 dev_err(&pdev
->dev
, "can not allocate rx bounce buffer\n");
593 #if defined(CONFIG_TEGRA_SYSTEM_DMA)
594 tspi
->rx_dma_req
.complete
= tegra_spi_rx_dma_complete
;
595 tspi
->rx_dma_req
.to_memory
= 1;
596 tspi
->rx_dma_req
.dest_addr
= tspi
->rx_bb_phys
;
597 tspi
->rx_dma_req
.dest_bus_width
= 32;
598 tspi
->rx_dma_req
.source_addr
= tspi
->phys
+ SLINK_RX_FIFO
;
599 tspi
->rx_dma_req
.source_bus_width
= 32;
600 tspi
->rx_dma_req
.source_wrap
= 4;
601 tspi
->rx_dma_req
.req_sel
= spi_tegra_req_sels
[pdev
->id
];
602 tspi
->rx_dma_req
.dev
= tspi
;
604 /* Dmaengine Dma slave config */
605 tspi
->sconfig
.src_addr
= tspi
->phys
+ SLINK_RX_FIFO
;
606 tspi
->sconfig
.dst_addr
= tspi
->phys
+ SLINK_RX_FIFO
;
607 tspi
->sconfig
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
608 tspi
->sconfig
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
609 tspi
->sconfig
.slave_id
= spi_tegra_req_sels
[pdev
->id
];
610 tspi
->sconfig
.src_maxburst
= 1;
611 tspi
->sconfig
.dst_maxburst
= 1;
612 ret
= dmaengine_device_control(tspi
->rx_dma
,
613 DMA_SLAVE_CONFIG
, (unsigned long) &tspi
->sconfig
);
615 dev_err(&pdev
->dev
, "can not do slave configure for dma %d\n",
621 master
->dev
.of_node
= pdev
->dev
.of_node
;
622 ret
= spi_register_master(master
);
630 dma_free_coherent(&pdev
->dev
, sizeof(u32
) * BB_LEN
,
631 tspi
->rx_bb
, tspi
->rx_bb_phys
);
633 #if defined(CONFIG_TEGRA_SYSTEM_DMA)
634 tegra_dma_free_channel(tspi
->rx_dma
);
636 dma_release_channel(tspi
->rx_dma
);
643 release_mem_region(r
->start
, resource_size(r
));
645 spi_master_put(master
);
649 static int __devexit
spi_tegra_remove(struct platform_device
*pdev
)
651 struct spi_master
*master
;
652 struct spi_tegra_data
*tspi
;
655 master
= dev_get_drvdata(&pdev
->dev
);
656 tspi
= spi_master_get_devdata(master
);
658 spi_unregister_master(master
);
659 #if defined(CONFIG_TEGRA_SYSTEM_DMA)
660 tegra_dma_free_channel(tspi
->rx_dma
);
662 dma_release_channel(tspi
->rx_dma
);
665 dma_free_coherent(&pdev
->dev
, sizeof(u32
) * BB_LEN
,
666 tspi
->rx_bb
, tspi
->rx_bb_phys
);
671 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
672 release_mem_region(r
->start
, resource_size(r
));
677 MODULE_ALIAS("platform:spi_tegra");
680 static struct of_device_id spi_tegra_of_match_table
[] __devinitdata
= {
681 { .compatible
= "nvidia,tegra20-spi", },
684 MODULE_DEVICE_TABLE(of
, spi_tegra_of_match_table
);
685 #else /* CONFIG_OF */
686 #define spi_tegra_of_match_table NULL
687 #endif /* CONFIG_OF */
689 static struct platform_driver spi_tegra_driver
= {
692 .owner
= THIS_MODULE
,
693 .of_match_table
= spi_tegra_of_match_table
,
695 .probe
= spi_tegra_probe
,
696 .remove
= __devexit_p(spi_tegra_remove
),
698 module_platform_driver(spi_tegra_driver
);
700 MODULE_LICENSE("GPL");