2 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmapool.h>
25 #include <linux/err.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/kernel.h>
30 #include <linux/kthread.h>
31 #include <linux/module.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
35 #include <linux/of_device.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spi/spi-tegra.h>
38 #include <linux/clk/tegra.h>
40 #define SLINK_COMMAND 0x000
41 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
42 #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
43 #define SLINK_BOTH_EN (1 << 10)
44 #define SLINK_CS_SW (1 << 11)
45 #define SLINK_CS_VALUE (1 << 12)
46 #define SLINK_CS_POLARITY (1 << 13)
47 #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
48 #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
49 #define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
50 #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
51 #define SLINK_IDLE_SDA_MASK (3 << 16)
52 #define SLINK_CS_POLARITY1 (1 << 20)
53 #define SLINK_CK_SDA (1 << 21)
54 #define SLINK_CS_POLARITY2 (1 << 22)
55 #define SLINK_CS_POLARITY3 (1 << 23)
56 #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
57 #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
58 #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
59 #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
60 #define SLINK_IDLE_SCLK_MASK (3 << 24)
61 #define SLINK_M_S (1 << 28)
62 #define SLINK_WAIT (1 << 29)
63 #define SLINK_GO (1 << 30)
64 #define SLINK_ENB (1 << 31)
66 #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA)
68 #define SLINK_COMMAND2 0x004
69 #define SLINK_LSBFE (1 << 0)
70 #define SLINK_SSOE (1 << 1)
71 #define SLINK_SPIE (1 << 4)
72 #define SLINK_BIDIROE (1 << 6)
73 #define SLINK_MODFEN (1 << 7)
74 #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
75 #define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
76 #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
77 #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
78 #define SLINK_FIFO_REFILLS_0 (0 << 22)
79 #define SLINK_FIFO_REFILLS_1 (1 << 22)
80 #define SLINK_FIFO_REFILLS_2 (2 << 22)
81 #define SLINK_FIFO_REFILLS_3 (3 << 22)
82 #define SLINK_FIFO_REFILLS_MASK (3 << 22)
83 #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
84 #define SLINK_SPC0 (1 << 29)
85 #define SLINK_TXEN (1 << 30)
86 #define SLINK_RXEN (1 << 31)
88 #define SLINK_STATUS 0x008
89 #define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
90 #define SLINK_WORD(val) (((val) >> 5) & 0x1f)
91 #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
92 #define SLINK_MODF (1 << 16)
93 #define SLINK_RX_UNF (1 << 18)
94 #define SLINK_TX_OVF (1 << 19)
95 #define SLINK_TX_FULL (1 << 20)
96 #define SLINK_TX_EMPTY (1 << 21)
97 #define SLINK_RX_FULL (1 << 22)
98 #define SLINK_RX_EMPTY (1 << 23)
99 #define SLINK_TX_UNF (1 << 24)
100 #define SLINK_RX_OVF (1 << 25)
101 #define SLINK_TX_FLUSH (1 << 26)
102 #define SLINK_RX_FLUSH (1 << 27)
103 #define SLINK_SCLK (1 << 28)
104 #define SLINK_ERR (1 << 29)
105 #define SLINK_RDY (1 << 30)
106 #define SLINK_BSY (1 << 31)
107 #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \
108 SLINK_TX_UNF | SLINK_RX_OVF)
110 #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY)
112 #define SLINK_MAS_DATA 0x010
113 #define SLINK_SLAVE_DATA 0x014
115 #define SLINK_DMA_CTL 0x018
116 #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
117 #define SLINK_TX_TRIG_1 (0 << 16)
118 #define SLINK_TX_TRIG_4 (1 << 16)
119 #define SLINK_TX_TRIG_8 (2 << 16)
120 #define SLINK_TX_TRIG_16 (3 << 16)
121 #define SLINK_TX_TRIG_MASK (3 << 16)
122 #define SLINK_RX_TRIG_1 (0 << 18)
123 #define SLINK_RX_TRIG_4 (1 << 18)
124 #define SLINK_RX_TRIG_8 (2 << 18)
125 #define SLINK_RX_TRIG_16 (3 << 18)
126 #define SLINK_RX_TRIG_MASK (3 << 18)
127 #define SLINK_PACKED (1 << 20)
128 #define SLINK_PACK_SIZE_4 (0 << 21)
129 #define SLINK_PACK_SIZE_8 (1 << 21)
130 #define SLINK_PACK_SIZE_16 (2 << 21)
131 #define SLINK_PACK_SIZE_32 (3 << 21)
132 #define SLINK_PACK_SIZE_MASK (3 << 21)
133 #define SLINK_IE_TXC (1 << 26)
134 #define SLINK_IE_RXC (1 << 27)
135 #define SLINK_DMA_EN (1 << 31)
137 #define SLINK_STATUS2 0x01c
138 #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
139 #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16)
140 #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6)
142 #define SLINK_TX_FIFO 0x100
143 #define SLINK_RX_FIFO 0x180
145 #define DATA_DIR_TX (1 << 0)
146 #define DATA_DIR_RX (1 << 1)
148 #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
150 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
151 #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20)
152 #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0)
154 #define SLINK_STATUS2_RESET \
155 (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16)
157 #define MAX_CHIP_SELECT 4
158 #define SLINK_FIFO_DEPTH 32
160 struct tegra_slink_chip_data
{
164 struct tegra_slink_data
{
166 struct spi_master
*master
;
167 const struct tegra_slink_chip_data
*chip_data
;
175 u32 spi_max_frequency
;
178 struct spi_device
*cur_spi
;
181 unsigned words_per_32bit
;
182 unsigned bytes_per_word
;
183 unsigned curr_dma_words
;
184 unsigned cur_direction
;
189 unsigned dma_buf_size
;
190 unsigned max_buf_size
;
191 bool is_curr_dma_xfer
;
194 struct completion rx_dma_complete
;
195 struct completion tx_dma_complete
;
201 unsigned long packed_size
;
207 u32 def_command2_reg
;
209 struct completion xfer_completion
;
210 struct spi_transfer
*curr_xfer
;
211 struct dma_chan
*rx_dma_chan
;
213 dma_addr_t rx_dma_phys
;
214 struct dma_async_tx_descriptor
*rx_dma_desc
;
216 struct dma_chan
*tx_dma_chan
;
218 dma_addr_t tx_dma_phys
;
219 struct dma_async_tx_descriptor
*tx_dma_desc
;
222 static int tegra_slink_runtime_suspend(struct device
*dev
);
223 static int tegra_slink_runtime_resume(struct device
*dev
);
225 static inline unsigned long tegra_slink_readl(struct tegra_slink_data
*tspi
,
228 return readl(tspi
->base
+ reg
);
231 static inline void tegra_slink_writel(struct tegra_slink_data
*tspi
,
232 unsigned long val
, unsigned long reg
)
234 writel(val
, tspi
->base
+ reg
);
236 /* Read back register to make sure that register writes completed */
237 if (reg
!= SLINK_TX_FIFO
)
238 readl(tspi
->base
+ SLINK_MAS_DATA
);
241 static void tegra_slink_clear_status(struct tegra_slink_data
*tspi
)
244 unsigned long val_write
= 0;
246 val
= tegra_slink_readl(tspi
, SLINK_STATUS
);
248 /* Write 1 to clear status register */
249 val_write
= SLINK_RDY
| SLINK_FIFO_ERROR
;
250 tegra_slink_writel(tspi
, val_write
, SLINK_STATUS
);
253 static unsigned long tegra_slink_get_packed_size(struct tegra_slink_data
*tspi
,
254 struct spi_transfer
*t
)
258 switch (tspi
->bytes_per_word
) {
260 val
= SLINK_PACK_SIZE_4
;
263 val
= SLINK_PACK_SIZE_8
;
266 val
= SLINK_PACK_SIZE_16
;
269 val
= SLINK_PACK_SIZE_32
;
277 static unsigned tegra_slink_calculate_curr_xfer_param(
278 struct spi_device
*spi
, struct tegra_slink_data
*tspi
,
279 struct spi_transfer
*t
)
281 unsigned remain_len
= t
->len
- tspi
->cur_pos
;
283 unsigned bits_per_word
;
285 unsigned total_fifo_words
;
287 bits_per_word
= t
->bits_per_word
;
288 tspi
->bytes_per_word
= (bits_per_word
- 1) / 8 + 1;
290 if (bits_per_word
== 8 || bits_per_word
== 16) {
292 tspi
->words_per_32bit
= 32/bits_per_word
;
295 tspi
->words_per_32bit
= 1;
297 tspi
->packed_size
= tegra_slink_get_packed_size(tspi
, t
);
299 if (tspi
->is_packed
) {
300 max_len
= min(remain_len
, tspi
->max_buf_size
);
301 tspi
->curr_dma_words
= max_len
/tspi
->bytes_per_word
;
302 total_fifo_words
= max_len
/4;
304 max_word
= (remain_len
- 1) / tspi
->bytes_per_word
+ 1;
305 max_word
= min(max_word
, tspi
->max_buf_size
/4);
306 tspi
->curr_dma_words
= max_word
;
307 total_fifo_words
= max_word
;
309 return total_fifo_words
;
312 static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
313 struct tegra_slink_data
*tspi
, struct spi_transfer
*t
)
316 unsigned tx_empty_count
;
317 unsigned long fifo_status
;
318 unsigned max_n_32bit
;
321 unsigned int written_words
;
322 unsigned fifo_words_left
;
323 u8
*tx_buf
= (u8
*)t
->tx_buf
+ tspi
->cur_tx_pos
;
325 fifo_status
= tegra_slink_readl(tspi
, SLINK_STATUS2
);
326 tx_empty_count
= SLINK_TX_FIFO_EMPTY_COUNT(fifo_status
);
328 if (tspi
->is_packed
) {
329 fifo_words_left
= tx_empty_count
* tspi
->words_per_32bit
;
330 written_words
= min(fifo_words_left
, tspi
->curr_dma_words
);
331 nbytes
= written_words
* tspi
->bytes_per_word
;
332 max_n_32bit
= DIV_ROUND_UP(nbytes
, 4);
333 for (count
= 0; count
< max_n_32bit
; count
++) {
335 for (i
= 0; (i
< 4) && nbytes
; i
++, nbytes
--)
336 x
|= (*tx_buf
++) << (i
*8);
337 tegra_slink_writel(tspi
, x
, SLINK_TX_FIFO
);
340 max_n_32bit
= min(tspi
->curr_dma_words
, tx_empty_count
);
341 written_words
= max_n_32bit
;
342 nbytes
= written_words
* tspi
->bytes_per_word
;
343 for (count
= 0; count
< max_n_32bit
; count
++) {
345 for (i
= 0; nbytes
&& (i
< tspi
->bytes_per_word
);
347 x
|= ((*tx_buf
++) << i
*8);
348 tegra_slink_writel(tspi
, x
, SLINK_TX_FIFO
);
351 tspi
->cur_tx_pos
+= written_words
* tspi
->bytes_per_word
;
352 return written_words
;
355 static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
356 struct tegra_slink_data
*tspi
, struct spi_transfer
*t
)
358 unsigned rx_full_count
;
359 unsigned long fifo_status
;
362 unsigned int read_words
= 0;
364 u8
*rx_buf
= (u8
*)t
->rx_buf
+ tspi
->cur_rx_pos
;
366 fifo_status
= tegra_slink_readl(tspi
, SLINK_STATUS2
);
367 rx_full_count
= SLINK_RX_FIFO_FULL_COUNT(fifo_status
);
368 if (tspi
->is_packed
) {
369 len
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
370 for (count
= 0; count
< rx_full_count
; count
++) {
371 x
= tegra_slink_readl(tspi
, SLINK_RX_FIFO
);
372 for (i
= 0; len
&& (i
< 4); i
++, len
--)
373 *rx_buf
++ = (x
>> i
*8) & 0xFF;
375 tspi
->cur_rx_pos
+= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
376 read_words
+= tspi
->curr_dma_words
;
378 unsigned int bits_per_word
;
380 bits_per_word
= t
->bits_per_word
;
381 for (count
= 0; count
< rx_full_count
; count
++) {
382 x
= tegra_slink_readl(tspi
, SLINK_RX_FIFO
);
383 for (i
= 0; (i
< tspi
->bytes_per_word
); i
++)
384 *rx_buf
++ = (x
>> (i
*8)) & 0xFF;
386 tspi
->cur_rx_pos
+= rx_full_count
* tspi
->bytes_per_word
;
387 read_words
+= rx_full_count
;
392 static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
393 struct tegra_slink_data
*tspi
, struct spi_transfer
*t
)
397 /* Make the dma buffer to read by cpu */
398 dma_sync_single_for_cpu(tspi
->dev
, tspi
->tx_dma_phys
,
399 tspi
->dma_buf_size
, DMA_TO_DEVICE
);
401 if (tspi
->is_packed
) {
402 len
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
403 memcpy(tspi
->tx_dma_buf
, t
->tx_buf
+ tspi
->cur_pos
, len
);
407 u8
*tx_buf
= (u8
*)t
->tx_buf
+ tspi
->cur_tx_pos
;
408 unsigned consume
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
411 for (count
= 0; count
< tspi
->curr_dma_words
; count
++) {
413 for (i
= 0; consume
&& (i
< tspi
->bytes_per_word
);
415 x
|= ((*tx_buf
++) << i
* 8);
416 tspi
->tx_dma_buf
[count
] = x
;
419 tspi
->cur_tx_pos
+= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
421 /* Make the dma buffer to read by dma */
422 dma_sync_single_for_device(tspi
->dev
, tspi
->tx_dma_phys
,
423 tspi
->dma_buf_size
, DMA_TO_DEVICE
);
426 static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
427 struct tegra_slink_data
*tspi
, struct spi_transfer
*t
)
431 /* Make the dma buffer to read by cpu */
432 dma_sync_single_for_cpu(tspi
->dev
, tspi
->rx_dma_phys
,
433 tspi
->dma_buf_size
, DMA_FROM_DEVICE
);
435 if (tspi
->is_packed
) {
436 len
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
437 memcpy(t
->rx_buf
+ tspi
->cur_rx_pos
, tspi
->rx_dma_buf
, len
);
441 unsigned char *rx_buf
= t
->rx_buf
+ tspi
->cur_rx_pos
;
443 unsigned int rx_mask
, bits_per_word
;
445 bits_per_word
= t
->bits_per_word
;
446 rx_mask
= (1 << bits_per_word
) - 1;
447 for (count
= 0; count
< tspi
->curr_dma_words
; count
++) {
448 x
= tspi
->rx_dma_buf
[count
];
450 for (i
= 0; (i
< tspi
->bytes_per_word
); i
++)
451 *rx_buf
++ = (x
>> (i
*8)) & 0xFF;
454 tspi
->cur_rx_pos
+= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
456 /* Make the dma buffer to read by dma */
457 dma_sync_single_for_device(tspi
->dev
, tspi
->rx_dma_phys
,
458 tspi
->dma_buf_size
, DMA_FROM_DEVICE
);
461 static void tegra_slink_dma_complete(void *args
)
463 struct completion
*dma_complete
= args
;
465 complete(dma_complete
);
468 static int tegra_slink_start_tx_dma(struct tegra_slink_data
*tspi
, int len
)
470 INIT_COMPLETION(tspi
->tx_dma_complete
);
471 tspi
->tx_dma_desc
= dmaengine_prep_slave_single(tspi
->tx_dma_chan
,
472 tspi
->tx_dma_phys
, len
, DMA_MEM_TO_DEV
,
473 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
474 if (!tspi
->tx_dma_desc
) {
475 dev_err(tspi
->dev
, "Not able to get desc for Tx\n");
479 tspi
->tx_dma_desc
->callback
= tegra_slink_dma_complete
;
480 tspi
->tx_dma_desc
->callback_param
= &tspi
->tx_dma_complete
;
482 dmaengine_submit(tspi
->tx_dma_desc
);
483 dma_async_issue_pending(tspi
->tx_dma_chan
);
487 static int tegra_slink_start_rx_dma(struct tegra_slink_data
*tspi
, int len
)
489 INIT_COMPLETION(tspi
->rx_dma_complete
);
490 tspi
->rx_dma_desc
= dmaengine_prep_slave_single(tspi
->rx_dma_chan
,
491 tspi
->rx_dma_phys
, len
, DMA_DEV_TO_MEM
,
492 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
493 if (!tspi
->rx_dma_desc
) {
494 dev_err(tspi
->dev
, "Not able to get desc for Rx\n");
498 tspi
->rx_dma_desc
->callback
= tegra_slink_dma_complete
;
499 tspi
->rx_dma_desc
->callback_param
= &tspi
->rx_dma_complete
;
501 dmaengine_submit(tspi
->rx_dma_desc
);
502 dma_async_issue_pending(tspi
->rx_dma_chan
);
506 static int tegra_slink_start_dma_based_transfer(
507 struct tegra_slink_data
*tspi
, struct spi_transfer
*t
)
510 unsigned long test_val
;
513 unsigned long status
;
515 /* Make sure that Rx and Tx fifo are empty */
516 status
= tegra_slink_readl(tspi
, SLINK_STATUS
);
517 if ((status
& SLINK_FIFO_EMPTY
) != SLINK_FIFO_EMPTY
) {
519 "Rx/Tx fifo are not empty status 0x%08lx\n", status
);
523 val
= SLINK_DMA_BLOCK_SIZE(tspi
->curr_dma_words
- 1);
524 val
|= tspi
->packed_size
;
526 len
= DIV_ROUND_UP(tspi
->curr_dma_words
* tspi
->bytes_per_word
,
529 len
= tspi
->curr_dma_words
* 4;
531 /* Set attention level based on length of transfer */
533 val
|= SLINK_TX_TRIG_1
| SLINK_RX_TRIG_1
;
534 else if (((len
) >> 4) & 0x1)
535 val
|= SLINK_TX_TRIG_4
| SLINK_RX_TRIG_4
;
537 val
|= SLINK_TX_TRIG_8
| SLINK_RX_TRIG_8
;
539 if (tspi
->cur_direction
& DATA_DIR_TX
)
542 if (tspi
->cur_direction
& DATA_DIR_RX
)
545 tegra_slink_writel(tspi
, val
, SLINK_DMA_CTL
);
546 tspi
->dma_control_reg
= val
;
548 if (tspi
->cur_direction
& DATA_DIR_TX
) {
549 tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi
, t
);
551 ret
= tegra_slink_start_tx_dma(tspi
, len
);
554 "Starting tx dma failed, err %d\n", ret
);
558 /* Wait for tx fifo to be fill before starting slink */
559 test_val
= tegra_slink_readl(tspi
, SLINK_STATUS
);
560 while (!(test_val
& SLINK_TX_FULL
))
561 test_val
= tegra_slink_readl(tspi
, SLINK_STATUS
);
564 if (tspi
->cur_direction
& DATA_DIR_RX
) {
565 /* Make the dma buffer to read by dma */
566 dma_sync_single_for_device(tspi
->dev
, tspi
->rx_dma_phys
,
567 tspi
->dma_buf_size
, DMA_FROM_DEVICE
);
569 ret
= tegra_slink_start_rx_dma(tspi
, len
);
572 "Starting rx dma failed, err %d\n", ret
);
573 if (tspi
->cur_direction
& DATA_DIR_TX
)
574 dmaengine_terminate_all(tspi
->tx_dma_chan
);
578 tspi
->is_curr_dma_xfer
= true;
579 if (tspi
->is_packed
) {
581 tegra_slink_writel(tspi
, val
, SLINK_DMA_CTL
);
582 /* HW need small delay after settign Packed mode */
585 tspi
->dma_control_reg
= val
;
588 tegra_slink_writel(tspi
, val
, SLINK_DMA_CTL
);
592 static int tegra_slink_start_cpu_based_transfer(
593 struct tegra_slink_data
*tspi
, struct spi_transfer
*t
)
598 val
= tspi
->packed_size
;
599 if (tspi
->cur_direction
& DATA_DIR_TX
)
602 if (tspi
->cur_direction
& DATA_DIR_RX
)
605 tegra_slink_writel(tspi
, val
, SLINK_DMA_CTL
);
606 tspi
->dma_control_reg
= val
;
608 if (tspi
->cur_direction
& DATA_DIR_TX
)
609 cur_words
= tegra_slink_fill_tx_fifo_from_client_txbuf(tspi
, t
);
611 cur_words
= tspi
->curr_dma_words
;
612 val
|= SLINK_DMA_BLOCK_SIZE(cur_words
- 1);
613 tegra_slink_writel(tspi
, val
, SLINK_DMA_CTL
);
614 tspi
->dma_control_reg
= val
;
616 tspi
->is_curr_dma_xfer
= false;
617 if (tspi
->is_packed
) {
619 tegra_slink_writel(tspi
, val
, SLINK_DMA_CTL
);
623 tspi
->dma_control_reg
= val
;
625 tegra_slink_writel(tspi
, val
, SLINK_DMA_CTL
);
629 static int tegra_slink_init_dma_param(struct tegra_slink_data
*tspi
,
632 struct dma_chan
*dma_chan
;
636 struct dma_slave_config dma_sconfig
;
640 dma_cap_set(DMA_SLAVE
, mask
);
641 dma_chan
= dma_request_channel(mask
, NULL
, NULL
);
644 "Dma channel is not available, will try later\n");
645 return -EPROBE_DEFER
;
648 dma_buf
= dma_alloc_coherent(tspi
->dev
, tspi
->dma_buf_size
,
649 &dma_phys
, GFP_KERNEL
);
651 dev_err(tspi
->dev
, " Not able to allocate the dma buffer\n");
652 dma_release_channel(dma_chan
);
656 dma_sconfig
.slave_id
= tspi
->dma_req_sel
;
658 dma_sconfig
.src_addr
= tspi
->phys
+ SLINK_RX_FIFO
;
659 dma_sconfig
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
660 dma_sconfig
.src_maxburst
= 0;
662 dma_sconfig
.dst_addr
= tspi
->phys
+ SLINK_TX_FIFO
;
663 dma_sconfig
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
664 dma_sconfig
.dst_maxburst
= 0;
667 ret
= dmaengine_slave_config(dma_chan
, &dma_sconfig
);
671 tspi
->rx_dma_chan
= dma_chan
;
672 tspi
->rx_dma_buf
= dma_buf
;
673 tspi
->rx_dma_phys
= dma_phys
;
675 tspi
->tx_dma_chan
= dma_chan
;
676 tspi
->tx_dma_buf
= dma_buf
;
677 tspi
->tx_dma_phys
= dma_phys
;
682 dma_free_coherent(tspi
->dev
, tspi
->dma_buf_size
, dma_buf
, dma_phys
);
683 dma_release_channel(dma_chan
);
687 static void tegra_slink_deinit_dma_param(struct tegra_slink_data
*tspi
,
692 struct dma_chan
*dma_chan
;
695 dma_buf
= tspi
->rx_dma_buf
;
696 dma_chan
= tspi
->rx_dma_chan
;
697 dma_phys
= tspi
->rx_dma_phys
;
698 tspi
->rx_dma_chan
= NULL
;
699 tspi
->rx_dma_buf
= NULL
;
701 dma_buf
= tspi
->tx_dma_buf
;
702 dma_chan
= tspi
->tx_dma_chan
;
703 dma_phys
= tspi
->tx_dma_phys
;
704 tspi
->tx_dma_buf
= NULL
;
705 tspi
->tx_dma_chan
= NULL
;
710 dma_free_coherent(tspi
->dev
, tspi
->dma_buf_size
, dma_buf
, dma_phys
);
711 dma_release_channel(dma_chan
);
714 static int tegra_slink_start_transfer_one(struct spi_device
*spi
,
715 struct spi_transfer
*t
, bool is_first_of_msg
,
718 struct tegra_slink_data
*tspi
= spi_master_get_devdata(spi
->master
);
721 unsigned total_fifo_words
;
723 struct tegra_spi_device_controller_data
*cdata
= spi
->controller_data
;
724 unsigned long command
;
725 unsigned long command2
;
727 bits_per_word
= t
->bits_per_word
;
729 if (speed
!= tspi
->cur_speed
) {
730 clk_set_rate(tspi
->clk
, speed
* 4);
731 tspi
->cur_speed
= speed
;
736 tspi
->cur_rx_pos
= 0;
737 tspi
->cur_tx_pos
= 0;
739 total_fifo_words
= tegra_slink_calculate_curr_xfer_param(spi
, tspi
, t
);
741 if (is_first_of_msg
) {
742 tegra_slink_clear_status(tspi
);
744 command
= tspi
->def_command_reg
;
745 command
|= SLINK_BIT_LENGTH(bits_per_word
- 1);
747 command2
= tspi
->def_command2_reg
;
748 command2
|= SLINK_SS_EN_CS(spi
->chip_select
);
750 /* possibly use the hw based chip select */
751 tspi
->is_hw_based_cs
= false;
752 if (cdata
&& cdata
->is_hw_based_cs
&& is_single_xfer
&&
753 ((tspi
->curr_dma_words
* tspi
->bytes_per_word
) ==
754 (t
->len
- tspi
->cur_pos
))) {
758 setup_count
= cdata
->cs_setup_clk_count
>> 1;
759 setup_count
= max(setup_count
, 3);
760 command2
|= SLINK_SS_SETUP(setup_count
);
761 if (tspi
->chip_data
->cs_hold_time
) {
764 hold_count
= cdata
->cs_hold_clk_count
;
765 hold_count
= max(hold_count
, 0xF);
766 sts2
= tegra_slink_readl(tspi
, SLINK_STATUS2
);
767 sts2
&= ~SLINK_SS_HOLD_TIME(0xF);
768 sts2
|= SLINK_SS_HOLD_TIME(hold_count
);
769 tegra_slink_writel(tspi
, sts2
, SLINK_STATUS2
);
771 tspi
->is_hw_based_cs
= true;
774 if (tspi
->is_hw_based_cs
)
775 command
&= ~SLINK_CS_SW
;
777 command
|= SLINK_CS_SW
| SLINK_CS_VALUE
;
779 command
&= ~SLINK_MODES
;
780 if (spi
->mode
& SPI_CPHA
)
781 command
|= SLINK_CK_SDA
;
783 if (spi
->mode
& SPI_CPOL
)
784 command
|= SLINK_IDLE_SCLK_DRIVE_HIGH
;
786 command
|= SLINK_IDLE_SCLK_DRIVE_LOW
;
788 command
= tspi
->command_reg
;
789 command
&= ~SLINK_BIT_LENGTH(~0);
790 command
|= SLINK_BIT_LENGTH(bits_per_word
- 1);
792 command2
= tspi
->command2_reg
;
793 command2
&= ~(SLINK_RXEN
| SLINK_TXEN
);
796 tegra_slink_writel(tspi
, command
, SLINK_COMMAND
);
797 tspi
->command_reg
= command
;
799 tspi
->cur_direction
= 0;
801 command2
|= SLINK_RXEN
;
802 tspi
->cur_direction
|= DATA_DIR_RX
;
805 command2
|= SLINK_TXEN
;
806 tspi
->cur_direction
|= DATA_DIR_TX
;
808 tegra_slink_writel(tspi
, command2
, SLINK_COMMAND2
);
809 tspi
->command2_reg
= command2
;
811 if (total_fifo_words
> SLINK_FIFO_DEPTH
)
812 ret
= tegra_slink_start_dma_based_transfer(tspi
, t
);
814 ret
= tegra_slink_start_cpu_based_transfer(tspi
, t
);
818 static int tegra_slink_setup(struct spi_device
*spi
)
820 struct tegra_slink_data
*tspi
= spi_master_get_devdata(spi
->master
);
824 unsigned int cs_pol_bit
[MAX_CHIP_SELECT
] = {
831 dev_dbg(&spi
->dev
, "setup %d bpw, %scpol, %scpha, %dHz\n",
833 spi
->mode
& SPI_CPOL
? "" : "~",
834 spi
->mode
& SPI_CPHA
? "" : "~",
837 BUG_ON(spi
->chip_select
>= MAX_CHIP_SELECT
);
839 /* Set speed to the spi max fequency if spi device has not set */
840 spi
->max_speed_hz
= spi
->max_speed_hz
? : tspi
->spi_max_frequency
;
841 ret
= pm_runtime_get_sync(tspi
->dev
);
843 dev_err(tspi
->dev
, "pm runtime failed, e = %d\n", ret
);
847 spin_lock_irqsave(&tspi
->lock
, flags
);
848 val
= tspi
->def_command_reg
;
849 if (spi
->mode
& SPI_CS_HIGH
)
850 val
|= cs_pol_bit
[spi
->chip_select
];
852 val
&= ~cs_pol_bit
[spi
->chip_select
];
853 tspi
->def_command_reg
= val
;
854 tegra_slink_writel(tspi
, tspi
->def_command_reg
, SLINK_COMMAND
);
855 spin_unlock_irqrestore(&tspi
->lock
, flags
);
857 pm_runtime_put(tspi
->dev
);
861 static int tegra_slink_prepare_transfer(struct spi_master
*master
)
863 struct tegra_slink_data
*tspi
= spi_master_get_devdata(master
);
865 return pm_runtime_get_sync(tspi
->dev
);
868 static int tegra_slink_unprepare_transfer(struct spi_master
*master
)
870 struct tegra_slink_data
*tspi
= spi_master_get_devdata(master
);
872 pm_runtime_put(tspi
->dev
);
876 static int tegra_slink_transfer_one_message(struct spi_master
*master
,
877 struct spi_message
*msg
)
879 bool is_first_msg
= true;
881 struct tegra_slink_data
*tspi
= spi_master_get_devdata(master
);
882 struct spi_transfer
*xfer
;
883 struct spi_device
*spi
= msg
->spi
;
887 msg
->actual_length
= 0;
888 single_xfer
= list_is_singular(&msg
->transfers
);
889 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
) {
890 INIT_COMPLETION(tspi
->xfer_completion
);
891 ret
= tegra_slink_start_transfer_one(spi
, xfer
,
892 is_first_msg
, single_xfer
);
895 "spi can not start transfer, err %d\n", ret
);
898 is_first_msg
= false;
899 ret
= wait_for_completion_timeout(&tspi
->xfer_completion
,
901 if (WARN_ON(ret
== 0)) {
903 "spi trasfer timeout, err %d\n", ret
);
908 if (tspi
->tx_status
|| tspi
->rx_status
) {
909 dev_err(tspi
->dev
, "Error in Transfer\n");
913 msg
->actual_length
+= xfer
->len
;
914 if (xfer
->cs_change
&& xfer
->delay_usecs
) {
915 tegra_slink_writel(tspi
, tspi
->def_command_reg
,
917 udelay(xfer
->delay_usecs
);
922 tegra_slink_writel(tspi
, tspi
->def_command_reg
, SLINK_COMMAND
);
923 tegra_slink_writel(tspi
, tspi
->def_command2_reg
, SLINK_COMMAND2
);
925 spi_finalize_current_message(master
);
929 static irqreturn_t
handle_cpu_based_xfer(struct tegra_slink_data
*tspi
)
931 struct spi_transfer
*t
= tspi
->curr_xfer
;
934 spin_lock_irqsave(&tspi
->lock
, flags
);
935 if (tspi
->tx_status
|| tspi
->rx_status
||
936 (tspi
->status_reg
& SLINK_BSY
)) {
938 "CpuXfer ERROR bit set 0x%x\n", tspi
->status_reg
);
940 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi
->command_reg
,
941 tspi
->command2_reg
, tspi
->dma_control_reg
);
942 tegra_periph_reset_assert(tspi
->clk
);
944 tegra_periph_reset_deassert(tspi
->clk
);
945 complete(&tspi
->xfer_completion
);
949 if (tspi
->cur_direction
& DATA_DIR_RX
)
950 tegra_slink_read_rx_fifo_to_client_rxbuf(tspi
, t
);
952 if (tspi
->cur_direction
& DATA_DIR_TX
)
953 tspi
->cur_pos
= tspi
->cur_tx_pos
;
955 tspi
->cur_pos
= tspi
->cur_rx_pos
;
957 if (tspi
->cur_pos
== t
->len
) {
958 complete(&tspi
->xfer_completion
);
962 tegra_slink_calculate_curr_xfer_param(tspi
->cur_spi
, tspi
, t
);
963 tegra_slink_start_cpu_based_transfer(tspi
, t
);
965 spin_unlock_irqrestore(&tspi
->lock
, flags
);
969 static irqreturn_t
handle_dma_based_xfer(struct tegra_slink_data
*tspi
)
971 struct spi_transfer
*t
= tspi
->curr_xfer
;
974 unsigned total_fifo_words
;
977 /* Abort dmas if any error */
978 if (tspi
->cur_direction
& DATA_DIR_TX
) {
979 if (tspi
->tx_status
) {
980 dmaengine_terminate_all(tspi
->tx_dma_chan
);
983 wait_status
= wait_for_completion_interruptible_timeout(
984 &tspi
->tx_dma_complete
, SLINK_DMA_TIMEOUT
);
985 if (wait_status
<= 0) {
986 dmaengine_terminate_all(tspi
->tx_dma_chan
);
987 dev_err(tspi
->dev
, "TxDma Xfer failed\n");
993 if (tspi
->cur_direction
& DATA_DIR_RX
) {
994 if (tspi
->rx_status
) {
995 dmaengine_terminate_all(tspi
->rx_dma_chan
);
998 wait_status
= wait_for_completion_interruptible_timeout(
999 &tspi
->rx_dma_complete
, SLINK_DMA_TIMEOUT
);
1000 if (wait_status
<= 0) {
1001 dmaengine_terminate_all(tspi
->rx_dma_chan
);
1002 dev_err(tspi
->dev
, "RxDma Xfer failed\n");
1008 spin_lock_irqsave(&tspi
->lock
, flags
);
1011 "DmaXfer: ERROR bit set 0x%x\n", tspi
->status_reg
);
1013 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi
->command_reg
,
1014 tspi
->command2_reg
, tspi
->dma_control_reg
);
1015 tegra_periph_reset_assert(tspi
->clk
);
1017 tegra_periph_reset_deassert(tspi
->clk
);
1018 complete(&tspi
->xfer_completion
);
1019 spin_unlock_irqrestore(&tspi
->lock
, flags
);
1023 if (tspi
->cur_direction
& DATA_DIR_RX
)
1024 tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi
, t
);
1026 if (tspi
->cur_direction
& DATA_DIR_TX
)
1027 tspi
->cur_pos
= tspi
->cur_tx_pos
;
1029 tspi
->cur_pos
= tspi
->cur_rx_pos
;
1031 if (tspi
->cur_pos
== t
->len
) {
1032 complete(&tspi
->xfer_completion
);
1036 /* Continue transfer in current message */
1037 total_fifo_words
= tegra_slink_calculate_curr_xfer_param(tspi
->cur_spi
,
1039 if (total_fifo_words
> SLINK_FIFO_DEPTH
)
1040 err
= tegra_slink_start_dma_based_transfer(tspi
, t
);
1042 err
= tegra_slink_start_cpu_based_transfer(tspi
, t
);
1045 spin_unlock_irqrestore(&tspi
->lock
, flags
);
1049 static irqreturn_t
tegra_slink_isr_thread(int irq
, void *context_data
)
1051 struct tegra_slink_data
*tspi
= context_data
;
1053 if (!tspi
->is_curr_dma_xfer
)
1054 return handle_cpu_based_xfer(tspi
);
1055 return handle_dma_based_xfer(tspi
);
1058 static irqreturn_t
tegra_slink_isr(int irq
, void *context_data
)
1060 struct tegra_slink_data
*tspi
= context_data
;
1062 tspi
->status_reg
= tegra_slink_readl(tspi
, SLINK_STATUS
);
1063 if (tspi
->cur_direction
& DATA_DIR_TX
)
1064 tspi
->tx_status
= tspi
->status_reg
&
1065 (SLINK_TX_OVF
| SLINK_TX_UNF
);
1067 if (tspi
->cur_direction
& DATA_DIR_RX
)
1068 tspi
->rx_status
= tspi
->status_reg
&
1069 (SLINK_RX_OVF
| SLINK_RX_UNF
);
1070 tegra_slink_clear_status(tspi
);
1072 return IRQ_WAKE_THREAD
;
1075 static struct tegra_spi_platform_data
*tegra_slink_parse_dt(
1076 struct platform_device
*pdev
)
1078 struct tegra_spi_platform_data
*pdata
;
1079 const unsigned int *prop
;
1080 struct device_node
*np
= pdev
->dev
.of_node
;
1083 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1085 dev_err(&pdev
->dev
, "Memory alloc for pdata failed\n");
1089 if (of_property_read_u32_array(np
, "nvidia,dma-request-selector",
1091 pdata
->dma_req_sel
= of_dma
[1];
1093 prop
= of_get_property(np
, "spi-max-frequency", NULL
);
1095 pdata
->spi_max_frequency
= be32_to_cpup(prop
);
1100 const struct tegra_slink_chip_data tegra30_spi_cdata
= {
1101 .cs_hold_time
= true,
1104 const struct tegra_slink_chip_data tegra20_spi_cdata
= {
1105 .cs_hold_time
= false,
1108 static struct of_device_id tegra_slink_of_match
[] = {
1109 { .compatible
= "nvidia,tegra30-slink", .data
= &tegra30_spi_cdata
, },
1110 { .compatible
= "nvidia,tegra20-slink", .data
= &tegra20_spi_cdata
, },
1113 MODULE_DEVICE_TABLE(of
, tegra_slink_of_match
);
1115 static int tegra_slink_probe(struct platform_device
*pdev
)
1117 struct spi_master
*master
;
1118 struct tegra_slink_data
*tspi
;
1120 struct tegra_spi_platform_data
*pdata
= pdev
->dev
.platform_data
;
1122 const struct tegra_slink_chip_data
*cdata
= NULL
;
1123 const struct of_device_id
*match
;
1125 match
= of_match_device(of_match_ptr(tegra_slink_of_match
), &pdev
->dev
);
1127 dev_err(&pdev
->dev
, "Error: No device match found\n");
1130 cdata
= match
->data
;
1131 if (!pdata
&& pdev
->dev
.of_node
)
1132 pdata
= tegra_slink_parse_dt(pdev
);
1135 dev_err(&pdev
->dev
, "No platform data, exiting\n");
1139 if (!pdata
->spi_max_frequency
)
1140 pdata
->spi_max_frequency
= 25000000; /* 25MHz */
1142 master
= spi_alloc_master(&pdev
->dev
, sizeof(*tspi
));
1144 dev_err(&pdev
->dev
, "master allocation failed\n");
1148 /* the spi->mode bits understood by this driver: */
1149 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1150 master
->setup
= tegra_slink_setup
;
1151 master
->prepare_transfer_hardware
= tegra_slink_prepare_transfer
;
1152 master
->transfer_one_message
= tegra_slink_transfer_one_message
;
1153 master
->unprepare_transfer_hardware
= tegra_slink_unprepare_transfer
;
1154 master
->num_chipselect
= MAX_CHIP_SELECT
;
1155 master
->bus_num
= -1;
1157 dev_set_drvdata(&pdev
->dev
, master
);
1158 tspi
= spi_master_get_devdata(master
);
1159 tspi
->master
= master
;
1160 tspi
->dma_req_sel
= pdata
->dma_req_sel
;
1161 tspi
->dev
= &pdev
->dev
;
1162 tspi
->chip_data
= cdata
;
1163 spin_lock_init(&tspi
->lock
);
1165 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1167 dev_err(&pdev
->dev
, "No IO memory resource\n");
1169 goto exit_free_master
;
1171 tspi
->phys
= r
->start
;
1172 tspi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
1173 if (IS_ERR(tspi
->base
)) {
1174 ret
= PTR_ERR(tspi
->base
);
1175 goto exit_free_master
;
1178 spi_irq
= platform_get_irq(pdev
, 0);
1179 tspi
->irq
= spi_irq
;
1180 ret
= request_threaded_irq(tspi
->irq
, tegra_slink_isr
,
1181 tegra_slink_isr_thread
, IRQF_ONESHOT
,
1182 dev_name(&pdev
->dev
), tspi
);
1184 dev_err(&pdev
->dev
, "Failed to register ISR for IRQ %d\n",
1186 goto exit_free_master
;
1189 tspi
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1190 if (IS_ERR(tspi
->clk
)) {
1191 dev_err(&pdev
->dev
, "can not get clock\n");
1192 ret
= PTR_ERR(tspi
->clk
);
1196 tspi
->max_buf_size
= SLINK_FIFO_DEPTH
<< 2;
1197 tspi
->dma_buf_size
= DEFAULT_SPI_DMA_BUF_LEN
;
1198 tspi
->spi_max_frequency
= pdata
->spi_max_frequency
;
1200 if (pdata
->dma_req_sel
) {
1201 ret
= tegra_slink_init_dma_param(tspi
, true);
1203 dev_err(&pdev
->dev
, "RxDma Init failed, err %d\n", ret
);
1207 ret
= tegra_slink_init_dma_param(tspi
, false);
1209 dev_err(&pdev
->dev
, "TxDma Init failed, err %d\n", ret
);
1210 goto exit_rx_dma_free
;
1212 tspi
->max_buf_size
= tspi
->dma_buf_size
;
1213 init_completion(&tspi
->tx_dma_complete
);
1214 init_completion(&tspi
->rx_dma_complete
);
1217 init_completion(&tspi
->xfer_completion
);
1219 pm_runtime_enable(&pdev
->dev
);
1220 if (!pm_runtime_enabled(&pdev
->dev
)) {
1221 ret
= tegra_slink_runtime_resume(&pdev
->dev
);
1223 goto exit_pm_disable
;
1226 ret
= pm_runtime_get_sync(&pdev
->dev
);
1228 dev_err(&pdev
->dev
, "pm runtime get failed, e = %d\n", ret
);
1229 goto exit_pm_disable
;
1231 tspi
->def_command_reg
= SLINK_M_S
;
1232 tspi
->def_command2_reg
= SLINK_CS_ACTIVE_BETWEEN
;
1233 tegra_slink_writel(tspi
, tspi
->def_command_reg
, SLINK_COMMAND
);
1234 tegra_slink_writel(tspi
, tspi
->def_command2_reg
, SLINK_COMMAND2
);
1235 pm_runtime_put(&pdev
->dev
);
1237 master
->dev
.of_node
= pdev
->dev
.of_node
;
1238 ret
= spi_register_master(master
);
1240 dev_err(&pdev
->dev
, "can not register to master err %d\n", ret
);
1241 goto exit_pm_disable
;
1246 pm_runtime_disable(&pdev
->dev
);
1247 if (!pm_runtime_status_suspended(&pdev
->dev
))
1248 tegra_slink_runtime_suspend(&pdev
->dev
);
1249 tegra_slink_deinit_dma_param(tspi
, false);
1251 tegra_slink_deinit_dma_param(tspi
, true);
1253 free_irq(spi_irq
, tspi
);
1255 spi_master_put(master
);
1259 static int tegra_slink_remove(struct platform_device
*pdev
)
1261 struct spi_master
*master
= dev_get_drvdata(&pdev
->dev
);
1262 struct tegra_slink_data
*tspi
= spi_master_get_devdata(master
);
1264 free_irq(tspi
->irq
, tspi
);
1265 spi_unregister_master(master
);
1267 if (tspi
->tx_dma_chan
)
1268 tegra_slink_deinit_dma_param(tspi
, false);
1270 if (tspi
->rx_dma_chan
)
1271 tegra_slink_deinit_dma_param(tspi
, true);
1273 pm_runtime_disable(&pdev
->dev
);
1274 if (!pm_runtime_status_suspended(&pdev
->dev
))
1275 tegra_slink_runtime_suspend(&pdev
->dev
);
1280 #ifdef CONFIG_PM_SLEEP
1281 static int tegra_slink_suspend(struct device
*dev
)
1283 struct spi_master
*master
= dev_get_drvdata(dev
);
1285 return spi_master_suspend(master
);
1288 static int tegra_slink_resume(struct device
*dev
)
1290 struct spi_master
*master
= dev_get_drvdata(dev
);
1291 struct tegra_slink_data
*tspi
= spi_master_get_devdata(master
);
1294 ret
= pm_runtime_get_sync(dev
);
1296 dev_err(dev
, "pm runtime failed, e = %d\n", ret
);
1299 tegra_slink_writel(tspi
, tspi
->command_reg
, SLINK_COMMAND
);
1300 tegra_slink_writel(tspi
, tspi
->command2_reg
, SLINK_COMMAND2
);
1301 pm_runtime_put(dev
);
1303 return spi_master_resume(master
);
1307 static int tegra_slink_runtime_suspend(struct device
*dev
)
1309 struct spi_master
*master
= dev_get_drvdata(dev
);
1310 struct tegra_slink_data
*tspi
= spi_master_get_devdata(master
);
1312 /* Flush all write which are in PPSB queue by reading back */
1313 tegra_slink_readl(tspi
, SLINK_MAS_DATA
);
1315 clk_disable_unprepare(tspi
->clk
);
1319 static int tegra_slink_runtime_resume(struct device
*dev
)
1321 struct spi_master
*master
= dev_get_drvdata(dev
);
1322 struct tegra_slink_data
*tspi
= spi_master_get_devdata(master
);
1325 ret
= clk_prepare_enable(tspi
->clk
);
1327 dev_err(tspi
->dev
, "clk_prepare failed: %d\n", ret
);
1333 static const struct dev_pm_ops slink_pm_ops
= {
1334 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend
,
1335 tegra_slink_runtime_resume
, NULL
)
1336 SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend
, tegra_slink_resume
)
1338 static struct platform_driver tegra_slink_driver
= {
1340 .name
= "spi-tegra-slink",
1341 .owner
= THIS_MODULE
,
1342 .pm
= &slink_pm_ops
,
1343 .of_match_table
= of_match_ptr(tegra_slink_of_match
),
1345 .probe
= tegra_slink_probe
,
1346 .remove
= tegra_slink_remove
,
1348 module_platform_driver(tegra_slink_driver
);
1350 MODULE_ALIAS("platform:spi-tegra-slink");
1351 MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");
1352 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1353 MODULE_LICENSE("GPL v2");