4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sourav Poddar <sourav.poddar@ti.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GPLv2.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/omap-dma.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
29 #include <linux/slab.h>
30 #include <linux/pm_runtime.h>
32 #include <linux/of_device.h>
33 #include <linux/pinctrl/consumer.h>
35 #include <linux/spi/spi.h>
42 struct completion transfer_complete
;
44 /* list synchronization */
45 struct mutex list_lock
;
47 struct spi_master
*master
;
52 struct ti_qspi_regs ctx_reg
;
54 u32 spi_max_frequency
;
59 #define QSPI_PID (0x0)
60 #define QSPI_SYSCONFIG (0x10)
61 #define QSPI_INTR_STATUS_RAW_SET (0x20)
62 #define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
63 #define QSPI_INTR_ENABLE_SET_REG (0x28)
64 #define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
65 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
66 #define QSPI_SPI_DC_REG (0x44)
67 #define QSPI_SPI_CMD_REG (0x48)
68 #define QSPI_SPI_STATUS_REG (0x4c)
69 #define QSPI_SPI_DATA_REG (0x50)
70 #define QSPI_SPI_SETUP0_REG (0x54)
71 #define QSPI_SPI_SWITCH_REG (0x64)
72 #define QSPI_SPI_SETUP1_REG (0x58)
73 #define QSPI_SPI_SETUP2_REG (0x5c)
74 #define QSPI_SPI_SETUP3_REG (0x60)
75 #define QSPI_SPI_DATA_REG_1 (0x68)
76 #define QSPI_SPI_DATA_REG_2 (0x6c)
77 #define QSPI_SPI_DATA_REG_3 (0x70)
79 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
81 #define QSPI_FCLK 192000000
84 #define QSPI_CLK_EN (1 << 31)
85 #define QSPI_CLK_DIV_MAX 0xffff
88 #define QSPI_EN_CS(n) (n << 28)
89 #define QSPI_WLEN(n) ((n - 1) << 19)
90 #define QSPI_3_PIN (1 << 18)
91 #define QSPI_RD_SNGL (1 << 16)
92 #define QSPI_WR_SNGL (2 << 16)
93 #define QSPI_RD_DUAL (3 << 16)
94 #define QSPI_RD_QUAD (7 << 16)
95 #define QSPI_INVAL (4 << 16)
96 #define QSPI_WC_CMD_INT_EN (1 << 14)
97 #define QSPI_FLEN(n) ((n - 1) << 0)
102 /* INTERRUPT REGISTER */
103 #define QSPI_WC_INT_EN (1 << 1)
104 #define QSPI_WC_INT_DISABLE (1 << 1)
107 #define QSPI_DD(m, n) (m << (3 + n * 8))
108 #define QSPI_CKPHA(n) (1 << (2 + n * 8))
109 #define QSPI_CSPOL(n) (1 << (1 + n * 8))
110 #define QSPI_CKPOL(n) (1 << (n * 8))
112 #define QSPI_FRAME 4096
114 #define QSPI_AUTOSUSPEND_TIMEOUT 2000
116 static inline unsigned long ti_qspi_read(struct ti_qspi
*qspi
,
119 return readl(qspi
->base
+ reg
);
122 static inline void ti_qspi_write(struct ti_qspi
*qspi
,
123 unsigned long val
, unsigned long reg
)
125 writel(val
, qspi
->base
+ reg
);
128 static int ti_qspi_setup(struct spi_device
*spi
)
130 struct ti_qspi
*qspi
= spi_master_get_devdata(spi
->master
);
131 struct ti_qspi_regs
*ctx_reg
= &qspi
->ctx_reg
;
132 int clk_div
= 0, ret
;
133 u32 clk_ctrl_reg
, clk_rate
, clk_mask
;
135 if (spi
->master
->busy
) {
136 dev_dbg(qspi
->dev
, "master busy doing other trasnfers\n");
140 if (!qspi
->spi_max_frequency
) {
141 dev_err(qspi
->dev
, "spi max frequency not defined\n");
145 clk_rate
= clk_get_rate(qspi
->fclk
);
147 clk_div
= DIV_ROUND_UP(clk_rate
, qspi
->spi_max_frequency
) - 1;
150 dev_dbg(qspi
->dev
, "clock divider < 0, using /1 divider\n");
154 if (clk_div
> QSPI_CLK_DIV_MAX
) {
155 dev_dbg(qspi
->dev
, "clock divider >%d , using /%d divider\n",
156 QSPI_CLK_DIV_MAX
, QSPI_CLK_DIV_MAX
+ 1);
160 dev_dbg(qspi
->dev
, "hz: %d, clock divider %d\n",
161 qspi
->spi_max_frequency
, clk_div
);
163 ret
= pm_runtime_get_sync(qspi
->dev
);
165 dev_err(qspi
->dev
, "pm_runtime_get_sync() failed\n");
169 clk_ctrl_reg
= ti_qspi_read(qspi
, QSPI_SPI_CLOCK_CNTRL_REG
);
171 clk_ctrl_reg
&= ~QSPI_CLK_EN
;
174 ti_qspi_write(qspi
, clk_ctrl_reg
, QSPI_SPI_CLOCK_CNTRL_REG
);
177 clk_mask
= QSPI_CLK_EN
| clk_div
;
178 ti_qspi_write(qspi
, clk_mask
, QSPI_SPI_CLOCK_CNTRL_REG
);
179 ctx_reg
->clkctrl
= clk_mask
;
181 pm_runtime_mark_last_busy(qspi
->dev
);
182 ret
= pm_runtime_put_autosuspend(qspi
->dev
);
184 dev_err(qspi
->dev
, "pm_runtime_put_autosuspend() failed\n");
191 static void ti_qspi_restore_ctx(struct ti_qspi
*qspi
)
193 struct ti_qspi_regs
*ctx_reg
= &qspi
->ctx_reg
;
195 ti_qspi_write(qspi
, ctx_reg
->clkctrl
, QSPI_SPI_CLOCK_CNTRL_REG
);
198 static int qspi_write_msg(struct ti_qspi
*qspi
, struct spi_transfer
*t
)
200 int wlen
, count
, ret
;
205 cmd
= qspi
->cmd
| QSPI_WR_SNGL
;
207 wlen
= t
->bits_per_word
;
212 dev_dbg(qspi
->dev
, "tx cmd %08x dc %08x data %02x\n",
213 cmd
, qspi
->dc
, *txbuf
);
214 writeb(*txbuf
, qspi
->base
+ QSPI_SPI_DATA_REG
);
215 ti_qspi_write(qspi
, cmd
, QSPI_SPI_CMD_REG
);
216 ret
= wait_for_completion_timeout(&qspi
->transfer_complete
,
217 QSPI_COMPLETION_TIMEOUT
);
219 dev_err(qspi
->dev
, "write timed out\n");
226 dev_dbg(qspi
->dev
, "tx cmd %08x dc %08x data %04x\n",
227 cmd
, qspi
->dc
, *txbuf
);
228 writew(*((u16
*)txbuf
), qspi
->base
+ QSPI_SPI_DATA_REG
);
229 ti_qspi_write(qspi
, cmd
, QSPI_SPI_CMD_REG
);
230 ret
= wait_for_completion_timeout(&qspi
->transfer_complete
,
231 QSPI_COMPLETION_TIMEOUT
);
233 dev_err(qspi
->dev
, "write timed out\n");
240 dev_dbg(qspi
->dev
, "tx cmd %08x dc %08x data %08x\n",
241 cmd
, qspi
->dc
, *txbuf
);
242 writel(*((u32
*)txbuf
), qspi
->base
+ QSPI_SPI_DATA_REG
);
243 ti_qspi_write(qspi
, cmd
, QSPI_SPI_CMD_REG
);
244 ret
= wait_for_completion_timeout(&qspi
->transfer_complete
,
245 QSPI_COMPLETION_TIMEOUT
);
247 dev_err(qspi
->dev
, "write timed out\n");
259 static int qspi_read_msg(struct ti_qspi
*qspi
, struct spi_transfer
*t
)
261 int wlen
, count
, ret
;
267 switch (t
->rx_nbits
) {
279 wlen
= t
->bits_per_word
;
282 dev_dbg(qspi
->dev
, "rx cmd %08x dc %08x\n", cmd
, qspi
->dc
);
283 ti_qspi_write(qspi
, cmd
, QSPI_SPI_CMD_REG
);
284 ret
= wait_for_completion_timeout(&qspi
->transfer_complete
,
285 QSPI_COMPLETION_TIMEOUT
);
287 dev_err(qspi
->dev
, "read timed out\n");
292 *rxbuf
= readb(qspi
->base
+ QSPI_SPI_DATA_REG
);
297 *((u16
*)rxbuf
) = readw(qspi
->base
+ QSPI_SPI_DATA_REG
);
302 *((u32
*)rxbuf
) = readl(qspi
->base
+ QSPI_SPI_DATA_REG
);
312 static int qspi_transfer_msg(struct ti_qspi
*qspi
, struct spi_transfer
*t
)
317 ret
= qspi_write_msg(qspi
, t
);
319 dev_dbg(qspi
->dev
, "Error while writing\n");
325 ret
= qspi_read_msg(qspi
, t
);
327 dev_dbg(qspi
->dev
, "Error while reading\n");
335 static int ti_qspi_start_transfer_one(struct spi_master
*master
,
336 struct spi_message
*m
)
338 struct ti_qspi
*qspi
= spi_master_get_devdata(master
);
339 struct spi_device
*spi
= m
->spi
;
340 struct spi_transfer
*t
;
344 /* setup device control reg */
347 if (spi
->mode
& SPI_CPHA
)
348 qspi
->dc
|= QSPI_CKPHA(spi
->chip_select
);
349 if (spi
->mode
& SPI_CPOL
)
350 qspi
->dc
|= QSPI_CKPOL(spi
->chip_select
);
351 if (spi
->mode
& SPI_CS_HIGH
)
352 qspi
->dc
|= QSPI_CSPOL(spi
->chip_select
);
354 frame_length
= (m
->frame_length
<< 3) / spi
->bits_per_word
;
356 frame_length
= clamp(frame_length
, 0, QSPI_FRAME
);
358 /* setup command reg */
360 qspi
->cmd
|= QSPI_EN_CS(spi
->chip_select
);
361 qspi
->cmd
|= QSPI_FLEN(frame_length
);
362 qspi
->cmd
|= QSPI_WC_CMD_INT_EN
;
364 ti_qspi_write(qspi
, QSPI_WC_INT_EN
, QSPI_INTR_ENABLE_SET_REG
);
365 ti_qspi_write(qspi
, qspi
->dc
, QSPI_SPI_DC_REG
);
367 mutex_lock(&qspi
->list_lock
);
369 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
370 qspi
->cmd
|= QSPI_WLEN(t
->bits_per_word
);
372 ret
= qspi_transfer_msg(qspi
, t
);
374 dev_dbg(qspi
->dev
, "transfer message failed\n");
375 mutex_unlock(&qspi
->list_lock
);
379 m
->actual_length
+= t
->len
;
382 mutex_unlock(&qspi
->list_lock
);
385 spi_finalize_current_message(master
);
387 ti_qspi_write(qspi
, qspi
->cmd
| QSPI_INVAL
, QSPI_SPI_CMD_REG
);
392 static irqreturn_t
ti_qspi_isr(int irq
, void *dev_id
)
394 struct ti_qspi
*qspi
= dev_id
;
398 irqreturn_t ret
= IRQ_HANDLED
;
400 int_stat
= ti_qspi_read(qspi
, QSPI_INTR_STATUS_ENABLED_CLEAR
);
401 stat
= ti_qspi_read(qspi
, QSPI_SPI_STATUS_REG
);
404 dev_dbg(qspi
->dev
, "No IRQ triggered\n");
409 ti_qspi_write(qspi
, QSPI_WC_INT_DISABLE
,
410 QSPI_INTR_STATUS_ENABLED_CLEAR
);
412 complete(&qspi
->transfer_complete
);
417 static int ti_qspi_runtime_resume(struct device
*dev
)
419 struct ti_qspi
*qspi
;
420 struct spi_master
*master
;
422 master
= dev_get_drvdata(dev
);
423 qspi
= spi_master_get_devdata(master
);
424 ti_qspi_restore_ctx(qspi
);
429 static const struct of_device_id ti_qspi_match
[] = {
430 {.compatible
= "ti,dra7xxx-qspi" },
431 {.compatible
= "ti,am4372-qspi" },
434 MODULE_DEVICE_TABLE(of
, ti_qspi_match
);
436 static int ti_qspi_probe(struct platform_device
*pdev
)
438 struct ti_qspi
*qspi
;
439 struct spi_master
*master
;
441 struct device_node
*np
= pdev
->dev
.of_node
;
443 int ret
= 0, num_cs
, irq
;
445 master
= spi_alloc_master(&pdev
->dev
, sizeof(*qspi
));
449 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_RX_DUAL
| SPI_RX_QUAD
;
451 master
->bus_num
= -1;
452 master
->flags
= SPI_MASTER_HALF_DUPLEX
;
453 master
->setup
= ti_qspi_setup
;
454 master
->auto_runtime_pm
= true;
455 master
->transfer_one_message
= ti_qspi_start_transfer_one
;
456 master
->dev
.of_node
= pdev
->dev
.of_node
;
457 master
->bits_per_word_mask
= BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
459 if (!of_property_read_u32(np
, "num-cs", &num_cs
))
460 master
->num_chipselect
= num_cs
;
462 platform_set_drvdata(pdev
, master
);
464 qspi
= spi_master_get_devdata(master
);
465 qspi
->master
= master
;
466 qspi
->dev
= &pdev
->dev
;
468 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
470 irq
= platform_get_irq(pdev
, 0);
472 dev_err(&pdev
->dev
, "no irq resource?\n");
476 mutex_init(&qspi
->list_lock
);
478 qspi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
479 if (IS_ERR(qspi
->base
)) {
480 ret
= PTR_ERR(qspi
->base
);
484 ret
= devm_request_irq(&pdev
->dev
, irq
, ti_qspi_isr
, 0,
485 dev_name(&pdev
->dev
), qspi
);
487 dev_err(&pdev
->dev
, "Failed to register ISR for IRQ %d\n",
492 qspi
->fclk
= devm_clk_get(&pdev
->dev
, "fck");
493 if (IS_ERR(qspi
->fclk
)) {
494 ret
= PTR_ERR(qspi
->fclk
);
495 dev_err(&pdev
->dev
, "could not get clk: %d\n", ret
);
498 init_completion(&qspi
->transfer_complete
);
500 pm_runtime_use_autosuspend(&pdev
->dev
);
501 pm_runtime_set_autosuspend_delay(&pdev
->dev
, QSPI_AUTOSUSPEND_TIMEOUT
);
502 pm_runtime_enable(&pdev
->dev
);
504 if (!of_property_read_u32(np
, "spi-max-frequency", &max_freq
))
505 qspi
->spi_max_frequency
= max_freq
;
507 ret
= spi_register_master(master
);
514 spi_master_put(master
);
518 static int ti_qspi_remove(struct platform_device
*pdev
)
520 struct ti_qspi
*qspi
= platform_get_drvdata(pdev
);
522 ti_qspi_write(qspi
, QSPI_WC_INT_DISABLE
, QSPI_INTR_ENABLE_CLEAR_REG
);
523 spi_unregister_master(qspi
->master
);
528 static const struct dev_pm_ops ti_qspi_pm_ops
= {
529 .runtime_resume
= ti_qspi_runtime_resume
,
532 static struct platform_driver ti_qspi_driver
= {
533 .probe
= ti_qspi_probe
,
534 .remove
= ti_qspi_remove
,
536 .name
= "ti,dra7xxx-qspi",
537 .owner
= THIS_MODULE
,
538 .pm
= &ti_qspi_pm_ops
,
539 .of_match_table
= ti_qspi_match
,
543 module_platform_driver(ti_qspi_driver
);
545 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
546 MODULE_LICENSE("GPL v2");
547 MODULE_DESCRIPTION("TI QSPI controller driver");