projects / deliverable / linux.git / blob
? search:


c36d516570666c7a6767b89c80d4a5f2e574928d
[deliverable/linux.git] / drivers / spi / spi-topcliff-pch.c
1 /*
2 * SPI bus driver for the Topcliff PCH used by Intel SoCs
3 *
4 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/wait.h>
23 #include <linux/spi/spi.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/spi/spidev.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30
31 #include <linux/dmaengine.h>
32 #include <linux/pch_dma.h>
33
34 /* Register offsets */
35 #define PCH_SPCR 0x00 /* SPI control register */
36 #define PCH_SPBRR 0x04 /* SPI baud rate register */
37 #define PCH_SPSR 0x08 /* SPI status register */
38 #define PCH_SPDWR 0x0C /* SPI write data register */
39 #define PCH_SPDRR 0x10 /* SPI read data register */
40 #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
41 #define PCH_SRST 0x1C /* SPI reset register */
42 #define PCH_ADDRESS_SIZE 0x20
43
44 #define PCH_SPSR_TFD 0x000007C0
45 #define PCH_SPSR_RFD 0x0000F800
46
47 #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11)
48 #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6)
49
50 #define PCH_RX_THOLD 7
51 #define PCH_RX_THOLD_MAX 15
52
53 #define PCH_MAX_BAUDRATE 5000000
54 #define PCH_MAX_FIFO_DEPTH 16
55
56 #define STATUS_RUNNING 1
57 #define STATUS_EXITING 2
58 #define PCH_SLEEP_TIME 10
59
60 #define SSN_LOW 0x02U
61 #define SSN_HIGH 0x03U
62 #define SSN_NO_CONTROL 0x00U
63 #define PCH_MAX_CS 0xFF
64 #define PCI_DEVICE_ID_GE_SPI 0x8816
65
66 #define SPCR_SPE_BIT (1 << 0)
67 #define SPCR_MSTR_BIT (1 << 1)
68 #define SPCR_LSBF_BIT (1 << 4)
69 #define SPCR_CPHA_BIT (1 << 5)
70 #define SPCR_CPOL_BIT (1 << 6)
71 #define SPCR_TFIE_BIT (1 << 8)
72 #define SPCR_RFIE_BIT (1 << 9)
73 #define SPCR_FIE_BIT (1 << 10)
74 #define SPCR_ORIE_BIT (1 << 11)
75 #define SPCR_MDFIE_BIT (1 << 12)
76 #define SPCR_FICLR_BIT (1 << 24)
77 #define SPSR_TFI_BIT (1 << 0)
78 #define SPSR_RFI_BIT (1 << 1)
79 #define SPSR_FI_BIT (1 << 2)
80 #define SPSR_ORF_BIT (1 << 3)
81 #define SPBRR_SIZE_BIT (1 << 10)
82
83 #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
84 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
85
86 #define SPCR_RFIC_FIELD 20
87 #define SPCR_TFIC_FIELD 16
88
89 #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
90 #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD)
91 #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD)
92
93 #define PCH_CLOCK_HZ 50000000
94 #define PCH_MAX_SPBR 1023
95
96 /* Definition for ML7213 by OKI SEMICONDUCTOR */
97 #define PCI_VENDOR_ID_ROHM 0x10DB
98 #define PCI_DEVICE_ID_ML7213_SPI 0x802c
99 #define PCI_DEVICE_ID_ML7223_SPI 0x800F
100
101 /*
102 * Set the number of SPI instance max
103 * Intel EG20T PCH : 1ch
104 * OKI SEMICONDUCTOR ML7213 IOH : 2ch
105 * OKI SEMICONDUCTOR ML7223 IOH : 1ch
106 */
107 #define PCH_SPI_MAX_DEV 2
108
109 #define PCH_BUF_SIZE 4096
110 #define PCH_DMA_TRANS_SIZE 12
111
112 static int use_dma = 1;
113
114 struct pch_spi_dma_ctrl {
115 struct dma_async_tx_descriptor *desc_tx;
116 struct dma_async_tx_descriptor *desc_rx;
117 struct pch_dma_slave param_tx;
118 struct pch_dma_slave param_rx;
119 struct dma_chan *chan_tx;
120 struct dma_chan *chan_rx;
121 struct scatterlist *sg_tx_p;
122 struct scatterlist *sg_rx_p;
123 struct scatterlist sg_tx;
124 struct scatterlist sg_rx;
125 int nent;
126 void *tx_buf_virt;
127 void *rx_buf_virt;
128 dma_addr_t tx_buf_dma;
129 dma_addr_t rx_buf_dma;
130 };
131 /**
132 * struct pch_spi_data - Holds the SPI channel specific details
133 * @io_remap_addr: The remapped PCI base address
134 * @master: Pointer to the SPI master structure
135 * @work: Reference to work queue handler
136 * @wk: Workqueue for carrying out execution of the
137 * requests
138 * @wait: Wait queue for waking up upon receiving an
139 * interrupt.
140 * @transfer_complete: Status of SPI Transfer
141 * @bcurrent_msg_processing: Status flag for message processing
142 * @lock: Lock for protecting this structure
143 * @queue: SPI Message queue
144 * @status: Status of the SPI driver
145 * @bpw_len: Length of data to be transferred in bits per
146 * word
147 * @transfer_active: Flag showing active transfer
148 * @tx_index: Transmit data count; for bookkeeping during
149 * transfer
150 * @rx_index: Receive data count; for bookkeeping during
151 * transfer
152 * @tx_buff: Buffer for data to be transmitted
153 * @rx_index: Buffer for Received data
154 * @n_curnt_chip: The chip number that this SPI driver currently
155 * operates on
156 * @current_chip: Reference to the current chip that this SPI
157 * driver currently operates on
158 * @current_msg: The current message that this SPI driver is
159 * handling
160 * @cur_trans: The current transfer that this SPI driver is
161 * handling
162 * @board_dat: Reference to the SPI device data structure
163 * @plat_dev: platform_device structure
164 * @ch: SPI channel number
165 * @irq_reg_sts: Status of IRQ registration
166 */
167 struct pch_spi_data {
168 void __iomem *io_remap_addr;
169 unsigned long io_base_addr;
170 struct spi_master *master;
171 struct work_struct work;
172 struct workqueue_struct *wk;
173 wait_queue_head_t wait;
174 u8 transfer_complete;
175 u8 bcurrent_msg_processing;
176 spinlock_t lock;
177 struct list_head queue;
178 u8 status;
179 u32 bpw_len;
180 u8 transfer_active;
181 u32 tx_index;
182 u32 rx_index;
183 u16 *pkt_tx_buff;
184 u16 *pkt_rx_buff;
185 u8 n_curnt_chip;
186 struct spi_device *current_chip;
187 struct spi_message *current_msg;
188 struct spi_transfer *cur_trans;
189 struct pch_spi_board_data *board_dat;
190 struct platform_device *plat_dev;
191 int ch;
192 struct pch_spi_dma_ctrl dma;
193 int use_dma;
194 u8 irq_reg_sts;
195 };
196
197 /**
198 * struct pch_spi_board_data - Holds the SPI device specific details
199 * @pdev: Pointer to the PCI device
200 * @suspend_sts: Status of suspend
201 * @num: The number of SPI device instance
202 */
203 struct pch_spi_board_data {
204 struct pci_dev *pdev;
205 u8 suspend_sts;
206 int num;
207 };
208
209 struct pch_pd_dev_save {
210 int num;
211 struct platform_device *pd_save[PCH_SPI_MAX_DEV];
212 struct pch_spi_board_data *board_dat;
213 };
214
215 static struct pci_device_id pch_spi_pcidev_id[] = {
216 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
217 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
218 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
219 { }
220 };
221
222 /**
223 * pch_spi_writereg() - Performs register writes
224 * @master: Pointer to struct spi_master.
225 * @idx: Register offset.
226 * @val: Value to be written to register.
227 */
228 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
229 {
230 struct pch_spi_data *data = spi_master_get_devdata(master);
231 iowrite32(val, (data->io_remap_addr + idx));
232 }
233
234 /**
235 * pch_spi_readreg() - Performs register reads
236 * @master: Pointer to struct spi_master.
237 * @idx: Register offset.
238 */
239 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
240 {
241 struct pch_spi_data *data = spi_master_get_devdata(master);
242 return ioread32(data->io_remap_addr + idx);
243 }
244
245 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
246 u32 set, u32 clr)
247 {
248 u32 tmp = pch_spi_readreg(master, idx);
249 tmp = (tmp & ~clr) | set;
250 pch_spi_writereg(master, idx, tmp);
251 }
252
253 static void pch_spi_set_master_mode(struct spi_master *master)
254 {
255 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
256 }
257
258 /**
259 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
260 * @master: Pointer to struct spi_master.
261 */
262 static void pch_spi_clear_fifo(struct spi_master *master)
263 {
264 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
265 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
266 }
267
268 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
269 void __iomem *io_remap_addr)
270 {
271 u32 n_read, tx_index, rx_index, bpw_len;
272 u16 *pkt_rx_buffer, *pkt_tx_buff;
273 int read_cnt;
274 u32 reg_spcr_val;
275 void __iomem *spsr;
276 void __iomem *spdrr;
277 void __iomem *spdwr;
278
279 spsr = io_remap_addr + PCH_SPSR;
280 iowrite32(reg_spsr_val, spsr);
281
282 if (data->transfer_active) {
283 rx_index = data->rx_index;
284 tx_index = data->tx_index;
285 bpw_len = data->bpw_len;
286 pkt_rx_buffer = data->pkt_rx_buff;
287 pkt_tx_buff = data->pkt_tx_buff;
288
289 spdrr = io_remap_addr + PCH_SPDRR;
290 spdwr = io_remap_addr + PCH_SPDWR;
291
292 n_read = PCH_READABLE(reg_spsr_val);
293
294 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
295 pkt_rx_buffer[rx_index++] = ioread32(spdrr);
296 if (tx_index < bpw_len)
297 iowrite32(pkt_tx_buff[tx_index++], spdwr);
298 }
299
300 /* disable RFI if not needed */
301 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
302 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
303 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
304
305 /* reset rx threshold */
306 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
307 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
308
309 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
310 }
311
312 /* update counts */
313 data->tx_index = tx_index;
314 data->rx_index = rx_index;
315
316 }
317
318 /* if transfer complete interrupt */
319 if (reg_spsr_val & SPSR_FI_BIT) {
320 if (tx_index < bpw_len)
321 dev_err(&data->master->dev,
322 "%s : Transfer is not completed", __func__);
323 /* disable interrupts */
324 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
325
326 /* transfer is completed;inform pch_spi_process_messages */
327 data->transfer_complete = true;
328 data->transfer_active = false;
329 wake_up(&data->wait);
330 }
331 }
332
333 /**
334 * pch_spi_handler() - Interrupt handler
335 * @irq: The interrupt number.
336 * @dev_id: Pointer to struct pch_spi_board_data.
337 */
338 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
339 {
340 u32 reg_spsr_val;
341 void __iomem *spsr;
342 void __iomem *io_remap_addr;
343 irqreturn_t ret = IRQ_NONE;
344 struct pch_spi_data *data = dev_id;
345 struct pch_spi_board_data *board_dat = data->board_dat;
346
347 if (board_dat->suspend_sts) {
348 dev_dbg(&board_dat->pdev->dev,
349 "%s returning due to suspend\n", __func__);
350 return IRQ_NONE;
351 }
352 if (data->use_dma)
353 return IRQ_NONE;
354
355 io_remap_addr = data->io_remap_addr;
356 spsr = io_remap_addr + PCH_SPSR;
357
358 reg_spsr_val = ioread32(spsr);
359
360 if (reg_spsr_val & SPSR_ORF_BIT)
361 dev_err(&board_dat->pdev->dev, "%s Over run error", __func__);
362
363 /* Check if the interrupt is for SPI device */
364 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
365 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
366 ret = IRQ_HANDLED;
367 }
368
369 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
370 __func__, ret);
371
372 return ret;
373 }
374
375 /**
376 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
377 * @master: Pointer to struct spi_master.
378 * @speed_hz: Baud rate.
379 */
380 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
381 {
382 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
383
384 /* if baud rate is less than we can support limit it */
385 if (n_spbr > PCH_MAX_SPBR)
386 n_spbr = PCH_MAX_SPBR;
387
388 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
389 }
390
391 /**
392 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
393 * @master: Pointer to struct spi_master.
394 * @bits_per_word: Bits per word for SPI transfer.
395 */
396 static void pch_spi_set_bits_per_word(struct spi_master *master,
397 u8 bits_per_word)
398 {
399 if (bits_per_word == 8)
400 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
401 else
402 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
403 }
404
405 /**
406 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
407 * @spi: Pointer to struct spi_device.
408 */
409 static void pch_spi_setup_transfer(struct spi_device *spi)
410 {
411 u32 flags = 0;
412
413 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
414 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
415 spi->max_speed_hz);
416 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
417
418 /* set bits per word */
419 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
420
421 if (!(spi->mode & SPI_LSB_FIRST))
422 flags |= SPCR_LSBF_BIT;
423 if (spi->mode & SPI_CPOL)
424 flags |= SPCR_CPOL_BIT;
425 if (spi->mode & SPI_CPHA)
426 flags |= SPCR_CPHA_BIT;
427 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
428 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
429
430 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */
431 pch_spi_clear_fifo(spi->master);
432 }
433
434 /**
435 * pch_spi_reset() - Clears SPI registers
436 * @master: Pointer to struct spi_master.
437 */
438 static void pch_spi_reset(struct spi_master *master)
439 {
440 /* write 1 to reset SPI */
441 pch_spi_writereg(master, PCH_SRST, 0x1);
442
443 /* clear reset */
444 pch_spi_writereg(master, PCH_SRST, 0x0);
445 }
446
447 static int pch_spi_setup(struct spi_device *pspi)
448 {
449 /* check bits per word */
450 if (pspi->bits_per_word == 0) {
451 pspi->bits_per_word = 8;
452 dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__);
453 }
454
455 if ((pspi->bits_per_word != 8) && (pspi->bits_per_word != 16)) {
456 dev_err(&pspi->dev, "%s Invalid bits per word\n", __func__);
457 return -EINVAL;
458 }
459
460 /* Check baud rate setting */
461 /* if baud rate of chip is greater than
462 max we can support,return error */
463 if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE)
464 pspi->max_speed_hz = PCH_MAX_BAUDRATE;
465
466 dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__,
467 (pspi->mode) & (SPI_CPOL | SPI_CPHA));
468
469 return 0;
470 }
471
472 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
473 {
474
475 struct spi_transfer *transfer;
476 struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
477 int retval;
478 unsigned long flags;
479
480 /* validate spi message and baud rate */
481 if (unlikely(list_empty(&pmsg->transfers) == 1)) {
482 dev_err(&pspi->dev, "%s list empty\n", __func__);
483 retval = -EINVAL;
484 goto err_out;
485 }
486
487 if (unlikely(pspi->max_speed_hz == 0)) {
488 dev_err(&pspi->dev, "%s pch_spi_tranfer maxspeed=%d\n",
489 __func__, pspi->max_speed_hz);
490 retval = -EINVAL;
491 goto err_out;
492 }
493
494 dev_dbg(&pspi->dev, "%s Transfer List not empty. "
495 "Transfer Speed is set.\n", __func__);
496
497 spin_lock_irqsave(&data->lock, flags);
498 /* validate Tx/Rx buffers and Transfer length */
499 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
500 if (!transfer->tx_buf && !transfer->rx_buf) {
501 dev_err(&pspi->dev,
502 "%s Tx and Rx buffer NULL\n", __func__);
503 retval = -EINVAL;
504 goto err_return_spinlock;
505 }
506
507 if (!transfer->len) {
508 dev_err(&pspi->dev, "%s Transfer length invalid\n",
509 __func__);
510 retval = -EINVAL;
511 goto err_return_spinlock;
512 }
513
514 dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length"
515 " valid\n", __func__);
516
517 /* if baud rate has been specified validate the same */
518 if (transfer->speed_hz > PCH_MAX_BAUDRATE)
519 transfer->speed_hz = PCH_MAX_BAUDRATE;
520
521 /* if bits per word has been specified validate the same */
522 if (transfer->bits_per_word) {
523 if ((transfer->bits_per_word != 8)
524 && (transfer->bits_per_word != 16)) {
525 retval = -EINVAL;
526 dev_err(&pspi->dev,
527 "%s Invalid bits per word\n", __func__);
528 goto err_return_spinlock;
529 }
530 }
531 }
532 spin_unlock_irqrestore(&data->lock, flags);
533
534 /* We won't process any messages if we have been asked to terminate */
535 if (data->status == STATUS_EXITING) {
536 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
537 retval = -ESHUTDOWN;
538 goto err_out;
539 }
540
541 /* If suspended ,return -EINVAL */
542 if (data->board_dat->suspend_sts) {
543 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
544 retval = -EINVAL;
545 goto err_out;
546 }
547
548 /* set status of message */
549 pmsg->actual_length = 0;
550 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
551
552 pmsg->status = -EINPROGRESS;
553 spin_lock_irqsave(&data->lock, flags);
554 /* add message to queue */
555 list_add_tail(&pmsg->queue, &data->queue);
556 spin_unlock_irqrestore(&data->lock, flags);
557
558 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
559
560 /* schedule work queue to run */
561 queue_work(data->wk, &data->work);
562 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
563
564 retval = 0;
565
566 err_out:
567 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
568 return retval;
569 err_return_spinlock:
570 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
571 spin_unlock_irqrestore(&data->lock, flags);
572 return retval;
573 }
574
575 static inline void pch_spi_select_chip(struct pch_spi_data *data,
576 struct spi_device *pspi)
577 {
578 if (data->current_chip != NULL) {
579 if (pspi->chip_select != data->n_curnt_chip) {
580 dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
581 data->current_chip = NULL;
582 }
583 }
584
585 data->current_chip = pspi;
586
587 data->n_curnt_chip = data->current_chip->chip_select;
588
589 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
590 pch_spi_setup_transfer(pspi);
591 }
592
593 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
594 {
595 int size;
596 u32 n_writes;
597 int j;
598 struct spi_message *pmsg;
599 const u8 *tx_buf;
600 const u16 *tx_sbuf;
601
602 /* set baud rate if needed */
603 if (data->cur_trans->speed_hz) {
604 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
605 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
606 }
607
608 /* set bits per word if needed */
609 if (data->cur_trans->bits_per_word &&
610 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
611 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
612 pch_spi_set_bits_per_word(data->master,
613 data->cur_trans->bits_per_word);
614 *bpw = data->cur_trans->bits_per_word;
615 } else {
616 *bpw = data->current_msg->spi->bits_per_word;
617 }
618
619 /* reset Tx/Rx index */
620 data->tx_index = 0;
621 data->rx_index = 0;
622
623 data->bpw_len = data->cur_trans->len / (*bpw / 8);
624
625 /* find alloc size */
626 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
627
628 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
629 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
630 if (data->pkt_tx_buff != NULL) {
631 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
632 if (!data->pkt_rx_buff)
633 kfree(data->pkt_tx_buff);
634 }
635
636 if (!data->pkt_rx_buff) {
637 /* flush queue and set status of all transfers to -ENOMEM */
638 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
639 list_for_each_entry(pmsg, data->queue.next, queue) {
640 pmsg->status = -ENOMEM;
641
642 if (pmsg->complete != 0)
643 pmsg->complete(pmsg->context);
644
645 /* delete from queue */
646 list_del_init(&pmsg->queue);
647 }
648 return;
649 }
650
651 /* copy Tx Data */
652 if (data->cur_trans->tx_buf != NULL) {
653 if (*bpw == 8) {
654 tx_buf = data->cur_trans->tx_buf;
655 for (j = 0; j < data->bpw_len; j++)
656 data->pkt_tx_buff[j] = *tx_buf++;
657 } else {
658 tx_sbuf = data->cur_trans->tx_buf;
659 for (j = 0; j < data->bpw_len; j++)
660 data->pkt_tx_buff[j] = *tx_sbuf++;
661 }
662 }
663
664 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
665 n_writes = data->bpw_len;
666 if (n_writes > PCH_MAX_FIFO_DEPTH)
667 n_writes = PCH_MAX_FIFO_DEPTH;
668
669 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
670 "0x2 to SSNXCR\n", __func__);
671 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
672
673 for (j = 0; j < n_writes; j++)
674 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
675
676 /* update tx_index */
677 data->tx_index = j;
678
679 /* reset transfer complete flag */
680 data->transfer_complete = false;
681 data->transfer_active = true;
682 }
683
684 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
685 {
686 struct spi_message *pmsg;
687 dev_dbg(&data->master->dev, "%s called\n", __func__);
688 /* Invoke complete callback
689 * [To the spi core..indicating end of transfer] */
690 data->current_msg->status = 0;
691
692 if (data->current_msg->complete != 0) {
693 dev_dbg(&data->master->dev,
694 "%s:Invoking callback of SPI core\n", __func__);
695 data->current_msg->complete(data->current_msg->context);
696 }
697
698 /* update status in global variable */
699 data->bcurrent_msg_processing = false;
700
701 dev_dbg(&data->master->dev,
702 "%s:data->bcurrent_msg_processing = false\n", __func__);
703
704 data->current_msg = NULL;
705 data->cur_trans = NULL;
706
707 /* check if we have items in list and not suspending
708 * return 1 if list empty */
709 if ((list_empty(&data->queue) == 0) &&
710 (!data->board_dat->suspend_sts) &&
711 (data->status != STATUS_EXITING)) {
712 /* We have some more work to do (either there is more tranint
713 * bpw;sfer requests in the current message or there are
714 *more messages)
715 */
716 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
717 queue_work(data->wk, &data->work);
718 } else if (data->board_dat->suspend_sts ||
719 data->status == STATUS_EXITING) {
720 dev_dbg(&data->master->dev,
721 "%s suspend/remove initiated, flushing queue\n",
722 __func__);
723 list_for_each_entry(pmsg, data->queue.next, queue) {
724 pmsg->status = -EIO;
725
726 if (pmsg->complete)
727 pmsg->complete(pmsg->context);
728
729 /* delete from queue */
730 list_del_init(&pmsg->queue);
731 }
732 }
733 }
734
735 static void pch_spi_set_ir(struct pch_spi_data *data)
736 {
737 /* enable interrupts, set threshold, enable SPI */
738 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
739 /* set receive threshold to PCH_RX_THOLD */
740 pch_spi_setclr_reg(data->master, PCH_SPCR,
741 PCH_RX_THOLD << SPCR_RFIC_FIELD |
742 SPCR_FIE_BIT | SPCR_RFIE_BIT |
743 SPCR_ORIE_BIT | SPCR_SPE_BIT,
744 MASK_RFIC_SPCR_BITS | PCH_ALL);
745 else
746 /* set receive threshold to maximum */
747 pch_spi_setclr_reg(data->master, PCH_SPCR,
748 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
749 SPCR_FIE_BIT | SPCR_ORIE_BIT |
750 SPCR_SPE_BIT,
751 MASK_RFIC_SPCR_BITS | PCH_ALL);
752
753 /* Wait until the transfer completes; go to sleep after
754 initiating the transfer. */
755 dev_dbg(&data->master->dev,
756 "%s:waiting for transfer to get over\n", __func__);
757
758 wait_event_interruptible(data->wait, data->transfer_complete);
759
760 /* clear all interrupts */
761 pch_spi_writereg(data->master, PCH_SPSR,
762 pch_spi_readreg(data->master, PCH_SPSR));
763 /* Disable interrupts and SPI transfer */
764 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
765 /* clear FIFO */
766 pch_spi_clear_fifo(data->master);
767 }
768
769 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
770 {
771 int j;
772 u8 *rx_buf;
773 u16 *rx_sbuf;
774
775 /* copy Rx Data */
776 if (!data->cur_trans->rx_buf)
777 return;
778
779 if (bpw == 8) {
780 rx_buf = data->cur_trans->rx_buf;
781 for (j = 0; j < data->bpw_len; j++)
782 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
783 } else {
784 rx_sbuf = data->cur_trans->rx_buf;
785 for (j = 0; j < data->bpw_len; j++)
786 *rx_sbuf++ = data->pkt_rx_buff[j];
787 }
788 }
789
790 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
791 {
792 int j;
793 u8 *rx_buf;
794 u16 *rx_sbuf;
795 const u8 *rx_dma_buf;
796 const u16 *rx_dma_sbuf;
797
798 /* copy Rx Data */
799 if (!data->cur_trans->rx_buf)
800 return;
801
802 if (bpw == 8) {
803 rx_buf = data->cur_trans->rx_buf;
804 rx_dma_buf = data->dma.rx_buf_virt;
805 for (j = 0; j < data->bpw_len; j++)
806 *rx_buf++ = *rx_dma_buf++ & 0xFF;
807 } else {
808 rx_sbuf = data->cur_trans->rx_buf;
809 rx_dma_sbuf = data->dma.rx_buf_virt;
810 for (j = 0; j < data->bpw_len; j++)
811 *rx_sbuf++ = *rx_dma_sbuf++;
812 }
813 }
814
815 static void pch_spi_start_transfer(struct pch_spi_data *data)
816 {
817 struct pch_spi_dma_ctrl *dma;
818 unsigned long flags;
819
820 dma = &data->dma;
821
822 spin_lock_irqsave(&data->lock, flags);
823
824 /* disable interrupts, SPI set enable */
825 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
826
827 spin_unlock_irqrestore(&data->lock, flags);
828
829 /* Wait until the transfer completes; go to sleep after
830 initiating the transfer. */
831 dev_dbg(&data->master->dev,
832 "%s:waiting for transfer to get over\n", __func__);
833 wait_event_interruptible(data->wait, data->transfer_complete);
834
835 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
836 DMA_FROM_DEVICE);
837
838 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
839 DMA_FROM_DEVICE);
840 memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
841
842 async_tx_ack(dma->desc_rx);
843 async_tx_ack(dma->desc_tx);
844 kfree(dma->sg_tx_p);
845 kfree(dma->sg_rx_p);
846
847 spin_lock_irqsave(&data->lock, flags);
848
849 /* clear fifo threshold, disable interrupts, disable SPI transfer */
850 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
851 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
852 SPCR_SPE_BIT);
853 /* clear all interrupts */
854 pch_spi_writereg(data->master, PCH_SPSR,
855 pch_spi_readreg(data->master, PCH_SPSR));
856 /* clear FIFO */
857 pch_spi_clear_fifo(data->master);
858
859 spin_unlock_irqrestore(&data->lock, flags);
860 }
861
862 static void pch_dma_rx_complete(void *arg)
863 {
864 struct pch_spi_data *data = arg;
865
866 /* transfer is completed;inform pch_spi_process_messages_dma */
867 data->transfer_complete = true;
868 wake_up_interruptible(&data->wait);
869 }
870
871 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
872 {
873 struct pch_dma_slave *param = slave;
874
875 if ((chan->chan_id == param->chan_id) &&
876 (param->dma_dev == chan->device->dev)) {
877 chan->private = param;
878 return true;
879 } else {
880 return false;
881 }
882 }
883
884 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
885 {
886 dma_cap_mask_t mask;
887 struct dma_chan *chan;
888 struct pci_dev *dma_dev;
889 struct pch_dma_slave *param;
890 struct pch_spi_dma_ctrl *dma;
891 unsigned int width;
892
893 if (bpw == 8)
894 width = PCH_DMA_WIDTH_1_BYTE;
895 else
896 width = PCH_DMA_WIDTH_2_BYTES;
897
898 dma = &data->dma;
899 dma_cap_zero(mask);
900 dma_cap_set(DMA_SLAVE, mask);
901
902 /* Get DMA's dev information */
903 dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0));
904
905 /* Set Tx DMA */
906 param = &dma->param_tx;
907 param->dma_dev = &dma_dev->dev;
908 param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */
909 param->tx_reg = data->io_base_addr + PCH_SPDWR;
910 param->width = width;
911 chan = dma_request_channel(mask, pch_spi_filter, param);
912 if (!chan) {
913 dev_err(&data->master->dev,
914 "ERROR: dma_request_channel FAILS(Tx)\n");
915 data->use_dma = 0;
916 return;
917 }
918 dma->chan_tx = chan;
919
920 /* Set Rx DMA */
921 param = &dma->param_rx;
922 param->dma_dev = &dma_dev->dev;
923 param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */
924 param->rx_reg = data->io_base_addr + PCH_SPDRR;
925 param->width = width;
926 chan = dma_request_channel(mask, pch_spi_filter, param);
927 if (!chan) {
928 dev_err(&data->master->dev,
929 "ERROR: dma_request_channel FAILS(Rx)\n");
930 dma_release_channel(dma->chan_tx);
931 dma->chan_tx = NULL;
932 data->use_dma = 0;
933 return;
934 }
935 dma->chan_rx = chan;
936 }
937
938 static void pch_spi_release_dma(struct pch_spi_data *data)
939 {
940 struct pch_spi_dma_ctrl *dma;
941
942 dma = &data->dma;
943 if (dma->chan_tx) {
944 dma_release_channel(dma->chan_tx);
945 dma->chan_tx = NULL;
946 }
947 if (dma->chan_rx) {
948 dma_release_channel(dma->chan_rx);
949 dma->chan_rx = NULL;
950 }
951 return;
952 }
953
954 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
955 {
956 const u8 *tx_buf;
957 const u16 *tx_sbuf;
958 u8 *tx_dma_buf;
959 u16 *tx_dma_sbuf;
960 struct scatterlist *sg;
961 struct dma_async_tx_descriptor *desc_tx;
962 struct dma_async_tx_descriptor *desc_rx;
963 int num;
964 int i;
965 int size;
966 int rem;
967 unsigned long flags;
968 struct pch_spi_dma_ctrl *dma;
969
970 dma = &data->dma;
971
972 /* set baud rate if needed */
973 if (data->cur_trans->speed_hz) {
974 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
975 spin_lock_irqsave(&data->lock, flags);
976 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
977 spin_unlock_irqrestore(&data->lock, flags);
978 }
979
980 /* set bits per word if needed */
981 if (data->cur_trans->bits_per_word &&
982 (data->current_msg->spi->bits_per_word !=
983 data->cur_trans->bits_per_word)) {
984 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
985 spin_lock_irqsave(&data->lock, flags);
986 pch_spi_set_bits_per_word(data->master,
987 data->cur_trans->bits_per_word);
988 spin_unlock_irqrestore(&data->lock, flags);
989 *bpw = data->cur_trans->bits_per_word;
990 } else {
991 *bpw = data->current_msg->spi->bits_per_word;
992 }
993 data->bpw_len = data->cur_trans->len / (*bpw / 8);
994
995 /* copy Tx Data */
996 if (data->cur_trans->tx_buf != NULL) {
997 if (*bpw == 8) {
998 tx_buf = data->cur_trans->tx_buf;
999 tx_dma_buf = dma->tx_buf_virt;
1000 for (i = 0; i < data->bpw_len; i++)
1001 *tx_dma_buf++ = *tx_buf++;
1002 } else {
1003 tx_sbuf = data->cur_trans->tx_buf;
1004 tx_dma_sbuf = dma->tx_buf_virt;
1005 for (i = 0; i < data->bpw_len; i++)
1006 *tx_dma_sbuf++ = *tx_sbuf++;
1007 }
1008 }
1009 if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
1010 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1011 size = PCH_DMA_TRANS_SIZE;
1012 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
1013 } else {
1014 num = 1;
1015 size = data->bpw_len;
1016 rem = data->bpw_len;
1017 }
1018 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1019 __func__, num, size, rem);
1020 spin_lock_irqsave(&data->lock, flags);
1021
1022 /* set receive fifo threshold and transmit fifo threshold */
1023 pch_spi_setclr_reg(data->master, PCH_SPCR,
1024 ((size - 1) << SPCR_RFIC_FIELD) |
1025 ((PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE) <<
1026 SPCR_TFIC_FIELD),
1027 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1028
1029 spin_unlock_irqrestore(&data->lock, flags);
1030
1031 /* RX */
1032 dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1033 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1034 /* offset, length setting */
1035 sg = dma->sg_rx_p;
1036 for (i = 0; i < num; i++, sg++) {
1037 if (i == 0) {
1038 sg->offset = 0;
1039 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1040 sg->offset);
1041 sg_dma_len(sg) = rem;
1042 } else {
1043 sg->offset = rem + size * (i - 1);
1044 sg->offset = sg->offset * (*bpw / 8);
1045 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1046 sg->offset);
1047 sg_dma_len(sg) = size;
1048 }
1049 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1050 }
1051 sg = dma->sg_rx_p;
1052 desc_rx = dma->chan_rx->device->device_prep_slave_sg(dma->chan_rx, sg,
1053 num, DMA_FROM_DEVICE,
1054 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1055 if (!desc_rx) {
1056 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1057 __func__);
1058 return;
1059 }
1060 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1061 desc_rx->callback = pch_dma_rx_complete;
1062 desc_rx->callback_param = data;
1063 dma->nent = num;
1064 dma->desc_rx = desc_rx;
1065
1066 /* TX */
1067 dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1068 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1069 /* offset, length setting */
1070 sg = dma->sg_tx_p;
1071 for (i = 0; i < num; i++, sg++) {
1072 if (i == 0) {
1073 sg->offset = 0;
1074 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1075 sg->offset);
1076 sg_dma_len(sg) = rem;
1077 } else {
1078 sg->offset = rem + size * (i - 1);
1079 sg->offset = sg->offset * (*bpw / 8);
1080 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1081 sg->offset);
1082 sg_dma_len(sg) = size;
1083 }
1084 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1085 }
1086 sg = dma->sg_tx_p;
1087 desc_tx = dma->chan_tx->device->device_prep_slave_sg(dma->chan_tx,
1088 sg, num, DMA_TO_DEVICE,
1089 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1090 if (!desc_tx) {
1091 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1092 __func__);
1093 return;
1094 }
1095 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1096 desc_tx->callback = NULL;
1097 desc_tx->callback_param = data;
1098 dma->nent = num;
1099 dma->desc_tx = desc_tx;
1100
1101 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
1102 "0x2 to SSNXCR\n", __func__);
1103
1104 spin_lock_irqsave(&data->lock, flags);
1105 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1106 desc_rx->tx_submit(desc_rx);
1107 desc_tx->tx_submit(desc_tx);
1108 spin_unlock_irqrestore(&data->lock, flags);
1109
1110 /* reset transfer complete flag */
1111 data->transfer_complete = false;
1112 }
1113
1114 static void pch_spi_process_messages(struct work_struct *pwork)
1115 {
1116 struct spi_message *pmsg;
1117 struct pch_spi_data *data;
1118 int bpw;
1119
1120 data = container_of(pwork, struct pch_spi_data, work);
1121 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1122
1123 spin_lock(&data->lock);
1124 /* check if suspend has been initiated;if yes flush queue */
1125 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1126 dev_dbg(&data->master->dev, "%s suspend/remove initiated,"
1127 "flushing queue\n", __func__);
1128 list_for_each_entry(pmsg, data->queue.next, queue) {
1129 pmsg->status = -EIO;
1130
1131 if (pmsg->complete != 0) {
1132 spin_unlock(&data->lock);
1133 pmsg->complete(pmsg->context);
1134 spin_lock(&data->lock);
1135 }
1136
1137 /* delete from queue */
1138 list_del_init(&pmsg->queue);
1139 }
1140
1141 spin_unlock(&data->lock);
1142 return;
1143 }
1144
1145 data->bcurrent_msg_processing = true;
1146 dev_dbg(&data->master->dev,
1147 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1148
1149 /* Get the message from the queue and delete it from there. */
1150 data->current_msg = list_entry(data->queue.next, struct spi_message,
1151 queue);
1152
1153 list_del_init(&data->current_msg->queue);
1154
1155 data->current_msg->status = 0;
1156
1157 pch_spi_select_chip(data, data->current_msg->spi);
1158
1159 spin_unlock(&data->lock);
1160
1161 if (data->use_dma)
1162 pch_spi_request_dma(data,
1163 data->current_msg->spi->bits_per_word);
1164 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1165 do {
1166 /* If we are already processing a message get the next
1167 transfer structure from the message otherwise retrieve
1168 the 1st transfer request from the message. */
1169 spin_lock(&data->lock);
1170 if (data->cur_trans == NULL) {
1171 data->cur_trans =
1172 list_entry(data->current_msg->transfers.next,
1173 struct spi_transfer, transfer_list);
1174 dev_dbg(&data->master->dev, "%s "
1175 ":Getting 1st transfer message\n", __func__);
1176 } else {
1177 data->cur_trans =
1178 list_entry(data->cur_trans->transfer_list.next,
1179 struct spi_transfer, transfer_list);
1180 dev_dbg(&data->master->dev, "%s "
1181 ":Getting next transfer message\n", __func__);
1182 }
1183 spin_unlock(&data->lock);
1184
1185 if (data->use_dma) {
1186 pch_spi_handle_dma(data, &bpw);
1187 pch_spi_start_transfer(data);
1188 pch_spi_copy_rx_data_for_dma(data, bpw);
1189 } else {
1190 pch_spi_set_tx(data, &bpw);
1191 pch_spi_set_ir(data);
1192 pch_spi_copy_rx_data(data, bpw);
1193 kfree(data->pkt_rx_buff);
1194 data->pkt_rx_buff = NULL;
1195 kfree(data->pkt_tx_buff);
1196 data->pkt_tx_buff = NULL;
1197 }
1198 /* increment message count */
1199 data->current_msg->actual_length += data->cur_trans->len;
1200
1201 dev_dbg(&data->master->dev,
1202 "%s:data->current_msg->actual_length=%d\n",
1203 __func__, data->current_msg->actual_length);
1204
1205 /* check for delay */
1206 if (data->cur_trans->delay_usecs) {
1207 dev_dbg(&data->master->dev, "%s:"
1208 "delay in usec=%d\n", __func__,
1209 data->cur_trans->delay_usecs);
1210 udelay(data->cur_trans->delay_usecs);
1211 }
1212
1213 spin_lock(&data->lock);
1214
1215 /* No more transfer in this message. */
1216 if ((data->cur_trans->transfer_list.next) ==
1217 &(data->current_msg->transfers)) {
1218 pch_spi_nomore_transfer(data);
1219 }
1220
1221 spin_unlock(&data->lock);
1222
1223 } while (data->cur_trans != NULL);
1224
1225 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1226 if (data->use_dma)
1227 pch_spi_release_dma(data);
1228 }
1229
1230 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1231 struct pch_spi_data *data)
1232 {
1233 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1234
1235 /* free workqueue */
1236 if (data->wk != NULL) {
1237 destroy_workqueue(data->wk);
1238 data->wk = NULL;
1239 dev_dbg(&board_dat->pdev->dev,
1240 "%s destroy_workqueue invoked successfully\n",
1241 __func__);
1242 }
1243 }
1244
1245 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1246 struct pch_spi_data *data)
1247 {
1248 int retval = 0;
1249
1250 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1251
1252 /* create workqueue */
1253 data->wk = create_singlethread_workqueue(KBUILD_MODNAME);
1254 if (!data->wk) {
1255 dev_err(&board_dat->pdev->dev,
1256 "%s create_singlet hread_workqueue failed\n", __func__);
1257 retval = -EBUSY;
1258 goto err_return;
1259 }
1260
1261 /* reset PCH SPI h/w */
1262 pch_spi_reset(data->master);
1263 dev_dbg(&board_dat->pdev->dev,
1264 "%s pch_spi_reset invoked successfully\n", __func__);
1265
1266 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1267
1268 err_return:
1269 if (retval != 0) {
1270 dev_err(&board_dat->pdev->dev,
1271 "%s FAIL:invoking pch_spi_free_resources\n", __func__);
1272 pch_spi_free_resources(board_dat, data);
1273 }
1274
1275 dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1276
1277 return retval;
1278 }
1279
1280 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1281 struct pch_spi_data *data)
1282 {
1283 struct pch_spi_dma_ctrl *dma;
1284
1285 dma = &data->dma;
1286 if (dma->tx_buf_dma)
1287 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1288 dma->tx_buf_virt, dma->tx_buf_dma);
1289 if (dma->rx_buf_dma)
1290 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1291 dma->rx_buf_virt, dma->rx_buf_dma);
1292 return;
1293 }
1294
1295 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1296 struct pch_spi_data *data)
1297 {
1298 struct pch_spi_dma_ctrl *dma;
1299
1300 dma = &data->dma;
1301 /* Get Consistent memory for Tx DMA */
1302 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1303 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1304 /* Get Consistent memory for Rx DMA */
1305 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1306 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1307 }
1308
1309 static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
1310 {
1311 int ret;
1312 struct spi_master *master;
1313 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1314 struct pch_spi_data *data;
1315
1316 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1317
1318 master = spi_alloc_master(&board_dat->pdev->dev,
1319 sizeof(struct pch_spi_data));
1320 if (!master) {
1321 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1322 plat_dev->id);
1323 return -ENOMEM;
1324 }
1325
1326 data = spi_master_get_devdata(master);
1327 data->master = master;
1328
1329 platform_set_drvdata(plat_dev, data);
1330
1331 /* baseaddress + address offset) */
1332 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1333 PCH_ADDRESS_SIZE * plat_dev->id;
1334 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0) +
1335 PCH_ADDRESS_SIZE * plat_dev->id;
1336 if (!data->io_remap_addr) {
1337 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1338 ret = -ENOMEM;
1339 goto err_pci_iomap;
1340 }
1341
1342 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1343 plat_dev->id, data->io_remap_addr);
1344
1345 /* initialize members of SPI master */
1346 master->bus_num = -1;
1347 master->num_chipselect = PCH_MAX_CS;
1348 master->setup = pch_spi_setup;
1349 master->transfer = pch_spi_transfer;
1350
1351 data->board_dat = board_dat;
1352 data->plat_dev = plat_dev;
1353 data->n_curnt_chip = 255;
1354 data->status = STATUS_RUNNING;
1355 data->ch = plat_dev->id;
1356 data->use_dma = use_dma;
1357
1358 INIT_LIST_HEAD(&data->queue);
1359 spin_lock_init(&data->lock);
1360 INIT_WORK(&data->work, pch_spi_process_messages);
1361 init_waitqueue_head(&data->wait);
1362
1363 ret = pch_spi_get_resources(board_dat, data);
1364 if (ret) {
1365 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1366 goto err_spi_get_resources;
1367 }
1368
1369 ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1370 IRQF_SHARED, KBUILD_MODNAME, data);
1371 if (ret) {
1372 dev_err(&plat_dev->dev,
1373 "%s request_irq failed\n", __func__);
1374 goto err_request_irq;
1375 }
1376 data->irq_reg_sts = true;
1377
1378 pch_spi_set_master_mode(master);
1379
1380 ret = spi_register_master(master);
1381 if (ret != 0) {
1382 dev_err(&plat_dev->dev,
1383 "%s spi_register_master FAILED\n", __func__);
1384 goto err_spi_register_master;
1385 }
1386
1387 if (use_dma) {
1388 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1389 pch_alloc_dma_buf(board_dat, data);
1390 }
1391
1392 return 0;
1393
1394 err_spi_register_master:
1395 free_irq(board_dat->pdev->irq, board_dat);
1396 err_request_irq:
1397 pch_spi_free_resources(board_dat, data);
1398 err_spi_get_resources:
1399 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1400 err_pci_iomap:
1401 spi_master_put(master);
1402
1403 return ret;
1404 }
1405
1406 static int __devexit pch_spi_pd_remove(struct platform_device *plat_dev)
1407 {
1408 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1409 struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1410 int count;
1411 unsigned long flags;
1412
1413 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1414 __func__, plat_dev->id, board_dat->pdev->irq);
1415
1416 if (use_dma)
1417 pch_free_dma_buf(board_dat, data);
1418
1419 /* check for any pending messages; no action is taken if the queue
1420 * is still full; but at least we tried. Unload anyway */
1421 count = 500;
1422 spin_lock_irqsave(&data->lock, flags);
1423 data->status = STATUS_EXITING;
1424 while ((list_empty(&data->queue) == 0) && --count) {
1425 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1426 __func__);
1427 spin_unlock_irqrestore(&data->lock, flags);
1428 msleep(PCH_SLEEP_TIME);
1429 spin_lock_irqsave(&data->lock, flags);
1430 }
1431 spin_unlock_irqrestore(&data->lock, flags);
1432
1433 pch_spi_free_resources(board_dat, data);
1434 /* disable interrupts & free IRQ */
1435 if (data->irq_reg_sts) {
1436 /* disable interrupts */
1437 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1438 data->irq_reg_sts = false;
1439 free_irq(board_dat->pdev->irq, data);
1440 }
1441
1442 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1443 spi_unregister_master(data->master);
1444 spi_master_put(data->master);
1445 platform_set_drvdata(plat_dev, NULL);
1446
1447 return 0;
1448 }
1449 #ifdef CONFIG_PM
1450 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1451 pm_message_t state)
1452 {
1453 u8 count;
1454 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1455 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1456
1457 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1458
1459 if (!board_dat) {
1460 dev_err(&pd_dev->dev,
1461 "%s pci_get_drvdata returned NULL\n", __func__);
1462 return -EFAULT;
1463 }
1464
1465 /* check if the current message is processed:
1466 Only after thats done the transfer will be suspended */
1467 count = 255;
1468 while ((--count) > 0) {
1469 if (!(data->bcurrent_msg_processing))
1470 break;
1471 msleep(PCH_SLEEP_TIME);
1472 }
1473
1474 /* Free IRQ */
1475 if (data->irq_reg_sts) {
1476 /* disable all interrupts */
1477 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1478 pch_spi_reset(data->master);
1479 free_irq(board_dat->pdev->irq, data);
1480
1481 data->irq_reg_sts = false;
1482 dev_dbg(&pd_dev->dev,
1483 "%s free_irq invoked successfully.\n", __func__);
1484 }
1485
1486 return 0;
1487 }
1488
1489 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1490 {
1491 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1492 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1493 int retval;
1494
1495 if (!board_dat) {
1496 dev_err(&pd_dev->dev,
1497 "%s pci_get_drvdata returned NULL\n", __func__);
1498 return -EFAULT;
1499 }
1500
1501 if (!data->irq_reg_sts) {
1502 /* register IRQ */
1503 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1504 IRQF_SHARED, KBUILD_MODNAME, data);
1505 if (retval < 0) {
1506 dev_err(&pd_dev->dev,
1507 "%s request_irq failed\n", __func__);
1508 return retval;
1509 }
1510
1511 /* reset PCH SPI h/w */
1512 pch_spi_reset(data->master);
1513 pch_spi_set_master_mode(data->master);
1514 data->irq_reg_sts = true;
1515 }
1516 return 0;
1517 }
1518 #else
1519 #define pch_spi_pd_suspend NULL
1520 #define pch_spi_pd_resume NULL
1521 #endif
1522
1523 static struct platform_driver pch_spi_pd_driver = {
1524 .driver = {
1525 .name = "pch-spi",
1526 .owner = THIS_MODULE,
1527 },
1528 .probe = pch_spi_pd_probe,
1529 .remove = __devexit_p(pch_spi_pd_remove),
1530 .suspend = pch_spi_pd_suspend,
1531 .resume = pch_spi_pd_resume
1532 };
1533
1534 static int __devinit pch_spi_probe(struct pci_dev *pdev,
1535 const struct pci_device_id *id)
1536 {
1537 struct pch_spi_board_data *board_dat;
1538 struct platform_device *pd_dev = NULL;
1539 int retval;
1540 int i;
1541 struct pch_pd_dev_save *pd_dev_save;
1542
1543 pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL);
1544 if (!pd_dev_save) {
1545 dev_err(&pdev->dev, "%s Can't allocate pd_dev_sav\n", __func__);
1546 return -ENOMEM;
1547 }
1548
1549 board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1550 if (!board_dat) {
1551 dev_err(&pdev->dev, "%s Can't allocate board_dat\n", __func__);
1552 retval = -ENOMEM;
1553 goto err_no_mem;
1554 }
1555
1556 retval = pci_request_regions(pdev, KBUILD_MODNAME);
1557 if (retval) {
1558 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1559 goto pci_request_regions;
1560 }
1561
1562 board_dat->pdev = pdev;
1563 board_dat->num = id->driver_data;
1564 pd_dev_save->num = id->driver_data;
1565 pd_dev_save->board_dat = board_dat;
1566
1567 retval = pci_enable_device(pdev);
1568 if (retval) {
1569 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1570 goto pci_enable_device;
1571 }
1572
1573 for (i = 0; i < board_dat->num; i++) {
1574 pd_dev = platform_device_alloc("pch-spi", i);
1575 if (!pd_dev) {
1576 dev_err(&pdev->dev, "platform_device_alloc failed\n");
1577 goto err_platform_device;
1578 }
1579 pd_dev_save->pd_save[i] = pd_dev;
1580 pd_dev->dev.parent = &pdev->dev;
1581
1582 retval = platform_device_add_data(pd_dev, board_dat,
1583 sizeof(*board_dat));
1584 if (retval) {
1585 dev_err(&pdev->dev,
1586 "platform_device_add_data failed\n");
1587 platform_device_put(pd_dev);
1588 goto err_platform_device;
1589 }
1590
1591 retval = platform_device_add(pd_dev);
1592 if (retval) {
1593 dev_err(&pdev->dev, "platform_device_add failed\n");
1594 platform_device_put(pd_dev);
1595 goto err_platform_device;
1596 }
1597 }
1598
1599 pci_set_drvdata(pdev, pd_dev_save);
1600
1601 return 0;
1602
1603 err_platform_device:
1604 pci_disable_device(pdev);
1605 pci_enable_device:
1606 pci_release_regions(pdev);
1607 pci_request_regions:
1608 kfree(board_dat);
1609 err_no_mem:
1610 kfree(pd_dev_save);
1611
1612 return retval;
1613 }
1614
1615 static void __devexit pch_spi_remove(struct pci_dev *pdev)
1616 {
1617 int i;
1618 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1619
1620 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1621
1622 for (i = 0; i < pd_dev_save->num; i++)
1623 platform_device_unregister(pd_dev_save->pd_save[i]);
1624
1625 pci_disable_device(pdev);
1626 pci_release_regions(pdev);
1627 kfree(pd_dev_save->board_dat);
1628 kfree(pd_dev_save);
1629 }
1630
1631 #ifdef CONFIG_PM
1632 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1633 {
1634 int retval;
1635 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1636
1637 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1638
1639 pd_dev_save->board_dat->suspend_sts = true;
1640
1641 /* save config space */
1642 retval = pci_save_state(pdev);
1643 if (retval == 0) {
1644 pci_enable_wake(pdev, PCI_D3hot, 0);
1645 pci_disable_device(pdev);
1646 pci_set_power_state(pdev, PCI_D3hot);
1647 } else {
1648 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1649 }
1650
1651 return retval;
1652 }
1653
1654 static int pch_spi_resume(struct pci_dev *pdev)
1655 {
1656 int retval;
1657 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1658 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1659
1660 pci_set_power_state(pdev, PCI_D0);
1661 pci_restore_state(pdev);
1662
1663 retval = pci_enable_device(pdev);
1664 if (retval < 0) {
1665 dev_err(&pdev->dev,
1666 "%s pci_enable_device failed\n", __func__);
1667 } else {
1668 pci_enable_wake(pdev, PCI_D3hot, 0);
1669
1670 /* set suspend status to false */
1671 pd_dev_save->board_dat->suspend_sts = false;
1672 }
1673
1674 return retval;
1675 }
1676 #else
1677 #define pch_spi_suspend NULL
1678 #define pch_spi_resume NULL
1679
1680 #endif
1681
1682 static struct pci_driver pch_spi_pcidev = {
1683 .name = "pch_spi",
1684 .id_table = pch_spi_pcidev_id,
1685 .probe = pch_spi_probe,
1686 .remove = pch_spi_remove,
1687 .suspend = pch_spi_suspend,
1688 .resume = pch_spi_resume,
1689 };
1690
1691 static int __init pch_spi_init(void)
1692 {
1693 int ret;
1694 ret = platform_driver_register(&pch_spi_pd_driver);
1695 if (ret)
1696 return ret;
1697
1698 ret = pci_register_driver(&pch_spi_pcidev);
1699 if (ret)
1700 return ret;
1701
1702 return 0;
1703 }
1704 module_init(pch_spi_init);
1705
1706 static void __exit pch_spi_exit(void)
1707 {
1708 pci_unregister_driver(&pch_spi_pcidev);
1709 platform_driver_unregister(&pch_spi_pd_driver);
1710 }
1711 module_exit(pch_spi_exit);
1712
1713 module_param(use_dma, int, 0644);
1714 MODULE_PARM_DESC(use_dma,
1715 "to use DMA for data transfers pass 1 else 0; default 1");
1716
1717 MODULE_LICENSE("GPL");
1718 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7xxx IOH SPI Driver");
Linux kernel - Deliverables
This page took 0.078101 seconds and 4 git commands to generate.