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staging: brcm80211: fixed double #include problem
[deliverable/linux.git] / drivers / staging / brcm80211 / brcmfmac / dhd_sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/printk.h>
20 #include <linux/pci_ids.h>
21 #include <linux/netdevice.h>
22 #include <linux/sched.h>
23 #include <linux/mmc/sdio.h>
24 #include <asm/unaligned.h>
25 #include <defs.h>
26 #include <brcmu_wifi.h>
27 #include <brcmu_utils.h>
28 #include <brcm_hw_ids.h>
29 #include <soc.h>
30 #include "sdio_host.h"
31
32 /* register access macros */
33 #ifndef __BIG_ENDIAN
34 #ifndef __mips__
35 #define R_REG(r) \
36 bcmsdh_reg_read(NULL, (unsigned long)(r), sizeof(*(r)))
37 #else /* __mips__ */
38 #define R_REG(r) \
39 ({ \
40 __typeof(*(r)) __osl_v; \
41 __asm__ __volatile__("sync"); \
42 __osl_v = bcmsdh_reg_read(NULL, (unsigned long)(r),\
43 sizeof(*(r))); \
44 __asm__ __volatile__("sync"); \
45 __osl_v; \
46 })
47 #endif /* __mips__ */
48
49 #define W_REG(r, v) do { \
50 bcmsdh_reg_write(NULL, (unsigned long)(r), sizeof(*(r)), (v)); \
51 } while (0)
52 #else /* __BIG_ENDIAN */
53 #define R_REG(r) \
54 bcmsdh_reg_read(NULL, (unsigned long)(r), sizeof(*(r)))
55 #define W_REG(r, v) do { \
56 bcmsdh_reg_write(NULL, (unsigned long)(r), sizeof(*(r)), (v)); \
57 } while (0)
58 #endif /* __BIG_ENDIAN */
59
60 #define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
61 #define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
62
63 #define SET_REG(r, mask, val) \
64 W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
65
66 #ifdef DHD_DEBUG
67
68 /* ARM trap handling */
69
70 /* Trap types defined by ARM (see arminc.h) */
71
72 /* Trap locations in lo memory */
73 #define TRAP_STRIDE 4
74 #define FIRST_TRAP TR_RST
75 #define LAST_TRAP (TR_FIQ * TRAP_STRIDE)
76
77 #if defined(__ARM_ARCH_4T__)
78 #define MAX_TRAP_TYPE (TR_FIQ + 1)
79 #elif defined(__ARM_ARCH_7M__)
80 #define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS)
81 #endif /* __ARM_ARCH_7M__ */
82
83 /* The trap structure is defined here as offsets for assembly */
84 #define TR_TYPE 0x00
85 #define TR_EPC 0x04
86 #define TR_CPSR 0x08
87 #define TR_SPSR 0x0c
88 #define TR_REGS 0x10
89 #define TR_REG(n) (TR_REGS + (n) * 4)
90 #define TR_SP TR_REG(13)
91 #define TR_LR TR_REG(14)
92 #define TR_PC TR_REG(15)
93
94 #define TRAP_T_SIZE 80
95
96 typedef struct _trap_struct {
97 u32 type;
98 u32 epc;
99 u32 cpsr;
100 u32 spsr;
101 u32 r0;
102 u32 r1;
103 u32 r2;
104 u32 r3;
105 u32 r4;
106 u32 r5;
107 u32 r6;
108 u32 r7;
109 u32 r8;
110 u32 r9;
111 u32 r10;
112 u32 r11;
113 u32 r12;
114 u32 r13;
115 u32 r14;
116 u32 pc;
117 } trap_t;
118
119 #define CBUF_LEN (128)
120
121 #define LOG_BUF_LEN 1024
122
123 typedef struct {
124 u32 buf; /* Can't be pointer on (64-bit) hosts */
125 uint buf_size;
126 uint idx;
127 char *_buf_compat; /* Redundant pointer for backward compat. */
128 } rte_log_t;
129
130 typedef struct {
131 /* Virtual UART
132 * When there is no UART (e.g. Quickturn),
133 * the host should write a complete
134 * input line directly into cbuf and then write
135 * the length into vcons_in.
136 * This may also be used when there is a real UART
137 * (at risk of conflicting with
138 * the real UART). vcons_out is currently unused.
139 */
140 volatile uint vcons_in;
141 volatile uint vcons_out;
142
143 /* Output (logging) buffer
144 * Console output is written to a ring buffer log_buf at index log_idx.
145 * The host may read the output when it sees log_idx advance.
146 * Output will be lost if the output wraps around faster than the host
147 * polls.
148 */
149 rte_log_t log;
150
151 /* Console input line buffer
152 * Characters are read one at a time into cbuf
153 * until <CR> is received, then
154 * the buffer is processed as a command line.
155 * Also used for virtual UART.
156 */
157 uint cbuf_idx;
158 char cbuf[CBUF_LEN];
159 } rte_cons_t;
160
161 #endif /* DHD_DEBUG */
162 #include <chipcommon.h>
163
164 #include "sbsdio.h"
165
166 #include "dngl_stats.h"
167 #include "dhd.h"
168 #include "dhd_bus.h"
169 #include "dhd_proto.h"
170 #include "dhd_dbg.h"
171 #include <sdiovar.h>
172 #include <bcmchip.h>
173
174 #ifndef DHDSDIO_MEM_DUMP_FNAME
175 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
176 #endif
177
178 #define TXQLEN 2048 /* bulk tx queue length */
179 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
180 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
181 #define PRIOMASK 7
182
183 #define TXRETRIES 2 /* # of retries for tx frames */
184
185 #if defined(CONFIG_MACH_SANDGATE2G)
186 #define DHD_RXBOUND 250 /* Default for max rx frames in
187 one scheduling */
188 #else
189 #define DHD_RXBOUND 50 /* Default for max rx frames in
190 one scheduling */
191 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
192
193 #define DHD_TXBOUND 20 /* Default for max tx frames in
194 one scheduling */
195
196 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
197
198 #define MEMBLOCK 2048 /* Block size used for downloading
199 of dongle image */
200 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
201 biggest possible glom */
202
203 /* Packet alignment for most efficient SDIO (can change based on platform) */
204 #ifndef DHD_SDALIGN
205 #define DHD_SDALIGN 32
206 #endif
207 #if !ISPOWEROF2(DHD_SDALIGN)
208 #error DHD_SDALIGN is not a power of 2!
209 #endif
210
211 #ifndef DHD_FIRSTREAD
212 #define DHD_FIRSTREAD 32
213 #endif
214 #if !ISPOWEROF2(DHD_FIRSTREAD)
215 #error DHD_FIRSTREAD is not a power of 2!
216 #endif
217
218 /* Total length of frame header for dongle protocol */
219 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
220 #ifdef SDTEST
221 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
222 #else
223 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
224 #endif
225
226 /*
227 * Software allocation of To SB Mailbox resources
228 */
229
230 /* tosbmailbox bits corresponding to intstatus bits */
231 #define SMB_NAK (1 << 0) /* Frame NAK */
232 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
233 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
234 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
235
236 /* tosbmailboxdata */
237 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
238
239 /*
240 * Software allocation of To Host Mailbox resources
241 */
242
243 /* intstatus bits */
244 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
245 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
246 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
247 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
248
249 /* tohostmailboxdata */
250 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
251 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
252 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
253 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
254
255 #define HMB_DATA_FCDATA_MASK 0xff000000
256 #define HMB_DATA_FCDATA_SHIFT 24
257
258 #define HMB_DATA_VERSION_MASK 0x00ff0000
259 #define HMB_DATA_VERSION_SHIFT 16
260
261 /*
262 * Software-defined protocol header
263 */
264
265 /* Current protocol version */
266 #define SDPCM_PROT_VERSION 4
267
268 /* SW frame header */
269 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
270
271 #define SDPCM_CHANNEL_MASK 0x00000f00
272 #define SDPCM_CHANNEL_SHIFT 8
273 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
274
275 #define SDPCM_NEXTLEN_OFFSET 2
276
277 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
278 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
279 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
280 #define SDPCM_DOFFSET_MASK 0xff000000
281 #define SDPCM_DOFFSET_SHIFT 24
282 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
283 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
284 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
285 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
286
287 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
288
289 /* logical channel numbers */
290 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
291 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
292 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
293 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
294 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
295
296 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
297
298 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
299
300 /* For TEST_CHANNEL packets, define another 4-byte header */
301 #define SDPCM_TEST_HDRLEN 4 /*
302 * Generally: Cmd(1), Ext(1), Len(2);
303 * Semantics of Ext byte depend on
304 * command. Len is current or requested
305 * frame length, not including test
306 * header; sent little-endian.
307 */
308 #define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext:pattern id. */
309 #define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext:pattern id. */
310 #define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext:pattern id. */
311 #define SDPCM_TEST_BURST 0x04 /*
312 * Receiver to send a burst.
313 * Ext is a frame count
314 */
315 #define SDPCM_TEST_SEND 0x05 /*
316 * Receiver sets send mode.
317 * Ext is boolean on/off
318 */
319
320 /* Handy macro for filling in datagen packets with a pattern */
321 #define SDPCM_TEST_FILL(byteno, id) ((u8)(id + byteno))
322
323 /*
324 * Shared structure between dongle and the host.
325 * The structure contains pointers to trap or assert information.
326 */
327 #define SDPCM_SHARED_VERSION 0x0002
328 #define SDPCM_SHARED_VERSION_MASK 0x00FF
329 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
330 #define SDPCM_SHARED_ASSERT 0x0200
331 #define SDPCM_SHARED_TRAP 0x0400
332
333
334 /* Space for header read, limit for data packets */
335 #ifndef MAX_HDR_READ
336 #define MAX_HDR_READ 32
337 #endif
338 #if !ISPOWEROF2(MAX_HDR_READ)
339 #error MAX_HDR_READ is not a power of 2!
340 #endif
341
342 #define MAX_RX_DATASZ 2048
343
344 /* Maximum milliseconds to wait for F2 to come up */
345 #define DHD_WAIT_F2RDY 3000
346
347 /* Bump up limit on waiting for HT to account for first startup;
348 * if the image is doing a CRC calculation before programming the PMU
349 * for HT availability, it could take a couple hundred ms more, so
350 * max out at a 1 second (1000000us).
351 */
352 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
353 #undef PMU_MAX_TRANSITION_DLY
354 #define PMU_MAX_TRANSITION_DLY 1000000
355 #endif
356
357 /* Value for ChipClockCSR during initial setup */
358 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
359 SBSDIO_ALP_AVAIL_REQ)
360 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
361
362 /* Flags for SDH calls */
363 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
364
365 /* sbimstate */
366 #define SBIM_IBE 0x20000 /* inbanderror */
367 #define SBIM_TO 0x40000 /* timeout */
368 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
369 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
370
371 /* sbtmstatelow */
372 #define SBTML_RESET 0x0001 /* reset */
373 #define SBTML_REJ_MASK 0x0006 /* reject field */
374 #define SBTML_REJ 0x0002 /* reject */
375 #define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */
376
377 #define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */
378
379 /* sbtmstatehigh */
380 #define SBTMH_SERR 0x0001 /* serror */
381 #define SBTMH_INT 0x0002 /* interrupt */
382 #define SBTMH_BUSY 0x0004 /* busy */
383 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
384
385 #define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */
386
387 /* sbidlow */
388 #define SBIDL_INIT 0x80 /* initiator */
389
390 /* sbidhigh */
391 #define SBIDH_RC_MASK 0x000f /* revision code */
392 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
393 #define SBIDH_RCE_SHIFT 8
394 #define SBCOREREV(sbidh) \
395 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
396 #define SBIDH_CC_MASK 0x8ff0 /* core code */
397 #define SBIDH_CC_SHIFT 4
398 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
399 #define SBIDH_VC_SHIFT 16
400
401 /*
402 * Conversion of 802.1D priority to precedence level
403 */
404 #define PRIO2PREC(prio) \
405 (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
406 ((prio^2)) : (prio))
407
408 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
409 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
410 uint len);
411
412 /* Core reg address translation */
413 #define CORE_CC_REG(base, field) (base + offsetof(chipcregs_t, field))
414 #define CORE_BUS_REG(base, field) \
415 (base + offsetof(struct sdpcmd_regs, field))
416 #define CORE_SB(base, field) \
417 (base + SBCONFIGOFF + offsetof(sbconfig_t, field))
418
419 #ifdef DHD_DEBUG
420 /* Device console log buffer state */
421 typedef struct dhd_console {
422 uint count; /* Poll interval msec counter */
423 uint log_addr; /* Log struct address (fixed) */
424 rte_log_t log; /* Log struct (host copy) */
425 uint bufsize; /* Size of log buffer */
426 u8 *buf; /* Log buffer (host copy) */
427 uint last; /* Last buffer read index */
428 } dhd_console_t;
429 #endif /* DHD_DEBUG */
430
431 struct sdpcm_shared {
432 u32 flags;
433 u32 trap_addr;
434 u32 assert_exp_addr;
435 u32 assert_file_addr;
436 u32 assert_line;
437 u32 console_addr; /* Address of rte_cons_t */
438 u32 msgtrace_addr;
439 u8 tag[32];
440 };
441
442
443 /* misc chip info needed by some of the routines */
444 struct chip_info {
445 u32 chip;
446 u32 chiprev;
447 u32 cccorebase;
448 u32 ccrev;
449 u32 cccaps;
450 u32 buscorebase;
451 u32 buscorerev;
452 u32 buscoretype;
453 u32 ramcorebase;
454 u32 armcorebase;
455 u32 pmurev;
456 u32 ramsize;
457 };
458
459 /* Private data for SDIO bus interaction */
460 typedef struct dhd_bus {
461 dhd_pub_t *dhd;
462
463 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
464 struct chip_info *ci; /* Chip info struct */
465 char *vars; /* Variables (from CIS and/or other) */
466 uint varsz; /* Size of variables buffer */
467 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
468
469 struct sdpcmd_regs *regs; /* SDIO core */
470 uint sdpcmrev; /* SDIO core revision */
471 uint armrev; /* CPU core revision */
472 uint ramrev; /* SOCRAM core revision */
473 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
474 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
475
476 u32 bus; /* gSPI or SDIO bus */
477 u32 hostintmask; /* Copy of Host Interrupt Mask */
478 u32 intstatus; /* Intstatus bits (events) pending */
479 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
480 bool fcstate; /* State of dongle flow-control */
481
482 u16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
483 char *fw_path; /* module_param: path to firmware image */
484 char *nv_path; /* module_param: path to nvram vars file */
485 const char *nvram_params; /* user specified nvram params. */
486
487 uint blocksize; /* Block size of SDIO transfers */
488 uint roundup; /* Max roundup limit */
489
490 struct pktq txq; /* Queue length used for flow-control */
491 u8 flowcontrol; /* per prio flow control bitmask */
492 u8 tx_seq; /* Transmit sequence number (next) */
493 u8 tx_max; /* Maximum transmit sequence allowed */
494
495 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
496 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
497 u16 nextlen; /* Next Read Len from last header */
498 u8 rx_seq; /* Receive sequence number (expected) */
499 bool rxskip; /* Skip receive (awaiting NAK ACK) */
500
501 struct sk_buff *glomd; /* Packet containing glomming descriptor */
502 struct sk_buff *glom; /* Packet chain for glommed superframe */
503 uint glomerr; /* Glom packet read errors */
504
505 u8 *rxbuf; /* Buffer for receiving control packets */
506 uint rxblen; /* Allocated length of rxbuf */
507 u8 *rxctl; /* Aligned pointer into rxbuf */
508 u8 *databuf; /* Buffer for receiving big glom packet */
509 u8 *dataptr; /* Aligned pointer into databuf */
510 uint rxlen; /* Length of valid data in buffer */
511
512 u8 sdpcm_ver; /* Bus protocol reported by dongle */
513
514 bool intr; /* Use interrupts */
515 bool poll; /* Use polling */
516 bool ipend; /* Device interrupt is pending */
517 bool intdis; /* Interrupts disabled by isr */
518 uint intrcount; /* Count of device interrupt callbacks */
519 uint lastintrs; /* Count as of last watchdog timer */
520 uint spurious; /* Count of spurious interrupts */
521 uint pollrate; /* Ticks between device polls */
522 uint polltick; /* Tick counter */
523 uint pollcnt; /* Count of active polls */
524
525 #ifdef DHD_DEBUG
526 dhd_console_t console; /* Console output polling support */
527 uint console_addr; /* Console address from shared struct */
528 #endif /* DHD_DEBUG */
529
530 uint regfails; /* Count of R_REG/W_REG failures */
531
532 uint clkstate; /* State of sd and backplane clock(s) */
533 bool activity; /* Activity flag for clock down */
534 s32 idletime; /* Control for activity timeout */
535 s32 idlecount; /* Activity timeout counter */
536 s32 idleclock; /* How to set bus driver when idle */
537 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
538 bool use_rxchain; /* If dhd should use PKT chains */
539 bool sleeping; /* Is SDIO bus sleeping? */
540 bool rxflow_mode; /* Rx flow control mode */
541 bool rxflow; /* Is rx flow control on */
542 uint prev_rxlim_hit; /* Is prev rx limit exceeded
543 (per dpc schedule) */
544 bool alp_only; /* Don't use HT clock (ALP only) */
545 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
546 bool usebufpool;
547
548 #ifdef SDTEST
549 /* external loopback */
550 bool ext_loop;
551 u8 loopid;
552
553 /* pktgen configuration */
554 uint pktgen_freq; /* Ticks between bursts */
555 uint pktgen_count; /* Packets to send each burst */
556 uint pktgen_print; /* Bursts between count displays */
557 uint pktgen_total; /* Stop after this many */
558 uint pktgen_minlen; /* Minimum packet data len */
559 uint pktgen_maxlen; /* Maximum packet data len */
560 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
561 uint pktgen_stop; /* Number of tx failures causing stop */
562
563 /* active pktgen fields */
564 uint pktgen_tick; /* Tick counter for bursts */
565 uint pktgen_ptick; /* Burst counter for printing */
566 uint pktgen_sent; /* Number of test packets generated */
567 uint pktgen_rcvd; /* Number of test packets received */
568 uint pktgen_fail; /* Number of failed send attempts */
569 u16 pktgen_len; /* Length of next packet to send */
570 #endif /* SDTEST */
571
572 /* Some additional counters */
573 uint tx_sderrs; /* Count of tx attempts with sd errors */
574 uint fcqueued; /* Tx packets that got queued */
575 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
576 uint rx_toolong; /* Receive frames too long to receive */
577 uint rxc_errors; /* SDIO errors when reading control frames */
578 uint rx_hdrfail; /* SDIO errors on header reads */
579 uint rx_badhdr; /* Bad received headers (roosync?) */
580 uint rx_badseq; /* Mismatched rx sequence number */
581 uint fc_rcvd; /* Number of flow-control events received */
582 uint fc_xoff; /* Number which turned on flow-control */
583 uint fc_xon; /* Number which turned off flow-control */
584 uint rxglomfail; /* Failed deglom attempts */
585 uint rxglomframes; /* Number of glom frames (superframes) */
586 uint rxglompkts; /* Number of packets from glom frames */
587 uint f2rxhdrs; /* Number of header reads */
588 uint f2rxdata; /* Number of frame data reads */
589 uint f2txdata; /* Number of f2 frame writes */
590 uint f1regdata; /* Number of f1 register accesses */
591
592 u8 *ctrl_frame_buf;
593 u32 ctrl_frame_len;
594 bool ctrl_frame_stat;
595 } dhd_bus_t;
596
597 typedef volatile struct _sbconfig {
598 u32 PAD[2];
599 u32 sbipsflag; /* initiator port ocp slave flag */
600 u32 PAD[3];
601 u32 sbtpsflag; /* target port ocp slave flag */
602 u32 PAD[11];
603 u32 sbtmerrloga; /* (sonics >= 2.3) */
604 u32 PAD;
605 u32 sbtmerrlog; /* (sonics >= 2.3) */
606 u32 PAD[3];
607 u32 sbadmatch3; /* address match3 */
608 u32 PAD;
609 u32 sbadmatch2; /* address match2 */
610 u32 PAD;
611 u32 sbadmatch1; /* address match1 */
612 u32 PAD[7];
613 u32 sbimstate; /* initiator agent state */
614 u32 sbintvec; /* interrupt mask */
615 u32 sbtmstatelow; /* target state */
616 u32 sbtmstatehigh; /* target state */
617 u32 sbbwa0; /* bandwidth allocation table0 */
618 u32 PAD;
619 u32 sbimconfiglow; /* initiator configuration */
620 u32 sbimconfighigh; /* initiator configuration */
621 u32 sbadmatch0; /* address match0 */
622 u32 PAD;
623 u32 sbtmconfiglow; /* target configuration */
624 u32 sbtmconfighigh; /* target configuration */
625 u32 sbbconfig; /* broadcast configuration */
626 u32 PAD;
627 u32 sbbstate; /* broadcast state */
628 u32 PAD[3];
629 u32 sbactcnfg; /* activate configuration */
630 u32 PAD[3];
631 u32 sbflagst; /* current sbflags */
632 u32 PAD[3];
633 u32 sbidlow; /* identification */
634 u32 sbidhigh; /* identification */
635 } sbconfig_t;
636
637 /* clkstate */
638 #define CLK_NONE 0
639 #define CLK_SDONLY 1
640 #define CLK_PENDING 2 /* Not used yet */
641 #define CLK_AVAIL 3
642
643 #define DHD_NOPMU(dhd) (false)
644
645 #ifdef DHD_DEBUG
646 static int qcount[NUMPRIO];
647 static int tx_packets[NUMPRIO];
648 #endif /* DHD_DEBUG */
649
650 /* Deferred transmit */
651 const uint dhd_deferred_tx = 1;
652
653 extern uint dhd_watchdog_ms;
654 extern void dhd_os_wd_timer(void *bus, uint wdtick);
655
656 /* Tx/Rx bounds */
657 uint dhd_txbound;
658 uint dhd_rxbound;
659 uint dhd_txminmax;
660
661 /* override the RAM size if possible */
662 #define DONGLE_MIN_MEMSIZE (128 * 1024)
663 int dhd_dongle_memsize;
664
665 static bool dhd_alignctl;
666
667 static bool sd1idle;
668
669 static bool retrydata;
670 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
671
672 static const uint watermark = 8;
673 static const uint firstread = DHD_FIRSTREAD;
674
675 #define HDATLEN (firstread - (SDPCM_HDRLEN))
676
677 /* Retry count for register access failures */
678 static const uint retry_limit = 2;
679
680 /* Force even SD lengths (some host controllers mess up on odd bytes) */
681 static bool forcealign;
682
683 #define ALIGNMENT 4
684
685 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
686 extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
687 #endif
688
689 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
690 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
691 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
692 #define PKTALIGN(_p, _len, _align) \
693 do { \
694 uint datalign; \
695 datalign = (unsigned long)((_p)->data); \
696 datalign = roundup(datalign, (_align)) - datalign; \
697 ASSERT(datalign < (_align)); \
698 ASSERT((_p)->len >= ((_len) + datalign)); \
699 if (datalign) \
700 skb_pull((_p), datalign); \
701 __skb_trim((_p), (_len)); \
702 } while (0)
703
704 /* Limit on rounding up frames */
705 static const uint max_roundup = 512;
706
707 /* Try doing readahead */
708 static bool dhd_readahead;
709
710 /* To check if there's window offered */
711 #define DATAOK(bus) \
712 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
713 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
714
715 /* Macros to get register read/write status */
716 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
717 #define R_SDREG(regvar, regaddr, retryvar) \
718 do { \
719 retryvar = 0; \
720 do { \
721 regvar = R_REG(regaddr); \
722 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
723 if (retryvar) { \
724 bus->regfails += (retryvar-1); \
725 if (retryvar > retry_limit) { \
726 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
727 __func__, __LINE__)); \
728 regvar = 0; \
729 } \
730 } \
731 } while (0)
732
733 #define W_SDREG(regval, regaddr, retryvar) \
734 do { \
735 retryvar = 0; \
736 do { \
737 W_REG(regaddr, regval); \
738 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
739 if (retryvar) { \
740 bus->regfails += (retryvar-1); \
741 if (retryvar > retry_limit) \
742 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
743 __func__, __LINE__)); \
744 } \
745 } while (0)
746
747 #define DHD_BUS SDIO_BUS
748
749 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
750
751 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
752
753 #ifdef SDTEST
754 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
755 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
756 #endif
757
758 #ifdef DHD_DEBUG
759 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
760 static int dhdsdio_mem_dump(dhd_bus_t *bus);
761 #endif /* DHD_DEBUG */
762 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
763
764 static void dhdsdio_release(dhd_bus_t *bus);
765 static void dhdsdio_release_malloc(dhd_bus_t *bus);
766 static void dhdsdio_disconnect(void *ptr);
767 static bool dhdsdio_chipmatch(u16 chipid);
768 static bool dhdsdio_probe_attach(dhd_bus_t *bus, void *sdh,
769 void *regsva, u16 devid);
770 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh);
771 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh);
772 static void dhdsdio_release_dongle(dhd_bus_t *bus);
773
774 static uint process_nvram_vars(char *varbuf, uint len);
775
776 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
777 static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
778 uint flags, u8 *buf, uint nbytes,
779 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
780 void *handle);
781
782 static bool dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh);
783 static int _dhdsdio_download_firmware(struct dhd_bus *bus);
784
785 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
786 static int dhdsdio_download_nvram(struct dhd_bus *bus);
787 static void dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase);
788 static int dhdsdio_chip_attach(struct dhd_bus *bus, void *regs);
789 static void dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase);
790 static void dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus,
791 u32 drivestrength);
792 static void dhdsdio_chip_detach(struct dhd_bus *bus);
793
794 /* Packet free applicable unconditionally for sdio and sdspi.
795 * Conditional if bufpool was present for gspi bus.
796 */
797 static void dhdsdio_pktfree2(dhd_bus_t *bus, struct sk_buff *pkt)
798 {
799 dhd_os_sdlock_rxq(bus->dhd);
800 if ((bus->bus != SPI_BUS) || bus->usebufpool)
801 brcmu_pkt_buf_free_skb(pkt);
802 dhd_os_sdunlock_rxq(bus->dhd);
803 }
804
805 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
806 {
807 s32 min_size = DONGLE_MIN_MEMSIZE;
808 /* Restrict the memsize to user specified limit */
809 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
810 dhd_dongle_memsize, min_size));
811 if ((dhd_dongle_memsize > min_size) &&
812 (dhd_dongle_memsize < (s32) bus->orig_ramsize))
813 bus->ramsize = dhd_dongle_memsize;
814 }
815
816 static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
817 {
818 int err = 0;
819 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
820 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
821 if (!err)
822 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
823 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
824 if (!err)
825 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
826 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
827 &err);
828 return err;
829 }
830
831 /* Turn backplane clock on or off */
832 static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
833 {
834 int err;
835 u8 clkctl, clkreq, devctl;
836 bcmsdh_info_t *sdh;
837
838 DHD_TRACE(("%s: Enter\n", __func__));
839
840 #if defined(OOB_INTR_ONLY)
841 pendok = false;
842 #endif
843 clkctl = 0;
844 sdh = bus->sdh;
845
846 if (on) {
847 /* Request HT Avail */
848 clkreq =
849 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
850
851 if ((bus->ci->chip == BCM4329_CHIP_ID)
852 && (bus->ci->chiprev == 0))
853 clkreq |= SBSDIO_FORCE_ALP;
854
855 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
856 clkreq, &err);
857 if (err) {
858 DHD_ERROR(("%s: HT Avail request error: %d\n",
859 __func__, err));
860 return -EBADE;
861 }
862
863 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
864 && (bus->ci->buscorerev == 9))) {
865 u32 dummy, retries;
866 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
867 }
868
869 /* Check current status */
870 clkctl =
871 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
872 &err);
873 if (err) {
874 DHD_ERROR(("%s: HT Avail read error: %d\n",
875 __func__, err));
876 return -EBADE;
877 }
878
879 /* Go to pending and await interrupt if appropriate */
880 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
881 /* Allow only clock-available interrupt */
882 devctl =
883 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
884 &err);
885 if (err) {
886 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
887 __func__, err));
888 return -EBADE;
889 }
890
891 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
892 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
893 devctl, &err);
894 DHD_INFO(("CLKCTL: set PENDING\n"));
895 bus->clkstate = CLK_PENDING;
896
897 return 0;
898 } else if (bus->clkstate == CLK_PENDING) {
899 /* Cancel CA-only interrupt filter */
900 devctl =
901 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
902 &err);
903 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
904 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
905 devctl, &err);
906 }
907
908 /* Otherwise, wait here (polling) for HT Avail */
909 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
910 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
911 ((clkctl =
912 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
913 SBSDIO_FUNC1_CHIPCLKCSR,
914 &err)),
915 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
916 PMU_MAX_TRANSITION_DLY);
917 }
918 if (err) {
919 DHD_ERROR(("%s: HT Avail request error: %d\n",
920 __func__, err));
921 return -EBADE;
922 }
923 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
924 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
925 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
926 return -EBADE;
927 }
928
929 /* Mark clock available */
930 bus->clkstate = CLK_AVAIL;
931 DHD_INFO(("CLKCTL: turned ON\n"));
932
933 #if defined(DHD_DEBUG)
934 if (bus->alp_only == true) {
935 #if !defined(BCMLXSDMMC)
936 if (!SBSDIO_ALPONLY(clkctl)) {
937 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
938 __func__));
939 }
940 #endif /* !defined(BCMLXSDMMC) */
941 } else {
942 if (SBSDIO_ALPONLY(clkctl)) {
943 DHD_ERROR(("%s: HT Clock should be on.\n",
944 __func__));
945 }
946 }
947 #endif /* defined (DHD_DEBUG) */
948
949 bus->activity = true;
950 } else {
951 clkreq = 0;
952
953 if (bus->clkstate == CLK_PENDING) {
954 /* Cancel CA-only interrupt filter */
955 devctl =
956 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
957 &err);
958 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
959 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
960 devctl, &err);
961 }
962
963 bus->clkstate = CLK_SDONLY;
964 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
965 clkreq, &err);
966 DHD_INFO(("CLKCTL: turned OFF\n"));
967 if (err) {
968 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
969 __func__, err));
970 return -EBADE;
971 }
972 }
973 return 0;
974 }
975
976 /* Change idle/active SD state */
977 static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
978 {
979 DHD_TRACE(("%s: Enter\n", __func__));
980
981 if (on)
982 bus->clkstate = CLK_SDONLY;
983 else
984 bus->clkstate = CLK_NONE;
985
986 return 0;
987 }
988
989 /* Transition SD and backplane clock readiness */
990 static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
991 {
992 #ifdef DHD_DEBUG
993 uint oldstate = bus->clkstate;
994 #endif /* DHD_DEBUG */
995
996 DHD_TRACE(("%s: Enter\n", __func__));
997
998 /* Early exit if we're already there */
999 if (bus->clkstate == target) {
1000 if (target == CLK_AVAIL) {
1001 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1002 bus->activity = true;
1003 }
1004 return 0;
1005 }
1006
1007 switch (target) {
1008 case CLK_AVAIL:
1009 /* Make sure SD clock is available */
1010 if (bus->clkstate == CLK_NONE)
1011 dhdsdio_sdclk(bus, true);
1012 /* Now request HT Avail on the backplane */
1013 dhdsdio_htclk(bus, true, pendok);
1014 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1015 bus->activity = true;
1016 break;
1017
1018 case CLK_SDONLY:
1019 /* Remove HT request, or bring up SD clock */
1020 if (bus->clkstate == CLK_NONE)
1021 dhdsdio_sdclk(bus, true);
1022 else if (bus->clkstate == CLK_AVAIL)
1023 dhdsdio_htclk(bus, false, false);
1024 else
1025 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
1026 bus->clkstate, target));
1027 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1028 break;
1029
1030 case CLK_NONE:
1031 /* Make sure to remove HT request */
1032 if (bus->clkstate == CLK_AVAIL)
1033 dhdsdio_htclk(bus, false, false);
1034 /* Now remove the SD clock */
1035 dhdsdio_sdclk(bus, false);
1036 dhd_os_wd_timer(bus->dhd, 0);
1037 break;
1038 }
1039 #ifdef DHD_DEBUG
1040 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
1041 #endif /* DHD_DEBUG */
1042
1043 return 0;
1044 }
1045
1046 int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
1047 {
1048 bcmsdh_info_t *sdh = bus->sdh;
1049 struct sdpcmd_regs *regs = bus->regs;
1050 uint retries = 0;
1051
1052 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
1053 (sleep ? "SLEEP" : "WAKE"),
1054 (bus->sleeping ? "SLEEP" : "WAKE")));
1055
1056 /* Done if we're already in the requested state */
1057 if (sleep == bus->sleeping)
1058 return 0;
1059
1060 /* Going to sleep: set the alarm and turn off the lights... */
1061 if (sleep) {
1062 /* Don't sleep if something is pending */
1063 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1064 return -EBUSY;
1065
1066 /* Disable SDIO interrupts (no longer interested) */
1067 bcmsdh_intr_disable(bus->sdh);
1068
1069 /* Make sure the controller has the bus up */
1070 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1071
1072 /* Tell device to start using OOB wakeup */
1073 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
1074 if (retries > retry_limit)
1075 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1076
1077 /* Turn off our contribution to the HT clock request */
1078 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1079
1080 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
1081 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1082
1083 /* Isolate the bus */
1084 if (bus->ci->chip != BCM4329_CHIP_ID
1085 && bus->ci->chip != BCM4319_CHIP_ID) {
1086 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
1087 SBSDIO_DEVCTL_PADS_ISO, NULL);
1088 }
1089
1090 /* Change state */
1091 bus->sleeping = true;
1092
1093 } else {
1094 /* Waking up: bus power up is ok, set local state */
1095
1096 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
1097 0, NULL);
1098
1099 /* Force pad isolation off if possible
1100 (in case power never toggled) */
1101 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1102 && (bus->ci->buscorerev >= 10))
1103 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
1104 NULL);
1105
1106 /* Make sure the controller has the bus up */
1107 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1108
1109 /* Send misc interrupt to indicate OOB not needed */
1110 W_SDREG(0, &regs->tosbmailboxdata, retries);
1111 if (retries <= retry_limit)
1112 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
1113
1114 if (retries > retry_limit)
1115 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
1116
1117 /* Make sure we have SD bus access */
1118 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1119
1120 /* Change state */
1121 bus->sleeping = false;
1122
1123 /* Enable interrupts again */
1124 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
1125 bus->intdis = false;
1126 bcmsdh_intr_enable(bus->sdh);
1127 }
1128 }
1129
1130 return 0;
1131 }
1132
1133 #if defined(OOB_INTR_ONLY)
1134 void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
1135 {
1136 #if defined(HW_OOB)
1137 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
1138 #else
1139 sdpcmd_regs_t *regs = bus->regs;
1140 uint retries = 0;
1141
1142 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1143 if (enable == true) {
1144
1145 /* Tell device to start using OOB wakeup */
1146 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
1147 if (retries > retry_limit)
1148 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1149
1150 } else {
1151 /* Send misc interrupt to indicate OOB not needed */
1152 W_SDREG(0, &regs->tosbmailboxdata, retries);
1153 if (retries <= retry_limit)
1154 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
1155 }
1156
1157 /* Turn off our contribution to the HT clock request */
1158 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1159 #endif /* !defined(HW_OOB) */
1160 }
1161 #endif /* defined(OOB_INTR_ONLY) */
1162
1163 #define BUS_WAKE(bus) \
1164 do { \
1165 if ((bus)->sleeping) \
1166 dhdsdio_bussleep((bus), false); \
1167 } while (0);
1168
1169 /* Writes a HW/SW header into the packet and sends it. */
1170 /* Assumes: (a) header space already there, (b) caller holds lock */
1171 static int dhdsdio_txpkt(dhd_bus_t *bus, struct sk_buff *pkt, uint chan,
1172 bool free_pkt)
1173 {
1174 int ret;
1175 u8 *frame;
1176 u16 len, pad = 0;
1177 u32 swheader;
1178 uint retries = 0;
1179 bcmsdh_info_t *sdh;
1180 struct sk_buff *new;
1181 int i;
1182
1183 DHD_TRACE(("%s: Enter\n", __func__));
1184
1185 sdh = bus->sdh;
1186
1187 if (bus->dhd->dongle_reset) {
1188 ret = -EPERM;
1189 goto done;
1190 }
1191
1192 frame = (u8 *) (pkt->data);
1193
1194 /* Add alignment padding, allocate new packet if needed */
1195 pad = ((unsigned long)frame % DHD_SDALIGN);
1196 if (pad) {
1197 if (skb_headroom(pkt) < pad) {
1198 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
1199 __func__, skb_headroom(pkt), pad));
1200 bus->dhd->tx_realloc++;
1201 new = brcmu_pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
1202 if (!new) {
1203 DHD_ERROR(("%s: couldn't allocate new %d-byte "
1204 "packet\n",
1205 __func__, pkt->len + DHD_SDALIGN));
1206 ret = -ENOMEM;
1207 goto done;
1208 }
1209
1210 PKTALIGN(new, pkt->len, DHD_SDALIGN);
1211 memcpy(new->data, pkt->data, pkt->len);
1212 if (free_pkt)
1213 brcmu_pkt_buf_free_skb(pkt);
1214 /* free the pkt if canned one is not used */
1215 free_pkt = true;
1216 pkt = new;
1217 frame = (u8 *) (pkt->data);
1218 ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
1219 pad = 0;
1220 } else {
1221 skb_push(pkt, pad);
1222 frame = (u8 *) (pkt->data);
1223
1224 ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
1225 memset(frame, 0, pad + SDPCM_HDRLEN);
1226 }
1227 }
1228 ASSERT(pad < DHD_SDALIGN);
1229
1230 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1231 len = (u16) (pkt->len);
1232 *(u16 *) frame = cpu_to_le16(len);
1233 *(((u16 *) frame) + 1) = cpu_to_le16(~len);
1234
1235 /* Software tag: channel, sequence number, data offset */
1236 swheader =
1237 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1238 (((pad +
1239 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1240
1241 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1242 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1243
1244 #ifdef DHD_DEBUG
1245 tx_packets[pkt->priority]++;
1246 if (DHD_BYTES_ON() &&
1247 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
1248 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
1249 printk(KERN_DEBUG "Tx Frame:\n");
1250 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
1251 } else if (DHD_HDRS_ON()) {
1252 printk(KERN_DEBUG "TxHdr:\n");
1253 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1254 frame, min_t(u16, len, 16));
1255 }
1256 #endif
1257
1258 /* Raise len to next SDIO block to eliminate tail command */
1259 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1260 u16 pad = bus->blocksize - (len % bus->blocksize);
1261 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1262 #ifdef NOTUSED
1263 if (pad <= skb_tailroom(pkt))
1264 #endif /* NOTUSED */
1265 len += pad;
1266 } else if (len % DHD_SDALIGN) {
1267 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1268 }
1269
1270 /* Some controllers have trouble with odd bytes -- round to even */
1271 if (forcealign && (len & (ALIGNMENT - 1))) {
1272 #ifdef NOTUSED
1273 if (skb_tailroom(pkt))
1274 #endif
1275 len = roundup(len, ALIGNMENT);
1276 #ifdef NOTUSED
1277 else
1278 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1279 __func__, len));
1280 #endif
1281 }
1282
1283 do {
1284 ret =
1285 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1286 F2SYNC, frame, len, pkt, NULL, NULL);
1287 bus->f2txdata++;
1288 ASSERT(ret != -BCME_PENDING);
1289
1290 if (ret < 0) {
1291 /* On failure, abort the command
1292 and terminate the frame */
1293 DHD_INFO(("%s: sdio error %d, abort command and "
1294 "terminate frame.\n", __func__, ret));
1295 bus->tx_sderrs++;
1296
1297 bcmsdh_abort(sdh, SDIO_FUNC_2);
1298 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1299 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1300 NULL);
1301 bus->f1regdata++;
1302
1303 for (i = 0; i < 3; i++) {
1304 u8 hi, lo;
1305 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1306 SBSDIO_FUNC1_WFRAMEBCHI,
1307 NULL);
1308 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1309 SBSDIO_FUNC1_WFRAMEBCLO,
1310 NULL);
1311 bus->f1regdata += 2;
1312 if ((hi == 0) && (lo == 0))
1313 break;
1314 }
1315
1316 }
1317 if (ret == 0)
1318 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1319
1320 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1321
1322 done:
1323 /* restore pkt buffer pointer before calling tx complete routine */
1324 skb_pull(pkt, SDPCM_HDRLEN + pad);
1325 dhd_os_sdunlock(bus->dhd);
1326 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1327 dhd_os_sdlock(bus->dhd);
1328
1329 if (free_pkt)
1330 brcmu_pkt_buf_free_skb(pkt);
1331
1332 return ret;
1333 }
1334
1335 int dhd_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1336 {
1337 int ret = -EBADE;
1338 uint datalen, prec;
1339
1340 DHD_TRACE(("%s: Enter\n", __func__));
1341
1342 datalen = pkt->len;
1343
1344 #ifdef SDTEST
1345 /* Push the test header if doing loopback */
1346 if (bus->ext_loop) {
1347 u8 *data;
1348 skb_push(pkt, SDPCM_TEST_HDRLEN);
1349 data = pkt->data;
1350 *data++ = SDPCM_TEST_ECHOREQ;
1351 *data++ = (u8) bus->loopid++;
1352 *data++ = (datalen >> 0);
1353 *data++ = (datalen >> 8);
1354 datalen += SDPCM_TEST_HDRLEN;
1355 }
1356 #endif /* SDTEST */
1357
1358 /* Add space for the header */
1359 skb_push(pkt, SDPCM_HDRLEN);
1360 ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1361
1362 prec = PRIO2PREC((pkt->priority & PRIOMASK));
1363
1364 /* Check for existing queue, current flow-control,
1365 pending event, or pending clock */
1366 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1367 || bus->dpc_sched || (!DATAOK(bus))
1368 || (bus->flowcontrol & NBITVAL(prec))
1369 || (bus->clkstate != CLK_AVAIL)) {
1370 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1371 pktq_len(&bus->txq)));
1372 bus->fcqueued++;
1373
1374 /* Priority based enq */
1375 dhd_os_sdlock_txq(bus->dhd);
1376 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1377 skb_pull(pkt, SDPCM_HDRLEN);
1378 dhd_txcomplete(bus->dhd, pkt, false);
1379 brcmu_pkt_buf_free_skb(pkt);
1380 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1381 ret = -ENOSR;
1382 } else {
1383 ret = 0;
1384 }
1385 dhd_os_sdunlock_txq(bus->dhd);
1386
1387 if (pktq_len(&bus->txq) >= TXHI)
1388 dhd_txflowcontrol(bus->dhd, 0, ON);
1389
1390 #ifdef DHD_DEBUG
1391 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1392 qcount[prec] = pktq_plen(&bus->txq, prec);
1393 #endif
1394 /* Schedule DPC if needed to send queued packet(s) */
1395 if (dhd_deferred_tx && !bus->dpc_sched) {
1396 bus->dpc_sched = true;
1397 dhd_sched_dpc(bus->dhd);
1398 }
1399 } else {
1400 /* Lock: we're about to use shared data/code (and SDIO) */
1401 dhd_os_sdlock(bus->dhd);
1402
1403 /* Otherwise, send it now */
1404 BUS_WAKE(bus);
1405 /* Make sure back plane ht clk is on, no pending allowed */
1406 dhdsdio_clkctl(bus, CLK_AVAIL, true);
1407
1408 #ifndef SDTEST
1409 DHD_TRACE(("%s: calling txpkt\n", __func__));
1410 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1411 #else
1412 ret = dhdsdio_txpkt(bus, pkt,
1413 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1414 SDPCM_DATA_CHANNEL), true);
1415 #endif
1416 if (ret)
1417 bus->dhd->tx_errors++;
1418 else
1419 bus->dhd->dstats.tx_bytes += datalen;
1420
1421 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1422 bus->activity = false;
1423 dhdsdio_clkctl(bus, CLK_NONE, true);
1424 }
1425
1426 dhd_os_sdunlock(bus->dhd);
1427 }
1428
1429 return ret;
1430 }
1431
1432 static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1433 {
1434 struct sk_buff *pkt;
1435 u32 intstatus = 0;
1436 uint retries = 0;
1437 int ret = 0, prec_out;
1438 uint cnt = 0;
1439 uint datalen;
1440 u8 tx_prec_map;
1441
1442 dhd_pub_t *dhd = bus->dhd;
1443 struct sdpcmd_regs *regs = bus->regs;
1444
1445 DHD_TRACE(("%s: Enter\n", __func__));
1446
1447 tx_prec_map = ~bus->flowcontrol;
1448
1449 /* Send frames until the limit or some other event */
1450 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1451 dhd_os_sdlock_txq(bus->dhd);
1452 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1453 if (pkt == NULL) {
1454 dhd_os_sdunlock_txq(bus->dhd);
1455 break;
1456 }
1457 dhd_os_sdunlock_txq(bus->dhd);
1458 datalen = pkt->len - SDPCM_HDRLEN;
1459
1460 #ifndef SDTEST
1461 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1462 #else
1463 ret = dhdsdio_txpkt(bus, pkt,
1464 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1465 SDPCM_DATA_CHANNEL), true);
1466 #endif
1467 if (ret)
1468 bus->dhd->tx_errors++;
1469 else
1470 bus->dhd->dstats.tx_bytes += datalen;
1471
1472 /* In poll mode, need to check for other events */
1473 if (!bus->intr && cnt) {
1474 /* Check device status, signal pending interrupt */
1475 R_SDREG(intstatus, &regs->intstatus, retries);
1476 bus->f2txdata++;
1477 if (bcmsdh_regfail(bus->sdh))
1478 break;
1479 if (intstatus & bus->hostintmask)
1480 bus->ipend = true;
1481 }
1482 }
1483
1484 /* Deflow-control stack if needed */
1485 if (dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1486 dhd->txoff && (pktq_len(&bus->txq) < TXLOW))
1487 dhd_txflowcontrol(dhd, 0, OFF);
1488
1489 return cnt;
1490 }
1491
1492 int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1493 {
1494 u8 *frame;
1495 u16 len;
1496 u32 swheader;
1497 uint retries = 0;
1498 bcmsdh_info_t *sdh = bus->sdh;
1499 u8 doff = 0;
1500 int ret = -1;
1501 int i;
1502
1503 DHD_TRACE(("%s: Enter\n", __func__));
1504
1505 if (bus->dhd->dongle_reset)
1506 return -EIO;
1507
1508 /* Back the pointer to make a room for bus header */
1509 frame = msg - SDPCM_HDRLEN;
1510 len = (msglen += SDPCM_HDRLEN);
1511
1512 /* Add alignment padding (optional for ctl frames) */
1513 if (dhd_alignctl) {
1514 doff = ((unsigned long)frame % DHD_SDALIGN);
1515 if (doff) {
1516 frame -= doff;
1517 len += doff;
1518 msglen += doff;
1519 memset(frame, 0, doff + SDPCM_HDRLEN);
1520 }
1521 ASSERT(doff < DHD_SDALIGN);
1522 }
1523 doff += SDPCM_HDRLEN;
1524
1525 /* Round send length to next SDIO block */
1526 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1527 u16 pad = bus->blocksize - (len % bus->blocksize);
1528 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1529 len += pad;
1530 } else if (len % DHD_SDALIGN) {
1531 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1532 }
1533
1534 /* Satisfy length-alignment requirements */
1535 if (forcealign && (len & (ALIGNMENT - 1)))
1536 len = roundup(len, ALIGNMENT);
1537
1538 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1539
1540 /* Need to lock here to protect txseq and SDIO tx calls */
1541 dhd_os_sdlock(bus->dhd);
1542
1543 BUS_WAKE(bus);
1544
1545 /* Make sure backplane clock is on */
1546 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1547
1548 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1549 *(u16 *) frame = cpu_to_le16((u16) msglen);
1550 *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1551
1552 /* Software tag: channel, sequence number, data offset */
1553 swheader =
1554 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1555 SDPCM_CHANNEL_MASK)
1556 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1557 SDPCM_DOFFSET_MASK);
1558 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1559 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1560
1561 if (!DATAOK(bus)) {
1562 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1563 __func__, bus->tx_max, bus->tx_seq));
1564 bus->ctrl_frame_stat = true;
1565 /* Send from dpc */
1566 bus->ctrl_frame_buf = frame;
1567 bus->ctrl_frame_len = len;
1568
1569 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1570
1571 if (bus->ctrl_frame_stat == false) {
1572 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1573 ret = 0;
1574 } else {
1575 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1576 ret = -1;
1577 }
1578 }
1579
1580 if (ret == -1) {
1581 #ifdef DHD_DEBUG
1582 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
1583 printk(KERN_DEBUG "Tx Frame:\n");
1584 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1585 frame, len);
1586 } else if (DHD_HDRS_ON()) {
1587 printk(KERN_DEBUG "TxHdr:\n");
1588 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1589 frame, min_t(u16, len, 16));
1590 }
1591 #endif
1592
1593 do {
1594 bus->ctrl_frame_stat = false;
1595 ret =
1596 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1597 SDIO_FUNC_2, F2SYNC, frame, len,
1598 NULL, NULL, NULL);
1599
1600 ASSERT(ret != -BCME_PENDING);
1601
1602 if (ret < 0) {
1603 /* On failure, abort the command and
1604 terminate the frame */
1605 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1606 __func__, ret));
1607 bus->tx_sderrs++;
1608
1609 bcmsdh_abort(sdh, SDIO_FUNC_2);
1610
1611 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1612 SBSDIO_FUNC1_FRAMECTRL,
1613 SFC_WF_TERM, NULL);
1614 bus->f1regdata++;
1615
1616 for (i = 0; i < 3; i++) {
1617 u8 hi, lo;
1618 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1619 SBSDIO_FUNC1_WFRAMEBCHI,
1620 NULL);
1621 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1622 SBSDIO_FUNC1_WFRAMEBCLO,
1623 NULL);
1624 bus->f1regdata += 2;
1625 if ((hi == 0) && (lo == 0))
1626 break;
1627 }
1628
1629 }
1630 if (ret == 0) {
1631 bus->tx_seq =
1632 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1633 }
1634 } while ((ret < 0) && retries++ < TXRETRIES);
1635 }
1636
1637 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1638 bus->activity = false;
1639 dhdsdio_clkctl(bus, CLK_NONE, true);
1640 }
1641
1642 dhd_os_sdunlock(bus->dhd);
1643
1644 if (ret)
1645 bus->dhd->tx_ctlerrs++;
1646 else
1647 bus->dhd->tx_ctlpkts++;
1648
1649 return ret ? -EIO : 0;
1650 }
1651
1652 int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1653 {
1654 int timeleft;
1655 uint rxlen = 0;
1656 bool pending;
1657
1658 DHD_TRACE(("%s: Enter\n", __func__));
1659
1660 if (bus->dhd->dongle_reset)
1661 return -EIO;
1662
1663 /* Wait until control frame is available */
1664 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1665
1666 dhd_os_sdlock(bus->dhd);
1667 rxlen = bus->rxlen;
1668 memcpy(msg, bus->rxctl, min(msglen, rxlen));
1669 bus->rxlen = 0;
1670 dhd_os_sdunlock(bus->dhd);
1671
1672 if (rxlen) {
1673 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1674 __func__, rxlen, msglen));
1675 } else if (timeleft == 0) {
1676 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1677 #ifdef DHD_DEBUG
1678 dhd_os_sdlock(bus->dhd);
1679 dhdsdio_checkdied(bus, NULL, 0);
1680 dhd_os_sdunlock(bus->dhd);
1681 #endif /* DHD_DEBUG */
1682 } else if (pending == true) {
1683 DHD_CTL(("%s: cancelled\n", __func__));
1684 return -ERESTARTSYS;
1685 } else {
1686 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1687 #ifdef DHD_DEBUG
1688 dhd_os_sdlock(bus->dhd);
1689 dhdsdio_checkdied(bus, NULL, 0);
1690 dhd_os_sdunlock(bus->dhd);
1691 #endif /* DHD_DEBUG */
1692 }
1693
1694 if (rxlen)
1695 bus->dhd->rx_ctlpkts++;
1696 else
1697 bus->dhd->rx_ctlerrs++;
1698
1699 return rxlen ? (int)rxlen : -ETIMEDOUT;
1700 }
1701
1702 /* IOVar table */
1703 enum {
1704 IOV_INTR = 1,
1705 IOV_POLLRATE,
1706 IOV_SDREG,
1707 IOV_SBREG,
1708 IOV_SDCIS,
1709 IOV_MEMBYTES,
1710 IOV_MEMSIZE,
1711 #ifdef DHD_DEBUG
1712 IOV_CHECKDIED,
1713 #endif
1714 IOV_DOWNLOAD,
1715 IOV_FORCEEVEN,
1716 IOV_SDIOD_DRIVE,
1717 IOV_READAHEAD,
1718 IOV_SDRXCHAIN,
1719 IOV_ALIGNCTL,
1720 IOV_SDALIGN,
1721 IOV_DEVRESET,
1722 IOV_CPU,
1723 #ifdef SDTEST
1724 IOV_PKTGEN,
1725 IOV_EXTLOOP,
1726 #endif /* SDTEST */
1727 IOV_SPROM,
1728 IOV_TXBOUND,
1729 IOV_RXBOUND,
1730 IOV_TXMINMAX,
1731 IOV_IDLETIME,
1732 IOV_IDLECLOCK,
1733 IOV_SD1IDLE,
1734 IOV_SLEEP,
1735 IOV_VARS
1736 };
1737
1738 const struct brcmu_iovar dhdsdio_iovars[] = {
1739 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1740 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1741 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1742 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1743 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1744 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1745 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1746 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1747 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1748 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1749 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1750 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1751 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1752 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1753 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1754 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1755 #ifdef DHD_DEBUG
1756 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1757 ,
1758 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1759 ,
1760 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1761 ,
1762 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1763 ,
1764 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1765 ,
1766 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1767 ,
1768 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1769 ,
1770 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1771 ,
1772 #ifdef DHD_DEBUG
1773 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1774 ,
1775 #endif /* DHD_DEBUG */
1776 #endif /* DHD_DEBUG */
1777 #ifdef SDTEST
1778 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1779 ,
1780 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1781 ,
1782 #endif /* SDTEST */
1783
1784 {NULL, 0, 0, 0, 0}
1785 };
1786
1787 static void
1788 dhd_dump_pct(struct brcmu_strbuf *strbuf, char *desc, uint num, uint div)
1789 {
1790 uint q1, q2;
1791
1792 if (!div) {
1793 brcmu_bprintf(strbuf, "%s N/A", desc);
1794 } else {
1795 q1 = num / div;
1796 q2 = (100 * (num - (q1 * div))) / div;
1797 brcmu_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1798 }
1799 }
1800
1801 void dhd_bus_dump(dhd_pub_t *dhdp, struct brcmu_strbuf *strbuf)
1802 {
1803 dhd_bus_t *bus = dhdp->bus;
1804
1805 brcmu_bprintf(strbuf, "Bus SDIO structure:\n");
1806 brcmu_bprintf(strbuf,
1807 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1808 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1809 brcmu_bprintf(strbuf,
1810 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1811 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1812 bus->rxskip, bus->rxlen, bus->rx_seq);
1813 brcmu_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1814 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1815 brcmu_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1816 bus->pollrate, bus->pollcnt, bus->regfails);
1817
1818 brcmu_bprintf(strbuf, "\nAdditional counters:\n");
1819 brcmu_bprintf(strbuf,
1820 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1821 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1822 bus->rxc_errors);
1823 brcmu_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1824 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1825 brcmu_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n",
1826 bus->fc_rcvd, bus->fc_xoff, bus->fc_xon);
1827 brcmu_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1828 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1829 brcmu_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs"
1830 " %d\n",
1831 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1832 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1833 {
1834 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1835 (bus->f2rxhdrs + bus->f2rxdata));
1836 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1837 bus->f1regdata);
1838 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1839 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1840 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1841 bus->intrcount);
1842 brcmu_bprintf(strbuf, "\n");
1843
1844 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1845 bus->dhd->rx_packets);
1846 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1847 bus->rxglomframes);
1848 brcmu_bprintf(strbuf, "\n");
1849
1850 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1851 bus->f2txdata);
1852 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1853 bus->f1regdata);
1854 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1855 (bus->f2txdata + bus->f1regdata));
1856 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1857 bus->intrcount);
1858 brcmu_bprintf(strbuf, "\n");
1859
1860 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1861 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1862 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1863 dhd_dump_pct(strbuf, ", pkts/f1sd",
1864 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1865 bus->f1regdata);
1866 dhd_dump_pct(strbuf, ", pkts/sd",
1867 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1868 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1869 bus->f1regdata));
1870 dhd_dump_pct(strbuf, ", pkts/int",
1871 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1872 bus->intrcount);
1873 brcmu_bprintf(strbuf, "\n\n");
1874 }
1875
1876 #ifdef SDTEST
1877 if (bus->pktgen_count) {
1878 brcmu_bprintf(strbuf, "pktgen config and count:\n");
1879 brcmu_bprintf(strbuf,
1880 "freq %d count %d print %d total %d min %d len %d\n",
1881 bus->pktgen_freq, bus->pktgen_count,
1882 bus->pktgen_print, bus->pktgen_total,
1883 bus->pktgen_minlen, bus->pktgen_maxlen);
1884 brcmu_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1885 bus->pktgen_sent, bus->pktgen_rcvd,
1886 bus->pktgen_fail);
1887 }
1888 #endif /* SDTEST */
1889 #ifdef DHD_DEBUG
1890 brcmu_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1891 bus->dpc_sched,
1892 (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1893 brcmu_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1894 bus->roundup);
1895 #endif /* DHD_DEBUG */
1896 brcmu_bprintf(strbuf,
1897 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1898 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1899 bus->sleeping);
1900 }
1901
1902 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1903 {
1904 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1905
1906 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1907 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1908 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1909 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1910 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1911 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1912 }
1913
1914 #ifdef SDTEST
1915 static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
1916 {
1917 dhd_pktgen_t pktgen;
1918
1919 pktgen.version = DHD_PKTGEN_VERSION;
1920 pktgen.freq = bus->pktgen_freq;
1921 pktgen.count = bus->pktgen_count;
1922 pktgen.print = bus->pktgen_print;
1923 pktgen.total = bus->pktgen_total;
1924 pktgen.minlen = bus->pktgen_minlen;
1925 pktgen.maxlen = bus->pktgen_maxlen;
1926 pktgen.numsent = bus->pktgen_sent;
1927 pktgen.numrcvd = bus->pktgen_rcvd;
1928 pktgen.numfail = bus->pktgen_fail;
1929 pktgen.mode = bus->pktgen_mode;
1930 pktgen.stop = bus->pktgen_stop;
1931
1932 memcpy(arg, &pktgen, sizeof(pktgen));
1933
1934 return 0;
1935 }
1936
1937 static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1938 {
1939 dhd_pktgen_t pktgen;
1940 uint oldcnt, oldmode;
1941
1942 memcpy(&pktgen, arg, sizeof(pktgen));
1943 if (pktgen.version != DHD_PKTGEN_VERSION)
1944 return -EINVAL;
1945
1946 oldcnt = bus->pktgen_count;
1947 oldmode = bus->pktgen_mode;
1948
1949 bus->pktgen_freq = pktgen.freq;
1950 bus->pktgen_count = pktgen.count;
1951 bus->pktgen_print = pktgen.print;
1952 bus->pktgen_total = pktgen.total;
1953 bus->pktgen_minlen = pktgen.minlen;
1954 bus->pktgen_maxlen = pktgen.maxlen;
1955 bus->pktgen_mode = pktgen.mode;
1956 bus->pktgen_stop = pktgen.stop;
1957
1958 bus->pktgen_tick = bus->pktgen_ptick = 0;
1959 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1960 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1961
1962 /* Clear counts for a new pktgen (mode change, or was stopped) */
1963 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1964 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1965
1966 return 0;
1967 }
1968 #endif /* SDTEST */
1969
1970 static int
1971 dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1972 uint size)
1973 {
1974 int bcmerror = 0;
1975 u32 sdaddr;
1976 uint dsize;
1977
1978 /* Determine initial transfer parameters */
1979 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1980 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1981 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1982 else
1983 dsize = size;
1984
1985 /* Set the backplane window to include the start address */
1986 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1987 if (bcmerror) {
1988 DHD_ERROR(("%s: window change failed\n", __func__));
1989 goto xfer_done;
1990 }
1991
1992 /* Do the transfer(s) */
1993 while (size) {
1994 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1995 __func__, (write ? "write" : "read"), dsize,
1996 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
1997 bcmerror =
1998 bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
1999 if (bcmerror) {
2000 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
2001 break;
2002 }
2003
2004 /* Adjust for next transfer (if any) */
2005 size -= dsize;
2006 if (size) {
2007 data += dsize;
2008 address += dsize;
2009 bcmerror = dhdsdio_set_siaddr_window(bus, address);
2010 if (bcmerror) {
2011 DHD_ERROR(("%s: window change failed\n",
2012 __func__));
2013 break;
2014 }
2015 sdaddr = 0;
2016 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2017 }
2018 }
2019
2020 xfer_done:
2021 /* Return the window to backplane enumeration space for core access */
2022 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
2023 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
2024 __func__, bcmsdh_cur_sbwad(bus->sdh)));
2025 }
2026
2027 return bcmerror;
2028 }
2029
2030 #ifdef DHD_DEBUG
2031 static int dhdsdio_readshared(dhd_bus_t *bus, struct sdpcm_shared *sh)
2032 {
2033 u32 addr;
2034 int rv;
2035
2036 /* Read last word in memory to determine address of
2037 sdpcm_shared structure */
2038 rv = dhdsdio_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr, 4);
2039 if (rv < 0)
2040 return rv;
2041
2042 addr = le32_to_cpu(addr);
2043
2044 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
2045
2046 /*
2047 * Check if addr is valid.
2048 * NVRAM length at the end of memory should have been overwritten.
2049 */
2050 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
2051 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
2052 __func__, addr));
2053 return -EBADE;
2054 }
2055
2056 /* Read rte_shared structure */
2057 rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
2058 sizeof(struct sdpcm_shared));
2059 if (rv < 0)
2060 return rv;
2061
2062 /* Endianness */
2063 sh->flags = le32_to_cpu(sh->flags);
2064 sh->trap_addr = le32_to_cpu(sh->trap_addr);
2065 sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
2066 sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
2067 sh->assert_line = le32_to_cpu(sh->assert_line);
2068 sh->console_addr = le32_to_cpu(sh->console_addr);
2069 sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
2070
2071 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
2072 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
2073 "is different than sdpcm_shared version %d in dongle\n",
2074 __func__, SDPCM_SHARED_VERSION,
2075 sh->flags & SDPCM_SHARED_VERSION_MASK));
2076 return -EBADE;
2077 }
2078
2079 return 0;
2080 }
2081
2082 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
2083 {
2084 int bcmerror = 0;
2085 uint msize = 512;
2086 char *mbuffer = NULL;
2087 uint maxstrlen = 256;
2088 char *str = NULL;
2089 trap_t tr;
2090 struct sdpcm_shared sdpcm_shared;
2091 struct brcmu_strbuf strbuf;
2092
2093 DHD_TRACE(("%s: Enter\n", __func__));
2094
2095 if (data == NULL) {
2096 /*
2097 * Called after a rx ctrl timeout. "data" is NULL.
2098 * allocate memory to trace the trap or assert.
2099 */
2100 size = msize;
2101 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
2102 if (mbuffer == NULL) {
2103 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
2104 msize));
2105 bcmerror = -ENOMEM;
2106 goto done;
2107 }
2108 }
2109
2110 str = kmalloc(maxstrlen, GFP_ATOMIC);
2111 if (str == NULL) {
2112 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
2113 bcmerror = -ENOMEM;
2114 goto done;
2115 }
2116
2117 bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
2118 if (bcmerror < 0)
2119 goto done;
2120
2121 brcmu_binit(&strbuf, data, size);
2122
2123 brcmu_bprintf(&strbuf,
2124 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
2125 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
2126
2127 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2128 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2129 * (Avoids conflict with real asserts for programmatic
2130 * parsing of output.)
2131 */
2132 brcmu_bprintf(&strbuf, "Assrt not built in dongle\n");
2133 }
2134
2135 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
2136 0) {
2137 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2138 * (Avoids conflict with real asserts for programmatic
2139 * parsing of output.)
2140 */
2141 brcmu_bprintf(&strbuf, "No trap%s in dongle",
2142 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
2143 ? "/assrt" : "");
2144 } else {
2145 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
2146 /* Download assert */
2147 brcmu_bprintf(&strbuf, "Dongle assert");
2148 if (sdpcm_shared.assert_exp_addr != 0) {
2149 str[0] = '\0';
2150 bcmerror = dhdsdio_membytes(bus, false,
2151 sdpcm_shared.assert_exp_addr,
2152 (u8 *) str, maxstrlen);
2153 if (bcmerror < 0)
2154 goto done;
2155
2156 str[maxstrlen - 1] = '\0';
2157 brcmu_bprintf(&strbuf, " expr \"%s\"", str);
2158 }
2159
2160 if (sdpcm_shared.assert_file_addr != 0) {
2161 str[0] = '\0';
2162 bcmerror = dhdsdio_membytes(bus, false,
2163 sdpcm_shared.assert_file_addr,
2164 (u8 *) str, maxstrlen);
2165 if (bcmerror < 0)
2166 goto done;
2167
2168 str[maxstrlen - 1] = '\0';
2169 brcmu_bprintf(&strbuf, " file \"%s\"", str);
2170 }
2171
2172 brcmu_bprintf(&strbuf, " line %d ",
2173 sdpcm_shared.assert_line);
2174 }
2175
2176 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2177 bcmerror = dhdsdio_membytes(bus, false,
2178 sdpcm_shared.trap_addr, (u8 *)&tr,
2179 sizeof(trap_t));
2180 if (bcmerror < 0)
2181 goto done;
2182
2183 brcmu_bprintf(&strbuf,
2184 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
2185 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
2186 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
2187 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
2188 tr.r14, tr.pc, sdpcm_shared.trap_addr,
2189 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
2190 tr.r6, tr.r7);
2191 }
2192 }
2193
2194 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
2195 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
2196
2197 #ifdef DHD_DEBUG
2198 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2199 /* Mem dump to a file on device */
2200 dhdsdio_mem_dump(bus);
2201 }
2202 #endif /* DHD_DEBUG */
2203
2204 done:
2205 kfree(mbuffer);
2206 kfree(str);
2207
2208 return bcmerror;
2209 }
2210
2211 static int dhdsdio_mem_dump(dhd_bus_t *bus)
2212 {
2213 int ret = 0;
2214 int size; /* Full mem size */
2215 int start = 0; /* Start address */
2216 int read_size = 0; /* Read size of each iteration */
2217 u8 *buf = NULL, *databuf = NULL;
2218
2219 /* Get full mem size */
2220 size = bus->ramsize;
2221 buf = kmalloc(size, GFP_ATOMIC);
2222 if (!buf) {
2223 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
2224 return -1;
2225 }
2226
2227 /* Read mem content */
2228 printk(KERN_DEBUG "Dump dongle memory");
2229 databuf = buf;
2230 while (size) {
2231 read_size = min(MEMBLOCK, size);
2232 ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
2233 if (ret) {
2234 DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
2235 kfree(buf);
2236 return -1;
2237 }
2238 printk(".");
2239
2240 /* Decrement size and increment start address */
2241 size -= read_size;
2242 start += read_size;
2243 databuf += read_size;
2244 }
2245 printk(KERN_DEBUG "Done\n");
2246
2247 /* free buf before return !!! */
2248 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
2249 DHD_ERROR(("%s: Error writing to files\n", __func__));
2250 return -1;
2251 }
2252
2253 /* buf free handled in write_to_file, not here */
2254 return 0;
2255 }
2256
2257 #define CONSOLE_LINE_MAX 192
2258
2259 static int dhdsdio_readconsole(dhd_bus_t *bus)
2260 {
2261 dhd_console_t *c = &bus->console;
2262 u8 line[CONSOLE_LINE_MAX], ch;
2263 u32 n, idx, addr;
2264 int rv;
2265
2266 /* Don't do anything until FWREADY updates console address */
2267 if (bus->console_addr == 0)
2268 return 0;
2269
2270 /* Read console log struct */
2271 addr = bus->console_addr + offsetof(rte_cons_t, log);
2272 rv = dhdsdio_membytes(bus, false, addr, (u8 *)&c->log,
2273 sizeof(c->log));
2274 if (rv < 0)
2275 return rv;
2276
2277 /* Allocate console buffer (one time only) */
2278 if (c->buf == NULL) {
2279 c->bufsize = le32_to_cpu(c->log.buf_size);
2280 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2281 if (c->buf == NULL)
2282 return -ENOMEM;
2283 }
2284
2285 idx = le32_to_cpu(c->log.idx);
2286
2287 /* Protect against corrupt value */
2288 if (idx > c->bufsize)
2289 return -EBADE;
2290
2291 /* Skip reading the console buffer if the index pointer
2292 has not moved */
2293 if (idx == c->last)
2294 return 0;
2295
2296 /* Read the console buffer */
2297 addr = le32_to_cpu(c->log.buf);
2298 rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2299 if (rv < 0)
2300 return rv;
2301
2302 while (c->last != idx) {
2303 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2304 if (c->last == idx) {
2305 /* This would output a partial line.
2306 * Instead, back up
2307 * the buffer pointer and output this
2308 * line next time around.
2309 */
2310 if (c->last >= n)
2311 c->last -= n;
2312 else
2313 c->last = c->bufsize - n;
2314 goto break2;
2315 }
2316 ch = c->buf[c->last];
2317 c->last = (c->last + 1) % c->bufsize;
2318 if (ch == '\n')
2319 break;
2320 line[n] = ch;
2321 }
2322
2323 if (n > 0) {
2324 if (line[n - 1] == '\r')
2325 n--;
2326 line[n] = 0;
2327 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2328 }
2329 }
2330 break2:
2331
2332 return 0;
2333 }
2334 #endif /* DHD_DEBUG */
2335
2336 int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2337 {
2338 int bcmerror = 0;
2339
2340 DHD_TRACE(("%s: Enter\n", __func__));
2341
2342 /* Basic sanity checks */
2343 if (bus->dhd->up) {
2344 bcmerror = -EISCONN;
2345 goto err;
2346 }
2347 if (!len) {
2348 bcmerror = -EOVERFLOW;
2349 goto err;
2350 }
2351
2352 /* Free the old ones and replace with passed variables */
2353 kfree(bus->vars);
2354
2355 bus->vars = kmalloc(len, GFP_ATOMIC);
2356 bus->varsz = bus->vars ? len : 0;
2357 if (bus->vars == NULL) {
2358 bcmerror = -ENOMEM;
2359 goto err;
2360 }
2361
2362 /* Copy the passed variables, which should include the
2363 terminating double-null */
2364 memcpy(bus->vars, arg, bus->varsz);
2365 err:
2366 return bcmerror;
2367 }
2368
2369 static int
2370 dhdsdio_doiovar(dhd_bus_t *bus, const struct brcmu_iovar *vi, u32 actionid,
2371 const char *name, void *params, int plen, void *arg, int len,
2372 int val_size)
2373 {
2374 int bcmerror = 0;
2375 s32 int_val = 0;
2376 bool bool_val = 0;
2377
2378 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2379 "len %d val_size %d\n",
2380 __func__, actionid, name, params, plen, arg, len, val_size));
2381
2382 bcmerror = brcmu_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2383 if (bcmerror != 0)
2384 goto exit;
2385
2386 if (plen >= (int)sizeof(int_val))
2387 memcpy(&int_val, params, sizeof(int_val));
2388
2389 bool_val = (int_val != 0) ? true : false;
2390
2391 /* Some ioctls use the bus */
2392 dhd_os_sdlock(bus->dhd);
2393
2394 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2395 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2396 actionid == IOV_GVAL(IOV_DEVRESET))) {
2397 bcmerror = -EPERM;
2398 goto exit;
2399 }
2400
2401 /* Handle sleep stuff before any clock mucking */
2402 if (vi->varid == IOV_SLEEP) {
2403 if (IOV_ISSET(actionid)) {
2404 bcmerror = dhdsdio_bussleep(bus, bool_val);
2405 } else {
2406 int_val = (s32) bus->sleeping;
2407 memcpy(arg, &int_val, val_size);
2408 }
2409 goto exit;
2410 }
2411
2412 /* Request clock to allow SDIO accesses */
2413 if (!bus->dhd->dongle_reset) {
2414 BUS_WAKE(bus);
2415 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2416 }
2417
2418 switch (actionid) {
2419 case IOV_GVAL(IOV_INTR):
2420 int_val = (s32) bus->intr;
2421 memcpy(arg, &int_val, val_size);
2422 break;
2423
2424 case IOV_SVAL(IOV_INTR):
2425 bus->intr = bool_val;
2426 bus->intdis = false;
2427 if (bus->dhd->up) {
2428 if (bus->intr) {
2429 DHD_INTR(("%s: enable SDIO device interrupts\n",
2430 __func__));
2431 bcmsdh_intr_enable(bus->sdh);
2432 } else {
2433 DHD_INTR(("%s: disable SDIO interrupts\n",
2434 __func__));
2435 bcmsdh_intr_disable(bus->sdh);
2436 }
2437 }
2438 break;
2439
2440 case IOV_GVAL(IOV_POLLRATE):
2441 int_val = (s32) bus->pollrate;
2442 memcpy(arg, &int_val, val_size);
2443 break;
2444
2445 case IOV_SVAL(IOV_POLLRATE):
2446 bus->pollrate = (uint) int_val;
2447 bus->poll = (bus->pollrate != 0);
2448 break;
2449
2450 case IOV_GVAL(IOV_IDLETIME):
2451 int_val = bus->idletime;
2452 memcpy(arg, &int_val, val_size);
2453 break;
2454
2455 case IOV_SVAL(IOV_IDLETIME):
2456 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2457 bcmerror = -EINVAL;
2458 else
2459 bus->idletime = int_val;
2460 break;
2461
2462 case IOV_GVAL(IOV_IDLECLOCK):
2463 int_val = (s32) bus->idleclock;
2464 memcpy(arg, &int_val, val_size);
2465 break;
2466
2467 case IOV_SVAL(IOV_IDLECLOCK):
2468 bus->idleclock = int_val;
2469 break;
2470
2471 case IOV_GVAL(IOV_SD1IDLE):
2472 int_val = (s32) sd1idle;
2473 memcpy(arg, &int_val, val_size);
2474 break;
2475
2476 case IOV_SVAL(IOV_SD1IDLE):
2477 sd1idle = bool_val;
2478 break;
2479
2480 case IOV_SVAL(IOV_MEMBYTES):
2481 case IOV_GVAL(IOV_MEMBYTES):
2482 {
2483 u32 address;
2484 uint size, dsize;
2485 u8 *data;
2486
2487 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2488
2489 ASSERT(plen >= 2 * sizeof(int));
2490
2491 address = (u32) int_val;
2492 memcpy(&int_val, (char *)params + sizeof(int_val),
2493 sizeof(int_val));
2494 size = (uint) int_val;
2495
2496 /* Do some validation */
2497 dsize = set ? plen - (2 * sizeof(int)) : len;
2498 if (dsize < size) {
2499 DHD_ERROR(("%s: error on %s membytes, addr "
2500 "0x%08x size %d dsize %d\n",
2501 __func__, (set ? "set" : "get"),
2502 address, size, dsize));
2503 bcmerror = -EINVAL;
2504 break;
2505 }
2506
2507 DHD_INFO(("%s: Request to %s %d bytes at address "
2508 "0x%08x\n",
2509 __func__, (set ? "write" : "read"), size, address));
2510
2511 /* If we know about SOCRAM, check for a fit */
2512 if ((bus->orig_ramsize) &&
2513 ((address > bus->orig_ramsize)
2514 || (address + size > bus->orig_ramsize))) {
2515 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2516 "bytes at 0x%08x\n",
2517 __func__, bus->orig_ramsize, size, address));
2518 bcmerror = -EINVAL;
2519 break;
2520 }
2521
2522 /* Generate the actual data pointer */
2523 data =
2524 set ? (u8 *) params +
2525 2 * sizeof(int) : (u8 *) arg;
2526
2527 /* Call to do the transfer */
2528 bcmerror =
2529 dhdsdio_membytes(bus, set, address, data, size);
2530
2531 break;
2532 }
2533
2534 case IOV_GVAL(IOV_MEMSIZE):
2535 int_val = (s32) bus->ramsize;
2536 memcpy(arg, &int_val, val_size);
2537 break;
2538
2539 case IOV_GVAL(IOV_SDIOD_DRIVE):
2540 int_val = (s32) dhd_sdiod_drive_strength;
2541 memcpy(arg, &int_val, val_size);
2542 break;
2543
2544 case IOV_SVAL(IOV_SDIOD_DRIVE):
2545 dhd_sdiod_drive_strength = int_val;
2546 dhdsdio_sdiod_drive_strength_init(bus,
2547 dhd_sdiod_drive_strength);
2548 break;
2549
2550 case IOV_SVAL(IOV_DOWNLOAD):
2551 bcmerror = dhdsdio_download_state(bus, bool_val);
2552 break;
2553
2554 case IOV_SVAL(IOV_VARS):
2555 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2556 break;
2557
2558 case IOV_GVAL(IOV_READAHEAD):
2559 int_val = (s32) dhd_readahead;
2560 memcpy(arg, &int_val, val_size);
2561 break;
2562
2563 case IOV_SVAL(IOV_READAHEAD):
2564 if (bool_val && !dhd_readahead)
2565 bus->nextlen = 0;
2566 dhd_readahead = bool_val;
2567 break;
2568
2569 case IOV_GVAL(IOV_SDRXCHAIN):
2570 int_val = (s32) bus->use_rxchain;
2571 memcpy(arg, &int_val, val_size);
2572 break;
2573
2574 case IOV_SVAL(IOV_SDRXCHAIN):
2575 if (bool_val && !bus->sd_rxchain)
2576 bcmerror = -ENOTSUPP;
2577 else
2578 bus->use_rxchain = bool_val;
2579 break;
2580 case IOV_GVAL(IOV_ALIGNCTL):
2581 int_val = (s32) dhd_alignctl;
2582 memcpy(arg, &int_val, val_size);
2583 break;
2584
2585 case IOV_SVAL(IOV_ALIGNCTL):
2586 dhd_alignctl = bool_val;
2587 break;
2588
2589 case IOV_GVAL(IOV_SDALIGN):
2590 int_val = DHD_SDALIGN;
2591 memcpy(arg, &int_val, val_size);
2592 break;
2593
2594 #ifdef DHD_DEBUG
2595 case IOV_GVAL(IOV_VARS):
2596 if (bus->varsz < (uint) len)
2597 memcpy(arg, bus->vars, bus->varsz);
2598 else
2599 bcmerror = -EOVERFLOW;
2600 break;
2601 #endif /* DHD_DEBUG */
2602
2603 #ifdef DHD_DEBUG
2604 case IOV_GVAL(IOV_SDREG):
2605 {
2606 sdreg_t *sd_ptr;
2607 u32 addr, size;
2608
2609 sd_ptr = (sdreg_t *) params;
2610
2611 addr = (unsigned long)bus->regs + sd_ptr->offset;
2612 size = sd_ptr->func;
2613 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2614 if (bcmsdh_regfail(bus->sdh))
2615 bcmerror = -EIO;
2616 memcpy(arg, &int_val, sizeof(s32));
2617 break;
2618 }
2619
2620 case IOV_SVAL(IOV_SDREG):
2621 {
2622 sdreg_t *sd_ptr;
2623 u32 addr, size;
2624
2625 sd_ptr = (sdreg_t *) params;
2626
2627 addr = (unsigned long)bus->regs + sd_ptr->offset;
2628 size = sd_ptr->func;
2629 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2630 if (bcmsdh_regfail(bus->sdh))
2631 bcmerror = -EIO;
2632 break;
2633 }
2634
2635 /* Same as above, but offset is not backplane
2636 (not SDIO core) */
2637 case IOV_GVAL(IOV_SBREG):
2638 {
2639 sdreg_t sdreg;
2640 u32 addr, size;
2641
2642 memcpy(&sdreg, params, sizeof(sdreg));
2643
2644 addr = SI_ENUM_BASE + sdreg.offset;
2645 size = sdreg.func;
2646 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2647 if (bcmsdh_regfail(bus->sdh))
2648 bcmerror = -EIO;
2649 memcpy(arg, &int_val, sizeof(s32));
2650 break;
2651 }
2652
2653 case IOV_SVAL(IOV_SBREG):
2654 {
2655 sdreg_t sdreg;
2656 u32 addr, size;
2657
2658 memcpy(&sdreg, params, sizeof(sdreg));
2659
2660 addr = SI_ENUM_BASE + sdreg.offset;
2661 size = sdreg.func;
2662 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2663 if (bcmsdh_regfail(bus->sdh))
2664 bcmerror = -EIO;
2665 break;
2666 }
2667
2668 case IOV_GVAL(IOV_SDCIS):
2669 {
2670 *(char *)arg = 0;
2671
2672 strcat(arg, "\nFunc 0\n");
2673 bcmsdh_cis_read(bus->sdh, 0x10,
2674 (u8 *) arg + strlen(arg),
2675 SBSDIO_CIS_SIZE_LIMIT);
2676 strcat(arg, "\nFunc 1\n");
2677 bcmsdh_cis_read(bus->sdh, 0x11,
2678 (u8 *) arg + strlen(arg),
2679 SBSDIO_CIS_SIZE_LIMIT);
2680 strcat(arg, "\nFunc 2\n");
2681 bcmsdh_cis_read(bus->sdh, 0x12,
2682 (u8 *) arg + strlen(arg),
2683 SBSDIO_CIS_SIZE_LIMIT);
2684 break;
2685 }
2686
2687 case IOV_GVAL(IOV_FORCEEVEN):
2688 int_val = (s32) forcealign;
2689 memcpy(arg, &int_val, val_size);
2690 break;
2691
2692 case IOV_SVAL(IOV_FORCEEVEN):
2693 forcealign = bool_val;
2694 break;
2695
2696 case IOV_GVAL(IOV_TXBOUND):
2697 int_val = (s32) dhd_txbound;
2698 memcpy(arg, &int_val, val_size);
2699 break;
2700
2701 case IOV_SVAL(IOV_TXBOUND):
2702 dhd_txbound = (uint) int_val;
2703 break;
2704
2705 case IOV_GVAL(IOV_RXBOUND):
2706 int_val = (s32) dhd_rxbound;
2707 memcpy(arg, &int_val, val_size);
2708 break;
2709
2710 case IOV_SVAL(IOV_RXBOUND):
2711 dhd_rxbound = (uint) int_val;
2712 break;
2713
2714 case IOV_GVAL(IOV_TXMINMAX):
2715 int_val = (s32) dhd_txminmax;
2716 memcpy(arg, &int_val, val_size);
2717 break;
2718
2719 case IOV_SVAL(IOV_TXMINMAX):
2720 dhd_txminmax = (uint) int_val;
2721 break;
2722 #endif /* DHD_DEBUG */
2723
2724 #ifdef SDTEST
2725 case IOV_GVAL(IOV_EXTLOOP):
2726 int_val = (s32) bus->ext_loop;
2727 memcpy(arg, &int_val, val_size);
2728 break;
2729
2730 case IOV_SVAL(IOV_EXTLOOP):
2731 bus->ext_loop = bool_val;
2732 break;
2733
2734 case IOV_GVAL(IOV_PKTGEN):
2735 bcmerror = dhdsdio_pktgen_get(bus, arg);
2736 break;
2737
2738 case IOV_SVAL(IOV_PKTGEN):
2739 bcmerror = dhdsdio_pktgen_set(bus, arg);
2740 break;
2741 #endif /* SDTEST */
2742
2743 case IOV_SVAL(IOV_DEVRESET):
2744 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2745 "busstate=%d\n",
2746 __func__, bool_val, bus->dhd->dongle_reset,
2747 bus->dhd->busstate));
2748
2749 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2750
2751 break;
2752
2753 case IOV_GVAL(IOV_DEVRESET):
2754 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2755
2756 /* Get its status */
2757 int_val = (bool) bus->dhd->dongle_reset;
2758 memcpy(arg, &int_val, val_size);
2759
2760 break;
2761
2762 default:
2763 bcmerror = -ENOTSUPP;
2764 break;
2765 }
2766
2767 exit:
2768 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2769 bus->activity = false;
2770 dhdsdio_clkctl(bus, CLK_NONE, true);
2771 }
2772
2773 dhd_os_sdunlock(bus->dhd);
2774
2775 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2776 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2777
2778 return bcmerror;
2779 }
2780
2781 static int dhdsdio_write_vars(dhd_bus_t *bus)
2782 {
2783 int bcmerror = 0;
2784 u32 varsize;
2785 u32 varaddr;
2786 u8 *vbuffer;
2787 u32 varsizew;
2788 #ifdef DHD_DEBUG
2789 char *nvram_ularray;
2790 #endif /* DHD_DEBUG */
2791
2792 /* Even if there are no vars are to be written, we still
2793 need to set the ramsize. */
2794 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2795 varaddr = (bus->ramsize - 4) - varsize;
2796
2797 if (bus->vars) {
2798 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2799 if (!vbuffer)
2800 return -ENOMEM;
2801
2802 memcpy(vbuffer, bus->vars, bus->varsz);
2803
2804 /* Write the vars list */
2805 bcmerror =
2806 dhdsdio_membytes(bus, true, varaddr, vbuffer, varsize);
2807 #ifdef DHD_DEBUG
2808 /* Verify NVRAM bytes */
2809 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2810 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2811 if (!nvram_ularray)
2812 return -ENOMEM;
2813
2814 /* Upload image to verify downloaded contents. */
2815 memset(nvram_ularray, 0xaa, varsize);
2816
2817 /* Read the vars list to temp buffer for comparison */
2818 bcmerror =
2819 dhdsdio_membytes(bus, false, varaddr, nvram_ularray,
2820 varsize);
2821 if (bcmerror) {
2822 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2823 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2824 }
2825 /* Compare the org NVRAM with the one read from RAM */
2826 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2827 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2828 __func__));
2829 } else
2830 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2831 __func__));
2832
2833 kfree(nvram_ularray);
2834 #endif /* DHD_DEBUG */
2835
2836 kfree(vbuffer);
2837 }
2838
2839 /* adjust to the user specified RAM */
2840 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2841 bus->orig_ramsize, bus->ramsize));
2842 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2843 varsize = ((bus->orig_ramsize - 4) - varaddr);
2844
2845 /*
2846 * Determine the length token:
2847 * Varsize, converted to words, in lower 16-bits, checksum
2848 * in upper 16-bits.
2849 */
2850 if (bcmerror) {
2851 varsizew = 0;
2852 } else {
2853 varsizew = varsize / 4;
2854 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2855 varsizew = cpu_to_le32(varsizew);
2856 }
2857
2858 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2859 varsizew));
2860
2861 /* Write the length token to the last word */
2862 bcmerror = dhdsdio_membytes(bus, true, (bus->orig_ramsize - 4),
2863 (u8 *)&varsizew, 4);
2864
2865 return bcmerror;
2866 }
2867
2868 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2869 {
2870 uint retries;
2871 u32 regdata;
2872 int bcmerror = 0;
2873
2874 /* To enter download state, disable ARM and reset SOCRAM.
2875 * To exit download state, simply reset ARM (default is RAM boot).
2876 */
2877 if (enter) {
2878 bus->alp_only = true;
2879
2880 dhdsdio_chip_disablecore(bus->sdh, bus->ci->armcorebase);
2881
2882 dhdsdio_chip_resetcore(bus->sdh, bus->ci->ramcorebase);
2883
2884 /* Clear the top bit of memory */
2885 if (bus->ramsize) {
2886 u32 zeros = 0;
2887 dhdsdio_membytes(bus, true, bus->ramsize - 4,
2888 (u8 *)&zeros, 4);
2889 }
2890 } else {
2891 regdata = bcmsdh_reg_read(bus->sdh,
2892 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
2893 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
2894 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
2895 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
2896 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2897 __func__));
2898 bcmerror = -EBADE;
2899 goto fail;
2900 }
2901
2902 bcmerror = dhdsdio_write_vars(bus);
2903 if (bcmerror) {
2904 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2905 bcmerror = 0;
2906 }
2907
2908 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2909
2910 dhdsdio_chip_resetcore(bus->sdh, bus->ci->armcorebase);
2911
2912 /* Allow HT Clock now that the ARM is running. */
2913 bus->alp_only = false;
2914
2915 bus->dhd->busstate = DHD_BUS_LOAD;
2916 }
2917 fail:
2918 return bcmerror;
2919 }
2920
2921 int
2922 dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2923 void *params, int plen, void *arg, int len, bool set)
2924 {
2925 dhd_bus_t *bus = dhdp->bus;
2926 const struct brcmu_iovar *vi = NULL;
2927 int bcmerror = 0;
2928 int val_size;
2929 u32 actionid;
2930
2931 DHD_TRACE(("%s: Enter\n", __func__));
2932
2933 ASSERT(name);
2934 ASSERT(len >= 0);
2935
2936 /* Get MUST have return space */
2937 ASSERT(set || (arg && len));
2938
2939 /* Set does NOT take qualifiers */
2940 ASSERT(!set || (!params && !plen));
2941
2942 /* Look up var locally; if not found pass to host driver */
2943 vi = brcmu_iovar_lookup(dhdsdio_iovars, name);
2944 if (vi == NULL) {
2945 dhd_os_sdlock(bus->dhd);
2946
2947 BUS_WAKE(bus);
2948
2949 /* Turn on clock in case SD command needs backplane */
2950 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2951
2952 bcmerror =
2953 bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2954 set);
2955
2956 /* Similar check for blocksize change */
2957 if (set && strcmp(name, "sd_blocksize") == 0) {
2958 s32 fnum = 2;
2959 if (bcmsdh_iovar_op
2960 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2961 &bus->blocksize, sizeof(s32),
2962 false) != 0) {
2963 bus->blocksize = 0;
2964 DHD_ERROR(("%s: fail on %s get\n", __func__,
2965 "sd_blocksize"));
2966 } else {
2967 DHD_INFO(("%s: noted %s update, value now %d\n",
2968 __func__, "sd_blocksize",
2969 bus->blocksize));
2970 }
2971 }
2972 bus->roundup = min(max_roundup, bus->blocksize);
2973
2974 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2975 bus->activity = false;
2976 dhdsdio_clkctl(bus, CLK_NONE, true);
2977 }
2978
2979 dhd_os_sdunlock(bus->dhd);
2980 goto exit;
2981 }
2982
2983 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2984 name, (set ? "set" : "get"), len, plen));
2985
2986 /* set up 'params' pointer in case this is a set command so that
2987 * the convenience int and bool code can be common to set and get
2988 */
2989 if (params == NULL) {
2990 params = arg;
2991 plen = len;
2992 }
2993
2994 if (vi->type == IOVT_VOID)
2995 val_size = 0;
2996 else if (vi->type == IOVT_BUFFER)
2997 val_size = len;
2998 else
2999 /* all other types are integer sized */
3000 val_size = sizeof(int);
3001
3002 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
3003 bcmerror =
3004 dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
3005 val_size);
3006
3007 exit:
3008 return bcmerror;
3009 }
3010
3011 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
3012 {
3013 u32 local_hostintmask;
3014 u8 saveclk;
3015 uint retries;
3016 int err;
3017
3018 DHD_TRACE(("%s: Enter\n", __func__));
3019
3020 if (enforce_mutex)
3021 dhd_os_sdlock(bus->dhd);
3022
3023 BUS_WAKE(bus);
3024
3025 /* Enable clock for device interrupts */
3026 dhdsdio_clkctl(bus, CLK_AVAIL, false);
3027
3028 /* Disable and clear interrupts at the chip level also */
3029 W_SDREG(0, &bus->regs->hostintmask, retries);
3030 local_hostintmask = bus->hostintmask;
3031 bus->hostintmask = 0;
3032
3033 /* Change our idea of bus state */
3034 bus->dhd->busstate = DHD_BUS_DOWN;
3035
3036 /* Force clocks on backplane to be sure F2 interrupt propagates */
3037 saveclk =
3038 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3039 &err);
3040 if (!err) {
3041 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3042 (saveclk | SBSDIO_FORCE_HT), &err);
3043 }
3044 if (err) {
3045 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3046 __func__, err));
3047 }
3048
3049 /* Turn off the bus (F2), free any pending packets */
3050 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3051 bcmsdh_intr_disable(bus->sdh);
3052 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3053 SDIO_FUNC_ENABLE_1, NULL);
3054
3055 /* Clear any pending interrupts now that F2 is disabled */
3056 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
3057
3058 /* Turn off the backplane clock (only) */
3059 dhdsdio_clkctl(bus, CLK_SDONLY, false);
3060
3061 /* Clear the data packet queues */
3062 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3063
3064 /* Clear any held glomming stuff */
3065 if (bus->glomd)
3066 brcmu_pkt_buf_free_skb(bus->glomd);
3067
3068 if (bus->glom)
3069 brcmu_pkt_buf_free_skb(bus->glom);
3070
3071 bus->glom = bus->glomd = NULL;
3072
3073 /* Clear rx control and wake any waiters */
3074 bus->rxlen = 0;
3075 dhd_os_ioctl_resp_wake(bus->dhd);
3076
3077 /* Reset some F2 state stuff */
3078 bus->rxskip = false;
3079 bus->tx_seq = bus->rx_seq = 0;
3080
3081 if (enforce_mutex)
3082 dhd_os_sdunlock(bus->dhd);
3083 }
3084
3085 int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
3086 {
3087 dhd_bus_t *bus = dhdp->bus;
3088 dhd_timeout_t tmo;
3089 uint retries = 0;
3090 u8 ready, enable;
3091 int err, ret = 0;
3092 u8 saveclk;
3093
3094 DHD_TRACE(("%s: Enter\n", __func__));
3095
3096 ASSERT(bus->dhd);
3097 if (!bus->dhd)
3098 return 0;
3099
3100 if (enforce_mutex)
3101 dhd_os_sdlock(bus->dhd);
3102
3103 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3104 dhdsdio_clkctl(bus, CLK_AVAIL, false);
3105 if (bus->clkstate != CLK_AVAIL)
3106 goto exit;
3107
3108 /* Force clocks on backplane to be sure F2 interrupt propagates */
3109 saveclk =
3110 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3111 &err);
3112 if (!err) {
3113 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3114 (saveclk | SBSDIO_FORCE_HT), &err);
3115 }
3116 if (err) {
3117 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3118 __func__, err));
3119 goto exit;
3120 }
3121
3122 /* Enable function 2 (frame transfers) */
3123 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
3124 &bus->regs->tosbmailboxdata, retries);
3125 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3126
3127 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, enable, NULL);
3128
3129 /* Give the dongle some time to do its thing and set IOR2 */
3130 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
3131
3132 ready = 0;
3133 while (ready != enable && !dhd_timeout_expired(&tmo))
3134 ready =
3135 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IORx,
3136 NULL);
3137
3138 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
3139 __func__, enable, ready, tmo.elapsed));
3140
3141 /* If F2 successfully enabled, set core and enable interrupts */
3142 if (ready == enable) {
3143 /* Set up the interrupt mask and enable interrupts */
3144 bus->hostintmask = HOSTINTMASK;
3145 W_SDREG(bus->hostintmask,
3146 (unsigned int *)CORE_BUS_REG(bus->ci->buscorebase,
3147 hostintmask), retries);
3148
3149 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
3150 (u8) watermark, &err);
3151
3152 /* Set bus state according to enable result */
3153 dhdp->busstate = DHD_BUS_DATA;
3154
3155 /* bcmsdh_intr_unmask(bus->sdh); */
3156
3157 bus->intdis = false;
3158 if (bus->intr) {
3159 DHD_INTR(("%s: enable SDIO device interrupts\n",
3160 __func__));
3161 bcmsdh_intr_enable(bus->sdh);
3162 } else {
3163 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3164 bcmsdh_intr_disable(bus->sdh);
3165 }
3166
3167 }
3168
3169 else {
3170 /* Disable F2 again */
3171 enable = SDIO_FUNC_ENABLE_1;
3172 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, enable,
3173 NULL);
3174 }
3175
3176 /* Restore previous clock setting */
3177 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3178 saveclk, &err);
3179
3180 /* If we didn't come up, turn off backplane clock */
3181 if (dhdp->busstate != DHD_BUS_DATA)
3182 dhdsdio_clkctl(bus, CLK_NONE, false);
3183
3184 exit:
3185 if (enforce_mutex)
3186 dhd_os_sdunlock(bus->dhd);
3187
3188 return ret;
3189 }
3190
3191 static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3192 {
3193 bcmsdh_info_t *sdh = bus->sdh;
3194 struct sdpcmd_regs *regs = bus->regs;
3195 uint retries = 0;
3196 u16 lastrbc;
3197 u8 hi, lo;
3198 int err;
3199
3200 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3201 (abort ? "abort command, " : ""),
3202 (rtx ? ", send NAK" : "")));
3203
3204 if (abort)
3205 bcmsdh_abort(sdh, SDIO_FUNC_2);
3206
3207 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3208 &err);
3209 bus->f1regdata++;
3210
3211 /* Wait until the packet has been flushed (device/FIFO stable) */
3212 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3213 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3214 NULL);
3215 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3216 NULL);
3217 bus->f1regdata += 2;
3218
3219 if ((hi == 0) && (lo == 0))
3220 break;
3221
3222 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3223 DHD_ERROR(("%s: count growing: last 0x%04x now "
3224 "0x%04x\n",
3225 __func__, lastrbc, ((hi << 8) + lo)));
3226 }
3227 lastrbc = (hi << 8) + lo;
3228 }
3229
3230 if (!retries) {
3231 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3232 __func__, lastrbc));
3233 } else {
3234 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3235 (0xffff - retries)));
3236 }
3237
3238 if (rtx) {
3239 bus->rxrtx++;
3240 W_SDREG(SMB_NAK, &regs->tosbmailbox, retries);
3241 bus->f1regdata++;
3242 if (retries <= retry_limit)
3243 bus->rxskip = true;
3244 }
3245
3246 /* Clear partial in any case */
3247 bus->nextlen = 0;
3248
3249 /* If we can't reach the device, signal failure */
3250 if (err || bcmsdh_regfail(sdh))
3251 bus->dhd->busstate = DHD_BUS_DOWN;
3252 }
3253
3254 static void
3255 dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3256 {
3257 bcmsdh_info_t *sdh = bus->sdh;
3258 uint rdlen, pad;
3259
3260 int sdret;
3261
3262 DHD_TRACE(("%s: Enter\n", __func__));
3263
3264 /* Control data already received in aligned rxctl */
3265 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3266 goto gotpkt;
3267
3268 ASSERT(bus->rxbuf);
3269 /* Set rxctl for frame (w/optional alignment) */
3270 bus->rxctl = bus->rxbuf;
3271 if (dhd_alignctl) {
3272 bus->rxctl += firstread;
3273 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3274 if (pad)
3275 bus->rxctl += (DHD_SDALIGN - pad);
3276 bus->rxctl -= firstread;
3277 }
3278 ASSERT(bus->rxctl >= bus->rxbuf);
3279
3280 /* Copy the already-read portion over */
3281 memcpy(bus->rxctl, hdr, firstread);
3282 if (len <= firstread)
3283 goto gotpkt;
3284
3285 /* Copy the full data pkt in gSPI case and process ioctl. */
3286 if (bus->bus == SPI_BUS) {
3287 memcpy(bus->rxctl, hdr, len);
3288 goto gotpkt;
3289 }
3290
3291 /* Raise rdlen to next SDIO block to avoid tail command */
3292 rdlen = len - firstread;
3293 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3294 pad = bus->blocksize - (rdlen % bus->blocksize);
3295 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3296 ((len + pad) < bus->dhd->maxctl))
3297 rdlen += pad;
3298 } else if (rdlen % DHD_SDALIGN) {
3299 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3300 }
3301
3302 /* Satisfy length-alignment requirements */
3303 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3304 rdlen = roundup(rdlen, ALIGNMENT);
3305
3306 /* Drop if the read is too big or it exceeds our maximum */
3307 if ((rdlen + firstread) > bus->dhd->maxctl) {
3308 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3309 __func__, rdlen, bus->dhd->maxctl));
3310 bus->dhd->rx_errors++;
3311 dhdsdio_rxfail(bus, false, false);
3312 goto done;
3313 }
3314
3315 if ((len - doff) > bus->dhd->maxctl) {
3316 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3317 "%d-byte limit\n",
3318 __func__, len, (len - doff), bus->dhd->maxctl));
3319 bus->dhd->rx_errors++;
3320 bus->rx_toolong++;
3321 dhdsdio_rxfail(bus, false, false);
3322 goto done;
3323 }
3324
3325 /* Read remainder of frame body into the rxctl buffer */
3326 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3327 F2SYNC, (bus->rxctl + firstread), rdlen,
3328 NULL, NULL, NULL);
3329 bus->f2rxdata++;
3330 ASSERT(sdret != -BCME_PENDING);
3331
3332 /* Control frame failures need retransmission */
3333 if (sdret < 0) {
3334 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3335 __func__, rdlen, sdret));
3336 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3337 dhdsdio_rxfail(bus, true, true);
3338 goto done;
3339 }
3340
3341 gotpkt:
3342
3343 #ifdef DHD_DEBUG
3344 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
3345 printk(KERN_DEBUG "RxCtrl:\n");
3346 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
3347 }
3348 #endif
3349
3350 /* Point to valid data and indicate its length */
3351 bus->rxctl += doff;
3352 bus->rxlen = len - doff;
3353
3354 done:
3355 /* Awake any waiters */
3356 dhd_os_ioctl_resp_wake(bus->dhd);
3357 }
3358
3359 static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
3360 {
3361 u16 dlen, totlen;
3362 u8 *dptr, num = 0;
3363
3364 u16 sublen, check;
3365 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3366
3367 int errcode;
3368 u8 chan, seq, doff, sfdoff;
3369 u8 txmax;
3370
3371 int ifidx = 0;
3372 bool usechain = bus->use_rxchain;
3373
3374 /* If packets, issue read(s) and send up packet chain */
3375 /* Return sequence numbers consumed? */
3376
3377 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3378 bus->glom));
3379
3380 /* If there's a descriptor, generate the packet chain */
3381 if (bus->glomd) {
3382 dhd_os_sdlock_rxq(bus->dhd);
3383
3384 pfirst = plast = pnext = NULL;
3385 dlen = (u16) (bus->glomd->len);
3386 dptr = bus->glomd->data;
3387 if (!dlen || (dlen & 1)) {
3388 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3389 __func__, dlen));
3390 dlen = 0;
3391 }
3392
3393 for (totlen = num = 0; dlen; num++) {
3394 /* Get (and move past) next length */
3395 sublen = get_unaligned_le16(dptr);
3396 dlen -= sizeof(u16);
3397 dptr += sizeof(u16);
3398 if ((sublen < SDPCM_HDRLEN) ||
3399 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3400 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3401 __func__, num, sublen));
3402 pnext = NULL;
3403 break;
3404 }
3405 if (sublen % DHD_SDALIGN) {
3406 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3407 __func__, sublen, DHD_SDALIGN));
3408 usechain = false;
3409 }
3410 totlen += sublen;
3411
3412 /* For last frame, adjust read len so total
3413 is a block multiple */
3414 if (!dlen) {
3415 sublen +=
3416 (roundup(totlen, bus->blocksize) - totlen);
3417 totlen = roundup(totlen, bus->blocksize);
3418 }
3419
3420 /* Allocate/chain packet for next subframe */
3421 pnext = brcmu_pkt_buf_get_skb(sublen + DHD_SDALIGN);
3422 if (pnext == NULL) {
3423 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed, "
3424 "num %d len %d\n", __func__,
3425 num, sublen));
3426 break;
3427 }
3428 ASSERT(!(pnext->prev));
3429 if (!pfirst) {
3430 ASSERT(!plast);
3431 pfirst = plast = pnext;
3432 } else {
3433 ASSERT(plast);
3434 plast->next = pnext;
3435 plast = pnext;
3436 }
3437
3438 /* Adhere to start alignment requirements */
3439 PKTALIGN(pnext, sublen, DHD_SDALIGN);
3440 }
3441
3442 /* If all allocations succeeded, save packet chain
3443 in bus structure */
3444 if (pnext) {
3445 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3446 "subframes\n", __func__, totlen, num));
3447 if (DHD_GLOM_ON() && bus->nextlen) {
3448 if (totlen != bus->nextlen) {
3449 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3450 __func__, bus->nextlen,
3451 totlen, rxseq));
3452 }
3453 }
3454 bus->glom = pfirst;
3455 pfirst = pnext = NULL;
3456 } else {
3457 if (pfirst)
3458 brcmu_pkt_buf_free_skb(pfirst);
3459 bus->glom = NULL;
3460 num = 0;
3461 }
3462
3463 /* Done with descriptor packet */
3464 brcmu_pkt_buf_free_skb(bus->glomd);
3465 bus->glomd = NULL;
3466 bus->nextlen = 0;
3467
3468 dhd_os_sdunlock_rxq(bus->dhd);
3469 }
3470
3471 /* Ok -- either we just generated a packet chain,
3472 or had one from before */
3473 if (bus->glom) {
3474 if (DHD_GLOM_ON()) {
3475 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3476 __func__));
3477 for (pnext = bus->glom; pnext; pnext = pnext->next) {
3478 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3479 pnext, (u8 *) (pnext->data),
3480 pnext->len, pnext->len));
3481 }
3482 }
3483
3484 pfirst = bus->glom;
3485 dlen = (u16) brcmu_pkttotlen(pfirst);
3486
3487 /* Do an SDIO read for the superframe. Configurable iovar to
3488 * read directly into the chained packet, or allocate a large
3489 * packet and and copy into the chain.
3490 */
3491 if (usechain) {
3492 errcode = bcmsdh_recv_buf(bus,
3493 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3494 F2SYNC, (u8 *) pfirst->data, dlen,
3495 pfirst, NULL, NULL);
3496 } else if (bus->dataptr) {
3497 errcode = bcmsdh_recv_buf(bus,
3498 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3499 F2SYNC, bus->dataptr, dlen,
3500 NULL, NULL, NULL);
3501 sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
3502 bus->dataptr);
3503 if (sublen != dlen) {
3504 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3505 __func__, dlen, sublen));
3506 errcode = -1;
3507 }
3508 pnext = NULL;
3509 } else {
3510 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3511 dlen));
3512 errcode = -1;
3513 }
3514 bus->f2rxdata++;
3515 ASSERT(errcode != -BCME_PENDING);
3516
3517 /* On failure, kill the superframe, allow a couple retries */
3518 if (errcode < 0) {
3519 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3520 __func__, dlen, errcode));
3521 bus->dhd->rx_errors++;
3522
3523 if (bus->glomerr++ < 3) {
3524 dhdsdio_rxfail(bus, true, true);
3525 } else {
3526 bus->glomerr = 0;
3527 dhdsdio_rxfail(bus, true, false);
3528 dhd_os_sdlock_rxq(bus->dhd);
3529 brcmu_pkt_buf_free_skb(bus->glom);
3530 dhd_os_sdunlock_rxq(bus->dhd);
3531 bus->rxglomfail++;
3532 bus->glom = NULL;
3533 }
3534 return 0;
3535 }
3536 #ifdef DHD_DEBUG
3537 if (DHD_GLOM_ON()) {
3538 printk(KERN_DEBUG "SUPERFRAME:\n");
3539 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3540 pfirst->data, min_t(int, pfirst->len, 48));
3541 }
3542 #endif
3543
3544 /* Validate the superframe header */
3545 dptr = (u8 *) (pfirst->data);
3546 sublen = get_unaligned_le16(dptr);
3547 check = get_unaligned_le16(dptr + sizeof(u16));
3548
3549 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3550 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3551 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3552 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3553 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3554 __func__, bus->nextlen, seq));
3555 bus->nextlen = 0;
3556 }
3557 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3558 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3559
3560 errcode = 0;
3561 if ((u16)~(sublen ^ check)) {
3562 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3563 "0x%04x/0x%04x\n", __func__, sublen, check));
3564 errcode = -1;
3565 } else if (roundup(sublen, bus->blocksize) != dlen) {
3566 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3567 "0x%04x, expect 0x%04x\n",
3568 __func__, sublen,
3569 roundup(sublen, bus->blocksize), dlen));
3570 errcode = -1;
3571 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3572 SDPCM_GLOM_CHANNEL) {
3573 DHD_ERROR(("%s (superframe): bad channel %d\n",
3574 __func__,
3575 SDPCM_PACKET_CHANNEL(&dptr
3576 [SDPCM_FRAMETAG_LEN])));
3577 errcode = -1;
3578 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3579 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3580 __func__));
3581 errcode = -1;
3582 } else if ((doff < SDPCM_HDRLEN) ||
3583 (doff > (pfirst->len - SDPCM_HDRLEN))) {
3584 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3585 "pkt %d min %d\n",
3586 __func__, doff, sublen,
3587 pfirst->len, SDPCM_HDRLEN));
3588 errcode = -1;
3589 }
3590
3591 /* Check sequence number of superframe SW header */
3592 if (rxseq != seq) {
3593 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3594 __func__, seq, rxseq));
3595 bus->rx_badseq++;
3596 rxseq = seq;
3597 }
3598
3599 /* Check window for sanity */
3600 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3601 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3602 __func__, txmax, bus->tx_seq));
3603 txmax = bus->tx_seq + 2;
3604 }
3605 bus->tx_max = txmax;
3606
3607 /* Remove superframe header, remember offset */
3608 skb_pull(pfirst, doff);
3609 sfdoff = doff;
3610
3611 /* Validate all the subframe headers */
3612 for (num = 0, pnext = pfirst; pnext && !errcode;
3613 num++, pnext = pnext->next) {
3614 dptr = (u8 *) (pnext->data);
3615 dlen = (u16) (pnext->len);
3616 sublen = get_unaligned_le16(dptr);
3617 check = get_unaligned_le16(dptr + sizeof(u16));
3618 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3619 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3620 #ifdef DHD_DEBUG
3621 if (DHD_GLOM_ON()) {
3622 printk(KERN_DEBUG "subframe:\n");
3623 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3624 dptr, 32);
3625 }
3626 #endif
3627
3628 if ((u16)~(sublen ^ check)) {
3629 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3630 "len/check 0x%04x/0x%04x\n",
3631 __func__, num, sublen, check));
3632 errcode = -1;
3633 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3634 DHD_ERROR(("%s (subframe %d): length mismatch: "
3635 "len 0x%04x, expect 0x%04x\n",
3636 __func__, num, sublen, dlen));
3637 errcode = -1;
3638 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3639 (chan != SDPCM_EVENT_CHANNEL)) {
3640 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3641 __func__, num, chan));
3642 errcode = -1;
3643 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3644 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3645 __func__, num, doff, sublen,
3646 SDPCM_HDRLEN));
3647 errcode = -1;
3648 }
3649 }
3650
3651 if (errcode) {
3652 /* Terminate frame on error, request
3653 a couple retries */
3654 if (bus->glomerr++ < 3) {
3655 /* Restore superframe header space */
3656 skb_push(pfirst, sfdoff);
3657 dhdsdio_rxfail(bus, true, true);
3658 } else {
3659 bus->glomerr = 0;
3660 dhdsdio_rxfail(bus, true, false);
3661 dhd_os_sdlock_rxq(bus->dhd);
3662 brcmu_pkt_buf_free_skb(bus->glom);
3663 dhd_os_sdunlock_rxq(bus->dhd);
3664 bus->rxglomfail++;
3665 bus->glom = NULL;
3666 }
3667 bus->nextlen = 0;
3668 return 0;
3669 }
3670
3671 /* Basic SD framing looks ok - process each packet (header) */
3672 save_pfirst = pfirst;
3673 bus->glom = NULL;
3674 plast = NULL;
3675
3676 dhd_os_sdlock_rxq(bus->dhd);
3677 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3678 pnext = pfirst->next;
3679 pfirst->next = NULL;
3680
3681 dptr = (u8 *) (pfirst->data);
3682 sublen = get_unaligned_le16(dptr);
3683 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3684 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3685 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3686
3687 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3688 "chan %d seq %d\n",
3689 __func__, num, pfirst, pfirst->data,
3690 pfirst->len, sublen, chan, seq));
3691
3692 ASSERT((chan == SDPCM_DATA_CHANNEL)
3693 || (chan == SDPCM_EVENT_CHANNEL));
3694
3695 if (rxseq != seq) {
3696 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3697 __func__, seq, rxseq));
3698 bus->rx_badseq++;
3699 rxseq = seq;
3700 }
3701 #ifdef DHD_DEBUG
3702 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3703 printk(KERN_DEBUG "Rx Subframe Data:\n");
3704 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3705 dptr, dlen);
3706 }
3707 #endif
3708
3709 __skb_trim(pfirst, sublen);
3710 skb_pull(pfirst, doff);
3711
3712 if (pfirst->len == 0) {
3713 brcmu_pkt_buf_free_skb(pfirst);
3714 if (plast) {
3715 plast->next = pnext;
3716 } else {
3717 ASSERT(save_pfirst == pfirst);
3718 save_pfirst = pnext;
3719 }
3720 continue;
3721 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3722 0) {
3723 DHD_ERROR(("%s: rx protocol error\n",
3724 __func__));
3725 bus->dhd->rx_errors++;
3726 brcmu_pkt_buf_free_skb(pfirst);
3727 if (plast) {
3728 plast->next = pnext;
3729 } else {
3730 ASSERT(save_pfirst == pfirst);
3731 save_pfirst = pnext;
3732 }
3733 continue;
3734 }
3735
3736 /* this packet will go up, link back into
3737 chain and count it */
3738 pfirst->next = pnext;
3739 plast = pfirst;
3740 num++;
3741
3742 #ifdef DHD_DEBUG
3743 if (DHD_GLOM_ON()) {
3744 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3745 "nxt/lnk %p/%p\n",
3746 __func__, num, pfirst, pfirst->data,
3747 pfirst->len, pfirst->next,
3748 pfirst->prev));
3749 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3750 pfirst->data,
3751 min_t(int, pfirst->len, 32));
3752 }
3753 #endif /* DHD_DEBUG */
3754 }
3755 dhd_os_sdunlock_rxq(bus->dhd);
3756 if (num) {
3757 dhd_os_sdunlock(bus->dhd);
3758 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3759 dhd_os_sdlock(bus->dhd);
3760 }
3761
3762 bus->rxglomframes++;
3763 bus->rxglompkts += num;
3764 }
3765 return num;
3766 }
3767
3768 /* Return true if there may be more frames to read */
3769 static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3770 {
3771 bcmsdh_info_t *sdh = bus->sdh;
3772
3773 u16 len, check; /* Extracted hardware header fields */
3774 u8 chan, seq, doff; /* Extracted software header fields */
3775 u8 fcbits; /* Extracted fcbits from software header */
3776
3777 struct sk_buff *pkt; /* Packet for event or data frames */
3778 u16 pad; /* Number of pad bytes to read */
3779 u16 rdlen; /* Total number of bytes to read */
3780 u8 rxseq; /* Next sequence number to expect */
3781 uint rxleft = 0; /* Remaining number of frames allowed */
3782 int sdret; /* Return code from bcmsdh calls */
3783 u8 txmax; /* Maximum tx sequence offered */
3784 bool len_consistent; /* Result of comparing readahead len and
3785 len from hw-hdr */
3786 u8 *rxbuf;
3787 int ifidx = 0;
3788 uint rxcount = 0; /* Total frames read */
3789
3790 #if defined(DHD_DEBUG) || defined(SDTEST)
3791 bool sdtest = false; /* To limit message spew from test mode */
3792 #endif
3793
3794 DHD_TRACE(("%s: Enter\n", __func__));
3795
3796 ASSERT(maxframes);
3797
3798 #ifdef SDTEST
3799 /* Allow pktgen to override maxframes */
3800 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3801 maxframes = bus->pktgen_count;
3802 sdtest = true;
3803 }
3804 #endif
3805
3806 /* Not finished unless we encounter no more frames indication */
3807 *finished = false;
3808
3809 for (rxseq = bus->rx_seq, rxleft = maxframes;
3810 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3811 rxseq++, rxleft--) {
3812
3813 /* Handle glomming separately */
3814 if (bus->glom || bus->glomd) {
3815 u8 cnt;
3816 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3817 __func__, bus->glomd, bus->glom));
3818 cnt = dhdsdio_rxglom(bus, rxseq);
3819 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3820 rxseq += cnt - 1;
3821 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3822 continue;
3823 }
3824
3825 /* Try doing single read if we can */
3826 if (dhd_readahead && bus->nextlen) {
3827 u16 nextlen = bus->nextlen;
3828 bus->nextlen = 0;
3829
3830 if (bus->bus == SPI_BUS) {
3831 rdlen = len = nextlen;
3832 } else {
3833 rdlen = len = nextlen << 4;
3834
3835 /* Pad read to blocksize for efficiency */
3836 if (bus->roundup && bus->blocksize
3837 && (rdlen > bus->blocksize)) {
3838 pad =
3839 bus->blocksize -
3840 (rdlen % bus->blocksize);
3841 if ((pad <= bus->roundup)
3842 && (pad < bus->blocksize)
3843 && ((rdlen + pad + firstread) <
3844 MAX_RX_DATASZ))
3845 rdlen += pad;
3846 } else if (rdlen % DHD_SDALIGN) {
3847 rdlen +=
3848 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3849 }
3850 }
3851
3852 /* We use bus->rxctl buffer in WinXP for initial
3853 * control pkt receives.
3854 * Later we use buffer-poll for data as well
3855 * as control packets.
3856 * This is required because dhd receives full
3857 * frame in gSPI unlike SDIO.
3858 * After the frame is received we have to
3859 * distinguish whether it is data
3860 * or non-data frame.
3861 */
3862 /* Allocate a packet buffer */
3863 dhd_os_sdlock_rxq(bus->dhd);
3864 pkt = brcmu_pkt_buf_get_skb(rdlen + DHD_SDALIGN);
3865 if (!pkt) {
3866 if (bus->bus == SPI_BUS) {
3867 bus->usebufpool = false;
3868 bus->rxctl = bus->rxbuf;
3869 if (dhd_alignctl) {
3870 bus->rxctl += firstread;
3871 pad = ((unsigned long)bus->rxctl %
3872 DHD_SDALIGN);
3873 if (pad)
3874 bus->rxctl +=
3875 (DHD_SDALIGN - pad);
3876 bus->rxctl -= firstread;
3877 }
3878 ASSERT(bus->rxctl >= bus->rxbuf);
3879 rxbuf = bus->rxctl;
3880 /* Read the entire frame */
3881 sdret = bcmsdh_recv_buf(bus,
3882 bcmsdh_cur_sbwad(sdh),
3883 SDIO_FUNC_2, F2SYNC,
3884 rxbuf, rdlen,
3885 NULL, NULL, NULL);
3886 bus->f2rxdata++;
3887 ASSERT(sdret != -BCME_PENDING);
3888
3889 /* Control frame failures need
3890 retransmission */
3891 if (sdret < 0) {
3892 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3893 __func__,
3894 rdlen, sdret));
3895 /* dhd.rx_ctlerrs is higher */
3896 bus->rxc_errors++;
3897 dhd_os_sdunlock_rxq(bus->dhd);
3898 dhdsdio_rxfail(bus, true,
3899 (bus->bus ==
3900 SPI_BUS) ? false
3901 : true);
3902 continue;
3903 }
3904 } else {
3905 /* Give up on data,
3906 request rtx of events */
3907 DHD_ERROR(("%s (nextlen): "
3908 "brcmu_pkt_buf_get_skb "
3909 "failed:"
3910 " len %d rdlen %d expected"
3911 " rxseq %d\n", __func__,
3912 len, rdlen, rxseq));
3913 /* Just go try again w/normal
3914 header read */
3915 dhd_os_sdunlock_rxq(bus->dhd);
3916 continue;
3917 }
3918 } else {
3919 if (bus->bus == SPI_BUS)
3920 bus->usebufpool = true;
3921
3922 ASSERT(!(pkt->prev));
3923 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
3924 rxbuf = (u8 *) (pkt->data);
3925 /* Read the entire frame */
3926 sdret = bcmsdh_recv_buf(bus,
3927 bcmsdh_cur_sbwad(sdh),
3928 SDIO_FUNC_2, F2SYNC,
3929 rxbuf, rdlen,
3930 pkt, NULL, NULL);
3931 bus->f2rxdata++;
3932 ASSERT(sdret != -BCME_PENDING);
3933
3934 if (sdret < 0) {
3935 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3936 __func__, rdlen, sdret));
3937 brcmu_pkt_buf_free_skb(pkt);
3938 bus->dhd->rx_errors++;
3939 dhd_os_sdunlock_rxq(bus->dhd);
3940 /* Force retry w/normal header read.
3941 * Don't attempt NAK for
3942 * gSPI
3943 */
3944 dhdsdio_rxfail(bus, true,
3945 (bus->bus ==
3946 SPI_BUS) ? false :
3947 true);
3948 continue;
3949 }
3950 }
3951 dhd_os_sdunlock_rxq(bus->dhd);
3952
3953 /* Now check the header */
3954 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3955
3956 /* Extract hardware header fields */
3957 len = get_unaligned_le16(bus->rxhdr);
3958 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3959
3960 /* All zeros means readahead info was bad */
3961 if (!(len | check)) {
3962 DHD_INFO(("%s (nextlen): read zeros in HW "
3963 "header???\n", __func__));
3964 dhdsdio_pktfree2(bus, pkt);
3965 continue;
3966 }
3967
3968 /* Validate check bytes */
3969 if ((u16)~(len ^ check)) {
3970 DHD_ERROR(("%s (nextlen): HW hdr error:"
3971 " nextlen/len/check"
3972 " 0x%04x/0x%04x/0x%04x\n",
3973 __func__, nextlen, len, check));
3974 bus->rx_badhdr++;
3975 dhdsdio_rxfail(bus, false, false);
3976 dhdsdio_pktfree2(bus, pkt);
3977 continue;
3978 }
3979
3980 /* Validate frame length */
3981 if (len < SDPCM_HDRLEN) {
3982 DHD_ERROR(("%s (nextlen): HW hdr length "
3983 "invalid: %d\n", __func__, len));
3984 dhdsdio_pktfree2(bus, pkt);
3985 continue;
3986 }
3987
3988 /* Check for consistency withreadahead info */
3989 len_consistent = (nextlen != (roundup(len, 16) >> 4));
3990 if (len_consistent) {
3991 /* Mismatch, force retry w/normal
3992 header (may be >4K) */
3993 DHD_ERROR(("%s (nextlen): mismatch, "
3994 "nextlen %d len %d rnd %d; "
3995 "expected rxseq %d\n",
3996 __func__, nextlen,
3997 len, roundup(len, 16), rxseq));
3998 dhdsdio_rxfail(bus, true, (bus->bus != SPI_BUS));
3999 dhdsdio_pktfree2(bus, pkt);
4000 continue;
4001 }
4002
4003 /* Extract software header fields */
4004 chan = SDPCM_PACKET_CHANNEL(
4005 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4006 seq = SDPCM_PACKET_SEQUENCE(
4007 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4008 doff = SDPCM_DOFFSET_VALUE(
4009 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4010 txmax = SDPCM_WINDOW_VALUE(
4011 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4012
4013 bus->nextlen =
4014 bus->rxhdr[SDPCM_FRAMETAG_LEN +
4015 SDPCM_NEXTLEN_OFFSET];
4016 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4017 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
4018 __func__, bus->nextlen, seq));
4019 bus->nextlen = 0;
4020 }
4021
4022 bus->dhd->rx_readahead_cnt++;
4023
4024 /* Handle Flow Control */
4025 fcbits = SDPCM_FCMASK_VALUE(
4026 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4027
4028 if (bus->flowcontrol != fcbits) {
4029 if (~bus->flowcontrol & fcbits)
4030 bus->fc_xoff++;
4031
4032 if (bus->flowcontrol & ~fcbits)
4033 bus->fc_xon++;
4034
4035 bus->fc_rcvd++;
4036 bus->flowcontrol = fcbits;
4037 }
4038
4039 /* Check and update sequence number */
4040 if (rxseq != seq) {
4041 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
4042 "%d\n", __func__, seq, rxseq));
4043 bus->rx_badseq++;
4044 rxseq = seq;
4045 }
4046
4047 /* Check window for sanity */
4048 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4049 DHD_ERROR(("%s: got unlikely tx max %d with "
4050 "tx_seq %d\n",
4051 __func__, txmax, bus->tx_seq));
4052 txmax = bus->tx_seq + 2;
4053 }
4054 bus->tx_max = txmax;
4055
4056 #ifdef DHD_DEBUG
4057 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4058 printk(KERN_DEBUG "Rx Data:\n");
4059 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4060 rxbuf, len);
4061 } else if (DHD_HDRS_ON()) {
4062 printk(KERN_DEBUG "RxHdr:\n");
4063 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4064 bus->rxhdr, SDPCM_HDRLEN);
4065 }
4066 #endif
4067
4068 if (chan == SDPCM_CONTROL_CHANNEL) {
4069 if (bus->bus == SPI_BUS) {
4070 dhdsdio_read_control(bus, rxbuf, len,
4071 doff);
4072 } else {
4073 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
4074 __func__, seq));
4075 /* Force retry w/normal header read */
4076 bus->nextlen = 0;
4077 dhdsdio_rxfail(bus, false, true);
4078 }
4079 dhdsdio_pktfree2(bus, pkt);
4080 continue;
4081 }
4082
4083 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
4084 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
4085 len, chan));
4086 continue;
4087 }
4088
4089 /* Validate data offset */
4090 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4091 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
4092 __func__, doff, len, SDPCM_HDRLEN));
4093 dhdsdio_rxfail(bus, false, false);
4094 dhdsdio_pktfree2(bus, pkt);
4095 continue;
4096 }
4097
4098 /* All done with this one -- now deliver the packet */
4099 goto deliver;
4100 }
4101 /* gSPI frames should not be handled in fractions */
4102 if (bus->bus == SPI_BUS)
4103 break;
4104
4105 /* Read frame header (hardware and software) */
4106 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh),
4107 SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
4108 NULL, NULL, NULL);
4109 bus->f2rxhdrs++;
4110 ASSERT(sdret != -BCME_PENDING);
4111
4112 if (sdret < 0) {
4113 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
4114 sdret));
4115 bus->rx_hdrfail++;
4116 dhdsdio_rxfail(bus, true, true);
4117 continue;
4118 }
4119 #ifdef DHD_DEBUG
4120 if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
4121 printk(KERN_DEBUG "RxHdr:\n");
4122 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4123 bus->rxhdr, SDPCM_HDRLEN);
4124 }
4125 #endif
4126
4127 /* Extract hardware header fields */
4128 len = get_unaligned_le16(bus->rxhdr);
4129 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
4130
4131 /* All zeros means no more frames */
4132 if (!(len | check)) {
4133 *finished = true;
4134 break;
4135 }
4136
4137 /* Validate check bytes */
4138 if ((u16) ~(len ^ check)) {
4139 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
4140 __func__, len, check));
4141 bus->rx_badhdr++;
4142 dhdsdio_rxfail(bus, false, false);
4143 continue;
4144 }
4145
4146 /* Validate frame length */
4147 if (len < SDPCM_HDRLEN) {
4148 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
4149 __func__, len));
4150 continue;
4151 }
4152
4153 /* Extract software header fields */
4154 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4155 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4156 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4157 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4158
4159 /* Validate data offset */
4160 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4161 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
4162 "seq %d\n",
4163 __func__, doff, len, SDPCM_HDRLEN, seq));
4164 bus->rx_badhdr++;
4165 ASSERT(0);
4166 dhdsdio_rxfail(bus, false, false);
4167 continue;
4168 }
4169
4170 /* Save the readahead length if there is one */
4171 bus->nextlen =
4172 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4173 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4174 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4175 "(%d), seq %d\n",
4176 __func__, bus->nextlen, seq));
4177 bus->nextlen = 0;
4178 }
4179
4180 /* Handle Flow Control */
4181 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4182
4183 if (bus->flowcontrol != fcbits) {
4184 if (~bus->flowcontrol & fcbits)
4185 bus->fc_xoff++;
4186
4187 if (bus->flowcontrol & ~fcbits)
4188 bus->fc_xon++;
4189
4190 bus->fc_rcvd++;
4191 bus->flowcontrol = fcbits;
4192 }
4193
4194 /* Check and update sequence number */
4195 if (rxseq != seq) {
4196 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4197 seq, rxseq));
4198 bus->rx_badseq++;
4199 rxseq = seq;
4200 }
4201
4202 /* Check window for sanity */
4203 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4204 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4205 __func__, txmax, bus->tx_seq));
4206 txmax = bus->tx_seq + 2;
4207 }
4208 bus->tx_max = txmax;
4209
4210 /* Call a separate function for control frames */
4211 if (chan == SDPCM_CONTROL_CHANNEL) {
4212 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4213 continue;
4214 }
4215
4216 ASSERT((chan == SDPCM_DATA_CHANNEL)
4217 || (chan == SDPCM_EVENT_CHANNEL)
4218 || (chan == SDPCM_TEST_CHANNEL)
4219 || (chan == SDPCM_GLOM_CHANNEL));
4220
4221 /* Length to read */
4222 rdlen = (len > firstread) ? (len - firstread) : 0;
4223
4224 /* May pad read to blocksize for efficiency */
4225 if (bus->roundup && bus->blocksize &&
4226 (rdlen > bus->blocksize)) {
4227 pad = bus->blocksize - (rdlen % bus->blocksize);
4228 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4229 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4230 rdlen += pad;
4231 } else if (rdlen % DHD_SDALIGN) {
4232 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4233 }
4234
4235 /* Satisfy length-alignment requirements */
4236 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4237 rdlen = roundup(rdlen, ALIGNMENT);
4238
4239 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4240 /* Too long -- skip this frame */
4241 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4242 __func__, len, rdlen));
4243 bus->dhd->rx_errors++;
4244 bus->rx_toolong++;
4245 dhdsdio_rxfail(bus, false, false);
4246 continue;
4247 }
4248
4249 dhd_os_sdlock_rxq(bus->dhd);
4250 pkt = brcmu_pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
4251 if (!pkt) {
4252 /* Give up on data, request rtx of events */
4253 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed: rdlen %d"
4254 " chan %d\n", __func__, rdlen, chan));
4255 bus->dhd->rx_dropped++;
4256 dhd_os_sdunlock_rxq(bus->dhd);
4257 dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4258 continue;
4259 }
4260 dhd_os_sdunlock_rxq(bus->dhd);
4261
4262 ASSERT(!(pkt->prev));
4263
4264 /* Leave room for what we already read, and align remainder */
4265 ASSERT(firstread < pkt->len);
4266 skb_pull(pkt, firstread);
4267 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
4268
4269 /* Read the remaining frame data */
4270 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4271 F2SYNC, ((u8 *) (pkt->data)), rdlen,
4272 pkt, NULL, NULL);
4273 bus->f2rxdata++;
4274 ASSERT(sdret != -BCME_PENDING);
4275
4276 if (sdret < 0) {
4277 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4278 __func__, rdlen,
4279 ((chan ==
4280 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4281 SDPCM_DATA_CHANNEL)
4282 ? "data" : "test")),
4283 sdret));
4284 dhd_os_sdlock_rxq(bus->dhd);
4285 brcmu_pkt_buf_free_skb(pkt);
4286 dhd_os_sdunlock_rxq(bus->dhd);
4287 bus->dhd->rx_errors++;
4288 dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4289 continue;
4290 }
4291
4292 /* Copy the already-read portion */
4293 skb_push(pkt, firstread);
4294 memcpy(pkt->data, bus->rxhdr, firstread);
4295
4296 #ifdef DHD_DEBUG
4297 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4298 printk(KERN_DEBUG "Rx Data:\n");
4299 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4300 pkt->data, len);
4301 }
4302 #endif
4303
4304 deliver:
4305 /* Save superframe descriptor and allocate packet frame */
4306 if (chan == SDPCM_GLOM_CHANNEL) {
4307 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4308 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4309 __func__, len));
4310 #ifdef DHD_DEBUG
4311 if (DHD_GLOM_ON()) {
4312 printk(KERN_DEBUG "Glom Data:\n");
4313 print_hex_dump_bytes("",
4314 DUMP_PREFIX_OFFSET,
4315 pkt->data, len);
4316 }
4317 #endif
4318 __skb_trim(pkt, len);
4319 ASSERT(doff == SDPCM_HDRLEN);
4320 skb_pull(pkt, SDPCM_HDRLEN);
4321 bus->glomd = pkt;
4322 } else {
4323 DHD_ERROR(("%s: glom superframe w/o "
4324 "descriptor!\n", __func__));
4325 dhdsdio_rxfail(bus, false, false);
4326 }
4327 continue;
4328 }
4329
4330 /* Fill in packet len and prio, deliver upward */
4331 __skb_trim(pkt, len);
4332 skb_pull(pkt, doff);
4333
4334 #ifdef SDTEST
4335 /* Test channel packets are processed separately */
4336 if (chan == SDPCM_TEST_CHANNEL) {
4337 dhdsdio_testrcv(bus, pkt, seq);
4338 continue;
4339 }
4340 #endif /* SDTEST */
4341
4342 if (pkt->len == 0) {
4343 dhd_os_sdlock_rxq(bus->dhd);
4344 brcmu_pkt_buf_free_skb(pkt);
4345 dhd_os_sdunlock_rxq(bus->dhd);
4346 continue;
4347 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4348 DHD_ERROR(("%s: rx protocol error\n", __func__));
4349 dhd_os_sdlock_rxq(bus->dhd);
4350 brcmu_pkt_buf_free_skb(pkt);
4351 dhd_os_sdunlock_rxq(bus->dhd);
4352 bus->dhd->rx_errors++;
4353 continue;
4354 }
4355
4356 /* Unlock during rx call */
4357 dhd_os_sdunlock(bus->dhd);
4358 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4359 dhd_os_sdlock(bus->dhd);
4360 }
4361 rxcount = maxframes - rxleft;
4362 #ifdef DHD_DEBUG
4363 /* Message if we hit the limit */
4364 if (!rxleft && !sdtest)
4365 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4366 maxframes));
4367 else
4368 #endif /* DHD_DEBUG */
4369 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4370 /* Back off rxseq if awaiting rtx, update rx_seq */
4371 if (bus->rxskip)
4372 rxseq--;
4373 bus->rx_seq = rxseq;
4374
4375 return rxcount;
4376 }
4377
4378 static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4379 {
4380 struct sdpcmd_regs *regs = bus->regs;
4381 u32 intstatus = 0;
4382 u32 hmb_data;
4383 u8 fcbits;
4384 uint retries = 0;
4385
4386 DHD_TRACE(("%s: Enter\n", __func__));
4387
4388 /* Read mailbox data and ack that we did so */
4389 R_SDREG(hmb_data, &regs->tohostmailboxdata, retries);
4390 if (retries <= retry_limit)
4391 W_SDREG(SMB_INT_ACK, &regs->tosbmailbox, retries);
4392 bus->f1regdata += 2;
4393
4394 /* Dongle recomposed rx frames, accept them again */
4395 if (hmb_data & HMB_DATA_NAKHANDLED) {
4396 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4397 bus->rx_seq));
4398 if (!bus->rxskip)
4399 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4400
4401 bus->rxskip = false;
4402 intstatus |= I_HMB_FRAME_IND;
4403 }
4404
4405 /*
4406 * DEVREADY does not occur with gSPI.
4407 */
4408 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4409 bus->sdpcm_ver =
4410 (hmb_data & HMB_DATA_VERSION_MASK) >>
4411 HMB_DATA_VERSION_SHIFT;
4412 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4413 DHD_ERROR(("Version mismatch, dongle reports %d, "
4414 "expecting %d\n",
4415 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4416 else
4417 DHD_INFO(("Dongle ready, protocol version %d\n",
4418 bus->sdpcm_ver));
4419 }
4420
4421 /*
4422 * Flow Control has been moved into the RX headers and this out of band
4423 * method isn't used any more.
4424 * remaining backward compatible with older dongles.
4425 */
4426 if (hmb_data & HMB_DATA_FC) {
4427 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
4428 HMB_DATA_FCDATA_SHIFT;
4429
4430 if (fcbits & ~bus->flowcontrol)
4431 bus->fc_xoff++;
4432
4433 if (bus->flowcontrol & ~fcbits)
4434 bus->fc_xon++;
4435
4436 bus->fc_rcvd++;
4437 bus->flowcontrol = fcbits;
4438 }
4439
4440 /* Shouldn't be any others */
4441 if (hmb_data & ~(HMB_DATA_DEVREADY |
4442 HMB_DATA_NAKHANDLED |
4443 HMB_DATA_FC |
4444 HMB_DATA_FWREADY |
4445 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4446 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4447 }
4448
4449 return intstatus;
4450 }
4451
4452 bool dhdsdio_dpc(dhd_bus_t *bus)
4453 {
4454 bcmsdh_info_t *sdh = bus->sdh;
4455 struct sdpcmd_regs *regs = bus->regs;
4456 u32 intstatus, newstatus = 0;
4457 uint retries = 0;
4458 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4459 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4460 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4461 bool rxdone = true; /* Flag for no more read data */
4462 bool resched = false; /* Flag indicating resched wanted */
4463
4464 DHD_TRACE(("%s: Enter\n", __func__));
4465
4466 /* Start with leftover status bits */
4467 intstatus = bus->intstatus;
4468
4469 dhd_os_sdlock(bus->dhd);
4470
4471 /* If waiting for HTAVAIL, check status */
4472 if (bus->clkstate == CLK_PENDING) {
4473 int err;
4474 u8 clkctl, devctl = 0;
4475
4476 #ifdef DHD_DEBUG
4477 /* Check for inconsistent device control */
4478 devctl =
4479 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4480 if (err) {
4481 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4482 __func__, err));
4483 bus->dhd->busstate = DHD_BUS_DOWN;
4484 } else {
4485 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4486 }
4487 #endif /* DHD_DEBUG */
4488
4489 /* Read CSR, if clock on switch to AVAIL, else ignore */
4490 clkctl =
4491 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4492 &err);
4493 if (err) {
4494 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4495 err));
4496 bus->dhd->busstate = DHD_BUS_DOWN;
4497 }
4498
4499 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4500 clkctl));
4501
4502 if (SBSDIO_HTAV(clkctl)) {
4503 devctl =
4504 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4505 &err);
4506 if (err) {
4507 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4508 __func__, err));
4509 bus->dhd->busstate = DHD_BUS_DOWN;
4510 }
4511 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4512 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4513 devctl, &err);
4514 if (err) {
4515 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4516 __func__, err));
4517 bus->dhd->busstate = DHD_BUS_DOWN;
4518 }
4519 bus->clkstate = CLK_AVAIL;
4520 } else {
4521 goto clkwait;
4522 }
4523 }
4524
4525 BUS_WAKE(bus);
4526
4527 /* Make sure backplane clock is on */
4528 dhdsdio_clkctl(bus, CLK_AVAIL, true);
4529 if (bus->clkstate == CLK_PENDING)
4530 goto clkwait;
4531
4532 /* Pending interrupt indicates new device status */
4533 if (bus->ipend) {
4534 bus->ipend = false;
4535 R_SDREG(newstatus, &regs->intstatus, retries);
4536 bus->f1regdata++;
4537 if (bcmsdh_regfail(bus->sdh))
4538 newstatus = 0;
4539 newstatus &= bus->hostintmask;
4540 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4541 if (newstatus) {
4542 W_SDREG(newstatus, &regs->intstatus, retries);
4543 bus->f1regdata++;
4544 }
4545 }
4546
4547 /* Merge new bits with previous */
4548 intstatus |= newstatus;
4549 bus->intstatus = 0;
4550
4551 /* Handle flow-control change: read new state in case our ack
4552 * crossed another change interrupt. If change still set, assume
4553 * FC ON for safety, let next loop through do the debounce.
4554 */
4555 if (intstatus & I_HMB_FC_CHANGE) {
4556 intstatus &= ~I_HMB_FC_CHANGE;
4557 W_SDREG(I_HMB_FC_CHANGE, &regs->intstatus, retries);
4558 R_SDREG(newstatus, &regs->intstatus, retries);
4559 bus->f1regdata += 2;
4560 bus->fcstate =
4561 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4562 intstatus |= (newstatus & bus->hostintmask);
4563 }
4564
4565 /* Handle host mailbox indication */
4566 if (intstatus & I_HMB_HOST_INT) {
4567 intstatus &= ~I_HMB_HOST_INT;
4568 intstatus |= dhdsdio_hostmail(bus);
4569 }
4570
4571 /* Generally don't ask for these, can get CRC errors... */
4572 if (intstatus & I_WR_OOSYNC) {
4573 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4574 intstatus &= ~I_WR_OOSYNC;
4575 }
4576
4577 if (intstatus & I_RD_OOSYNC) {
4578 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4579 intstatus &= ~I_RD_OOSYNC;
4580 }
4581
4582 if (intstatus & I_SBINT) {
4583 DHD_ERROR(("Dongle reports SBINT\n"));
4584 intstatus &= ~I_SBINT;
4585 }
4586
4587 /* Would be active due to wake-wlan in gSPI */
4588 if (intstatus & I_CHIPACTIVE) {
4589 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4590 intstatus &= ~I_CHIPACTIVE;
4591 }
4592
4593 /* Ignore frame indications if rxskip is set */
4594 if (bus->rxskip)
4595 intstatus &= ~I_HMB_FRAME_IND;
4596
4597 /* On frame indication, read available frames */
4598 if (PKT_AVAILABLE()) {
4599 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4600 if (rxdone || bus->rxskip)
4601 intstatus &= ~I_HMB_FRAME_IND;
4602 rxlimit -= min(framecnt, rxlimit);
4603 }
4604
4605 /* Keep still-pending events for next scheduling */
4606 bus->intstatus = intstatus;
4607
4608 clkwait:
4609 #if defined(OOB_INTR_ONLY)
4610 bcmsdh_oob_intr_set(1);
4611 #endif /* (OOB_INTR_ONLY) */
4612 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4613 * or clock availability. (Allows tx loop to check ipend if desired.)
4614 * (Unless register access seems hosed, as we may not be able to ACK...)
4615 */
4616 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4617 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4618 __func__, rxdone, framecnt));
4619 bus->intdis = false;
4620 bcmsdh_intr_enable(sdh);
4621 }
4622
4623 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4624 (bus->clkstate == CLK_AVAIL)) {
4625 int ret, i;
4626
4627 ret =
4628 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4629 F2SYNC, (u8 *) bus->ctrl_frame_buf,
4630 (u32) bus->ctrl_frame_len, NULL,
4631 NULL, NULL);
4632 ASSERT(ret != -BCME_PENDING);
4633
4634 if (ret < 0) {
4635 /* On failure, abort the command and
4636 terminate the frame */
4637 DHD_INFO(("%s: sdio error %d, abort command and "
4638 "terminate frame.\n", __func__, ret));
4639 bus->tx_sderrs++;
4640
4641 bcmsdh_abort(sdh, SDIO_FUNC_2);
4642
4643 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4644 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4645 NULL);
4646 bus->f1regdata++;
4647
4648 for (i = 0; i < 3; i++) {
4649 u8 hi, lo;
4650 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4651 SBSDIO_FUNC1_WFRAMEBCHI,
4652 NULL);
4653 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4654 SBSDIO_FUNC1_WFRAMEBCLO,
4655 NULL);
4656 bus->f1regdata += 2;
4657 if ((hi == 0) && (lo == 0))
4658 break;
4659 }
4660
4661 }
4662 if (ret == 0)
4663 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4664
4665 DHD_INFO(("Return_dpc value is : %d\n", ret));
4666 bus->ctrl_frame_stat = false;
4667 dhd_wait_event_wakeup(bus->dhd);
4668 }
4669 /* Send queued frames (limit 1 if rx may still be pending) */
4670 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4671 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4672 && DATAOK(bus)) {
4673 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4674 framecnt = dhdsdio_sendfromq(bus, framecnt);
4675 txlimit -= framecnt;
4676 }
4677
4678 /* Resched if events or tx frames are pending,
4679 else await next interrupt */
4680 /* On failed register access, all bets are off:
4681 no resched or interrupts */
4682 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4683 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4684 "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4685 bus->dhd->busstate = DHD_BUS_DOWN;
4686 bus->intstatus = 0;
4687 } else if (bus->clkstate == CLK_PENDING) {
4688 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4689 "I_CHIPACTIVE interrupt\n", __func__));
4690 resched = true;
4691 } else if (bus->intstatus || bus->ipend ||
4692 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
4693 && DATAOK(bus)) || PKT_AVAILABLE()) {
4694 resched = true;
4695 }
4696
4697 bus->dpc_sched = resched;
4698
4699 /* If we're done for now, turn off clock request. */
4700 if ((bus->clkstate != CLK_PENDING)
4701 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4702 bus->activity = false;
4703 dhdsdio_clkctl(bus, CLK_NONE, false);
4704 }
4705
4706 dhd_os_sdunlock(bus->dhd);
4707
4708 return resched;
4709 }
4710
4711 bool dhd_bus_dpc(struct dhd_bus *bus)
4712 {
4713 bool resched;
4714
4715 /* Call the DPC directly. */
4716 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4717 resched = dhdsdio_dpc(bus);
4718
4719 return resched;
4720 }
4721
4722 void dhdsdio_isr(void *arg)
4723 {
4724 dhd_bus_t *bus = (dhd_bus_t *) arg;
4725 bcmsdh_info_t *sdh;
4726
4727 DHD_TRACE(("%s: Enter\n", __func__));
4728
4729 if (!bus) {
4730 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4731 return;
4732 }
4733 sdh = bus->sdh;
4734
4735 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4736 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4737 __func__));
4738 return;
4739 }
4740 /* Count the interrupt call */
4741 bus->intrcount++;
4742 bus->ipend = true;
4743
4744 /* Shouldn't get this interrupt if we're sleeping? */
4745 if (bus->sleeping) {
4746 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4747 return;
4748 }
4749
4750 /* Disable additional interrupts (is this needed now)? */
4751 if (bus->intr)
4752 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4753 else
4754 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4755
4756 bcmsdh_intr_disable(sdh);
4757 bus->intdis = true;
4758
4759 #if defined(SDIO_ISR_THREAD)
4760 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4761 while (dhdsdio_dpc(bus))
4762 ;
4763 #else
4764 bus->dpc_sched = true;
4765 dhd_sched_dpc(bus->dhd);
4766 #endif
4767
4768 }
4769
4770 #ifdef SDTEST
4771 static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4772 {
4773 /* Default to specified length, or full range */
4774 if (dhd_pktgen_len) {
4775 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4776 bus->pktgen_minlen = bus->pktgen_maxlen;
4777 } else {
4778 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4779 bus->pktgen_minlen = 0;
4780 }
4781 bus->pktgen_len = (u16) bus->pktgen_minlen;
4782
4783 /* Default to per-watchdog burst with 10s print time */
4784 bus->pktgen_freq = 1;
4785 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4786 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4787
4788 /* Default to echo mode */
4789 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4790 bus->pktgen_stop = 1;
4791 }
4792
4793 static void dhdsdio_pktgen(dhd_bus_t *bus)
4794 {
4795 struct sk_buff *pkt;
4796 u8 *data;
4797 uint pktcount;
4798 uint fillbyte;
4799 u16 len;
4800
4801 /* Display current count if appropriate */
4802 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4803 bus->pktgen_ptick = 0;
4804 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4805 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4806 }
4807
4808 /* For recv mode, just make sure dongle has started sending */
4809 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4810 if (!bus->pktgen_rcvd)
4811 dhdsdio_sdtest_set(bus, true);
4812 return;
4813 }
4814
4815 /* Otherwise, generate or request the specified number of packets */
4816 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4817 /* Stop if total has been reached */
4818 if (bus->pktgen_total
4819 && (bus->pktgen_sent >= bus->pktgen_total)) {
4820 bus->pktgen_count = 0;
4821 break;
4822 }
4823
4824 /* Allocate an appropriate-sized packet */
4825 len = bus->pktgen_len;
4826 pkt = brcmu_pkt_buf_get_skb(
4827 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4828 true);
4829 if (!pkt) {
4830 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n",
4831 __func__));
4832 break;
4833 }
4834 PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4835 DHD_SDALIGN);
4836 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4837
4838 /* Write test header cmd and extra based on mode */
4839 switch (bus->pktgen_mode) {
4840 case DHD_PKTGEN_ECHO:
4841 *data++ = SDPCM_TEST_ECHOREQ;
4842 *data++ = (u8) bus->pktgen_sent;
4843 break;
4844
4845 case DHD_PKTGEN_SEND:
4846 *data++ = SDPCM_TEST_DISCARD;
4847 *data++ = (u8) bus->pktgen_sent;
4848 break;
4849
4850 case DHD_PKTGEN_RXBURST:
4851 *data++ = SDPCM_TEST_BURST;
4852 *data++ = (u8) bus->pktgen_count;
4853 break;
4854
4855 default:
4856 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4857 bus->pktgen_mode));
4858 brcmu_pkt_buf_free_skb(pkt, true);
4859 bus->pktgen_count = 0;
4860 return;
4861 }
4862
4863 /* Write test header length field */
4864 *data++ = (len >> 0);
4865 *data++ = (len >> 8);
4866
4867 /* Then fill in the remainder -- N/A for burst,
4868 but who cares... */
4869 for (fillbyte = 0; fillbyte < len; fillbyte++)
4870 *data++ =
4871 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4872
4873 #ifdef DHD_DEBUG
4874 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4875 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4876 printk(KERN_DEBUG "dhdsdio_pktgen: Tx Data:\n");
4877 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, data,
4878 pkt->len - SDPCM_HDRLEN);
4879 }
4880 #endif
4881
4882 /* Send it */
4883 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4884 bus->pktgen_fail++;
4885 if (bus->pktgen_stop
4886 && bus->pktgen_stop == bus->pktgen_fail)
4887 bus->pktgen_count = 0;
4888 }
4889 bus->pktgen_sent++;
4890
4891 /* Bump length if not fixed, wrap at max */
4892 if (++bus->pktgen_len > bus->pktgen_maxlen)
4893 bus->pktgen_len = (u16) bus->pktgen_minlen;
4894
4895 /* Special case for burst mode: just send one request! */
4896 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4897 break;
4898 }
4899 }
4900
4901 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4902 {
4903 struct sk_buff *pkt;
4904 u8 *data;
4905
4906 /* Allocate the packet */
4907 pkt = brcmu_pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
4908 DHD_SDALIGN, true);
4909 if (!pkt) {
4910 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n", __func__));
4911 return;
4912 }
4913 PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4914 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4915
4916 /* Fill in the test header */
4917 *data++ = SDPCM_TEST_SEND;
4918 *data++ = start;
4919 *data++ = (bus->pktgen_maxlen >> 0);
4920 *data++ = (bus->pktgen_maxlen >> 8);
4921
4922 /* Send it */
4923 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4924 bus->pktgen_fail++;
4925 }
4926
4927 static void dhdsdio_testrcv(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4928 {
4929 u8 *data;
4930 uint pktlen;
4931
4932 u8 cmd;
4933 u8 extra;
4934 u16 len;
4935 u16 offset;
4936
4937 /* Check for min length */
4938 pktlen = pkt->len;
4939 if (pktlen < SDPCM_TEST_HDRLEN) {
4940 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4941 pktlen));
4942 brcmu_pkt_buf_free_skb(pkt, false);
4943 return;
4944 }
4945
4946 /* Extract header fields */
4947 data = pkt->data;
4948 cmd = *data++;
4949 extra = *data++;
4950 len = *data++;
4951 len += *data++ << 8;
4952
4953 /* Check length for relevant commands */
4954 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4955 || cmd == SDPCM_TEST_ECHORSP) {
4956 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4957 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4958 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4959 pktlen, seq, cmd, extra, len));
4960 brcmu_pkt_buf_free_skb(pkt, false);
4961 return;
4962 }
4963 }
4964
4965 /* Process as per command */
4966 switch (cmd) {
4967 case SDPCM_TEST_ECHOREQ:
4968 /* Rx->Tx turnaround ok (even on NDIS w/current
4969 implementation) */
4970 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
4971 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0) {
4972 bus->pktgen_sent++;
4973 } else {
4974 bus->pktgen_fail++;
4975 brcmu_pkt_buf_free_skb(pkt, false);
4976 }
4977 bus->pktgen_rcvd++;
4978 break;
4979
4980 case SDPCM_TEST_ECHORSP:
4981 if (bus->ext_loop) {
4982 brcmu_pkt_buf_free_skb(pkt, false);
4983 bus->pktgen_rcvd++;
4984 break;
4985 }
4986
4987 for (offset = 0; offset < len; offset++, data++) {
4988 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4989 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4990 offset, len,
4991 SDPCM_TEST_FILL(offset, extra), *data));
4992 break;
4993 }
4994 }
4995 brcmu_pkt_buf_free_skb(pkt, false);
4996 bus->pktgen_rcvd++;
4997 break;
4998
4999 case SDPCM_TEST_DISCARD:
5000 brcmu_pkt_buf_free_skb(pkt, false);
5001 bus->pktgen_rcvd++;
5002 break;
5003
5004 case SDPCM_TEST_BURST:
5005 case SDPCM_TEST_SEND:
5006 default:
5007 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
5008 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
5009 pktlen, seq, cmd, extra, len));
5010 brcmu_pkt_buf_free_skb(pkt, false);
5011 break;
5012 }
5013
5014 /* For recv mode, stop at limie (and tell dongle to stop sending) */
5015 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
5016 if (bus->pktgen_total
5017 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
5018 bus->pktgen_count = 0;
5019 dhdsdio_sdtest_set(bus, false);
5020 }
5021 }
5022 }
5023 #endif /* SDTEST */
5024
5025 extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
5026 {
5027 dhd_bus_t *bus;
5028
5029 DHD_TIMER(("%s: Enter\n", __func__));
5030
5031 bus = dhdp->bus;
5032
5033 if (bus->dhd->dongle_reset)
5034 return false;
5035
5036 /* Ignore the timer if simulating bus down */
5037 if (bus->sleeping)
5038 return false;
5039
5040 dhd_os_sdlock(bus->dhd);
5041
5042 /* Poll period: check device if appropriate. */
5043 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
5044 u32 intstatus = 0;
5045
5046 /* Reset poll tick */
5047 bus->polltick = 0;
5048
5049 /* Check device if no interrupts */
5050 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
5051
5052 if (!bus->dpc_sched) {
5053 u8 devpend;
5054 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
5055 SDIO_CCCR_INTx,
5056 NULL);
5057 intstatus =
5058 devpend & (INTR_STATUS_FUNC1 |
5059 INTR_STATUS_FUNC2);
5060 }
5061
5062 /* If there is something, make like the ISR and
5063 schedule the DPC */
5064 if (intstatus) {
5065 bus->pollcnt++;
5066 bus->ipend = true;
5067 if (bus->intr)
5068 bcmsdh_intr_disable(bus->sdh);
5069
5070 bus->dpc_sched = true;
5071 dhd_sched_dpc(bus->dhd);
5072
5073 }
5074 }
5075
5076 /* Update interrupt tracking */
5077 bus->lastintrs = bus->intrcount;
5078 }
5079 #ifdef DHD_DEBUG
5080 /* Poll for console output periodically */
5081 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
5082 bus->console.count += dhd_watchdog_ms;
5083 if (bus->console.count >= dhd_console_ms) {
5084 bus->console.count -= dhd_console_ms;
5085 /* Make sure backplane clock is on */
5086 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5087 if (dhdsdio_readconsole(bus) < 0)
5088 dhd_console_ms = 0; /* On error,
5089 stop trying */
5090 }
5091 }
5092 #endif /* DHD_DEBUG */
5093
5094 #ifdef SDTEST
5095 /* Generate packets if configured */
5096 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
5097 /* Make sure backplane clock is on */
5098 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5099 bus->pktgen_tick = 0;
5100 dhdsdio_pktgen(bus);
5101 }
5102 #endif
5103
5104 /* On idle timeout clear activity flag and/or turn off clock */
5105 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
5106 if (++bus->idlecount >= bus->idletime) {
5107 bus->idlecount = 0;
5108 if (bus->activity) {
5109 bus->activity = false;
5110 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
5111 } else {
5112 dhdsdio_clkctl(bus, CLK_NONE, false);
5113 }
5114 }
5115 }
5116
5117 dhd_os_sdunlock(bus->dhd);
5118
5119 return bus->ipend;
5120 }
5121
5122 #ifdef DHD_DEBUG
5123 extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
5124 {
5125 dhd_bus_t *bus = dhdp->bus;
5126 u32 addr, val;
5127 int rv;
5128 struct sk_buff *pkt;
5129
5130 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
5131 if (bus->console_addr == 0)
5132 return -ENOTSUPP;
5133
5134 /* Exclusive bus access */
5135 dhd_os_sdlock(bus->dhd);
5136
5137 /* Don't allow input if dongle is in reset */
5138 if (bus->dhd->dongle_reset) {
5139 dhd_os_sdunlock(bus->dhd);
5140 return -EPERM;
5141 }
5142
5143 /* Request clock to allow SDIO accesses */
5144 BUS_WAKE(bus);
5145 /* No pend allowed since txpkt is called later, ht clk has to be on */
5146 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5147
5148 /* Zero cbuf_index */
5149 addr = bus->console_addr + offsetof(rte_cons_t, cbuf_idx);
5150 val = cpu_to_le32(0);
5151 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5152 if (rv < 0)
5153 goto done;
5154
5155 /* Write message into cbuf */
5156 addr = bus->console_addr + offsetof(rte_cons_t, cbuf);
5157 rv = dhdsdio_membytes(bus, true, addr, (u8 *)msg, msglen);
5158 if (rv < 0)
5159 goto done;
5160
5161 /* Write length into vcons_in */
5162 addr = bus->console_addr + offsetof(rte_cons_t, vcons_in);
5163 val = cpu_to_le32(msglen);
5164 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5165 if (rv < 0)
5166 goto done;
5167
5168 /* Bump dongle by sending an empty event pkt.
5169 * sdpcm_sendup (RX) checks for virtual console input.
5170 */
5171 pkt = brcmu_pkt_buf_get_skb(4 + SDPCM_RESERVE);
5172 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5173 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5174
5175 done:
5176 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5177 bus->activity = false;
5178 dhdsdio_clkctl(bus, CLK_NONE, true);
5179 }
5180
5181 dhd_os_sdunlock(bus->dhd);
5182
5183 return rv;
5184 }
5185 #endif /* DHD_DEBUG */
5186
5187 static bool dhdsdio_chipmatch(u16 chipid)
5188 {
5189 if (chipid == BCM4325_CHIP_ID)
5190 return true;
5191 if (chipid == BCM4329_CHIP_ID)
5192 return true;
5193 if (chipid == BCM4319_CHIP_ID)
5194 return true;
5195 return false;
5196 }
5197
5198 static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5199 u16 slot, u16 func, uint bustype, void *regsva,
5200 void *sdh)
5201 {
5202 int ret;
5203 dhd_bus_t *bus;
5204
5205 /* Init global variables at run-time, not as part of the declaration.
5206 * This is required to support init/de-init of the driver.
5207 * Initialization
5208 * of globals as part of the declaration results in non-deterministic
5209 * behavior since the value of the globals may be different on the
5210 * first time that the driver is initialized vs subsequent
5211 * initializations.
5212 */
5213 dhd_txbound = DHD_TXBOUND;
5214 dhd_rxbound = DHD_RXBOUND;
5215 dhd_alignctl = true;
5216 sd1idle = true;
5217 dhd_readahead = true;
5218 retrydata = false;
5219 dhd_dongle_memsize = 0;
5220 dhd_txminmax = DHD_TXMINMAX;
5221
5222 forcealign = true;
5223
5224 dhd_common_init();
5225
5226 DHD_TRACE(("%s: Enter\n", __func__));
5227 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5228
5229 /* We make assumptions about address window mappings */
5230 ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5231
5232 /* BCMSDH passes venid and devid based on CIS parsing -- but
5233 * low-power start
5234 * means early parse could fail, so here we should get either an ID
5235 * we recognize OR (-1) indicating we must request power first.
5236 */
5237 /* Check the Vendor ID */
5238 switch (venid) {
5239 case 0x0000:
5240 case PCI_VENDOR_ID_BROADCOM:
5241 break;
5242 default:
5243 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5244 return NULL;
5245 }
5246
5247 /* Check the Device ID and make sure it's one that we support */
5248 switch (devid) {
5249 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5250 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5251 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5252 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5253 break;
5254 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5255 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5256 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5257 case 0x4329:
5258 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5259 break;
5260 case BCM4319_D11N_ID: /* 4319 802.11n id */
5261 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5262 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5263 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5264 break;
5265 case 0:
5266 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5267 __func__));
5268 break;
5269
5270 default:
5271 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5272 __func__, venid, devid));
5273 return NULL;
5274 }
5275
5276 /* Allocate private bus interface state */
5277 bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5278 if (!bus) {
5279 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5280 goto fail;
5281 }
5282 bus->sdh = sdh;
5283 bus->cl_devid = (u16) devid;
5284 bus->bus = DHD_BUS;
5285 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5286 bus->usebufpool = false; /* Use bufpool if allocated,
5287 else use locally malloced rxbuf */
5288
5289 /* attempt to attach to the dongle */
5290 if (!(dhdsdio_probe_attach(bus, sdh, regsva, devid))) {
5291 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5292 goto fail;
5293 }
5294
5295 /* Attach to the dhd/OS/network interface */
5296 bus->dhd = dhd_attach(bus, SDPCM_RESERVE);
5297 if (!bus->dhd) {
5298 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5299 goto fail;
5300 }
5301
5302 /* Allocate buffers */
5303 if (!(dhdsdio_probe_malloc(bus, sdh))) {
5304 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5305 goto fail;
5306 }
5307
5308 if (!(dhdsdio_probe_init(bus, sdh))) {
5309 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5310 goto fail;
5311 }
5312
5313 /* Register interrupt callback, but mask it (not operational yet). */
5314 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5315 __func__));
5316 bcmsdh_intr_disable(sdh);
5317 ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5318 if (ret != 0) {
5319 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5320 __func__, ret));
5321 goto fail;
5322 }
5323 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5324
5325 DHD_INFO(("%s: completed!!\n", __func__));
5326
5327 /* if firmware path present try to download and bring up bus */
5328 ret = dhd_bus_start(bus->dhd);
5329 if (ret != 0) {
5330 if (ret == -ENOLINK) {
5331 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5332 goto fail;
5333 }
5334 }
5335 /* Ok, have the per-port tell the stack we're open for business */
5336 if (dhd_net_attach(bus->dhd, 0) != 0) {
5337 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5338 goto fail;
5339 }
5340
5341 return bus;
5342
5343 fail:
5344 dhdsdio_release(bus);
5345 return NULL;
5346 }
5347
5348 static bool
5349 dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
5350 {
5351 u8 clkctl = 0;
5352 int err = 0;
5353
5354 bus->alp_only = true;
5355
5356 /* Return the window to backplane enumeration space for core access */
5357 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5358 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5359
5360 #ifdef DHD_DEBUG
5361 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5362 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5363
5364 #endif /* DHD_DEBUG */
5365
5366 /*
5367 * Force PLL off until dhdsdio_chip_attach()
5368 * programs PLL control regs
5369 */
5370
5371 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5372 DHD_INIT_CLKCTL1, &err);
5373 if (!err)
5374 clkctl =
5375 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5376 &err);
5377
5378 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5379 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5380 "0x%02x read 0x%02x\n",
5381 err, DHD_INIT_CLKCTL1, clkctl));
5382 goto fail;
5383 }
5384
5385 if (dhdsdio_chip_attach(bus, regsva)) {
5386 DHD_ERROR(("%s: dhdsdio_chip_attach failed!\n", __func__));
5387 goto fail;
5388 }
5389
5390 bcmsdh_chipinfo(sdh, bus->ci->chip, bus->ci->chiprev);
5391
5392 if (!dhdsdio_chipmatch((u16) bus->ci->chip)) {
5393 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5394 __func__, bus->ci->chip));
5395 goto fail;
5396 }
5397
5398 dhdsdio_sdiod_drive_strength_init(bus, dhd_sdiod_drive_strength);
5399
5400 /* Get info on the ARM and SOCRAM cores... */
5401 if (!DHD_NOPMU(bus)) {
5402 bus->armrev = SBCOREREV(bcmsdh_reg_read(bus->sdh,
5403 CORE_SB(bus->ci->armcorebase, sbidhigh), 4));
5404 bus->orig_ramsize = bus->ci->ramsize;
5405 if (!(bus->orig_ramsize)) {
5406 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5407 __func__));
5408 goto fail;
5409 }
5410 bus->ramsize = bus->orig_ramsize;
5411 if (dhd_dongle_memsize)
5412 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5413
5414 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5415 bus->ramsize, bus->orig_ramsize));
5416 }
5417
5418 bus->regs = (void *)bus->ci->buscorebase;
5419
5420 /* Set core control so an SDIO reset does a backplane reset */
5421 OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
5422
5423 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5424
5425 /* Locate an appropriately-aligned portion of hdrbuf */
5426 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5427
5428 /* Set the poll and/or interrupt flags */
5429 bus->intr = (bool) dhd_intr;
5430 bus->poll = (bool) dhd_poll;
5431 if (bus->poll)
5432 bus->pollrate = 1;
5433
5434 return true;
5435
5436 fail:
5437 return false;
5438 }
5439
5440 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh)
5441 {
5442 DHD_TRACE(("%s: Enter\n", __func__));
5443
5444 if (bus->dhd->maxctl) {
5445 bus->rxblen =
5446 roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5447 ALIGNMENT) + DHD_SDALIGN;
5448 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5449 if (!(bus->rxbuf)) {
5450 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5451 __func__, bus->rxblen));
5452 goto fail;
5453 }
5454 }
5455
5456 /* Allocate buffer to receive glomed packet */
5457 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5458 if (!(bus->databuf)) {
5459 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5460 __func__, MAX_DATA_BUF));
5461 /* release rxbuf which was already located as above */
5462 if (!bus->rxblen)
5463 kfree(bus->rxbuf);
5464 goto fail;
5465 }
5466
5467 /* Align the buffer */
5468 if ((unsigned long)bus->databuf % DHD_SDALIGN)
5469 bus->dataptr =
5470 bus->databuf + (DHD_SDALIGN -
5471 ((unsigned long)bus->databuf % DHD_SDALIGN));
5472 else
5473 bus->dataptr = bus->databuf;
5474
5475 return true;
5476
5477 fail:
5478 return false;
5479 }
5480
5481 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh)
5482 {
5483 s32 fnum;
5484
5485 DHD_TRACE(("%s: Enter\n", __func__));
5486
5487 #ifdef SDTEST
5488 dhdsdio_pktgen_init(bus);
5489 #endif /* SDTEST */
5490
5491 /* Disable F2 to clear any intermediate frame state on the dongle */
5492 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, SDIO_FUNC_ENABLE_1,
5493 NULL);
5494
5495 bus->dhd->busstate = DHD_BUS_DOWN;
5496 bus->sleeping = false;
5497 bus->rxflow = false;
5498 bus->prev_rxlim_hit = 0;
5499
5500 /* Done with backplane-dependent accesses, can drop clock... */
5501 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5502
5503 /* ...and initialize clock/power states */
5504 bus->clkstate = CLK_SDONLY;
5505 bus->idletime = (s32) dhd_idletime;
5506 bus->idleclock = DHD_IDLE_ACTIVE;
5507
5508 /* Query the F2 block size, set roundup accordingly */
5509 fnum = 2;
5510 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5511 &bus->blocksize, sizeof(s32), false) != 0) {
5512 bus->blocksize = 0;
5513 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5514 } else {
5515 DHD_INFO(("%s: Initial value for %s is %d\n",
5516 __func__, "sd_blocksize", bus->blocksize));
5517 }
5518 bus->roundup = min(max_roundup, bus->blocksize);
5519
5520 /* Query if bus module supports packet chaining,
5521 default to use if supported */
5522 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5523 &bus->sd_rxchain, sizeof(s32),
5524 false) != 0) {
5525 bus->sd_rxchain = false;
5526 } else {
5527 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5528 __func__,
5529 (bus->sd_rxchain ? "supports" : "does not support")));
5530 }
5531 bus->use_rxchain = (bool) bus->sd_rxchain;
5532
5533 return true;
5534 }
5535
5536 bool
5537 dhd_bus_download_firmware(struct dhd_bus *bus, char *fw_path, char *nv_path)
5538 {
5539 bool ret;
5540 bus->fw_path = fw_path;
5541 bus->nv_path = nv_path;
5542
5543 ret = dhdsdio_download_firmware(bus, bus->sdh);
5544
5545 return ret;
5546 }
5547
5548 static bool
5549 dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh)
5550 {
5551 bool ret;
5552
5553 /* Download the firmware */
5554 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5555
5556 ret = _dhdsdio_download_firmware(bus) == 0;
5557
5558 dhdsdio_clkctl(bus, CLK_SDONLY, false);
5559
5560 return ret;
5561 }
5562
5563 /* Detach and free everything */
5564 static void dhdsdio_release(dhd_bus_t *bus)
5565 {
5566 DHD_TRACE(("%s: Enter\n", __func__));
5567
5568 if (bus) {
5569 /* De-register interrupt handler */
5570 bcmsdh_intr_disable(bus->sdh);
5571 bcmsdh_intr_dereg(bus->sdh);
5572
5573 if (bus->dhd) {
5574 dhd_detach(bus->dhd);
5575 dhdsdio_release_dongle(bus);
5576 bus->dhd = NULL;
5577 }
5578
5579 dhdsdio_release_malloc(bus);
5580
5581 kfree(bus);
5582 }
5583
5584 DHD_TRACE(("%s: Disconnected\n", __func__));
5585 }
5586
5587 static void dhdsdio_release_malloc(dhd_bus_t *bus)
5588 {
5589 DHD_TRACE(("%s: Enter\n", __func__));
5590
5591 if (bus->dhd && bus->dhd->dongle_reset)
5592 return;
5593
5594 if (bus->rxbuf) {
5595 kfree(bus->rxbuf);
5596 bus->rxctl = bus->rxbuf = NULL;
5597 bus->rxlen = 0;
5598 }
5599
5600 kfree(bus->databuf);
5601 bus->databuf = NULL;
5602 }
5603
5604 static void dhdsdio_release_dongle(dhd_bus_t *bus)
5605 {
5606 DHD_TRACE(("%s: Enter\n", __func__));
5607
5608 if (bus->dhd && bus->dhd->dongle_reset)
5609 return;
5610
5611 if (bus->ci) {
5612 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5613 dhdsdio_clkctl(bus, CLK_NONE, false);
5614 dhdsdio_chip_detach(bus);
5615 if (bus->vars && bus->varsz)
5616 kfree(bus->vars);
5617 bus->vars = NULL;
5618 }
5619
5620 DHD_TRACE(("%s: Disconnected\n", __func__));
5621 }
5622
5623 static void dhdsdio_disconnect(void *ptr)
5624 {
5625 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5626
5627 DHD_TRACE(("%s: Enter\n", __func__));
5628
5629 if (bus) {
5630 ASSERT(bus->dhd);
5631 dhdsdio_release(bus);
5632 }
5633
5634 DHD_TRACE(("%s: Disconnected\n", __func__));
5635 }
5636
5637 /* Register/Unregister functions are called by the main DHD entry
5638 * point (e.g. module insertion) to link with the bus driver, in
5639 * order to look for or await the device.
5640 */
5641
5642 static bcmsdh_driver_t dhd_sdio = {
5643 dhdsdio_probe,
5644 dhdsdio_disconnect
5645 };
5646
5647 int dhd_bus_register(void)
5648 {
5649 DHD_TRACE(("%s: Enter\n", __func__));
5650
5651 return bcmsdh_register(&dhd_sdio);
5652 }
5653
5654 void dhd_bus_unregister(void)
5655 {
5656 DHD_TRACE(("%s: Enter\n", __func__));
5657
5658 bcmsdh_unregister();
5659 }
5660
5661 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5662 {
5663 int bcmerror = -1;
5664 int offset = 0;
5665 uint len;
5666 void *image = NULL;
5667 u8 *memblock = NULL, *memptr;
5668
5669 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5670
5671 image = dhd_os_open_image(fw_path);
5672 if (image == NULL)
5673 goto err;
5674
5675 memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5676 if (memblock == NULL) {
5677 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5678 __func__, MEMBLOCK));
5679 goto err;
5680 }
5681 if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5682 memptr +=
5683 (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5684
5685 /* Download image */
5686 while ((len =
5687 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5688 bcmerror = dhdsdio_membytes(bus, true, offset, memptr, len);
5689 if (bcmerror) {
5690 DHD_ERROR(("%s: error %d on writing %d membytes at "
5691 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5692 goto err;
5693 }
5694
5695 offset += MEMBLOCK;
5696 }
5697
5698 err:
5699 kfree(memblock);
5700
5701 if (image)
5702 dhd_os_close_image(image);
5703
5704 return bcmerror;
5705 }
5706
5707 /*
5708 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5709 * and ending in a NUL.
5710 * Removes carriage returns, empty lines, comment lines, and converts
5711 * newlines to NULs.
5712 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5713 * by two NULs.
5714 */
5715
5716 static uint process_nvram_vars(char *varbuf, uint len)
5717 {
5718 char *dp;
5719 bool findNewline;
5720 int column;
5721 uint buf_len, n;
5722
5723 dp = varbuf;
5724
5725 findNewline = false;
5726 column = 0;
5727
5728 for (n = 0; n < len; n++) {
5729 if (varbuf[n] == 0)
5730 break;
5731 if (varbuf[n] == '\r')
5732 continue;
5733 if (findNewline && varbuf[n] != '\n')
5734 continue;
5735 findNewline = false;
5736 if (varbuf[n] == '#') {
5737 findNewline = true;
5738 continue;
5739 }
5740 if (varbuf[n] == '\n') {
5741 if (column == 0)
5742 continue;
5743 *dp++ = 0;
5744 column = 0;
5745 continue;
5746 }
5747 *dp++ = varbuf[n];
5748 column++;
5749 }
5750 buf_len = dp - varbuf;
5751
5752 while (dp < varbuf + n)
5753 *dp++ = 0;
5754
5755 return buf_len;
5756 }
5757
5758 /*
5759 EXAMPLE: nvram_array
5760 nvram_arry format:
5761 name=value
5762 Use carriage return at the end of each assignment,
5763 and an empty string with
5764 carriage return at the end of array.
5765
5766 For example:
5767 unsigned char nvram_array[] = {"name1=value1\n",
5768 "name2=value2\n", "\n"};
5769 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5770
5771 Search "EXAMPLE: nvram_array" to see how the array is activated.
5772 */
5773
5774 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5775 {
5776 bus->nvram_params = nvram_params;
5777 }
5778
5779 static int dhdsdio_download_nvram(struct dhd_bus *bus)
5780 {
5781 int bcmerror = -1;
5782 uint len;
5783 void *image = NULL;
5784 char *memblock = NULL;
5785 char *bufp;
5786 char *nv_path;
5787 bool nvram_file_exists;
5788
5789 nv_path = bus->nv_path;
5790
5791 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5792 if (!nvram_file_exists && (bus->nvram_params == NULL))
5793 return 0;
5794
5795 if (nvram_file_exists) {
5796 image = dhd_os_open_image(nv_path);
5797 if (image == NULL)
5798 goto err;
5799 }
5800
5801 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5802 if (memblock == NULL) {
5803 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5804 __func__, MEMBLOCK));
5805 goto err;
5806 }
5807
5808 /* Download variables */
5809 if (nvram_file_exists) {
5810 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5811 } else {
5812 len = strlen(bus->nvram_params);
5813 ASSERT(len <= MEMBLOCK);
5814 if (len > MEMBLOCK)
5815 len = MEMBLOCK;
5816 memcpy(memblock, bus->nvram_params, len);
5817 }
5818
5819 if (len > 0 && len < MEMBLOCK) {
5820 bufp = (char *)memblock;
5821 bufp[len] = 0;
5822 len = process_nvram_vars(bufp, len);
5823 bufp += len;
5824 *bufp++ = 0;
5825 if (len)
5826 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5827 if (bcmerror) {
5828 DHD_ERROR(("%s: error downloading vars: %d\n",
5829 __func__, bcmerror));
5830 }
5831 } else {
5832 DHD_ERROR(("%s: error reading nvram file: %d\n",
5833 __func__, len));
5834 bcmerror = -EIO;
5835 }
5836
5837 err:
5838 kfree(memblock);
5839
5840 if (image)
5841 dhd_os_close_image(image);
5842
5843 return bcmerror;
5844 }
5845
5846 static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5847 {
5848 int bcmerror = -1;
5849
5850 bool embed = false; /* download embedded firmware */
5851 bool dlok = false; /* download firmware succeeded */
5852
5853 /* Out immediately if no image to download */
5854 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0'))
5855 return bcmerror;
5856
5857 /* Keep arm in reset */
5858 if (dhdsdio_download_state(bus, true)) {
5859 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5860 goto err;
5861 }
5862
5863 /* External image takes precedence if specified */
5864 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5865 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5866 DHD_ERROR(("%s: dongle image file download failed\n",
5867 __func__));
5868 goto err;
5869 } else {
5870 embed = false;
5871 dlok = true;
5872 }
5873 }
5874 if (!dlok) {
5875 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5876 goto err;
5877 }
5878
5879 /* EXAMPLE: nvram_array */
5880 /* If a valid nvram_arry is specified as above, it can be passed
5881 down to dongle */
5882 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5883
5884 /* External nvram takes precedence if specified */
5885 if (dhdsdio_download_nvram(bus)) {
5886 DHD_ERROR(("%s: dongle nvram file download failed\n",
5887 __func__));
5888 }
5889
5890 /* Take arm out of reset */
5891 if (dhdsdio_download_state(bus, false)) {
5892 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5893 __func__));
5894 goto err;
5895 }
5896
5897 bcmerror = 0;
5898
5899 err:
5900 return bcmerror;
5901 }
5902
5903
5904 static int
5905 dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5906 u8 *buf, uint nbytes, struct sk_buff *pkt,
5907 bcmsdh_cmplt_fn_t complete, void *handle)
5908 {
5909 return bcmsdh_send_buf
5910 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
5911 handle);
5912 }
5913
5914 uint dhd_bus_chip(struct dhd_bus *bus)
5915 {
5916 ASSERT(bus->ci != NULL);
5917 return bus->ci->chip;
5918 }
5919
5920 void *dhd_bus_pub(struct dhd_bus *bus)
5921 {
5922 return bus->dhd;
5923 }
5924
5925 void *dhd_bus_txq(struct dhd_bus *bus)
5926 {
5927 return &bus->txq;
5928 }
5929
5930 uint dhd_bus_hdrlen(struct dhd_bus *bus)
5931 {
5932 return SDPCM_HDRLEN;
5933 }
5934
5935 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
5936 {
5937 int bcmerror = 0;
5938 dhd_bus_t *bus;
5939
5940 bus = dhdp->bus;
5941
5942 if (flag == true) {
5943 if (!bus->dhd->dongle_reset) {
5944 /* Expect app to have torn down any
5945 connection before calling */
5946 /* Stop the bus, disable F2 */
5947 dhd_bus_stop(bus, false);
5948
5949 /* Clean tx/rx buffer pointers,
5950 detach from the dongle */
5951 dhdsdio_release_dongle(bus);
5952
5953 bus->dhd->dongle_reset = true;
5954 bus->dhd->up = false;
5955
5956 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
5957 /* App can now remove power from device */
5958 } else
5959 bcmerror = -EIO;
5960 } else {
5961 /* App must have restored power to device before calling */
5962
5963 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
5964
5965 if (bus->dhd->dongle_reset) {
5966 /* Turn on WLAN */
5967 /* Reset SD client */
5968 bcmsdh_reset(bus->sdh);
5969
5970 /* Attempt to re-attach & download */
5971 if (dhdsdio_probe_attach(bus, bus->sdh,
5972 (u32 *) SI_ENUM_BASE,
5973 bus->cl_devid)) {
5974 /* Attempt to download binary to the dongle */
5975 if (dhdsdio_probe_init
5976 (bus, bus->sdh)
5977 && dhdsdio_download_firmware(bus,
5978 bus->sdh)) {
5979
5980 /* Re-init bus, enable F2 transfer */
5981 dhd_bus_init((dhd_pub_t *) bus->dhd,
5982 false);
5983
5984 #if defined(OOB_INTR_ONLY)
5985 dhd_enable_oob_intr(bus, true);
5986 #endif /* defined(OOB_INTR_ONLY) */
5987
5988 bus->dhd->dongle_reset = false;
5989 bus->dhd->up = true;
5990
5991 DHD_TRACE(("%s: WLAN ON DONE\n",
5992 __func__));
5993 } else
5994 bcmerror = -EIO;
5995 } else
5996 bcmerror = -EIO;
5997 } else {
5998 bcmerror = -EISCONN;
5999 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6000 "is on\n", __func__));
6001 bcmerror = -EIO;
6002 }
6003 }
6004 return bcmerror;
6005 }
6006
6007 static int
6008 dhdsdio_chip_recognition(bcmsdh_info_t *sdh, struct chip_info *ci, void *regs)
6009 {
6010 u32 regdata;
6011
6012 /*
6013 * Get CC core rev
6014 * Chipid is assume to be at offset 0 from regs arg
6015 * For different chiptypes or old sdio hosts w/o chipcommon,
6016 * other ways of recognition should be added here.
6017 */
6018 ci->cccorebase = (u32)regs;
6019 regdata = bcmsdh_reg_read(sdh, CORE_CC_REG(ci->cccorebase, chipid), 4);
6020 ci->chip = regdata & CID_ID_MASK;
6021 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
6022
6023 DHD_INFO(("%s: chipid=0x%x chiprev=%d\n",
6024 __func__, ci->chip, ci->chiprev));
6025
6026 /* Address of cores for new chips should be added here */
6027 switch (ci->chip) {
6028 case BCM4329_CHIP_ID:
6029 ci->buscorebase = BCM4329_CORE_BUS_BASE;
6030 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
6031 ci->armcorebase = BCM4329_CORE_ARM_BASE;
6032 ci->ramsize = BCM4329_RAMSIZE;
6033 break;
6034 default:
6035 DHD_ERROR(("%s: chipid 0x%x is not supported\n",
6036 __func__, ci->chip));
6037 return -ENODEV;
6038 }
6039
6040 regdata = bcmsdh_reg_read(sdh,
6041 CORE_SB(ci->cccorebase, sbidhigh), 4);
6042 ci->ccrev = SBCOREREV(regdata);
6043
6044 regdata = bcmsdh_reg_read(sdh,
6045 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
6046 ci->pmurev = regdata & PCAP_REV_MASK;
6047
6048 regdata = bcmsdh_reg_read(sdh, CORE_SB(ci->buscorebase, sbidhigh), 4);
6049 ci->buscorerev = SBCOREREV(regdata);
6050 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
6051
6052 DHD_INFO(("%s: ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
6053 __func__, ci->ccrev, ci->pmurev,
6054 ci->buscorerev, ci->buscoretype));
6055
6056 /* get chipcommon capabilites */
6057 ci->cccaps = bcmsdh_reg_read(sdh,
6058 CORE_CC_REG(ci->cccorebase, capabilities), 4);
6059
6060 return 0;
6061 }
6062
6063 static void
6064 dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase)
6065 {
6066 u32 regdata;
6067
6068 regdata = bcmsdh_reg_read(sdh,
6069 CORE_SB(corebase, sbtmstatelow), 4);
6070 if (regdata & SBTML_RESET)
6071 return;
6072
6073 regdata = bcmsdh_reg_read(sdh,
6074 CORE_SB(corebase, sbtmstatelow), 4);
6075 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
6076 /*
6077 * set target reject and spin until busy is clear
6078 * (preserve core-specific bits)
6079 */
6080 regdata = bcmsdh_reg_read(sdh,
6081 CORE_SB(corebase, sbtmstatelow), 4);
6082 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6083 regdata | SBTML_REJ);
6084
6085 regdata = bcmsdh_reg_read(sdh,
6086 CORE_SB(corebase, sbtmstatelow), 4);
6087 udelay(1);
6088 SPINWAIT((bcmsdh_reg_read(sdh,
6089 CORE_SB(corebase, sbtmstatehigh), 4) &
6090 SBTMH_BUSY), 100000);
6091
6092 regdata = bcmsdh_reg_read(sdh,
6093 CORE_SB(corebase, sbtmstatehigh), 4);
6094 if (regdata & SBTMH_BUSY)
6095 DHD_ERROR(("%s: ARM core still busy\n", __func__));
6096
6097 regdata = bcmsdh_reg_read(sdh,
6098 CORE_SB(corebase, sbidlow), 4);
6099 if (regdata & SBIDL_INIT) {
6100 regdata = bcmsdh_reg_read(sdh,
6101 CORE_SB(corebase, sbimstate), 4) |
6102 SBIM_RJ;
6103 bcmsdh_reg_write(sdh,
6104 CORE_SB(corebase, sbimstate), 4,
6105 regdata);
6106 regdata = bcmsdh_reg_read(sdh,
6107 CORE_SB(corebase, sbimstate), 4);
6108 udelay(1);
6109 SPINWAIT((bcmsdh_reg_read(sdh,
6110 CORE_SB(corebase, sbimstate), 4) &
6111 SBIM_BY), 100000);
6112 }
6113
6114 /* set reset and reject while enabling the clocks */
6115 bcmsdh_reg_write(sdh,
6116 CORE_SB(corebase, sbtmstatelow), 4,
6117 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6118 SBTML_REJ | SBTML_RESET));
6119 regdata = bcmsdh_reg_read(sdh,
6120 CORE_SB(corebase, sbtmstatelow), 4);
6121 udelay(10);
6122
6123 /* clear the initiator reject bit */
6124 regdata = bcmsdh_reg_read(sdh,
6125 CORE_SB(corebase, sbidlow), 4);
6126 if (regdata & SBIDL_INIT) {
6127 regdata = bcmsdh_reg_read(sdh,
6128 CORE_SB(corebase, sbimstate), 4) &
6129 ~SBIM_RJ;
6130 bcmsdh_reg_write(sdh,
6131 CORE_SB(corebase, sbimstate), 4,
6132 regdata);
6133 }
6134 }
6135
6136 /* leave reset and reject asserted */
6137 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6138 (SBTML_REJ | SBTML_RESET));
6139 udelay(1);
6140 }
6141
6142 static int
6143 dhdsdio_chip_attach(struct dhd_bus *bus, void *regs)
6144 {
6145 struct chip_info *ci;
6146 int err;
6147 u8 clkval, clkset;
6148
6149 DHD_TRACE(("%s: Enter\n", __func__));
6150
6151 /* alloc chip_info_t */
6152 ci = kmalloc(sizeof(struct chip_info), GFP_ATOMIC);
6153 if (NULL == ci) {
6154 DHD_ERROR(("%s: malloc failed!\n", __func__));
6155 return -ENOMEM;
6156 }
6157
6158 memset((unsigned char *)ci, 0, sizeof(struct chip_info));
6159
6160 /* bus/core/clk setup for register access */
6161 /* Try forcing SDIO core to do ALPAvail request only */
6162 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
6163 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
6164 clkset, &err);
6165 if (err) {
6166 DHD_ERROR(("%s: error writing for HT off\n", __func__));
6167 goto fail;
6168 }
6169
6170 /* If register supported, wait for ALPAvail and then force ALP */
6171 /* This may take up to 15 milliseconds */
6172 clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6173 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
6174 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
6175 SPINWAIT(((clkval =
6176 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6177 SBSDIO_FUNC1_CHIPCLKCSR,
6178 NULL)),
6179 !SBSDIO_ALPAV(clkval)),
6180 PMU_MAX_TRANSITION_DLY);
6181 if (!SBSDIO_ALPAV(clkval)) {
6182 DHD_ERROR(("%s: timeout on ALPAV wait, clkval 0x%02x\n",
6183 __func__, clkval));
6184 err = -EBUSY;
6185 goto fail;
6186 }
6187 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
6188 SBSDIO_FORCE_ALP;
6189 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
6190 SBSDIO_FUNC1_CHIPCLKCSR,
6191 clkset, &err);
6192 udelay(65);
6193 } else {
6194 DHD_ERROR(("%s: ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
6195 __func__, clkset, clkval));
6196 err = -EACCES;
6197 goto fail;
6198 }
6199
6200 /* Also, disable the extra SDIO pull-ups */
6201 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,
6202 NULL);
6203
6204 err = dhdsdio_chip_recognition(bus->sdh, ci, regs);
6205 if (err)
6206 goto fail;
6207
6208 /*
6209 * Make sure any on-chip ARM is off (in case strapping is wrong),
6210 * or downloaded code was already running.
6211 */
6212 dhdsdio_chip_disablecore(bus->sdh, ci->armcorebase);
6213
6214 bcmsdh_reg_write(bus->sdh,
6215 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
6216 bcmsdh_reg_write(bus->sdh,
6217 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
6218
6219 /* Disable F2 to clear any intermediate frame state on the dongle */
6220 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
6221 SDIO_FUNC_ENABLE_1, NULL);
6222
6223 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
6224 clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6225 0, NULL);
6226
6227 /* Done with backplane-dependent accesses, can drop clock... */
6228 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0,
6229 NULL);
6230
6231 bus->ci = ci;
6232 return 0;
6233 fail:
6234 bus->ci = NULL;
6235 kfree(ci);
6236 return err;
6237 }
6238
6239 static void
6240 dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase)
6241 {
6242 u32 regdata;
6243
6244 /*
6245 * Must do the disable sequence first to work for
6246 * arbitrary current core state.
6247 */
6248 dhdsdio_chip_disablecore(sdh, corebase);
6249
6250 /*
6251 * Now do the initialization sequence.
6252 * set reset while enabling the clock and
6253 * forcing them on throughout the core
6254 */
6255 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6256 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6257 SBTML_RESET);
6258 udelay(1);
6259
6260 regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbtmstatehigh), 4);
6261 if (regdata & SBTMH_SERR)
6262 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatehigh), 4, 0);
6263
6264 regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbimstate), 4);
6265 if (regdata & (SBIM_IBE | SBIM_TO))
6266 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbimstate), 4,
6267 regdata & ~(SBIM_IBE | SBIM_TO));
6268
6269 /* clear reset and allow it to propagate throughout the core */
6270 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6271 (SICF_FGC << SBTML_SICF_SHIFT) |
6272 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6273 udelay(1);
6274
6275 /* leave clock enabled */
6276 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6277 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6278 udelay(1);
6279 }
6280
6281 /* SDIO Pad drive strength to select value mappings */
6282 struct sdiod_drive_str {
6283 u8 strength; /* Pad Drive Strength in mA */
6284 u8 sel; /* Chip-specific select value */
6285 };
6286
6287 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
6288 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
6289 {
6290 4, 0x2}, {
6291 2, 0x3}, {
6292 1, 0x0}, {
6293 0, 0x0}
6294 };
6295
6296 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
6297 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
6298 {
6299 12, 0x7}, {
6300 10, 0x6}, {
6301 8, 0x5}, {
6302 6, 0x4}, {
6303 4, 0x2}, {
6304 2, 0x1}, {
6305 0, 0x0}
6306 };
6307
6308 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
6309 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
6310 {
6311 32, 0x7}, {
6312 26, 0x6}, {
6313 22, 0x5}, {
6314 16, 0x4}, {
6315 12, 0x3}, {
6316 8, 0x2}, {
6317 4, 0x1}, {
6318 0, 0x0}
6319 };
6320
6321 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
6322
6323 static void
6324 dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus, u32 drivestrength) {
6325 struct sdiod_drive_str *str_tab = NULL;
6326 u32 str_mask = 0;
6327 u32 str_shift = 0;
6328 char chn[8];
6329
6330 if (!(bus->ci->cccaps & CC_CAP_PMU))
6331 return;
6332
6333 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
6334 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
6335 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
6336 str_mask = 0x30000000;
6337 str_shift = 28;
6338 break;
6339 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
6340 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
6341 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
6342 str_mask = 0x00003800;
6343 str_shift = 11;
6344 break;
6345 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
6346 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
6347 str_mask = 0x00003800;
6348 str_shift = 11;
6349 break;
6350 default:
6351 DHD_ERROR(("No SDIO Drive strength init"
6352 "done for chip %s rev %d pmurev %d\n",
6353 brcmu_chipname(bus->ci->chip, chn, 8),
6354 bus->ci->chiprev, bus->ci->pmurev));
6355 break;
6356 }
6357
6358 if (str_tab != NULL) {
6359 u32 drivestrength_sel = 0;
6360 u32 cc_data_temp;
6361 int i;
6362
6363 for (i = 0; str_tab[i].strength != 0; i++) {
6364 if (drivestrength >= str_tab[i].strength) {
6365 drivestrength_sel = str_tab[i].sel;
6366 break;
6367 }
6368 }
6369
6370 bcmsdh_reg_write(bus->sdh,
6371 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6372 4, 1);
6373 cc_data_temp = bcmsdh_reg_read(bus->sdh,
6374 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
6375 cc_data_temp &= ~str_mask;
6376 drivestrength_sel <<= str_shift;
6377 cc_data_temp |= drivestrength_sel;
6378 bcmsdh_reg_write(bus->sdh,
6379 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6380 4, cc_data_temp);
6381
6382 DHD_INFO(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
6383 drivestrength, cc_data_temp));
6384 }
6385 }
6386
6387 static void
6388 dhdsdio_chip_detach(struct dhd_bus *bus)
6389 {
6390 DHD_TRACE(("%s: Enter\n", __func__));
6391
6392 kfree(bus->ci);
6393 bus->ci = NULL;
6394 }
Linux kernel - Deliverables
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