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staging: brcm80211: fixed double #include problem
[deliverable/linux.git] / drivers / staging / brcm80211 / brcmsmac / bmac.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16 #include <linux/pci.h>
17 #include <net/mac80211.h>
18
19 #include <brcm_hw_ids.h>
20 #include <aiutils.h>
21 #include <chipcommon.h>
22 #include "types.h"
23 #include "rate.h"
24 #include "phy/phy_hal.h"
25 #include "channel.h"
26 #include "main.h"
27 #include "ucode_loader.h"
28 #include "mac80211_if.h"
29 #include "bmac.h"
30
31 #define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
32
33 #define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
34 #define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us, default */
35 #define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us, default */
36 #define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
37
38 #define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
39
40 #ifndef BMAC_DUP_TO_REMOVE
41 #define WLC_RM_WAIT_TX_SUSPEND 4 /* Wait Tx Suspend */
42
43 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
44
45 #endif /* BMAC_DUP_TO_REMOVE */
46
47 #define DMAREG(wlc_hw, direction, fifonum) \
48 ((direction == DMA_TX) ? \
49 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
50 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
51
52 #define APHY_SLOT_TIME 9
53 #define BPHY_SLOT_TIME 20
54
55 /*
56 * The following table lists the buffer memory allocated to xmt fifos in HW.
57 * the size is in units of 256bytes(one block), total size is HW dependent
58 * ucode has default fifo partition, sw can overwrite if necessary
59 *
60 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
61 * the twiki is updated before making changes.
62 */
63
64 #define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */
65
66 static u16 xmtfifo_sz[][NFIFO] = {
67 {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
68 {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
69 {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
70 {20, 192, 192, 21, 17, 5}, /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
71 {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
72 };
73
74 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
75 static void wlc_coreinit(struct wlc_info *wlc);
76
77 /* used by wlc_wakeucode_init() */
78 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
79 const struct d11init *inits);
80 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
81 const uint nbytes);
82 static void wlc_ucode_download(struct wlc_hw_info *wlc);
83 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
84
85 /* used by wlc_dpc() */
86 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
87 u32 s2);
88 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
89 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
90
91 /* used by wlc_down() */
92 static void wlc_flushqueues(struct wlc_info *wlc);
93
94 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
95 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
96 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
97 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
98 uint tx_fifo);
99 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
100 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
101
102 /* Low Level Prototypes */
103 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
104 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
105 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
106 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
107 u32 sel);
108 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
109 u16 v, u32 sel);
110 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
111 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
112 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
113 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
114 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
115 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
116 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
117 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
118 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
119 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
120 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
121 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
122 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
123 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
124 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
125 static void wlc_gpio_init(struct wlc_info *wlc);
126 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
127 int len);
128 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
129 int len);
130 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
131 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
132 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
133 chanspec_t chanspec);
134 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
135 bool shortslot);
136 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
137 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
138 u8 rate);
139
140 /* === Low Level functions === */
141
142 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
143 {
144 wlc_hw->shortslot = shortslot;
145
146 if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
147 wlc_suspend_mac_and_wait(wlc_hw->wlc);
148 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
149 wlc_enable_mac(wlc_hw->wlc);
150 }
151 }
152
153 /*
154 * Update the slot timing for standard 11b/g (20us slots)
155 * or shortslot 11g (9us slots)
156 * The PSM needs to be suspended for this call.
157 */
158 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
159 bool shortslot)
160 {
161 d11regs_t *regs;
162
163 regs = wlc_hw->regs;
164
165 if (shortslot) {
166 /* 11g short slot: 11a timing */
167 W_REG(&regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
168 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
169 } else {
170 /* 11g long slot: 11b timing */
171 W_REG(&regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
172 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
173 }
174 }
175
176 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
177 {
178 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
179
180 /* init microcode host flags */
181 wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
182
183 /* do band-specific ucode IHR, SHM, and SCR inits */
184 if (D11REV_IS(wlc_hw->corerev, 23)) {
185 if (WLCISNPHY(wlc_hw->band)) {
186 wlc_write_inits(wlc_hw, d11n0bsinitvals16);
187 } else {
188 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
189 " %d\n", __func__, wlc_hw->unit,
190 wlc_hw->corerev);
191 }
192 } else {
193 if (D11REV_IS(wlc_hw->corerev, 24)) {
194 if (WLCISLCNPHY(wlc_hw->band)) {
195 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
196 } else
197 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
198 " core rev %d\n", __func__,
199 wlc_hw->unit, wlc_hw->corerev);
200 } else {
201 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
202 __func__, wlc_hw->unit, wlc_hw->corerev);
203 }
204 }
205 }
206
207 /* switch to new band but leave it inactive */
208 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
209 {
210 struct wlc_hw_info *wlc_hw = wlc->hw;
211 u32 macintmask;
212
213 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
214
215 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
216
217 /* disable interrupts */
218 macintmask = brcms_intrsoff(wlc->wl);
219
220 /* radio off */
221 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
222
223 wlc_bmac_core_phy_clk(wlc_hw, OFF);
224
225 wlc_setxband(wlc_hw, bandunit);
226
227 return macintmask;
228 }
229
230 /* Process received frames */
231 /*
232 * Return true if more frames need to be processed. false otherwise.
233 * Param 'bound' indicates max. # frames to process before break out.
234 */
235 static bool
236 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
237 {
238 struct sk_buff *p;
239 struct sk_buff *head = NULL;
240 struct sk_buff *tail = NULL;
241 uint n = 0;
242 uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
243 wlc_d11rxhdr_t *wlc_rxhdr = NULL;
244
245 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
246 /* gather received frames */
247 while ((p = dma_rx(wlc_hw->di[fifo]))) {
248
249 if (!tail)
250 head = tail = p;
251 else {
252 tail->prev = p;
253 tail = p;
254 }
255
256 /* !give others some time to run! */
257 if (++n >= bound_limit)
258 break;
259 }
260
261 /* post more rbufs */
262 dma_rxfill(wlc_hw->di[fifo]);
263
264 /* process each frame */
265 while ((p = head) != NULL) {
266 head = head->prev;
267 p->prev = NULL;
268
269 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
270
271 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
272 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
273
274 wlc_recv(wlc_hw->wlc, p);
275 }
276
277 return n >= bound_limit;
278 }
279
280 /* second-level interrupt processing
281 * Return true if another dpc needs to be re-scheduled. false otherwise.
282 * Param 'bounded' indicates if applicable loops should be bounded.
283 */
284 bool wlc_dpc(struct wlc_info *wlc, bool bounded)
285 {
286 u32 macintstatus;
287 struct wlc_hw_info *wlc_hw = wlc->hw;
288 d11regs_t *regs = wlc_hw->regs;
289 bool fatal = false;
290 struct wiphy *wiphy = wlc->wiphy;
291
292 if (DEVICEREMOVED(wlc)) {
293 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
294 __func__);
295 brcms_down(wlc->wl);
296 return false;
297 }
298
299 /* grab and clear the saved software intstatus bits */
300 macintstatus = wlc->macintstatus;
301 wlc->macintstatus = 0;
302
303 BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
304 wlc_hw->unit, macintstatus);
305
306 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
307
308 /* BCN template is available */
309 /* ZZZ: Use AP_ACTIVE ? */
310 if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub))
311 && (macintstatus & MI_BCNTPL)) {
312 wlc_update_beacon(wlc);
313 }
314
315 /* PMQ entry addition */
316 if (macintstatus & MI_PMQ) {
317 }
318
319 /* tx status */
320 if (macintstatus & MI_TFS) {
321 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
322 wlc->macintstatus |= MI_TFS;
323 if (fatal) {
324 wiphy_err(wiphy, "MI_TFS: fatal\n");
325 goto fatal;
326 }
327 }
328
329 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
330 wlc_tbtt(wlc);
331
332 /* ATIM window end */
333 if (macintstatus & MI_ATIMWINEND) {
334 BCMMSG(wlc->wiphy, "end of ATIM window\n");
335 OR_REG(&regs->maccommand, wlc->qvalid);
336 wlc->qvalid = 0;
337 }
338
339 /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
340 if (macintstatus & MI_DMAINT) {
341 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
342 wlc->macintstatus |= MI_DMAINT;
343 }
344 }
345
346 /* TX FIFO suspend/flush completion */
347 if (macintstatus & MI_TXSTOP) {
348 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
349 /* wiphy_err(wiphy, "dpc: fifo_suspend_comlete\n"); */
350 }
351 }
352
353 /* noise sample collected */
354 if (macintstatus & MI_BG_NOISE) {
355 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
356 }
357
358 if (macintstatus & MI_GP0) {
359 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
360 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
361
362 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
363 __func__, wlc_hw->sih->chip,
364 wlc_hw->sih->chiprev);
365 /* big hammer */
366 brcms_init(wlc->wl);
367 }
368
369 /* gptimer timeout */
370 if (macintstatus & MI_TO) {
371 W_REG(&regs->gptimer, 0);
372 }
373
374 if (macintstatus & MI_RFDISABLE) {
375 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
376 " RF Disable Input\n", wlc_hw->unit);
377 brcms_rfkill_set_hw_state(wlc->wl);
378 }
379
380 /* send any enq'd tx packets. Just makes sure to jump start tx */
381 if (!pktq_empty(&wlc->pkt_queue->q))
382 wlc_send_q(wlc);
383
384 /* it isn't done and needs to be resched if macintstatus is non-zero */
385 return wlc->macintstatus != 0;
386
387 fatal:
388 brcms_init(wlc->wl);
389 return wlc->macintstatus != 0;
390 }
391
392 /* common low-level watchdog code */
393 void wlc_bmac_watchdog(void *arg)
394 {
395 struct wlc_info *wlc = (struct wlc_info *) arg;
396 struct wlc_hw_info *wlc_hw = wlc->hw;
397
398 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
399
400 if (!wlc_hw->up)
401 return;
402
403 /* increment second count */
404 wlc_hw->now++;
405
406 /* Check for FIFO error interrupts */
407 wlc_bmac_fifoerrors(wlc_hw);
408
409 /* make sure RX dma has buffers */
410 dma_rxfill(wlc->hw->di[RX_FIFO]);
411
412 wlc_phy_watchdog(wlc_hw->band->pi);
413 }
414
415 void
416 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
417 bool mute, struct txpwr_limits *txpwr)
418 {
419 uint bandunit;
420
421 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
422
423 wlc_hw->chanspec = chanspec;
424
425 /* Switch bands if necessary */
426 if (NBANDS_HW(wlc_hw) > 1) {
427 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
428 if (wlc_hw->band->bandunit != bandunit) {
429 /* wlc_bmac_setband disables other bandunit,
430 * use light band switch if not up yet
431 */
432 if (wlc_hw->up) {
433 wlc_phy_chanspec_radio_set(wlc_hw->
434 bandstate[bandunit]->
435 pi, chanspec);
436 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
437 } else {
438 wlc_setxband(wlc_hw, bandunit);
439 }
440 }
441 }
442
443 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
444
445 if (!wlc_hw->up) {
446 if (wlc_hw->clk)
447 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
448 chanspec);
449 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
450 } else {
451 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
452 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
453
454 /* Update muting of the channel */
455 wlc_bmac_mute(wlc_hw, mute, 0);
456 }
457 }
458
459 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
460 {
461 state->machwcap = wlc_hw->machwcap;
462
463 return 0;
464 }
465
466 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
467 {
468 uint i;
469 char name[8];
470 /* ucode host flag 2 needed for pio mode, independent of band and fifo */
471 u16 pio_mhf2 = 0;
472 struct wlc_hw_info *wlc_hw = wlc->hw;
473 uint unit = wlc_hw->unit;
474 wlc_tunables_t *tune = wlc->pub->tunables;
475 struct wiphy *wiphy = wlc->wiphy;
476
477 /* name and offsets for dma_attach */
478 snprintf(name, sizeof(name), "wl%d", unit);
479
480 if (wlc_hw->di[0] == 0) { /* Init FIFOs */
481 uint addrwidth;
482 int dma_attach_err = 0;
483 /* Find out the DMA addressing capability and let OS know
484 * All the channels within one DMA core have 'common-minimum' same
485 * capability
486 */
487 addrwidth =
488 dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
489
490 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
491 wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
492 "resources failed\n", unit);
493 return false;
494 }
495
496 /*
497 * FIFO 0
498 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
499 * RX: RX_FIFO (RX data packets)
500 */
501 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
502 (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
503 NULL), DMAREG(wlc_hw, DMA_RX, 0),
504 (wme ? tune->ntxd : 0), tune->nrxd,
505 tune->rxbufsz, -1, tune->nrxbufpost,
506 WL_HWRXOFF, &brcm_msg_level);
507 dma_attach_err |= (NULL == wlc_hw->di[0]);
508
509 /*
510 * FIFO 1
511 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
512 * (legacy) TX_DATA_FIFO (TX data packets)
513 * RX: UNUSED
514 */
515 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
516 DMAREG(wlc_hw, DMA_TX, 1), NULL,
517 tune->ntxd, 0, 0, -1, 0, 0,
518 &brcm_msg_level);
519 dma_attach_err |= (NULL == wlc_hw->di[1]);
520
521 /*
522 * FIFO 2
523 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
524 * RX: UNUSED
525 */
526 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
527 DMAREG(wlc_hw, DMA_TX, 2), NULL,
528 tune->ntxd, 0, 0, -1, 0, 0,
529 &brcm_msg_level);
530 dma_attach_err |= (NULL == wlc_hw->di[2]);
531 /*
532 * FIFO 3
533 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
534 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
535 */
536 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
537 DMAREG(wlc_hw, DMA_TX, 3),
538 NULL, tune->ntxd, 0, 0, -1,
539 0, 0, &brcm_msg_level);
540 dma_attach_err |= (NULL == wlc_hw->di[3]);
541 /* Cleaner to leave this as if with AP defined */
542
543 if (dma_attach_err) {
544 wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
545 "\n", unit);
546 return false;
547 }
548
549 /* get pointer to dma engine tx flow control variable */
550 for (i = 0; i < NFIFO; i++)
551 if (wlc_hw->di[i])
552 wlc_hw->txavail[i] =
553 (uint *) dma_getvar(wlc_hw->di[i],
554 "&txavail");
555 }
556
557 /* initial ucode host flags */
558 wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
559
560 return true;
561 }
562
563 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
564 {
565 uint j;
566
567 for (j = 0; j < NFIFO; j++) {
568 if (wlc_hw->di[j]) {
569 dma_detach(wlc_hw->di[j]);
570 wlc_hw->di[j] = NULL;
571 }
572 }
573 }
574
575 /* low level attach
576 * run backplane attach, init nvram
577 * run phy attach
578 * initialize software state for each core and band
579 * put the whole chip in reset(driver down state), no clock
580 */
581 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
582 bool piomode, void *regsva, uint bustype, void *btparam)
583 {
584 struct wlc_hw_info *wlc_hw;
585 d11regs_t *regs;
586 char *macaddr = NULL;
587 char *vars;
588 uint err = 0;
589 uint j;
590 bool wme = false;
591 shared_phy_params_t sha_params;
592 struct wiphy *wiphy = wlc->wiphy;
593
594 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
595 device);
596
597 wme = true;
598
599 wlc_hw = wlc->hw;
600 wlc_hw->wlc = wlc;
601 wlc_hw->unit = unit;
602 wlc_hw->band = wlc_hw->bandstate[0];
603 wlc_hw->_piomode = piomode;
604
605 /* populate struct wlc_hw_info with default values */
606 wlc_bmac_info_init(wlc_hw);
607
608 /*
609 * Do the hardware portion of the attach.
610 * Also initialize software state that depends on the particular hardware
611 * we are running.
612 */
613 wlc_hw->sih = ai_attach(regsva, bustype, btparam,
614 &wlc_hw->vars, &wlc_hw->vars_size);
615 if (wlc_hw->sih == NULL) {
616 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: si_attach failed\n",
617 unit);
618 err = 11;
619 goto fail;
620 }
621 vars = wlc_hw->vars;
622
623 /*
624 * Get vendid/devid nvram overwrites, which could be different
625 * than those the BIOS recognizes for devices on PCMCIA_BUS,
626 * SDIO_BUS, and SROMless devices on PCI_BUS.
627 */
628 #ifdef BCMBUSTYPE
629 bustype = BCMBUSTYPE;
630 #endif
631 if (bustype != SI_BUS) {
632 char *var;
633
634 var = getvar(vars, "vendid");
635 if (var) {
636 vendor = (u16) simple_strtoul(var, NULL, 0);
637 wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
638 vendor);
639 }
640 var = getvar(vars, "devid");
641 if (var) {
642 u16 devid = (u16) simple_strtoul(var, NULL, 0);
643 if (devid != 0xffff) {
644 device = devid;
645 wiphy_err(wiphy, "Overriding device id = 0x%x"
646 "\n", device);
647 }
648 }
649
650 /* verify again the device is supported */
651 if (!wlc_chipmatch(vendor, device)) {
652 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported "
653 "vendor/device (0x%x/0x%x)\n",
654 unit, vendor, device);
655 err = 12;
656 goto fail;
657 }
658 }
659
660 wlc_hw->vendorid = vendor;
661 wlc_hw->deviceid = device;
662
663 /* set bar0 window to point at D11 core */
664 wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
665 wlc_hw->corerev = ai_corerev(wlc_hw->sih);
666
667 regs = wlc_hw->regs;
668
669 wlc->regs = wlc_hw->regs;
670
671 /* validate chip, chiprev and corerev */
672 if (!wlc_isgoodchip(wlc_hw)) {
673 err = 13;
674 goto fail;
675 }
676
677 /* initialize power control registers */
678 ai_clkctl_init(wlc_hw->sih);
679
680 /* request fastclock and force fastclock for the rest of attach
681 * bring the d11 core out of reset.
682 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
683 * But it will be called again inside wlc_corereset, after d11 is out of reset.
684 */
685 wlc_clkctl_clk(wlc_hw, CLK_FAST);
686 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
687
688 if (!wlc_bmac_validate_chip_access(wlc_hw)) {
689 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: validate_chip_access "
690 "failed\n", unit);
691 err = 14;
692 goto fail;
693 }
694
695 /* get the board rev, used just below */
696 j = getintvar(vars, "boardrev");
697 /* promote srom boardrev of 0xFF to 1 */
698 if (j == BOARDREV_PROMOTABLE)
699 j = BOARDREV_PROMOTED;
700 wlc_hw->boardrev = (u16) j;
701 if (!wlc_validboardtype(wlc_hw)) {
702 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported Broadcom "
703 "board type (0x%x)" " or revision level (0x%x)\n",
704 unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
705 err = 15;
706 goto fail;
707 }
708 wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
709 wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
710 wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
711
712 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
713 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
714
715 if ((wlc_hw->sih->bustype == PCI_BUS)
716 && (ai_pci_war16165(wlc_hw->sih)))
717 wlc->war16165 = true;
718
719 /* check device id(srom, nvram etc.) to set bands */
720 if (wlc_hw->deviceid == BCM43224_D11N_ID ||
721 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1) {
722 /* Dualband boards */
723 wlc_hw->_nbands = 2;
724 } else
725 wlc_hw->_nbands = 1;
726
727 if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
728 wlc_hw->_nbands = 1;
729
730 /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
731 * init of these values
732 */
733 wlc->vendorid = wlc_hw->vendorid;
734 wlc->deviceid = wlc_hw->deviceid;
735 wlc->pub->sih = wlc_hw->sih;
736 wlc->pub->corerev = wlc_hw->corerev;
737 wlc->pub->sromrev = wlc_hw->sromrev;
738 wlc->pub->boardrev = wlc_hw->boardrev;
739 wlc->pub->boardflags = wlc_hw->boardflags;
740 wlc->pub->boardflags2 = wlc_hw->boardflags2;
741 wlc->pub->_nbands = wlc_hw->_nbands;
742
743 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
744
745 if (wlc_hw->physhim == NULL) {
746 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_shim_attach "
747 "failed\n", unit);
748 err = 25;
749 goto fail;
750 }
751
752 /* pass all the parameters to wlc_phy_shared_attach in one struct */
753 sha_params.sih = wlc_hw->sih;
754 sha_params.physhim = wlc_hw->physhim;
755 sha_params.unit = unit;
756 sha_params.corerev = wlc_hw->corerev;
757 sha_params.vars = vars;
758 sha_params.vid = wlc_hw->vendorid;
759 sha_params.did = wlc_hw->deviceid;
760 sha_params.chip = wlc_hw->sih->chip;
761 sha_params.chiprev = wlc_hw->sih->chiprev;
762 sha_params.chippkg = wlc_hw->sih->chippkg;
763 sha_params.sromrev = wlc_hw->sromrev;
764 sha_params.boardtype = wlc_hw->sih->boardtype;
765 sha_params.boardrev = wlc_hw->boardrev;
766 sha_params.boardvendor = wlc_hw->sih->boardvendor;
767 sha_params.boardflags = wlc_hw->boardflags;
768 sha_params.boardflags2 = wlc_hw->boardflags2;
769 sha_params.bustype = wlc_hw->sih->bustype;
770 sha_params.buscorerev = wlc_hw->sih->buscorerev;
771
772 /* alloc and save pointer to shared phy state area */
773 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
774 if (!wlc_hw->phy_sh) {
775 err = 16;
776 goto fail;
777 }
778
779 /* initialize software state for each core and band */
780 for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
781 /*
782 * band0 is always 2.4Ghz
783 * band1, if present, is 5Ghz
784 */
785
786 /* So if this is a single band 11a card, use band 1 */
787 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
788 j = BAND_5G_INDEX;
789
790 wlc_setxband(wlc_hw, j);
791
792 wlc_hw->band->bandunit = j;
793 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
794 wlc->band->bandunit = j;
795 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
796 wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
797
798 wlc_hw->machwcap = R_REG(&regs->machwcap);
799 wlc_hw->machwcap_backup = wlc_hw->machwcap;
800
801 /* init tx fifo size */
802 wlc_hw->xmtfifo_sz =
803 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
804
805 /* Get a phy for this band */
806 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
807 (void *)regs, wlc_bmac_bandtype(wlc_hw), vars,
808 wlc->wiphy);
809 if (wlc_hw->band->pi == NULL) {
810 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_"
811 "attach failed\n", unit);
812 err = 17;
813 goto fail;
814 }
815
816 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
817
818 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
819 &wlc_hw->band->phyrev,
820 &wlc_hw->band->radioid,
821 &wlc_hw->band->radiorev);
822 wlc_hw->band->abgphy_encore =
823 wlc_phy_get_encore(wlc_hw->band->pi);
824 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
825 wlc_hw->band->core_flags =
826 wlc_phy_get_coreflags(wlc_hw->band->pi);
827
828 /* verify good phy_type & supported phy revision */
829 if (WLCISNPHY(wlc_hw->band)) {
830 if (NCONF_HAS(wlc_hw->band->phyrev))
831 goto good_phy;
832 else
833 goto bad_phy;
834 } else if (WLCISLCNPHY(wlc_hw->band)) {
835 if (LCNCONF_HAS(wlc_hw->band->phyrev))
836 goto good_phy;
837 else
838 goto bad_phy;
839 } else {
840 bad_phy:
841 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: unsupported "
842 "phy type/rev (%d/%d)\n", unit,
843 wlc_hw->band->phytype, wlc_hw->band->phyrev);
844 err = 18;
845 goto fail;
846 }
847
848 good_phy:
849 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
850 * high level attach. However we can not make that change until all low level access
851 * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
852 * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
853 * low only init when all fns updated.
854 */
855 wlc->band->pi = wlc_hw->band->pi;
856 wlc->band->phytype = wlc_hw->band->phytype;
857 wlc->band->phyrev = wlc_hw->band->phyrev;
858 wlc->band->radioid = wlc_hw->band->radioid;
859 wlc->band->radiorev = wlc_hw->band->radiorev;
860
861 /* default contention windows size limits */
862 wlc_hw->band->CWmin = APHY_CWMIN;
863 wlc_hw->band->CWmax = PHY_CWMAX;
864
865 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
866 err = 19;
867 goto fail;
868 }
869 }
870
871 /* disable core to match driver "down" state */
872 wlc_coredisable(wlc_hw);
873
874 /* Match driver "down" state */
875 if (wlc_hw->sih->bustype == PCI_BUS)
876 ai_pci_down(wlc_hw->sih);
877
878 /* register sb interrupt callback functions */
879 ai_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
880 (void *)wlc_wlintrsrestore, NULL, wlc);
881
882 /* turn off pll and xtal to match driver "down" state */
883 wlc_bmac_xtal(wlc_hw, OFF);
884
885 /* *********************************************************************
886 * The hardware is in the DOWN state at this point. D11 core
887 * or cores are in reset with clocks off, and the board PLLs
888 * are off if possible.
889 *
890 * Beyond this point, wlc->sbclk == false and chip registers
891 * should not be touched.
892 *********************************************************************
893 */
894
895 /* init etheraddr state variables */
896 macaddr = wlc_get_macaddr(wlc_hw);
897 if (macaddr == NULL) {
898 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: macaddr not found\n",
899 unit);
900 err = 21;
901 goto fail;
902 }
903 brcmu_ether_atoe(macaddr, wlc_hw->etheraddr);
904 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
905 is_zero_ether_addr(wlc_hw->etheraddr)) {
906 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: bad macaddr %s\n",
907 unit, macaddr);
908 err = 22;
909 goto fail;
910 }
911
912 BCMMSG(wlc->wiphy,
913 "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
914 wlc_hw->deviceid, wlc_hw->_nbands,
915 wlc_hw->sih->boardtype, macaddr);
916
917 return err;
918
919 fail:
920 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: failed with err %d\n", unit,
921 err);
922 return err;
923 }
924
925 /*
926 * Initialize wlc_info default values ...
927 * may get overrides later in this function
928 * BMAC_NOTES, move low out and resolve the dangling ones
929 */
930 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
931 {
932 struct wlc_info *wlc = wlc_hw->wlc;
933
934 /* set default sw macintmask value */
935 wlc->defmacintmask = DEF_MACINTMASK;
936
937 /* various 802.11g modes */
938 wlc_hw->shortslot = false;
939
940 wlc_hw->SFBL = RETRY_SHORT_FB;
941 wlc_hw->LFBL = RETRY_LONG_FB;
942
943 /* default mac retry limits */
944 wlc_hw->SRL = RETRY_SHORT_DEF;
945 wlc_hw->LRL = RETRY_LONG_DEF;
946 wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
947 }
948
949 /*
950 * low level detach
951 */
952 int wlc_bmac_detach(struct wlc_info *wlc)
953 {
954 uint i;
955 struct wlc_hwband *band;
956 struct wlc_hw_info *wlc_hw = wlc->hw;
957 int callbacks;
958
959 callbacks = 0;
960
961 if (wlc_hw->sih) {
962 /* detach interrupt sync mechanism since interrupt is disabled and per-port
963 * interrupt object may has been freed. this must be done before sb core switch
964 */
965 ai_deregister_intr_callback(wlc_hw->sih);
966
967 if (wlc_hw->sih->bustype == PCI_BUS)
968 ai_pci_sleep(wlc_hw->sih);
969 }
970
971 wlc_bmac_detach_dmapio(wlc_hw);
972
973 band = wlc_hw->band;
974 for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
975 if (band->pi) {
976 /* Detach this band's phy */
977 wlc_phy_detach(band->pi);
978 band->pi = NULL;
979 }
980 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
981 }
982
983 /* Free shared phy state */
984 wlc_phy_shared_detach(wlc_hw->phy_sh);
985
986 wlc_phy_shim_detach(wlc_hw->physhim);
987
988 /* free vars */
989 kfree(wlc_hw->vars);
990 wlc_hw->vars = NULL;
991
992 if (wlc_hw->sih) {
993 ai_detach(wlc_hw->sih);
994 wlc_hw->sih = NULL;
995 }
996
997 return callbacks;
998
999 }
1000
1001 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1002 {
1003 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1004
1005 /* reset the core */
1006 if (!DEVICEREMOVED(wlc_hw->wlc))
1007 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1008
1009 /* purge the dma rings */
1010 wlc_flushqueues(wlc_hw->wlc);
1011
1012 wlc_reset_bmac_done(wlc_hw->wlc);
1013 }
1014
1015 void
1016 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1017 bool mute) {
1018 u32 macintmask;
1019 bool fastclk;
1020 struct wlc_info *wlc = wlc_hw->wlc;
1021
1022 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1023
1024 /* request FAST clock if not on */
1025 fastclk = wlc_hw->forcefastclk;
1026 if (!fastclk)
1027 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1028
1029 /* disable interrupts */
1030 macintmask = brcms_intrsoff(wlc->wl);
1031
1032 /* set up the specified band and chanspec */
1033 wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1034 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1035
1036 /* do one-time phy inits and calibration */
1037 wlc_phy_cal_init(wlc_hw->band->pi);
1038
1039 /* core-specific initialization */
1040 wlc_coreinit(wlc);
1041
1042 /* suspend the tx fifos and mute the phy for preism cac time */
1043 if (mute)
1044 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1045
1046 /* band-specific inits */
1047 wlc_bmac_bsinit(wlc, chanspec);
1048
1049 /* restore macintmask */
1050 brcms_intrsrestore(wlc->wl, macintmask);
1051
1052 /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1053 * and wlc_enable_mac() will clear this override bit.
1054 */
1055 mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1056
1057 /*
1058 * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1059 */
1060 wlc_hw->mac_suspend_depth = 1;
1061
1062 /* restore the clk */
1063 if (!fastclk)
1064 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1065 }
1066
1067 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1068 {
1069 uint coremask;
1070
1071 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1072
1073 /*
1074 * Enable pll and xtal, initialize the power control registers,
1075 * and force fastclock for the remainder of wlc_up().
1076 */
1077 wlc_bmac_xtal(wlc_hw, ON);
1078 ai_clkctl_init(wlc_hw->sih);
1079 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1080
1081 /*
1082 * Configure pci/pcmcia here instead of in wlc_attach()
1083 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1084 */
1085 coremask = (1 << wlc_hw->wlc->core->coreidx);
1086
1087 if (wlc_hw->sih->bustype == PCI_BUS)
1088 ai_pci_setup(wlc_hw->sih, coremask);
1089
1090 /*
1091 * Need to read the hwradio status here to cover the case where the system
1092 * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1093 */
1094 if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1095 /* put SB PCI in down state again */
1096 if (wlc_hw->sih->bustype == PCI_BUS)
1097 ai_pci_down(wlc_hw->sih);
1098 wlc_bmac_xtal(wlc_hw, OFF);
1099 return -ENOMEDIUM;
1100 }
1101
1102 if (wlc_hw->sih->bustype == PCI_BUS)
1103 ai_pci_up(wlc_hw->sih);
1104
1105 /* reset the d11 core */
1106 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1107
1108 return 0;
1109 }
1110
1111 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1112 {
1113 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1114
1115 wlc_hw->up = true;
1116 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1117
1118 /* FULLY enable dynamic power control and d11 core interrupt */
1119 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1120 brcms_intrson(wlc_hw->wlc->wl);
1121 return 0;
1122 }
1123
1124 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1125 {
1126 bool dev_gone;
1127 uint callbacks = 0;
1128
1129 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1130
1131 if (!wlc_hw->up)
1132 return callbacks;
1133
1134 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1135
1136 /* disable interrupts */
1137 if (dev_gone)
1138 wlc_hw->wlc->macintmask = 0;
1139 else {
1140 /* now disable interrupts */
1141 brcms_intrsoff(wlc_hw->wlc->wl);
1142
1143 /* ensure we're running on the pll clock again */
1144 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1145 }
1146 /* down phy at the last of this stage */
1147 callbacks += wlc_phy_down(wlc_hw->band->pi);
1148
1149 return callbacks;
1150 }
1151
1152 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1153 {
1154 uint callbacks = 0;
1155 bool dev_gone;
1156
1157 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1158
1159 if (!wlc_hw->up)
1160 return callbacks;
1161
1162 wlc_hw->up = false;
1163 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1164
1165 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1166
1167 if (dev_gone) {
1168 wlc_hw->sbclk = false;
1169 wlc_hw->clk = false;
1170 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1171
1172 /* reclaim any posted packets */
1173 wlc_flushqueues(wlc_hw->wlc);
1174 } else {
1175
1176 /* Reset and disable the core */
1177 if (ai_iscoreup(wlc_hw->sih)) {
1178 if (R_REG(&wlc_hw->regs->maccontrol) &
1179 MCTL_EN_MAC)
1180 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1181 callbacks += brcms_reset(wlc_hw->wlc->wl);
1182 wlc_coredisable(wlc_hw);
1183 }
1184
1185 /* turn off primary xtal and pll */
1186 if (!wlc_hw->noreset) {
1187 if (wlc_hw->sih->bustype == PCI_BUS)
1188 ai_pci_down(wlc_hw->sih);
1189 wlc_bmac_xtal(wlc_hw, OFF);
1190 }
1191 }
1192
1193 return callbacks;
1194 }
1195
1196 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1197 {
1198 /* delay before first read of ucode state */
1199 udelay(40);
1200
1201 /* wait until ucode is no longer asleep */
1202 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1203 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1204 }
1205
1206 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1207 {
1208 memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1209 }
1210
1211 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1212 {
1213 return wlc_hw->band->bandtype;
1214 }
1215
1216 /* control chip clock to save power, enable dynamic clock or force fast clock */
1217 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1218 {
1219 if (PMUCTL_ENAB(wlc_hw->sih)) {
1220 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1221 * but mac core will still run on ALP(not HT) when it enters powersave mode,
1222 * which means the FCA bit may not be set.
1223 * should wakeup mac if driver wants it to run on HT.
1224 */
1225
1226 if (wlc_hw->clk) {
1227 if (mode == CLK_FAST) {
1228 OR_REG(&wlc_hw->regs->clk_ctl_st,
1229 CCS_FORCEHT);
1230
1231 udelay(64);
1232
1233 SPINWAIT(((R_REG
1234 (&wlc_hw->regs->
1235 clk_ctl_st) & CCS_HTAVAIL) == 0),
1236 PMU_MAX_TRANSITION_DLY);
1237 WARN_ON(!(R_REG
1238 (&wlc_hw->regs->
1239 clk_ctl_st) & CCS_HTAVAIL));
1240 } else {
1241 if ((wlc_hw->sih->pmurev == 0) &&
1242 (R_REG
1243 (&wlc_hw->regs->
1244 clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1245 SPINWAIT(((R_REG
1246 (&wlc_hw->regs->
1247 clk_ctl_st) & CCS_HTAVAIL)
1248 == 0),
1249 PMU_MAX_TRANSITION_DLY);
1250 AND_REG(&wlc_hw->regs->clk_ctl_st,
1251 ~CCS_FORCEHT);
1252 }
1253 }
1254 wlc_hw->forcefastclk = (mode == CLK_FAST);
1255 } else {
1256
1257 /* old chips w/o PMU, force HT through cc,
1258 * then use FCA to verify mac is running fast clock
1259 */
1260
1261 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1262
1263 /* check fast clock is available (if core is not in reset) */
1264 if (wlc_hw->forcefastclk && wlc_hw->clk)
1265 WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
1266 SISF_FCLKA));
1267
1268 /* keep the ucode wake bit on if forcefastclk is on
1269 * since we do not want ucode to put us back to slow clock
1270 * when it dozes for PM mode.
1271 * Code below matches the wake override bit with current forcefastclk state
1272 * Only setting bit in wake_override instead of waking ucode immediately
1273 * since old code (wlc.c 1.4499) had this behavior. Older code set
1274 * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1275 * (protected by an up check) was executed just below.
1276 */
1277 if (wlc_hw->forcefastclk)
1278 mboolset(wlc_hw->wake_override,
1279 WLC_WAKE_OVERRIDE_FORCEFAST);
1280 else
1281 mboolclr(wlc_hw->wake_override,
1282 WLC_WAKE_OVERRIDE_FORCEFAST);
1283 }
1284 }
1285
1286 /* set initial host flags value */
1287 static void
1288 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1289 {
1290 struct wlc_hw_info *wlc_hw = wlc->hw;
1291
1292 memset(mhfs, 0, MHFMAX * sizeof(u16));
1293
1294 mhfs[MHF2] |= mhf2_init;
1295
1296 /* prohibit use of slowclock on multifunction boards */
1297 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1298 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1299
1300 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1301 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1302 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1303 }
1304 }
1305
1306 /* set or clear ucode host flag bits
1307 * it has an optimization for no-change write
1308 * it only writes through shared memory when the core has clock;
1309 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1310 *
1311 *
1312 * bands values are: WLC_BAND_AUTO <--- Current band only
1313 * WLC_BAND_5G <--- 5G band only
1314 * WLC_BAND_2G <--- 2G band only
1315 * WLC_BAND_ALL <--- All bands
1316 */
1317 void
1318 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1319 int bands)
1320 {
1321 u16 save;
1322 u16 addr[MHFMAX] = {
1323 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1324 M_HOST_FLAGS5
1325 };
1326 struct wlc_hwband *band;
1327
1328 if ((val & ~mask) || idx >= MHFMAX)
1329 return; /* error condition */
1330
1331 switch (bands) {
1332 /* Current band only or all bands,
1333 * then set the band to current band
1334 */
1335 case WLC_BAND_AUTO:
1336 case WLC_BAND_ALL:
1337 band = wlc_hw->band;
1338 break;
1339 case WLC_BAND_5G:
1340 band = wlc_hw->bandstate[BAND_5G_INDEX];
1341 break;
1342 case WLC_BAND_2G:
1343 band = wlc_hw->bandstate[BAND_2G_INDEX];
1344 break;
1345 default:
1346 band = NULL; /* error condition */
1347 }
1348
1349 if (band) {
1350 save = band->mhfs[idx];
1351 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1352
1353 /* optimization: only write through if changed, and
1354 * changed band is the current band
1355 */
1356 if (wlc_hw->clk && (band->mhfs[idx] != save)
1357 && (band == wlc_hw->band))
1358 wlc_bmac_write_shm(wlc_hw, addr[idx],
1359 (u16) band->mhfs[idx]);
1360 }
1361
1362 if (bands == WLC_BAND_ALL) {
1363 wlc_hw->bandstate[0]->mhfs[idx] =
1364 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1365 wlc_hw->bandstate[1]->mhfs[idx] =
1366 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1367 }
1368 }
1369
1370 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1371 {
1372 struct wlc_hwband *band;
1373
1374 if (idx >= MHFMAX)
1375 return 0; /* error condition */
1376 switch (bands) {
1377 case WLC_BAND_AUTO:
1378 band = wlc_hw->band;
1379 break;
1380 case WLC_BAND_5G:
1381 band = wlc_hw->bandstate[BAND_5G_INDEX];
1382 break;
1383 case WLC_BAND_2G:
1384 band = wlc_hw->bandstate[BAND_2G_INDEX];
1385 break;
1386 default:
1387 band = NULL; /* error condition */
1388 }
1389
1390 if (!band)
1391 return 0;
1392
1393 return band->mhfs[idx];
1394 }
1395
1396 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1397 {
1398 u8 idx;
1399 u16 addr[] = {
1400 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1401 M_HOST_FLAGS5
1402 };
1403
1404 for (idx = 0; idx < MHFMAX; idx++) {
1405 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1406 }
1407 }
1408
1409 /* set the maccontrol register to desired reset state and
1410 * initialize the sw cache of the register
1411 */
1412 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1413 {
1414 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1415 wlc_hw->maccontrol = 0;
1416 wlc_hw->suspended_fifos = 0;
1417 wlc_hw->wake_override = 0;
1418 wlc_hw->mute_override = 0;
1419 wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1420 }
1421
1422 /* set or clear maccontrol bits */
1423 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1424 {
1425 u32 maccontrol;
1426 u32 new_maccontrol;
1427
1428 if (val & ~mask)
1429 return; /* error condition */
1430 maccontrol = wlc_hw->maccontrol;
1431 new_maccontrol = (maccontrol & ~mask) | val;
1432
1433 /* if the new maccontrol value is the same as the old, nothing to do */
1434 if (new_maccontrol == maccontrol)
1435 return;
1436
1437 /* something changed, cache the new value */
1438 wlc_hw->maccontrol = new_maccontrol;
1439
1440 /* write the new values with overrides applied */
1441 wlc_mctrl_write(wlc_hw);
1442 }
1443
1444 /* write the software state of maccontrol and overrides to the maccontrol register */
1445 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1446 {
1447 u32 maccontrol = wlc_hw->maccontrol;
1448
1449 /* OR in the wake bit if overridden */
1450 if (wlc_hw->wake_override)
1451 maccontrol |= MCTL_WAKE;
1452
1453 /* set AP and INFRA bits for mute if needed */
1454 if (wlc_hw->mute_override) {
1455 maccontrol &= ~(MCTL_AP);
1456 maccontrol |= MCTL_INFRA;
1457 }
1458
1459 W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1460 }
1461
1462 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1463 {
1464 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1465 mboolset(wlc_hw->wake_override, override_bit);
1466 return;
1467 }
1468
1469 mboolset(wlc_hw->wake_override, override_bit);
1470
1471 wlc_mctrl_write(wlc_hw);
1472 wlc_bmac_wait_for_wake(wlc_hw);
1473
1474 return;
1475 }
1476
1477 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1478 {
1479 mboolclr(wlc_hw->wake_override, override_bit);
1480
1481 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1482 return;
1483
1484 wlc_mctrl_write(wlc_hw);
1485
1486 return;
1487 }
1488
1489 /* When driver needs ucode to stop beaconing, it has to make sure that
1490 * MCTL_AP is clear and MCTL_INFRA is set
1491 * Mode MCTL_AP MCTL_INFRA
1492 * AP 1 1
1493 * STA 0 1 <--- This will ensure no beacons
1494 * IBSS 0 0
1495 */
1496 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1497 {
1498 wlc_hw->mute_override = 1;
1499
1500 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1501 * override, then there is no change to write
1502 */
1503 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1504 return;
1505
1506 wlc_mctrl_write(wlc_hw);
1507
1508 return;
1509 }
1510
1511 /* Clear the override on AP and INFRA bits */
1512 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1513 {
1514 if (wlc_hw->mute_override == 0)
1515 return;
1516
1517 wlc_hw->mute_override = 0;
1518
1519 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1520 * override, then there is no change to write
1521 */
1522 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1523 return;
1524
1525 wlc_mctrl_write(wlc_hw);
1526 }
1527
1528 /*
1529 * Write a MAC address to the given match reg offset in the RXE match engine.
1530 */
1531 void
1532 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1533 const u8 *addr)
1534 {
1535 d11regs_t *regs;
1536 u16 mac_l;
1537 u16 mac_m;
1538 u16 mac_h;
1539
1540 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: wlc_bmac_set_addrmatch\n",
1541 wlc_hw->unit);
1542
1543 regs = wlc_hw->regs;
1544 mac_l = addr[0] | (addr[1] << 8);
1545 mac_m = addr[2] | (addr[3] << 8);
1546 mac_h = addr[4] | (addr[5] << 8);
1547
1548 /* enter the MAC addr into the RXE match registers */
1549 W_REG(&regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1550 W_REG(&regs->rcm_mat_data, mac_l);
1551 W_REG(&regs->rcm_mat_data, mac_m);
1552 W_REG(&regs->rcm_mat_data, mac_h);
1553
1554 }
1555
1556 void
1557 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1558 void *buf)
1559 {
1560 d11regs_t *regs;
1561 u32 word;
1562 bool be_bit;
1563 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1564
1565 regs = wlc_hw->regs;
1566 W_REG(&regs->tplatewrptr, offset);
1567
1568 /* if MCTL_BIGEND bit set in mac control register,
1569 * the chip swaps data in fifo, as well as data in
1570 * template ram
1571 */
1572 be_bit = (R_REG(&regs->maccontrol) & MCTL_BIGEND) != 0;
1573
1574 while (len > 0) {
1575 memcpy(&word, buf, sizeof(u32));
1576
1577 if (be_bit)
1578 word = cpu_to_be32(word);
1579 else
1580 word = cpu_to_le32(word);
1581
1582 W_REG(&regs->tplatewrdata, word);
1583
1584 buf = (u8 *) buf + sizeof(u32);
1585 len -= sizeof(u32);
1586 }
1587 }
1588
1589 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1590 {
1591 wlc_hw->band->CWmin = newmin;
1592
1593 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1594 (void)R_REG(&wlc_hw->regs->objaddr);
1595 W_REG(&wlc_hw->regs->objdata, newmin);
1596 }
1597
1598 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1599 {
1600 wlc_hw->band->CWmax = newmax;
1601
1602 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1603 (void)R_REG(&wlc_hw->regs->objaddr);
1604 W_REG(&wlc_hw->regs->objdata, newmax);
1605 }
1606
1607 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1608 {
1609 bool fastclk;
1610
1611 /* request FAST clock if not on */
1612 fastclk = wlc_hw->forcefastclk;
1613 if (!fastclk)
1614 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1615
1616 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1617
1618 wlc_bmac_phy_reset(wlc_hw);
1619 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1620
1621 /* restore the clk */
1622 if (!fastclk)
1623 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1624 }
1625
1626 static void
1627 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1628 {
1629 d11regs_t *regs = wlc_hw->regs;
1630
1631 wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1632 bcn);
1633 /* write beacon length to SCR */
1634 wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1635 /* mark beacon0 valid */
1636 OR_REG(&regs->maccommand, MCMD_BCN0VLD);
1637 }
1638
1639 static void
1640 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1641 {
1642 d11regs_t *regs = wlc_hw->regs;
1643
1644 wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1645 bcn);
1646 /* write beacon length to SCR */
1647 wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1648 /* mark beacon1 valid */
1649 OR_REG(&regs->maccommand, MCMD_BCN1VLD);
1650 }
1651
1652 /* mac is assumed to be suspended at this point */
1653 void
1654 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1655 bool both)
1656 {
1657 d11regs_t *regs = wlc_hw->regs;
1658
1659 if (both) {
1660 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1661 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1662 } else {
1663 /* bcn 0 */
1664 if (!(R_REG(&regs->maccommand) & MCMD_BCN0VLD))
1665 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1666 /* bcn 1 */
1667 else if (!
1668 (R_REG(&regs->maccommand) & MCMD_BCN1VLD))
1669 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1670 }
1671 }
1672
1673 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1674 {
1675 u16 v;
1676 struct wlc_info *wlc = wlc_hw->wlc;
1677 /* update SYNTHPU_DLY */
1678
1679 if (WLCISLCNPHY(wlc->band)) {
1680 v = SYNTHPU_DLY_LPPHY_US;
1681 } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1682 v = SYNTHPU_DLY_NPHY_US;
1683 } else {
1684 v = SYNTHPU_DLY_BPHY_US;
1685 }
1686
1687 wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1688 }
1689
1690 /* band-specific init */
1691 static void
1692 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1693 {
1694 struct wlc_hw_info *wlc_hw = wlc->hw;
1695
1696 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1697 wlc_hw->band->bandunit);
1698
1699 wlc_ucode_bsinit(wlc_hw);
1700
1701 wlc_phy_init(wlc_hw->band->pi, chanspec);
1702
1703 wlc_ucode_txant_set(wlc_hw);
1704
1705 /* cwmin is band-specific, update hardware with value for current band */
1706 wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1707 wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1708
1709 wlc_bmac_update_slot_timing(wlc_hw,
1710 BAND_5G(wlc_hw->band->
1711 bandtype) ? true : wlc_hw->
1712 shortslot);
1713
1714 /* write phytype and phyvers */
1715 wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1716 wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1717
1718 /* initialize the txphyctl1 rate table since shmem is shared between bands */
1719 wlc_upd_ofdm_pctl1_table(wlc_hw);
1720
1721 wlc_bmac_upd_synthpu(wlc_hw);
1722 }
1723
1724 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1725 {
1726 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
1727
1728 wlc_hw->phyclk = clk;
1729
1730 if (OFF == clk) { /* clear gmode bit, put phy into reset */
1731
1732 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1733 (SICF_PRST | SICF_FGC));
1734 udelay(1);
1735 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1736 udelay(1);
1737
1738 } else { /* take phy out of reset */
1739
1740 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1741 udelay(1);
1742 ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1743 udelay(1);
1744
1745 }
1746 }
1747
1748 /* Perform a soft reset of the PHY PLL */
1749 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1750 {
1751 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1752
1753 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1754 offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1755 udelay(1);
1756 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1757 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1758 udelay(1);
1759 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1760 offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1761 udelay(1);
1762 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1763 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1764 udelay(1);
1765 }
1766
1767 /* light way to turn on phy clock without reset for NPHY only
1768 * refer to wlc_bmac_core_phy_clk for full version
1769 */
1770 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1771 {
1772 /* support(necessary for NPHY and HYPHY) only */
1773 if (!WLCISNPHY(wlc_hw->band))
1774 return;
1775
1776 if (ON == clk)
1777 ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1778 else
1779 ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1780
1781 }
1782
1783 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1784 {
1785 if (ON == clk)
1786 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1787 else
1788 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1789 }
1790
1791 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1792 {
1793 wlc_phy_t *pih = wlc_hw->band->pi;
1794 u32 phy_bw_clkbits;
1795 bool phy_in_reset = false;
1796
1797 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1798
1799 if (pih == NULL)
1800 return;
1801
1802 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1803
1804 /* Specific reset sequence required for NPHY rev 3 and 4 */
1805 if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1806 NREV_LE(wlc_hw->band->phyrev, 4)) {
1807 /* Set the PHY bandwidth */
1808 ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1809
1810 udelay(1);
1811
1812 /* Perform a soft reset of the PHY PLL */
1813 wlc_bmac_core_phypll_reset(wlc_hw);
1814
1815 /* reset the PHY */
1816 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1817 (SICF_PRST | SICF_PCLKE));
1818 phy_in_reset = true;
1819 } else {
1820
1821 ai_core_cflags(wlc_hw->sih,
1822 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1823 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1824 }
1825
1826 udelay(2);
1827 wlc_bmac_core_phy_clk(wlc_hw, ON);
1828
1829 if (pih)
1830 wlc_phy_anacore(pih, ON);
1831 }
1832
1833 /* switch to and initialize new band */
1834 static void
1835 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
1836 chanspec_t chanspec) {
1837 struct wlc_info *wlc = wlc_hw->wlc;
1838 u32 macintmask;
1839
1840 /* Enable the d11 core before accessing it */
1841 if (!ai_iscoreup(wlc_hw->sih)) {
1842 ai_core_reset(wlc_hw->sih, 0, 0);
1843 wlc_mctrl_reset(wlc_hw);
1844 }
1845
1846 macintmask = wlc_setband_inact(wlc, bandunit);
1847
1848 if (!wlc_hw->up)
1849 return;
1850
1851 wlc_bmac_core_phy_clk(wlc_hw, ON);
1852
1853 /* band-specific initializations */
1854 wlc_bmac_bsinit(wlc, chanspec);
1855
1856 /*
1857 * If there are any pending software interrupt bits,
1858 * then replace these with a harmless nonzero value
1859 * so wlc_dpc() will re-enable interrupts when done.
1860 */
1861 if (wlc->macintstatus)
1862 wlc->macintstatus = MI_DMAINT;
1863
1864 /* restore macintmask */
1865 brcms_intrsrestore(wlc->wl, macintmask);
1866
1867 /* ucode should still be suspended.. */
1868 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
1869 }
1870
1871 /* low-level band switch utility routine */
1872 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
1873 {
1874 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1875 bandunit);
1876
1877 wlc_hw->band = wlc_hw->bandstate[bandunit];
1878
1879 /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
1880 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
1881
1882 /* set gmode core flag */
1883 if (wlc_hw->sbclk && !wlc_hw->noreset) {
1884 ai_core_cflags(wlc_hw->sih, SICF_GMODE,
1885 ((bandunit == 0) ? SICF_GMODE : 0));
1886 }
1887 }
1888
1889 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
1890 {
1891
1892 /* reject unsupported corerev */
1893 if (!VALID_COREREV(wlc_hw->corerev)) {
1894 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1895 wlc_hw->corerev);
1896 return false;
1897 }
1898
1899 return true;
1900 }
1901
1902 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
1903 {
1904 bool goodboard = true;
1905 uint boardrev = wlc_hw->boardrev;
1906
1907 if (boardrev == 0)
1908 goodboard = false;
1909 else if (boardrev > 0xff) {
1910 uint brt = (boardrev & 0xf000) >> 12;
1911 uint b0 = (boardrev & 0xf00) >> 8;
1912 uint b1 = (boardrev & 0xf0) >> 4;
1913 uint b2 = boardrev & 0xf;
1914
1915 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1916 || (b2 > 9))
1917 goodboard = false;
1918 }
1919
1920 if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
1921 return goodboard;
1922
1923 return goodboard;
1924 }
1925
1926 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
1927 {
1928 const char *varname = "macaddr";
1929 char *macaddr;
1930
1931 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1932 macaddr = getvar(wlc_hw->vars, varname);
1933 if (macaddr != NULL)
1934 return macaddr;
1935
1936 if (NBANDS_HW(wlc_hw) > 1)
1937 varname = "et1macaddr";
1938 else
1939 varname = "il0macaddr";
1940
1941 macaddr = getvar(wlc_hw->vars, varname);
1942 if (macaddr == NULL) {
1943 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
1944 "getvar(%s) not found\n", wlc_hw->unit, varname);
1945 }
1946
1947 return macaddr;
1948 }
1949
1950 /*
1951 * Return true if radio is disabled, otherwise false.
1952 * hw radio disable signal is an external pin, users activate it asynchronously
1953 * this function could be called when driver is down and w/o clock
1954 * it operates on different registers depending on corerev and boardflag.
1955 */
1956 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
1957 {
1958 bool v, clk, xtal;
1959 u32 resetbits = 0, flags = 0;
1960
1961 xtal = wlc_hw->sbclk;
1962 if (!xtal)
1963 wlc_bmac_xtal(wlc_hw, ON);
1964
1965 /* may need to take core out of reset first */
1966 clk = wlc_hw->clk;
1967 if (!clk) {
1968 /*
1969 * mac no longer enables phyclk automatically when driver
1970 * accesses phyreg throughput mac. This can be skipped since
1971 * only mac reg is accessed below
1972 */
1973 flags |= SICF_PCLKE;
1974
1975 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
1976 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
1977 (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
1978 (wlc_hw->sih->chip == BCM43421_CHIP_ID))
1979 wlc_hw->regs =
1980 (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
1981 0);
1982 ai_core_reset(wlc_hw->sih, flags, resetbits);
1983 wlc_mctrl_reset(wlc_hw);
1984 }
1985
1986 v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
1987
1988 /* put core back into reset */
1989 if (!clk)
1990 ai_core_disable(wlc_hw->sih, 0);
1991
1992 if (!xtal)
1993 wlc_bmac_xtal(wlc_hw, OFF);
1994
1995 return v;
1996 }
1997
1998 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
1999 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2000 {
2001 if (wlc_hw->wlc->pub->hw_up)
2002 return;
2003
2004 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2005
2006 /*
2007 * Enable pll and xtal, initialize the power control registers,
2008 * and force fastclock for the remainder of wlc_up().
2009 */
2010 wlc_bmac_xtal(wlc_hw, ON);
2011 ai_clkctl_init(wlc_hw->sih);
2012 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2013
2014 if (wlc_hw->sih->bustype == PCI_BUS) {
2015 ai_pci_fixcfg(wlc_hw->sih);
2016
2017 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2018 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2019 (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2020 (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2021 wlc_hw->regs =
2022 (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2023 0);
2024 }
2025
2026 /* Inform phy that a POR reset has occurred so it does a complete phy init */
2027 wlc_phy_por_inform(wlc_hw->band->pi);
2028
2029 wlc_hw->ucode_loaded = false;
2030 wlc_hw->wlc->pub->hw_up = true;
2031
2032 if ((wlc_hw->boardflags & BFL_FEM)
2033 && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2034 if (!
2035 (wlc_hw->boardrev >= 0x1250
2036 && (wlc_hw->boardflags & BFL_FEM_BT)))
2037 ai_epa_4313war(wlc_hw->sih);
2038 }
2039 }
2040
2041 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2042 {
2043 struct dma_pub *di = wlc_hw->di[fifo];
2044 return dma_rxreset(di);
2045 }
2046
2047 /* d11 core reset
2048 * ensure fask clock during reset
2049 * reset dma
2050 * reset d11(out of reset)
2051 * reset phy(out of reset)
2052 * clear software macintstatus for fresh new start
2053 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2054 */
2055 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2056 {
2057 d11regs_t *regs;
2058 uint i;
2059 bool fastclk;
2060 u32 resetbits = 0;
2061
2062 if (flags == WLC_USE_COREFLAGS)
2063 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2064
2065 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2066
2067 regs = wlc_hw->regs;
2068
2069 /* request FAST clock if not on */
2070 fastclk = wlc_hw->forcefastclk;
2071 if (!fastclk)
2072 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2073
2074 /* reset the dma engines except first time thru */
2075 if (ai_iscoreup(wlc_hw->sih)) {
2076 for (i = 0; i < NFIFO; i++)
2077 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2078 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2079 "dma_txreset[%d]: cannot stop dma\n",
2080 wlc_hw->unit, __func__, i);
2081 }
2082
2083 if ((wlc_hw->di[RX_FIFO])
2084 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2085 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2086 "[%d]: cannot stop dma\n",
2087 wlc_hw->unit, __func__, RX_FIFO);
2088 }
2089 }
2090 /* if noreset, just stop the psm and return */
2091 if (wlc_hw->noreset) {
2092 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2093 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2094 return;
2095 }
2096
2097 /*
2098 * mac no longer enables phyclk automatically when driver accesses
2099 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2100 * band->pi is invalid. need to enable PHY CLK
2101 */
2102 flags |= SICF_PCLKE;
2103
2104 /* reset the core
2105 * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2106 * is cleared by the core_reset. have to re-request it.
2107 * This adds some delay and we can optimize it by also requesting fastclk through
2108 * chipcommon during this period if necessary. But that has to work coordinate
2109 * with other driver like mips/arm since they may touch chipcommon as well.
2110 */
2111 wlc_hw->clk = false;
2112 ai_core_reset(wlc_hw->sih, flags, resetbits);
2113 wlc_hw->clk = true;
2114 if (wlc_hw->band && wlc_hw->band->pi)
2115 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2116
2117 wlc_mctrl_reset(wlc_hw);
2118
2119 if (PMUCTL_ENAB(wlc_hw->sih))
2120 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2121
2122 wlc_bmac_phy_reset(wlc_hw);
2123
2124 /* turn on PHY_PLL */
2125 wlc_bmac_core_phypll_ctl(wlc_hw, true);
2126
2127 /* clear sw intstatus */
2128 wlc_hw->wlc->macintstatus = 0;
2129
2130 /* restore the clk setting */
2131 if (!fastclk)
2132 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2133 }
2134
2135 /* txfifo sizes needs to be modified(increased) since the newer cores
2136 * have more memory.
2137 */
2138 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2139 {
2140 d11regs_t *regs = wlc_hw->regs;
2141 u16 fifo_nu;
2142 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2143 u16 txfifo_def, txfifo_def1;
2144 u16 txfifo_cmd;
2145
2146 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2147 txfifo_startblk = TXFIFO_START_BLK;
2148
2149 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2150 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2151
2152 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2153 txfifo_def = (txfifo_startblk & 0xff) |
2154 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2155 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2156 ((((txfifo_endblk -
2157 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2158 txfifo_cmd =
2159 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2160
2161 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2162 W_REG(&regs->xmtfifodef, txfifo_def);
2163 W_REG(&regs->xmtfifodef1, txfifo_def1);
2164
2165 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2166
2167 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2168 }
2169 /*
2170 * need to propagate to shm location to be in sync since ucode/hw won't
2171 * do this
2172 */
2173 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2174 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2175 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2176 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2177 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2178 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2179 xmtfifo_sz[TX_AC_BK_FIFO]));
2180 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2181 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2182 xmtfifo_sz[TX_BCMC_FIFO]));
2183 }
2184
2185 /* d11 core init
2186 * reset PSM
2187 * download ucode/PCM
2188 * let ucode run to suspended
2189 * download ucode inits
2190 * config other core registers
2191 * init dma
2192 */
2193 static void wlc_coreinit(struct wlc_info *wlc)
2194 {
2195 struct wlc_hw_info *wlc_hw = wlc->hw;
2196 d11regs_t *regs;
2197 u32 sflags;
2198 uint bcnint_us;
2199 uint i = 0;
2200 bool fifosz_fixup = false;
2201 int err = 0;
2202 u16 buf[NFIFO];
2203 struct wiphy *wiphy = wlc->wiphy;
2204
2205 regs = wlc_hw->regs;
2206
2207 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2208
2209 /* reset PSM */
2210 wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2211
2212 wlc_ucode_download(wlc_hw);
2213 /*
2214 * FIFOSZ fixup. driver wants to controls the fifo allocation.
2215 */
2216 fifosz_fixup = true;
2217
2218 /* let the PSM run to the suspended state, set mode to BSS STA */
2219 W_REG(&regs->macintstatus, -1);
2220 wlc_bmac_mctrl(wlc_hw, ~0,
2221 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2222
2223 /* wait for ucode to self-suspend after auto-init */
2224 SPINWAIT(((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0),
2225 1000 * 1000);
2226 if ((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0)
2227 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
2228 "suspend!\n", wlc_hw->unit);
2229
2230 wlc_gpio_init(wlc);
2231
2232 sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
2233
2234 if (D11REV_IS(wlc_hw->corerev, 23)) {
2235 if (WLCISNPHY(wlc_hw->band))
2236 wlc_write_inits(wlc_hw, d11n0initvals16);
2237 else
2238 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2239 " %d\n", __func__, wlc_hw->unit,
2240 wlc_hw->corerev);
2241 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2242 if (WLCISLCNPHY(wlc_hw->band)) {
2243 wlc_write_inits(wlc_hw, d11lcn0initvals24);
2244 } else {
2245 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2246 " %d\n", __func__, wlc_hw->unit,
2247 wlc_hw->corerev);
2248 }
2249 } else {
2250 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
2251 __func__, wlc_hw->unit, wlc_hw->corerev);
2252 }
2253
2254 /* For old ucode, txfifo sizes needs to be modified(increased) */
2255 if (fifosz_fixup == true) {
2256 wlc_corerev_fifofixup(wlc_hw);
2257 }
2258
2259 /* check txfifo allocations match between ucode and driver */
2260 buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2261 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2262 i = TX_AC_BE_FIFO;
2263 err = -1;
2264 }
2265 buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2266 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2267 i = TX_AC_VI_FIFO;
2268 err = -1;
2269 }
2270 buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2271 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2272 buf[TX_AC_BK_FIFO] &= 0xff;
2273 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2274 i = TX_AC_BK_FIFO;
2275 err = -1;
2276 }
2277 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2278 i = TX_AC_VO_FIFO;
2279 err = -1;
2280 }
2281 buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2282 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2283 buf[TX_BCMC_FIFO] &= 0xff;
2284 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2285 i = TX_BCMC_FIFO;
2286 err = -1;
2287 }
2288 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2289 i = TX_ATIM_FIFO;
2290 err = -1;
2291 }
2292 if (err != 0) {
2293 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
2294 " driver size %d index %d\n", buf[i],
2295 wlc_hw->xmtfifo_sz[i], i);
2296 }
2297
2298 /* make sure we can still talk to the mac */
2299 WARN_ON(R_REG(&regs->maccontrol) == 0xffffffff);
2300
2301 /* band-specific inits done by wlc_bsinit() */
2302
2303 /* Set up frame burst size and antenna swap threshold init values */
2304 wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2305 wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2306
2307 /* enable one rx interrupt per received frame */
2308 W_REG(&regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2309
2310 /* set the station mode (BSS STA) */
2311 wlc_bmac_mctrl(wlc_hw,
2312 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2313 (MCTL_INFRA | MCTL_DISCARD_PMQ));
2314
2315 /* set up Beacon interval */
2316 bcnint_us = 0x8000 << 10;
2317 W_REG(&regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2318 W_REG(&regs->tsf_cfpstart, bcnint_us);
2319 W_REG(&regs->macintstatus, MI_GP1);
2320
2321 /* write interrupt mask */
2322 W_REG(&regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2323
2324 /* allow the MAC to control the PHY clock (dynamic on/off) */
2325 wlc_bmac_macphyclk_set(wlc_hw, ON);
2326
2327 /* program dynamic clock control fast powerup delay register */
2328 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
2329 W_REG(&regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2330
2331 /* tell the ucode the corerev */
2332 wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2333
2334 /* tell the ucode MAC capabilities */
2335 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2336 (u16) (wlc_hw->machwcap & 0xffff));
2337 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2338 (u16) ((wlc_hw->
2339 machwcap >> 16) & 0xffff));
2340
2341 /* write retry limits to SCR, this done after PSM init */
2342 W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2343 (void)R_REG(&regs->objaddr);
2344 W_REG(&regs->objdata, wlc_hw->SRL);
2345 W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2346 (void)R_REG(&regs->objaddr);
2347 W_REG(&regs->objdata, wlc_hw->LRL);
2348
2349 /* write rate fallback retry limits */
2350 wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2351 wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2352
2353 AND_REG(&regs->ifs_ctl, 0x0FFF);
2354 W_REG(&regs->ifs_aifsn, EDCF_AIFSN_MIN);
2355
2356 /* dma initializations */
2357 wlc->txpend16165war = 0;
2358
2359 /* init the tx dma engines */
2360 for (i = 0; i < NFIFO; i++) {
2361 if (wlc_hw->di[i])
2362 dma_txinit(wlc_hw->di[i]);
2363 }
2364
2365 /* init the rx dma engine(s) and post receive buffers */
2366 dma_rxinit(wlc_hw->di[RX_FIFO]);
2367 dma_rxfill(wlc_hw->di[RX_FIFO]);
2368 }
2369
2370 /* This function is used for changing the tsf frac register
2371 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2372 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2373 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2374 * HTPHY Formula is 2^26/freq(MHz) e.g.
2375 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2376 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2377 * For spuron: 123MHz -> 2^26/123 = 545600.5
2378 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2379 * For spur off: 120MHz -> 2^26/120 = 559240.5
2380 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2381 */
2382
2383 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2384 {
2385 d11regs_t *regs;
2386 regs = wlc_hw->regs;
2387
2388 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2389 (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2390 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2391 W_REG(&regs->tsf_clk_frac_l, 0x2082);
2392 W_REG(&regs->tsf_clk_frac_h, 0x8);
2393 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2394 W_REG(&regs->tsf_clk_frac_l, 0x5341);
2395 W_REG(&regs->tsf_clk_frac_h, 0x8);
2396 } else { /* 120Mhz */
2397 W_REG(&regs->tsf_clk_frac_l, 0x8889);
2398 W_REG(&regs->tsf_clk_frac_h, 0x8);
2399 }
2400 } else if (WLCISLCNPHY(wlc_hw->band)) {
2401 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2402 W_REG(&regs->tsf_clk_frac_l, 0x7CE0);
2403 W_REG(&regs->tsf_clk_frac_h, 0xC);
2404 } else { /* 80Mhz */
2405 W_REG(&regs->tsf_clk_frac_l, 0xCCCD);
2406 W_REG(&regs->tsf_clk_frac_h, 0xC);
2407 }
2408 }
2409 }
2410
2411 /* Initialize GPIOs that are controlled by D11 core */
2412 static void wlc_gpio_init(struct wlc_info *wlc)
2413 {
2414 struct wlc_hw_info *wlc_hw = wlc->hw;
2415 d11regs_t *regs;
2416 u32 gc, gm;
2417
2418 regs = wlc_hw->regs;
2419
2420 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2421 wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2422
2423 /*
2424 * Common GPIO setup:
2425 * G0 = LED 0 = WLAN Activity
2426 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2427 * G2 = LED 2 = WLAN 5 GHz Radio State
2428 * G4 = radio disable input (HI enabled, LO disabled)
2429 */
2430
2431 gc = gm = 0;
2432
2433 /* Allocate GPIOs for mimo antenna diversity feature */
2434 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2435 /* Enable antenna diversity, use 2x3 mode */
2436 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2437 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2438 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2439 MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2440
2441 /* init superswitch control */
2442 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2443
2444 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2445 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2446 /*
2447 * The board itself is powered by these GPIOs
2448 * (when not sending pattern) so set them high
2449 */
2450 OR_REG(&regs->psm_gpio_oe,
2451 (BOARD_GPIO_12 | BOARD_GPIO_13));
2452 OR_REG(&regs->psm_gpio_out,
2453 (BOARD_GPIO_12 | BOARD_GPIO_13));
2454
2455 /* Enable antenna diversity, use 2x4 mode */
2456 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2457 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2458 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2459 WLC_BAND_ALL);
2460
2461 /* Configure the desired clock to be 4Mhz */
2462 wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2463 ANTSEL_CLKDIV_4MHZ);
2464 }
2465
2466 /* gpio 9 controls the PA. ucode is responsible for wiggling out and oe */
2467 if (wlc_hw->boardflags & BFL_PACTRL)
2468 gm |= gc |= BOARD_GPIO_PACTRL;
2469
2470 /* apply to gpiocontrol register */
2471 ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2472 }
2473
2474 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2475 {
2476 struct wlc_info *wlc;
2477 wlc = wlc_hw->wlc;
2478
2479 if (wlc_hw->ucode_loaded)
2480 return;
2481
2482 if (D11REV_IS(wlc_hw->corerev, 23)) {
2483 if (WLCISNPHY(wlc_hw->band)) {
2484 wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2485 bcm43xx_16_mimosz);
2486 wlc_hw->ucode_loaded = true;
2487 } else
2488 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2489 "corerev %d\n",
2490 __func__, wlc_hw->unit, wlc_hw->corerev);
2491 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2492 if (WLCISLCNPHY(wlc_hw->band)) {
2493 wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2494 bcm43xx_24_lcnsz);
2495 wlc_hw->ucode_loaded = true;
2496 } else {
2497 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2498 "corerev %d\n",
2499 __func__, wlc_hw->unit, wlc_hw->corerev);
2500 }
2501 }
2502 }
2503
2504 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2505 const uint nbytes) {
2506 d11regs_t *regs = wlc_hw->regs;
2507 uint i;
2508 uint count;
2509
2510 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2511
2512 count = (nbytes / sizeof(u32));
2513
2514 W_REG(&regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2515 (void)R_REG(&regs->objaddr);
2516 for (i = 0; i < count; i++)
2517 W_REG(&regs->objdata, ucode[i]);
2518 }
2519
2520 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
2521 const struct d11init *inits)
2522 {
2523 int i;
2524 volatile u8 *base;
2525
2526 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2527
2528 base = (volatile u8 *)wlc_hw->regs;
2529
2530 for (i = 0; inits[i].addr != 0xffff; i++) {
2531 if (inits[i].size == 2)
2532 W_REG((u16 *)(base + inits[i].addr),
2533 inits[i].value);
2534 else if (inits[i].size == 4)
2535 W_REG((u32 *)(base + inits[i].addr),
2536 inits[i].value);
2537 }
2538 }
2539
2540 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2541 {
2542 u16 phyctl;
2543 u16 phytxant = wlc_hw->bmac_phytxant;
2544 u16 mask = PHY_TXC_ANT_MASK;
2545
2546 /* set the Probe Response frame phy control word */
2547 phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2548 phyctl = (phyctl & ~mask) | phytxant;
2549 wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2550
2551 /* set the Response (ACK/CTS) frame phy control word */
2552 phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2553 phyctl = (phyctl & ~mask) | phytxant;
2554 wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2555 }
2556
2557 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2558 {
2559 /* update sw state */
2560 wlc_hw->bmac_phytxant = phytxant;
2561
2562 /* push to ucode if up */
2563 if (!wlc_hw->up)
2564 return;
2565 wlc_ucode_txant_set(wlc_hw);
2566
2567 }
2568
2569 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2570 {
2571 return (u16) wlc_hw->wlc->stf->txant;
2572 }
2573
2574 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2575 {
2576 wlc_hw->antsel_type = antsel_type;
2577
2578 /* Update the antsel type for phy module to use */
2579 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2580 }
2581
2582 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2583 {
2584 bool fatal = false;
2585 uint unit;
2586 uint intstatus, idx;
2587 d11regs_t *regs = wlc_hw->regs;
2588 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2589
2590 unit = wlc_hw->unit;
2591
2592 for (idx = 0; idx < NFIFO; idx++) {
2593 /* read intstatus register and ignore any non-error bits */
2594 intstatus =
2595 R_REG(&regs->intctrlregs[idx].intstatus) & I_ERRORS;
2596 if (!intstatus)
2597 continue;
2598
2599 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2600 unit, idx, intstatus);
2601
2602 if (intstatus & I_RO) {
2603 wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2604 "overflow\n", unit, idx);
2605 fatal = true;
2606 }
2607
2608 if (intstatus & I_PC) {
2609 wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2610 unit, idx);
2611 fatal = true;
2612 }
2613
2614 if (intstatus & I_PD) {
2615 wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2616 idx);
2617 fatal = true;
2618 }
2619
2620 if (intstatus & I_DE) {
2621 wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2622 "error\n", unit, idx);
2623 fatal = true;
2624 }
2625
2626 if (intstatus & I_RU) {
2627 wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2628 "underflow\n", idx, unit);
2629 }
2630
2631 if (intstatus & I_XU) {
2632 wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2633 "underflow\n", idx, unit);
2634 fatal = true;
2635 }
2636
2637 if (fatal) {
2638 wlc_fatal_error(wlc_hw->wlc); /* big hammer */
2639 break;
2640 } else
2641 W_REG(&regs->intctrlregs[idx].intstatus,
2642 intstatus);
2643 }
2644 }
2645
2646 void wlc_intrson(struct wlc_info *wlc)
2647 {
2648 struct wlc_hw_info *wlc_hw = wlc->hw;
2649 wlc->macintmask = wlc->defmacintmask;
2650 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2651 }
2652
2653 /* callback for siutils.c, which has only wlc handler, no wl
2654 * they both check up, not only because there is no need to off/restore d11 interrupt
2655 * but also because per-port code may require sync with valid interrupt.
2656 */
2657
2658 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2659 {
2660 if (!wlc->hw->up)
2661 return 0;
2662
2663 return brcms_intrsoff(wlc->wl);
2664 }
2665
2666 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2667 {
2668 if (!wlc->hw->up)
2669 return;
2670
2671 brcms_intrsrestore(wlc->wl, macintmask);
2672 }
2673
2674 u32 wlc_intrsoff(struct wlc_info *wlc)
2675 {
2676 struct wlc_hw_info *wlc_hw = wlc->hw;
2677 u32 macintmask;
2678
2679 if (!wlc_hw->clk)
2680 return 0;
2681
2682 macintmask = wlc->macintmask; /* isr can still happen */
2683
2684 W_REG(&wlc_hw->regs->macintmask, 0);
2685 (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2686 udelay(1); /* ensure int line is no longer driven */
2687 wlc->macintmask = 0;
2688
2689 /* return previous macintmask; resolve race between us and our isr */
2690 return wlc->macintstatus ? 0 : macintmask;
2691 }
2692
2693 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2694 {
2695 struct wlc_hw_info *wlc_hw = wlc->hw;
2696 if (!wlc_hw->clk)
2697 return;
2698
2699 wlc->macintmask = macintmask;
2700 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2701 }
2702
2703 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2704 {
2705 u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2706
2707 if (on) {
2708 /* suspend tx fifos */
2709 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2710 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2711 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2712 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2713
2714 /* zero the address match register so we do not send ACKs */
2715 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2716 null_ether_addr);
2717 } else {
2718 /* resume tx fifos */
2719 if (!wlc_hw->wlc->tx_suspended) {
2720 wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2721 }
2722 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2723 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2724 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2725
2726 /* Restore address */
2727 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2728 wlc_hw->etheraddr);
2729 }
2730
2731 wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2732
2733 if (on)
2734 wlc_ucode_mute_override_set(wlc_hw);
2735 else
2736 wlc_ucode_mute_override_clear(wlc_hw);
2737 }
2738
2739 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2740 {
2741 if (fifo >= NFIFO)
2742 return -EINVAL;
2743
2744 *blocks = wlc_hw->xmtfifo_sz[fifo];
2745
2746 return 0;
2747 }
2748
2749 /* wlc_bmac_tx_fifo_suspended:
2750 * Check the MAC's tx suspend status for a tx fifo.
2751 *
2752 * When the MAC acknowledges a tx suspend, it indicates that no more
2753 * packets will be transmitted out the radio. This is independent of
2754 * DMA channel suspension---the DMA may have finished suspending, or may still
2755 * be pulling data into a tx fifo, by the time the MAC acks the suspend
2756 * request.
2757 */
2758 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2759 {
2760 /* check that a suspend has been requested and is no longer pending */
2761
2762 /*
2763 * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2764 * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2765 * chnstatus register.
2766 * The tx fifo suspend completion is independent of the DMA suspend completion and
2767 * may be acked before or after the DMA is suspended.
2768 */
2769 if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2770 (R_REG(&wlc_hw->regs->chnstatus) &
2771 (1 << tx_fifo)) == 0)
2772 return true;
2773
2774 return false;
2775 }
2776
2777 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2778 {
2779 u8 fifo = 1 << tx_fifo;
2780
2781 /* Two clients of this code, 11h Quiet period and scanning. */
2782
2783 /* only suspend if not already suspended */
2784 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2785 return;
2786
2787 /* force the core awake only if not already */
2788 if (wlc_hw->suspended_fifos == 0)
2789 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2790
2791 wlc_hw->suspended_fifos |= fifo;
2792
2793 if (wlc_hw->di[tx_fifo]) {
2794 /* Suspending AMPDU transmissions in the middle can cause underflow
2795 * which may result in mismatch between ucode and driver
2796 * so suspend the mac before suspending the FIFO
2797 */
2798 if (WLC_PHY_11N_CAP(wlc_hw->band))
2799 wlc_suspend_mac_and_wait(wlc_hw->wlc);
2800
2801 dma_txsuspend(wlc_hw->di[tx_fifo]);
2802
2803 if (WLC_PHY_11N_CAP(wlc_hw->band))
2804 wlc_enable_mac(wlc_hw->wlc);
2805 }
2806 }
2807
2808 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2809 {
2810 /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2811 * here for PIO otherwise the watchdog will catch the inconsistency and fire
2812 */
2813 /* Two clients of this code, 11h Quiet period and scanning. */
2814 if (wlc_hw->di[tx_fifo])
2815 dma_txresume(wlc_hw->di[tx_fifo]);
2816
2817 /* allow core to sleep again */
2818 if (wlc_hw->suspended_fifos == 0)
2819 return;
2820 else {
2821 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2822 if (wlc_hw->suspended_fifos == 0)
2823 wlc_ucode_wake_override_clear(wlc_hw,
2824 WLC_WAKE_OVERRIDE_TXFIFO);
2825 }
2826 }
2827
2828 /*
2829 * Read and clear macintmask and macintstatus and intstatus registers.
2830 * This routine should be called with interrupts off
2831 * Return:
2832 * -1 if DEVICEREMOVED(wlc) evaluates to true;
2833 * 0 if the interrupt is not for us, or we are in some special cases;
2834 * device interrupt status bits otherwise.
2835 */
2836 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
2837 {
2838 struct wlc_hw_info *wlc_hw = wlc->hw;
2839 d11regs_t *regs = wlc_hw->regs;
2840 u32 macintstatus;
2841
2842 /* macintstatus includes a DMA interrupt summary bit */
2843 macintstatus = R_REG(&regs->macintstatus);
2844
2845 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2846 macintstatus);
2847
2848 /* detect cardbus removed, in power down(suspend) and in reset */
2849 if (DEVICEREMOVED(wlc))
2850 return -1;
2851
2852 /* DEVICEREMOVED succeeds even when the core is still resetting,
2853 * handle that case here.
2854 */
2855 if (macintstatus == 0xffffffff)
2856 return 0;
2857
2858 /* defer unsolicited interrupts */
2859 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2860
2861 /* if not for us */
2862 if (macintstatus == 0)
2863 return 0;
2864
2865 /* interrupts are already turned off for CFE build
2866 * Caution: For CFE Turning off the interrupts again has some undesired
2867 * consequences
2868 */
2869 /* turn off the interrupts */
2870 W_REG(&regs->macintmask, 0);
2871 (void)R_REG(&regs->macintmask); /* sync readback */
2872 wlc->macintmask = 0;
2873
2874 /* clear device interrupts */
2875 W_REG(&regs->macintstatus, macintstatus);
2876
2877 /* MI_DMAINT is indication of non-zero intstatus */
2878 if (macintstatus & MI_DMAINT) {
2879 /*
2880 * only fifo interrupt enabled is I_RI in
2881 * RX_FIFO. If MI_DMAINT is set, assume it
2882 * is set and clear the interrupt.
2883 */
2884 W_REG(&regs->intctrlregs[RX_FIFO].intstatus,
2885 DEF_RXINTMASK);
2886 }
2887
2888 return macintstatus;
2889 }
2890
2891 /* Update wlc->macintstatus and wlc->intstatus[]. */
2892 /* Return true if they are updated successfully. false otherwise */
2893 bool wlc_intrsupd(struct wlc_info *wlc)
2894 {
2895 u32 macintstatus;
2896
2897 /* read and clear macintstatus and intstatus registers */
2898 macintstatus = wlc_intstatus(wlc, false);
2899
2900 /* device is removed */
2901 if (macintstatus == 0xffffffff)
2902 return false;
2903
2904 /* update interrupt status in software */
2905 wlc->macintstatus |= macintstatus;
2906
2907 return true;
2908 }
2909
2910 /*
2911 * First-level interrupt processing.
2912 * Return true if this was our interrupt, false otherwise.
2913 * *wantdpc will be set to true if further wlc_dpc() processing is required,
2914 * false otherwise.
2915 */
2916 bool wlc_isr(struct wlc_info *wlc, bool *wantdpc)
2917 {
2918 struct wlc_hw_info *wlc_hw = wlc->hw;
2919 u32 macintstatus;
2920
2921 *wantdpc = false;
2922
2923 if (!wlc_hw->up || !wlc->macintmask)
2924 return false;
2925
2926 /* read and clear macintstatus and intstatus registers */
2927 macintstatus = wlc_intstatus(wlc, true);
2928
2929 if (macintstatus == 0xffffffff)
2930 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2931 " path\n");
2932
2933 /* it is not for us */
2934 if (macintstatus == 0)
2935 return false;
2936
2937 *wantdpc = true;
2938
2939 /* save interrupt status bits */
2940 wlc->macintstatus = macintstatus;
2941
2942 return true;
2943
2944 }
2945
2946 static bool
2947 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
2948 {
2949 /* discard intermediate indications for ucode with one legitimate case:
2950 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
2951 * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
2952 * transmission count)
2953 */
2954 if (!(txs->status & TX_STATUS_AMPDU)
2955 && (txs->status & TX_STATUS_INTERMEDIATE)) {
2956 return false;
2957 }
2958
2959 return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
2960 }
2961
2962 /* process tx completion events in BMAC
2963 * Return true if more tx status need to be processed. false otherwise.
2964 */
2965 static bool
2966 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
2967 {
2968 bool morepending = false;
2969 struct wlc_info *wlc = wlc_hw->wlc;
2970 d11regs_t *regs;
2971 tx_status_t txstatus, *txs;
2972 u32 s1, s2;
2973 uint n = 0;
2974 /*
2975 * Param 'max_tx_num' indicates max. # tx status to process before
2976 * break out.
2977 */
2978 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
2979
2980 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2981
2982 txs = &txstatus;
2983 regs = wlc_hw->regs;
2984 while (!(*fatal)
2985 && (s1 = R_REG(&regs->frmtxstatus)) & TXS_V) {
2986
2987 if (s1 == 0xffffffff) {
2988 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
2989 wlc_hw->unit, __func__);
2990 return morepending;
2991 }
2992
2993 s2 = R_REG(&regs->frmtxstatus2);
2994
2995 txs->status = s1 & TXS_STATUS_MASK;
2996 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
2997 txs->sequence = s2 & TXS_SEQ_MASK;
2998 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
2999 txs->lasttxtime = 0;
3000
3001 *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3002
3003 /* !give others some time to run! */
3004 if (++n >= max_tx_num)
3005 break;
3006 }
3007
3008 if (*fatal)
3009 return 0;
3010
3011 if (n >= max_tx_num)
3012 morepending = true;
3013
3014 if (!pktq_empty(&wlc->pkt_queue->q))
3015 wlc_send_q(wlc);
3016
3017 return morepending;
3018 }
3019
3020 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3021 {
3022 struct wlc_hw_info *wlc_hw = wlc->hw;
3023 d11regs_t *regs = wlc_hw->regs;
3024 u32 mc, mi;
3025 struct wiphy *wiphy = wlc->wiphy;
3026
3027 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3028 wlc_hw->band->bandunit);
3029
3030 /*
3031 * Track overlapping suspend requests
3032 */
3033 wlc_hw->mac_suspend_depth++;
3034 if (wlc_hw->mac_suspend_depth > 1)
3035 return;
3036
3037 /* force the core awake */
3038 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3039
3040 mc = R_REG(&regs->maccontrol);
3041
3042 if (mc == 0xffffffff) {
3043 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3044 __func__);
3045 brcms_down(wlc->wl);
3046 return;
3047 }
3048 WARN_ON(mc & MCTL_PSM_JMP_0);
3049 WARN_ON(!(mc & MCTL_PSM_RUN));
3050 WARN_ON(!(mc & MCTL_EN_MAC));
3051
3052 mi = R_REG(&regs->macintstatus);
3053 if (mi == 0xffffffff) {
3054 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3055 __func__);
3056 brcms_down(wlc->wl);
3057 return;
3058 }
3059 WARN_ON(mi & MI_MACSSPNDD);
3060
3061 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3062
3063 SPINWAIT(!(R_REG(&regs->macintstatus) & MI_MACSSPNDD),
3064 WLC_MAX_MAC_SUSPEND);
3065
3066 if (!(R_REG(&regs->macintstatus) & MI_MACSSPNDD)) {
3067 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
3068 " and MI_MACSSPNDD is still not on.\n",
3069 wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3070 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
3071 "psm_brc 0x%04x\n", wlc_hw->unit,
3072 R_REG(&regs->psmdebug),
3073 R_REG(&regs->phydebug),
3074 R_REG(&regs->psm_brc));
3075 }
3076
3077 mc = R_REG(&regs->maccontrol);
3078 if (mc == 0xffffffff) {
3079 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3080 __func__);
3081 brcms_down(wlc->wl);
3082 return;
3083 }
3084 WARN_ON(mc & MCTL_PSM_JMP_0);
3085 WARN_ON(!(mc & MCTL_PSM_RUN));
3086 WARN_ON(mc & MCTL_EN_MAC);
3087 }
3088
3089 void wlc_enable_mac(struct wlc_info *wlc)
3090 {
3091 struct wlc_hw_info *wlc_hw = wlc->hw;
3092 d11regs_t *regs = wlc_hw->regs;
3093 u32 mc, mi;
3094
3095 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3096 wlc->band->bandunit);
3097
3098 /*
3099 * Track overlapping suspend requests
3100 */
3101 wlc_hw->mac_suspend_depth--;
3102 if (wlc_hw->mac_suspend_depth > 0)
3103 return;
3104
3105 mc = R_REG(&regs->maccontrol);
3106 WARN_ON(mc & MCTL_PSM_JMP_0);
3107 WARN_ON(mc & MCTL_EN_MAC);
3108 WARN_ON(!(mc & MCTL_PSM_RUN));
3109
3110 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3111 W_REG(&regs->macintstatus, MI_MACSSPNDD);
3112
3113 mc = R_REG(&regs->maccontrol);
3114 WARN_ON(mc & MCTL_PSM_JMP_0);
3115 WARN_ON(!(mc & MCTL_EN_MAC));
3116 WARN_ON(!(mc & MCTL_PSM_RUN));
3117
3118 mi = R_REG(&regs->macintstatus);
3119 WARN_ON(mi & MI_MACSSPNDD);
3120
3121 wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3122 }
3123
3124 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3125 {
3126 u8 rate;
3127 u8 rates[8] = {
3128 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3129 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3130 };
3131 u16 entry_ptr;
3132 u16 pctl1;
3133 uint i;
3134
3135 if (!WLC_PHY_11N_CAP(wlc_hw->band))
3136 return;
3137
3138 /* walk the phy rate table and update the entries */
3139 for (i = 0; i < ARRAY_SIZE(rates); i++) {
3140 rate = rates[i];
3141
3142 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3143
3144 /* read the SHM Rate Table entry OFDM PCTL1 values */
3145 pctl1 =
3146 wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3147
3148 /* modify the value */
3149 pctl1 &= ~PHY_TXC1_MODE_MASK;
3150 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3151
3152 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3153 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3154 pctl1);
3155 }
3156 }
3157
3158 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3159 {
3160 uint i;
3161 u8 plcp_rate = 0;
3162 struct plcp_signal_rate_lookup {
3163 u8 rate;
3164 u8 signal_rate;
3165 };
3166 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3167 const struct plcp_signal_rate_lookup rate_lookup[] = {
3168 {WLC_RATE_6M, 0xB},
3169 {WLC_RATE_9M, 0xF},
3170 {WLC_RATE_12M, 0xA},
3171 {WLC_RATE_18M, 0xE},
3172 {WLC_RATE_24M, 0x9},
3173 {WLC_RATE_36M, 0xD},
3174 {WLC_RATE_48M, 0x8},
3175 {WLC_RATE_54M, 0xC}
3176 };
3177
3178 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3179 if (rate == rate_lookup[i].rate) {
3180 plcp_rate = rate_lookup[i].signal_rate;
3181 break;
3182 }
3183 }
3184
3185 /* Find the SHM pointer to the rate table entry by looking in the
3186 * Direct-map Table
3187 */
3188 return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3189 }
3190
3191 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3192 {
3193 wlc_hw->hw_stf_ss_opmode = stf_mode;
3194
3195 if (wlc_hw->clk)
3196 wlc_upd_ofdm_pctl1_table(wlc_hw);
3197 }
3198
3199 void
3200 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3201 u32 *tsf_h_ptr)
3202 {
3203 d11regs_t *regs = wlc_hw->regs;
3204
3205 /* read the tsf timer low, then high to get an atomic read */
3206 *tsf_l_ptr = R_REG(&regs->tsf_timerlow);
3207 *tsf_h_ptr = R_REG(&regs->tsf_timerhigh);
3208
3209 return;
3210 }
3211
3212 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3213 {
3214 d11regs_t *regs;
3215 u32 w, val;
3216 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
3217
3218 BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
3219
3220 regs = wlc_hw->regs;
3221
3222 /* Validate dchip register access */
3223
3224 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3225 (void)R_REG(&regs->objaddr);
3226 w = R_REG(&regs->objdata);
3227
3228 /* Can we write and read back a 32bit register? */
3229 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3230 (void)R_REG(&regs->objaddr);
3231 W_REG(&regs->objdata, (u32) 0xaa5555aa);
3232
3233 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3234 (void)R_REG(&regs->objaddr);
3235 val = R_REG(&regs->objdata);
3236 if (val != (u32) 0xaa5555aa) {
3237 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3238 "expected 0xaa5555aa\n", wlc_hw->unit, val);
3239 return false;
3240 }
3241
3242 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3243 (void)R_REG(&regs->objaddr);
3244 W_REG(&regs->objdata, (u32) 0x55aaaa55);
3245
3246 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3247 (void)R_REG(&regs->objaddr);
3248 val = R_REG(&regs->objdata);
3249 if (val != (u32) 0x55aaaa55) {
3250 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3251 "expected 0x55aaaa55\n", wlc_hw->unit, val);
3252 return false;
3253 }
3254
3255 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3256 (void)R_REG(&regs->objaddr);
3257 W_REG(&regs->objdata, w);
3258
3259 /* clear CFPStart */
3260 W_REG(&regs->tsf_cfpstart, 0);
3261
3262 w = R_REG(&regs->maccontrol);
3263 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3264 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3265 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
3266 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
3267 (MCTL_IHR_EN | MCTL_WAKE),
3268 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3269 return false;
3270 }
3271
3272 return true;
3273 }
3274
3275 #define PHYPLL_WAIT_US 100000
3276
3277 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3278 {
3279 d11regs_t *regs;
3280 u32 tmp;
3281
3282 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3283
3284 tmp = 0;
3285 regs = wlc_hw->regs;
3286
3287 if (on) {
3288 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3289 OR_REG(&regs->clk_ctl_st,
3290 (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3291 CCS_ERSRC_REQ_PHYPLL));
3292 SPINWAIT((R_REG(&regs->clk_ctl_st) &
3293 (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3294 PHYPLL_WAIT_US);
3295
3296 tmp = R_REG(&regs->clk_ctl_st);
3297 if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3298 (CCS_ERSRC_AVAIL_HT)) {
3299 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
3300 " PLL failed\n", __func__);
3301 }
3302 } else {
3303 OR_REG(&regs->clk_ctl_st,
3304 (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3305 SPINWAIT((R_REG(&regs->clk_ctl_st) &
3306 (CCS_ERSRC_AVAIL_D11PLL |
3307 CCS_ERSRC_AVAIL_PHYPLL)) !=
3308 (CCS_ERSRC_AVAIL_D11PLL |
3309 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3310
3311 tmp = R_REG(&regs->clk_ctl_st);
3312 if ((tmp &
3313 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3314 !=
3315 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3316 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
3317 "PHY PLL failed\n", __func__);
3318 }
3319 }
3320 } else {
3321 /* Since the PLL may be shared, other cores can still be requesting it;
3322 * so we'll deassert the request but not wait for status to comply.
3323 */
3324 AND_REG(&regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3325 tmp = R_REG(&regs->clk_ctl_st);
3326 }
3327 }
3328
3329 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3330 {
3331 bool dev_gone;
3332
3333 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3334
3335 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3336
3337 if (dev_gone)
3338 return;
3339
3340 if (wlc_hw->noreset)
3341 return;
3342
3343 /* radio off */
3344 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3345
3346 /* turn off analog core */
3347 wlc_phy_anacore(wlc_hw->band->pi, OFF);
3348
3349 /* turn off PHYPLL to save power */
3350 wlc_bmac_core_phypll_ctl(wlc_hw, false);
3351
3352 /* No need to set wlc->pub->radio_active = OFF
3353 * because this function needs down capability and
3354 * radio_active is designed for BCMNODOWN.
3355 */
3356
3357 /* remove gpio controls */
3358 if (wlc_hw->ucode_dbgsel)
3359 ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3360
3361 wlc_hw->clk = false;
3362 ai_core_disable(wlc_hw->sih, 0);
3363 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3364 }
3365
3366 /* power both the pll and external oscillator on/off */
3367 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3368 {
3369 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
3370
3371 /* dont power down if plldown is false or we must poll hw radio disable */
3372 if (!want && wlc_hw->pllreq)
3373 return;
3374
3375 if (wlc_hw->sih)
3376 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3377
3378 wlc_hw->sbclk = want;
3379 if (!wlc_hw->sbclk) {
3380 wlc_hw->clk = false;
3381 if (wlc_hw->band && wlc_hw->band->pi)
3382 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3383 }
3384 }
3385
3386 static void wlc_flushqueues(struct wlc_info *wlc)
3387 {
3388 struct wlc_hw_info *wlc_hw = wlc->hw;
3389 uint i;
3390
3391 wlc->txpend16165war = 0;
3392
3393 /* free any posted tx packets */
3394 for (i = 0; i < NFIFO; i++)
3395 if (wlc_hw->di[i]) {
3396 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
3397 TXPKTPENDCLR(wlc, i);
3398 BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
3399 }
3400
3401 /* free any posted rx packets */
3402 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3403 }
3404
3405 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3406 {
3407 return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3408 }
3409
3410 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3411 {
3412 wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3413 }
3414
3415 static u16
3416 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3417 {
3418 d11regs_t *regs = wlc_hw->regs;
3419 volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3420 volatile u16 *objdata_hi = objdata_lo + 1;
3421 u16 v;
3422
3423 W_REG(&regs->objaddr, sel | (offset >> 2));
3424 (void)R_REG(&regs->objaddr);
3425 if (offset & 2) {
3426 v = R_REG(objdata_hi);
3427 } else {
3428 v = R_REG(objdata_lo);
3429 }
3430
3431 return v;
3432 }
3433
3434 static void
3435 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3436 {
3437 d11regs_t *regs = wlc_hw->regs;
3438 volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3439 volatile u16 *objdata_hi = objdata_lo + 1;
3440
3441 W_REG(&regs->objaddr, sel | (offset >> 2));
3442 (void)R_REG(&regs->objaddr);
3443 if (offset & 2) {
3444 W_REG(objdata_hi, v);
3445 } else {
3446 W_REG(objdata_lo, v);
3447 }
3448 }
3449
3450 /* Copy a buffer to shared memory of specified type .
3451 * SHM 'offset' needs to be an even address and
3452 * Buffer length 'len' must be an even number of bytes
3453 * 'sel' selects the type of memory
3454 */
3455 void
3456 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3457 int len, u32 sel)
3458 {
3459 u16 v;
3460 const u8 *p = (const u8 *)buf;
3461 int i;
3462
3463 if (len <= 0 || (offset & 1) || (len & 1))
3464 return;
3465
3466 for (i = 0; i < len; i += 2) {
3467 v = p[i] | (p[i + 1] << 8);
3468 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3469 }
3470 }
3471
3472 /* Copy a piece of shared memory of specified type to a buffer .
3473 * SHM 'offset' needs to be an even address and
3474 * Buffer length 'len' must be an even number of bytes
3475 * 'sel' selects the type of memory
3476 */
3477 void
3478 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3479 int len, u32 sel)
3480 {
3481 u16 v;
3482 u8 *p = (u8 *) buf;
3483 int i;
3484
3485 if (len <= 0 || (offset & 1) || (len & 1))
3486 return;
3487
3488 for (i = 0; i < len; i += 2) {
3489 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3490 p[i] = v & 0xFF;
3491 p[i + 1] = (v >> 8) & 0xFF;
3492 }
3493 }
3494
3495 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3496 {
3497 BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
3498 wlc_hw->vars_size);
3499
3500 *buf = wlc_hw->vars;
3501 *len = wlc_hw->vars_size;
3502 }
3503
3504 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3505 {
3506 wlc_hw->SRL = SRL;
3507 wlc_hw->LRL = LRL;
3508
3509 /* write retry limit to SCR, shouldn't need to suspend */
3510 if (wlc_hw->up) {
3511 W_REG(&wlc_hw->regs->objaddr,
3512 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3513 (void)R_REG(&wlc_hw->regs->objaddr);
3514 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3515 W_REG(&wlc_hw->regs->objaddr,
3516 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3517 (void)R_REG(&wlc_hw->regs->objaddr);
3518 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3519 }
3520 }
3521
3522 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3523 {
3524 if (set) {
3525 if (mboolisset(wlc_hw->pllreq, req_bit))
3526 return;
3527
3528 mboolset(wlc_hw->pllreq, req_bit);
3529
3530 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3531 if (!wlc_hw->sbclk) {
3532 wlc_bmac_xtal(wlc_hw, ON);
3533 }
3534 }
3535 } else {
3536 if (!mboolisset(wlc_hw->pllreq, req_bit))
3537 return;
3538
3539 mboolclr(wlc_hw->pllreq, req_bit);
3540
3541 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3542 if (wlc_hw->sbclk) {
3543 wlc_bmac_xtal(wlc_hw, OFF);
3544 }
3545 }
3546 }
3547
3548 return;
3549 }
3550
3551 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3552 {
3553 u16 table_ptr;
3554 u8 phy_rate, index;
3555
3556 /* get the phy specific rate encoding for the PLCP SIGNAL field */
3557 /* XXX4321 fixup needed ? */
3558 if (IS_OFDM(rate))
3559 table_ptr = M_RT_DIRMAP_A;
3560 else
3561 table_ptr = M_RT_DIRMAP_B;
3562
3563 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3564 * the index into the rate table.
3565 */
3566 phy_rate = rate_info[rate] & WLC_RATE_MASK;
3567 index = phy_rate & 0xf;
3568
3569 /* Find the SHM pointer to the rate table entry by looking in the
3570 * Direct-map Table
3571 */
3572 return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
3573 }
3574
3575 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3576 {
3577 wlc_hw->antsel_avail = antsel_avail;
3578 }
Linux kernel - Deliverables
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