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staging: brcm80211: fix checkpatch errors in brcmsmac driver
[deliverable/linux.git] / drivers / staging / brcm80211 / brcmsmac / srom.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/string.h>
19 #include <linux/io.h>
20 #include <linux/etherdevice.h>
21 #include <stdarg.h>
22
23 #include <chipcommon.h>
24 #include <brcmu_utils.h>
25 #include "nicpci.h"
26 #include "aiutils.h"
27 #include "otp.h"
28 #include "srom.h"
29
30 #define SROM_OFFSET(sih) ((sih->ccrev > 31) ? \
31 (((sih->cccaps & CC_CAP_SROM) == 0) ? NULL : \
32 ((u8 *)curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP)) : \
33 ((u8 *)curmap + PCI_BAR0_SPROM_OFFSET))
34
35 #if defined(BCMDBG)
36 #define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
37 #define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
38 #endif
39
40 /* Maximum srom: 6 Kilobits == 768 bytes */
41 #define SROM_MAX 768
42
43 /* PCI fields */
44 #define PCI_F0DEVID 48
45
46 #define SROM_WORDS 64
47
48 #define SROM_SSID 2
49
50 #define SROM_WL1LHMAXP 29
51
52 #define SROM_WL1LPAB0 30
53 #define SROM_WL1LPAB1 31
54 #define SROM_WL1LPAB2 32
55
56 #define SROM_WL1HPAB0 33
57 #define SROM_WL1HPAB1 34
58 #define SROM_WL1HPAB2 35
59
60 #define SROM_MACHI_IL0 36
61 #define SROM_MACMID_IL0 37
62 #define SROM_MACLO_IL0 38
63 #define SROM_MACHI_ET1 42
64 #define SROM_MACMID_ET1 43
65 #define SROM_MACLO_ET1 44
66 #define SROM3_MACHI 37
67 #define SROM3_MACMID 38
68 #define SROM3_MACLO 39
69
70 #define SROM_BXARSSI2G 40
71 #define SROM_BXARSSI5G 41
72
73 #define SROM_TRI52G 42
74 #define SROM_TRI5GHL 43
75
76 #define SROM_RXPO52G 45
77
78 #define SROM_AABREV 46
79 /* Fields in AABREV */
80 #define SROM_BR_MASK 0x00ff
81 #define SROM_CC_MASK 0x0f00
82 #define SROM_CC_SHIFT 8
83 #define SROM_AA0_MASK 0x3000
84 #define SROM_AA0_SHIFT 12
85 #define SROM_AA1_MASK 0xc000
86 #define SROM_AA1_SHIFT 14
87
88 #define SROM_WL0PAB0 47
89 #define SROM_WL0PAB1 48
90 #define SROM_WL0PAB2 49
91
92 #define SROM_LEDBH10 50
93 #define SROM_LEDBH32 51
94
95 #define SROM_WL10MAXP 52
96
97 #define SROM_WL1PAB0 53
98 #define SROM_WL1PAB1 54
99 #define SROM_WL1PAB2 55
100
101 #define SROM_ITT 56
102
103 #define SROM_BFL 57
104 #define SROM_BFL2 28
105 #define SROM3_BFL2 61
106
107 #define SROM_AG10 58
108
109 #define SROM_CCODE 59
110
111 #define SROM_OPO 60
112
113 #define SROM3_LEDDC 62
114
115 #define SROM_CRCREV 63
116
117 /* SROM Rev 4: Reallocate the software part of the srom to accommodate
118 * MIMO features. It assumes up to two PCIE functions and 440 bytes
119 * of usable srom i.e. the usable storage in chips with OTP that
120 * implements hardware redundancy.
121 */
122
123 #define SROM4_WORDS 220
124
125 #define SROM4_SIGN 32
126 #define SROM4_SIGNATURE 0x5372
127
128 #define SROM4_BREV 33
129
130 #define SROM4_BFL0 34
131 #define SROM4_BFL1 35
132 #define SROM4_BFL2 36
133 #define SROM4_BFL3 37
134 #define SROM5_BFL0 37
135 #define SROM5_BFL1 38
136 #define SROM5_BFL2 39
137 #define SROM5_BFL3 40
138
139 #define SROM4_MACHI 38
140 #define SROM4_MACMID 39
141 #define SROM4_MACLO 40
142 #define SROM5_MACHI 41
143 #define SROM5_MACMID 42
144 #define SROM5_MACLO 43
145
146 #define SROM4_CCODE 41
147 #define SROM4_REGREV 42
148 #define SROM5_CCODE 34
149 #define SROM5_REGREV 35
150
151 #define SROM4_LEDBH10 43
152 #define SROM4_LEDBH32 44
153 #define SROM5_LEDBH10 59
154 #define SROM5_LEDBH32 60
155
156 #define SROM4_LEDDC 45
157 #define SROM5_LEDDC 45
158
159 #define SROM4_AA 46
160
161 #define SROM4_AG10 47
162 #define SROM4_AG32 48
163
164 #define SROM4_TXPID2G 49
165 #define SROM4_TXPID5G 51
166 #define SROM4_TXPID5GL 53
167 #define SROM4_TXPID5GH 55
168
169 #define SROM4_TXRXC 61
170 #define SROM4_TXCHAIN_MASK 0x000f
171 #define SROM4_TXCHAIN_SHIFT 0
172 #define SROM4_RXCHAIN_MASK 0x00f0
173 #define SROM4_RXCHAIN_SHIFT 4
174 #define SROM4_SWITCH_MASK 0xff00
175 #define SROM4_SWITCH_SHIFT 8
176
177 /* Per-path fields */
178 #define MAX_PATH_SROM 4
179 #define SROM4_PATH0 64
180 #define SROM4_PATH1 87
181 #define SROM4_PATH2 110
182 #define SROM4_PATH3 133
183
184 #define SROM4_2G_ITT_MAXP 0
185 #define SROM4_2G_PA 1
186 #define SROM4_5G_ITT_MAXP 5
187 #define SROM4_5GLH_MAXP 6
188 #define SROM4_5G_PA 7
189 #define SROM4_5GL_PA 11
190 #define SROM4_5GH_PA 15
191
192 /* All the miriad power offsets */
193 #define SROM4_2G_CCKPO 156
194 #define SROM4_2G_OFDMPO 157
195 #define SROM4_5G_OFDMPO 159
196 #define SROM4_5GL_OFDMPO 161
197 #define SROM4_5GH_OFDMPO 163
198 #define SROM4_2G_MCSPO 165
199 #define SROM4_5G_MCSPO 173
200 #define SROM4_5GL_MCSPO 181
201 #define SROM4_5GH_MCSPO 189
202 #define SROM4_CDDPO 197
203 #define SROM4_STBCPO 198
204 #define SROM4_BW40PO 199
205 #define SROM4_BWDUPPO 200
206
207 #define SROM4_CRCREV 219
208
209 /* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
210 * This is acombined srom for both MIMO and SISO boards, usable in
211 * the .130 4Kilobit OTP with hardware redundancy.
212 */
213 #define SROM8_BREV 65
214
215 #define SROM8_BFL0 66
216 #define SROM8_BFL1 67
217 #define SROM8_BFL2 68
218 #define SROM8_BFL3 69
219
220 #define SROM8_MACHI 70
221 #define SROM8_MACMID 71
222 #define SROM8_MACLO 72
223
224 #define SROM8_CCODE 73
225 #define SROM8_REGREV 74
226
227 #define SROM8_LEDBH10 75
228 #define SROM8_LEDBH32 76
229
230 #define SROM8_LEDDC 77
231
232 #define SROM8_AA 78
233
234 #define SROM8_AG10 79
235 #define SROM8_AG32 80
236
237 #define SROM8_TXRXC 81
238
239 #define SROM8_BXARSSI2G 82
240 #define SROM8_BXARSSI5G 83
241 #define SROM8_TRI52G 84
242 #define SROM8_TRI5GHL 85
243 #define SROM8_RXPO52G 86
244
245 #define SROM8_FEM2G 87
246 #define SROM8_FEM5G 88
247 #define SROM8_FEM_ANTSWLUT_MASK 0xf800
248 #define SROM8_FEM_ANTSWLUT_SHIFT 11
249 #define SROM8_FEM_TR_ISO_MASK 0x0700
250 #define SROM8_FEM_TR_ISO_SHIFT 8
251 #define SROM8_FEM_PDET_RANGE_MASK 0x00f8
252 #define SROM8_FEM_PDET_RANGE_SHIFT 3
253 #define SROM8_FEM_EXTPA_GAIN_MASK 0x0006
254 #define SROM8_FEM_EXTPA_GAIN_SHIFT 1
255 #define SROM8_FEM_TSSIPOS_MASK 0x0001
256 #define SROM8_FEM_TSSIPOS_SHIFT 0
257
258 #define SROM8_THERMAL 89
259
260 /* Temp sense related entries */
261 #define SROM8_MPWR_RAWTS 90
262 #define SROM8_TS_SLP_OPT_CORRX 91
263 /* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
264 #define SROM8_FOC_HWIQ_IQSWP 92
265
266 /* Temperature delta for PHY calibration */
267 #define SROM8_PHYCAL_TEMPDELTA 93
268
269 /* Per-path offsets & fields */
270 #define SROM8_PATH0 96
271 #define SROM8_PATH1 112
272 #define SROM8_PATH2 128
273 #define SROM8_PATH3 144
274
275 #define SROM8_2G_ITT_MAXP 0
276 #define SROM8_2G_PA 1
277 #define SROM8_5G_ITT_MAXP 4
278 #define SROM8_5GLH_MAXP 5
279 #define SROM8_5G_PA 6
280 #define SROM8_5GL_PA 9
281 #define SROM8_5GH_PA 12
282
283 /* All the miriad power offsets */
284 #define SROM8_2G_CCKPO 160
285
286 #define SROM8_2G_OFDMPO 161
287 #define SROM8_5G_OFDMPO 163
288 #define SROM8_5GL_OFDMPO 165
289 #define SROM8_5GH_OFDMPO 167
290
291 #define SROM8_2G_MCSPO 169
292 #define SROM8_5G_MCSPO 177
293 #define SROM8_5GL_MCSPO 185
294 #define SROM8_5GH_MCSPO 193
295
296 #define SROM8_CDDPO 201
297 #define SROM8_STBCPO 202
298 #define SROM8_BW40PO 203
299 #define SROM8_BWDUPPO 204
300
301 /* SISO PA parameters are in the path0 spaces */
302 #define SROM8_SISO 96
303
304 /* Legacy names for SISO PA paramters */
305 #define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
306 #define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
307 #define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
308 #define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
309 #define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
310 #define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
311 #define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
312 #define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
313 #define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
314 #define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
315 #define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
316 #define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
317 #define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
318 #define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
319 #define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
320
321 /* SROM REV 9 */
322 #define SROM9_2GPO_CCKBW20 160
323 #define SROM9_2GPO_CCKBW20UL 161
324 #define SROM9_2GPO_LOFDMBW20 162
325 #define SROM9_2GPO_LOFDMBW20UL 164
326
327 #define SROM9_5GLPO_LOFDMBW20 166
328 #define SROM9_5GLPO_LOFDMBW20UL 168
329 #define SROM9_5GMPO_LOFDMBW20 170
330 #define SROM9_5GMPO_LOFDMBW20UL 172
331 #define SROM9_5GHPO_LOFDMBW20 174
332 #define SROM9_5GHPO_LOFDMBW20UL 176
333
334 #define SROM9_2GPO_MCSBW20 178
335 #define SROM9_2GPO_MCSBW20UL 180
336 #define SROM9_2GPO_MCSBW40 182
337
338 #define SROM9_5GLPO_MCSBW20 184
339 #define SROM9_5GLPO_MCSBW20UL 186
340 #define SROM9_5GLPO_MCSBW40 188
341 #define SROM9_5GMPO_MCSBW20 190
342 #define SROM9_5GMPO_MCSBW20UL 192
343 #define SROM9_5GMPO_MCSBW40 194
344 #define SROM9_5GHPO_MCSBW20 196
345 #define SROM9_5GHPO_MCSBW20UL 198
346 #define SROM9_5GHPO_MCSBW40 200
347
348 #define SROM9_PO_MCS32 202
349 #define SROM9_PO_LOFDM40DUP 203
350
351 /* SROM flags (see sromvar_t) */
352 #define SRFL_MORE 1 /* value continues as described by the next entry */
353 #define SRFL_NOFFS 2 /* value bits can't be all one's */
354 #define SRFL_PRHEX 4 /* value is in hexdecimal format */
355 #define SRFL_PRSIGN 8 /* value is in signed decimal format */
356 #define SRFL_CCODE 0x10 /* value is in country code format */
357 #define SRFL_ETHADDR 0x20 /* value is an Ethernet address */
358 #define SRFL_LEDDC 0x40 /* value is an LED duty cycle */
359 #define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */
360
361 /* Max. nvram variable table size */
362 #define MAXSZ_NVRAM_VARS 4096
363
364 typedef struct {
365 const char *name;
366 u32 revmask;
367 u32 flags;
368 u16 off;
369 u16 mask;
370 } sromvar_t;
371
372 typedef struct varbuf {
373 char *base; /* pointer to buffer base */
374 char *buf; /* pointer to current position */
375 unsigned int size; /* current (residual) size in bytes */
376 } varbuf_t;
377
378 /* Assumptions:
379 * - Ethernet address spans across 3 consective words
380 *
381 * Table rules:
382 * - Add multiple entries next to each other if a value spans across multiple words
383 * (even multiple fields in the same word) with each entry except the last having
384 * it's SRFL_MORE bit set.
385 * - Ethernet address entry does not follow above rule and must not have SRFL_MORE
386 * bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
387 * - The last entry's name field must be NULL to indicate the end of the table. Other
388 * entries must have non-NULL name.
389 */
390 static const sromvar_t pci_sromvars[] = {
391 {"devid", 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 0xffff},
392 {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK},
393 {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
394 {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
395 {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
396 {"boardflags", 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
397 {"", 0, 0, SROM_BFL2, 0xffff},
398 {"boardflags", 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
399 {"", 0, 0, SROM3_BFL2, 0xffff},
400 {"boardflags", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0, 0xffff},
401 {"", 0, 0, SROM4_BFL1, 0xffff},
402 {"boardflags", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0, 0xffff},
403 {"", 0, 0, SROM5_BFL1, 0xffff},
404 {"boardflags", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 0xffff},
405 {"", 0, 0, SROM8_BFL1, 0xffff},
406 {"boardflags2", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2, 0xffff},
407 {"", 0, 0, SROM4_BFL3, 0xffff},
408 {"boardflags2", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2, 0xffff},
409 {"", 0, 0, SROM5_BFL3, 0xffff},
410 {"boardflags2", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 0xffff},
411 {"", 0, 0, SROM8_BFL3, 0xffff},
412 {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
413 {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
414 {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff},
415 {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff},
416 {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff},
417 {"boardnum", 0xffffff00, 0, SROM8_MACLO, 0xffff},
418 {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
419 {"regrev", 0x00000008, 0, SROM_OPO, 0xff00},
420 {"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff},
421 {"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff},
422 {"regrev", 0xffffff00, 0, SROM8_REGREV, 0x00ff},
423 {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
424 {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
425 {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
426 {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
427 {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
428 {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
429 {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
430 {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
431 {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
432 {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
433 {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
434 {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
435 {"ledbh0", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
436 {"ledbh1", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
437 {"ledbh2", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
438 {"ledbh3", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
439 {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
440 {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
441 {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
442 {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff},
443 {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
444 {"pa0b0", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
445 {"pa0b1", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
446 {"pa0b2", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
447 {"pa0itssit", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
448 {"pa0maxpwr", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
449 {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff},
450 {"opo", 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
451 {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
452 {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff},
453 {"aa2g", 0xffffff00, 0, SROM8_AA, 0x00ff},
454 {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
455 {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00},
456 {"aa5g", 0xffffff00, 0, SROM8_AA, 0xff00},
457 {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff},
458 {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00},
459 {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff},
460 {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00},
461 {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff},
462 {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00},
463 {"ag0", 0xffffff00, 0, SROM8_AG10, 0x00ff},
464 {"ag1", 0xffffff00, 0, SROM8_AG10, 0xff00},
465 {"ag2", 0xffffff00, 0, SROM8_AG32, 0x00ff},
466 {"ag3", 0xffffff00, 0, SROM8_AG32, 0xff00},
467 {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
468 {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
469 {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
470 {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
471 {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
472 {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
473 {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
474 {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
475 {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
476 {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00},
477 {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
478 {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
479 {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
480 {"pa1b0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
481 {"pa1b1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
482 {"pa1b2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
483 {"pa1lob0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
484 {"pa1lob1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
485 {"pa1lob2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
486 {"pa1hib0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
487 {"pa1hib1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
488 {"pa1hib2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
489 {"pa1itssit", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
490 {"pa1maxpwr", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
491 {"pa1lomaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
492 {"pa1himaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
493 {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
494 {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
495 {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
496 {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
497 {"bxa2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
498 {"rssisav2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
499 {"rssismc2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
500 {"rssismf2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
501 {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
502 {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
503 {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
504 {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
505 {"bxa5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
506 {"rssisav5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
507 {"rssismc5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
508 {"rssismf5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
509 {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff},
510 {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00},
511 {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
512 {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00},
513 {"tri2g", 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
514 {"tri5g", 0xffffff00, 0, SROM8_TRI52G, 0xff00},
515 {"tri5gl", 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
516 {"tri5gh", 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
517 {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
518 {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
519 {"rxpo2g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
520 {"rxpo5g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
521 {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK},
522 {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK},
523 {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK},
524 {"txchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK},
525 {"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK},
526 {"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK},
527 {"tssipos2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK},
528 {"extpagain2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK},
529 {"pdetrange2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK},
530 {"triso2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
531 {"antswctl2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK},
532 {"tssipos5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK},
533 {"extpagain5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK},
534 {"pdetrange5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK},
535 {"triso5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
536 {"antswctl5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK},
537 {"tempthresh", 0xffffff00, 0, SROM8_THERMAL, 0xff00},
538 {"tempoffset", 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
539 {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
540 {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
541 {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
542 {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
543 {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
544 {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
545 {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
546 {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
547 {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
548 {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
549 {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
550 {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
551 {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
552 {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
553 {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
554 {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
555
556 {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
557 {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
558 {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
559 {"ccode", 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
560 {"macaddr", 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
561 {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
562 {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
563 {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
564 {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff},
565 {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff},
566 {"leddc", 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 0xffff},
567 {"leddc", 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC, 0xffff},
568 {"leddc", 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC, 0xffff},
569 {"leddc", 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC, 0xffff},
570 {"rawtempsense", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff},
571 {"measpower", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00},
572 {"tempsense_slope", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
573 0x00ff},
574 {"tempcorrx", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00},
575 {"tempsense_option", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
576 0x0300},
577 {"freqoffset_corr", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
578 0x000f},
579 {"iqcal_swp_dis", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010},
580 {"hw_iqcal_en", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020},
581 {"phycal_tempdelta", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff},
582
583 {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
584 {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
585 {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
586 {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
587 {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
588 {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
589 {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
590 {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
591 {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
592 {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
593 {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
594 {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
595 {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
596 {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
597 {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
598 {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
599 {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
600 {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
601 {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
602 {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
603 {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
604 {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
605 {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
606 {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
607 {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
608 {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
609 {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
610 {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
611 {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
612 {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
613 {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
614 {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
615 {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
616 {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
617 {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
618 {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
619 {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
620 {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
621 {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
622 {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
623 {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
624 {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
625 {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
626 {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
627 {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
628 {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
629 {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
630 {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
631 {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
632 {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
633 {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
634 {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
635 {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
636 {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
637 {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
638 {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
639 {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
640 {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
641 {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
642 {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
643 {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
644 {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
645 {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
646 {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
647 {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
648 {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
649 {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
650 {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
651 {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
652 {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
653 {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
654 {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
655 {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
656 {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
657 {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
658 {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
659 {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
660 {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
661 {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
662 {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
663 {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
664 {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
665 {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff},
666 {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff},
667 {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff},
668 {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
669 {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff},
670 {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff},
671 {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff},
672 {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
673
674 /* power per rate from sromrev 9 */
675 {"cckbw202gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
676 {"cckbw20ul2gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
677 {"legofdmbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20,
678 0xffff},
679 {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
680 {"legofdmbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL,
681 0xffff},
682 {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
683 {"legofdmbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20,
684 0xffff},
685 {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
686 {"legofdmbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL,
687 0xffff},
688 {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
689 {"legofdmbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20,
690 0xffff},
691 {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
692 {"legofdmbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL,
693 0xffff},
694 {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
695 {"legofdmbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20,
696 0xffff},
697 {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
698 {"legofdmbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL,
699 0xffff},
700 {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
701 {"mcsbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff},
702 {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
703 {"mcsbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff},
704 {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
705 {"mcsbw402gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff},
706 {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
707 {"mcsbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff},
708 {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
709 {"mcsbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20UL,
710 0xffff},
711 {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
712 {"mcsbw405glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff},
713 {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
714 {"mcsbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff},
715 {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
716 {"mcsbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20UL,
717 0xffff},
718 {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
719 {"mcsbw405gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff},
720 {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
721 {"mcsbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff},
722 {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
723 {"mcsbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20UL,
724 0xffff},
725 {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
726 {"mcsbw405ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff},
727 {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
728 {"mcs32po", 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
729 {"legofdm40duppo", 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
730
731 {NULL, 0, 0, 0, 0}
732 };
733
734 static const sromvar_t perpath_pci_sromvars[] = {
735 {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
736 {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
737 {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
738 {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
739 {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
740 {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
741 {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
742 {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
743 {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
744 {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
745 {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
746 {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
747 {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
748 {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
749 {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
750 {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff},
751 {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff},
752 {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff},
753 {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
754 {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff},
755 {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff},
756 {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff},
757 {"maxp2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
758 {"itt2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
759 {"itt5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
760 {"pa2gw0a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
761 {"pa2gw1a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
762 {"pa2gw2a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
763 {"maxp5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
764 {"maxp5gha", 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
765 {"maxp5gla", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
766 {"pa5gw0a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
767 {"pa5gw1a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
768 {"pa5gw2a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
769 {"pa5glw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
770 {"pa5glw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff},
771 {"pa5glw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff},
772 {"pa5ghw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
773 {"pa5ghw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff},
774 {"pa5ghw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff},
775 {NULL, 0, 0, 0, 0}
776 };
777
778 static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b);
779 static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
780 uint *count);
781 static int sprom_read_pci(struct si_pub *sih, u16 *sprom,
782 uint wordoff, u16 *buf, uint nwords, bool check_crc);
783 #if defined(BCMNVRAMR)
784 static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz);
785 #endif
786 static u16 srom_cc_cmd(struct si_pub *sih, void *ccregs, u32 cmd,
787 uint wordoff, u16 data);
788
789 static int initvars_table(char *start, char *end,
790 char **vars, uint *count);
791
792 /* Initialization of varbuf structure */
793 static void varbuf_init(varbuf_t *b, char *buf, uint size)
794 {
795 b->size = size;
796 b->base = b->buf = buf;
797 }
798
799 /* append a null terminated var=value string */
800 static int varbuf_append(varbuf_t *b, const char *fmt, ...)
801 {
802 va_list ap;
803 int r;
804 size_t len;
805 char *s;
806
807 if (b->size < 2)
808 return 0;
809
810 va_start(ap, fmt);
811 r = vsnprintf(b->buf, b->size, fmt, ap);
812 va_end(ap);
813
814 /* C99 snprintf behavior returns r >= size on overflow,
815 * others return -1 on overflow.
816 * All return -1 on format error.
817 * We need to leave room for 2 null terminations, one for the current var
818 * string, and one for final null of the var table. So check that the
819 * strlen written, r, leaves room for 2 chars.
820 */
821 if ((r == -1) || (r > (int)(b->size - 2))) {
822 b->size = 0;
823 return 0;
824 }
825
826 /* Remove any earlier occurrence of the same variable */
827 s = strchr(b->buf, '=');
828 if (s != NULL) {
829 len = (size_t) (s - b->buf);
830 for (s = b->base; s < b->buf;) {
831 if ((memcmp(s, b->buf, len) == 0) && s[len] == '=') {
832 len = strlen(s) + 1;
833 memmove(s, (s + len),
834 ((b->buf + r + 1) - (s + len)));
835 b->buf -= len;
836 b->size += (unsigned int)len;
837 break;
838 }
839
840 while (*s++)
841 ;
842 }
843 }
844
845 /* skip over this string's null termination */
846 r++;
847 b->size -= r;
848 b->buf += r;
849
850 return r;
851 }
852
853 /*
854 * Initialize local vars from the right source for this platform.
855 * Return 0 on success, nonzero on error.
856 */
857 int srom_var_init(struct si_pub *sih, uint bustype, void *curmap,
858 char **vars, uint *count)
859 {
860 uint len;
861
862 len = 0;
863
864 if (vars == NULL || count == NULL)
865 return 0;
866
867 *vars = NULL;
868 *count = 0;
869
870 if (curmap != NULL && bustype == PCI_BUS)
871 return initvars_srom_pci(sih, curmap, vars, count);
872
873 return -1;
874 }
875
876 /* In chips with chipcommon rev 32 and later, the srom is in chipcommon,
877 * not in the bus cores.
878 */
879 static u16
880 srom_cc_cmd(struct si_pub *sih, void *ccregs, u32 cmd,
881 uint wordoff, u16 data)
882 {
883 chipcregs_t *cc = (chipcregs_t *) ccregs;
884 uint wait_cnt = 1000;
885
886 if ((cmd == SRC_OP_READ) || (cmd == SRC_OP_WRITE)) {
887 W_REG(&cc->sromaddress, wordoff * 2);
888 if (cmd == SRC_OP_WRITE)
889 W_REG(&cc->sromdata, data);
890 }
891
892 W_REG(&cc->sromcontrol, SRC_START | cmd);
893
894 while (wait_cnt--) {
895 if ((R_REG(&cc->sromcontrol) & SRC_BUSY) == 0)
896 break;
897 }
898
899 if (!wait_cnt) {
900 return 0xffff;
901 }
902 if (cmd == SRC_OP_READ)
903 return (u16) R_REG(&cc->sromdata);
904 else
905 return 0xffff;
906 }
907
908 static inline void ltoh16_buf(u16 *buf, unsigned int size)
909 {
910 for (size /= 2; size; size--)
911 *(buf + size) = le16_to_cpu(*(buf + size));
912 }
913
914 static inline void htol16_buf(u16 *buf, unsigned int size)
915 {
916 for (size /= 2; size; size--)
917 *(buf + size) = cpu_to_le16(*(buf + size));
918 }
919
920 /*
921 * Read in and validate sprom.
922 * Return 0 on success, nonzero on error.
923 */
924 static int
925 sprom_read_pci(struct si_pub *sih, u16 *sprom, uint wordoff,
926 u16 *buf, uint nwords, bool check_crc)
927 {
928 int err = 0;
929 uint i;
930 void *ccregs = NULL;
931
932 /* read the sprom */
933 for (i = 0; i < nwords; i++) {
934
935 if (sih->ccrev > 31 && ISSIM_ENAB(sih)) {
936 /* use indirect since direct is too slow on QT */
937 if ((sih->cccaps & CC_CAP_SROM) == 0)
938 return 1;
939
940 ccregs = (void *)((u8 *) sprom - CC_SROM_OTP);
941 buf[i] =
942 srom_cc_cmd(sih, ccregs, SRC_OP_READ,
943 wordoff + i, 0);
944
945 } else {
946 if (ISSIM_ENAB(sih))
947 buf[i] = R_REG(&sprom[wordoff + i]);
948
949 buf[i] = R_REG(&sprom[wordoff + i]);
950 }
951
952 }
953
954 /* bypass crc checking for simulation to allow srom hack */
955 if (ISSIM_ENAB(sih))
956 return err;
957
958 if (check_crc) {
959
960 if (buf[0] == 0xffff) {
961 /* The hardware thinks that an srom that starts with 0xffff
962 * is blank, regardless of the rest of the content, so declare
963 * it bad.
964 */
965 return 1;
966 }
967
968 /* fixup the endianness so crc8 will pass */
969 htol16_buf(buf, nwords * 2);
970 if (brcmu_crc8((u8 *) buf, nwords * 2, CRC8_INIT_VALUE) !=
971 CRC8_GOOD_VALUE) {
972 /* DBG only pci always read srom4 first, then srom8/9 */
973 err = 1;
974 }
975 /* now correct the endianness of the byte array */
976 ltoh16_buf(buf, nwords * 2);
977 }
978 return err;
979 }
980
981 #if defined(BCMNVRAMR)
982 static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
983 {
984 u8 *otp;
985 uint sz = OTP_SZ_MAX / 2; /* size in words */
986 int err = 0;
987
988 otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
989 if (otp == NULL) {
990 return -EBADE;
991 }
992
993 err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
994
995 memcpy(buf, otp, bufsz);
996
997 kfree(otp);
998
999 /* Check CRC */
1000 if (buf[0] == 0xffff) {
1001 /* The hardware thinks that an srom that starts with 0xffff
1002 * is blank, regardless of the rest of the content, so declare
1003 * it bad.
1004 */
1005 return 1;
1006 }
1007
1008 /* fixup the endianness so crc8 will pass */
1009 htol16_buf(buf, bufsz);
1010 if (brcmu_crc8((u8 *) buf, SROM4_WORDS * 2, CRC8_INIT_VALUE) !=
1011 CRC8_GOOD_VALUE) {
1012 err = 1;
1013 }
1014 /* now correct the endianness of the byte array */
1015 ltoh16_buf(buf, bufsz);
1016
1017 return err;
1018 }
1019 #endif /* defined(BCMNVRAMR) */
1020 /*
1021 * Create variable table from memory.
1022 * Return 0 on success, nonzero on error.
1023 */
1024 static int initvars_table(char *start, char *end,
1025 char **vars, uint *count)
1026 {
1027 int c = (int)(end - start);
1028
1029 /* do it only when there is more than just the null string */
1030 if (c > 1) {
1031 char *vp = kmalloc(c, GFP_ATOMIC);
1032 if (!vp)
1033 return -ENOMEM;
1034 memcpy(vp, start, c);
1035 *vars = vp;
1036 *count = c;
1037 } else {
1038 *vars = NULL;
1039 *count = 0;
1040 }
1041
1042 return 0;
1043 }
1044
1045 /* Parse SROM and create name=value pairs. 'srom' points to
1046 * the SROM word array. 'off' specifies the offset of the
1047 * first word 'srom' points to, which should be either 0 or
1048 * SROM3_SWRG_OFF (full SROM or software region).
1049 */
1050
1051 static uint mask_shift(u16 mask)
1052 {
1053 uint i;
1054 for (i = 0; i < (sizeof(mask) << 3); i++) {
1055 if (mask & (1 << i))
1056 return i;
1057 }
1058 return 0;
1059 }
1060
1061 static uint mask_width(u16 mask)
1062 {
1063 int i;
1064 for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
1065 if (mask & (1 << i))
1066 return (uint) (i - mask_shift(mask) + 1);
1067 }
1068 return 0;
1069 }
1070
1071 static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b)
1072 {
1073 u16 w;
1074 u32 val;
1075 const sromvar_t *srv;
1076 uint width;
1077 uint flags;
1078 u32 sr = (1 << sromrev);
1079
1080 varbuf_append(b, "sromrev=%d", sromrev);
1081
1082 for (srv = pci_sromvars; srv->name != NULL; srv++) {
1083 const char *name;
1084
1085 if ((srv->revmask & sr) == 0)
1086 continue;
1087
1088 if (srv->off < off)
1089 continue;
1090
1091 flags = srv->flags;
1092 name = srv->name;
1093
1094 /* This entry is for mfgc only. Don't generate param for it, */
1095 if (flags & SRFL_NOVAR)
1096 continue;
1097
1098 if (flags & SRFL_ETHADDR) {
1099 u8 ea[ETH_ALEN];
1100
1101 ea[0] = (srom[srv->off - off] >> 8) & 0xff;
1102 ea[1] = srom[srv->off - off] & 0xff;
1103 ea[2] = (srom[srv->off + 1 - off] >> 8) & 0xff;
1104 ea[3] = srom[srv->off + 1 - off] & 0xff;
1105 ea[4] = (srom[srv->off + 2 - off] >> 8) & 0xff;
1106 ea[5] = srom[srv->off + 2 - off] & 0xff;
1107
1108 varbuf_append(b, "%s=%pM", name, ea);
1109 } else {
1110 w = srom[srv->off - off];
1111 val = (w & srv->mask) >> mask_shift(srv->mask);
1112 width = mask_width(srv->mask);
1113
1114 while (srv->flags & SRFL_MORE) {
1115 srv++;
1116 if (srv->off == 0 || srv->off < off)
1117 continue;
1118
1119 w = srom[srv->off - off];
1120 val +=
1121 ((w & srv->mask) >> mask_shift(srv->
1122 mask)) <<
1123 width;
1124 width += mask_width(srv->mask);
1125 }
1126
1127 if ((flags & SRFL_NOFFS)
1128 && ((int)val == (1 << width) - 1))
1129 continue;
1130
1131 if (flags & SRFL_CCODE) {
1132 if (val == 0)
1133 varbuf_append(b, "ccode=");
1134 else
1135 varbuf_append(b, "ccode=%c%c",
1136 (val >> 8), (val & 0xff));
1137 }
1138 /* LED Powersave duty cycle has to be scaled:
1139 *(oncount >> 24) (offcount >> 8)
1140 */
1141 else if (flags & SRFL_LEDDC) {
1142 u32 w32 = (((val >> 8) & 0xff) << 24) | /* oncount */
1143 (((val & 0xff)) << 8); /* offcount */
1144 varbuf_append(b, "leddc=%d", w32);
1145 } else if (flags & SRFL_PRHEX)
1146 varbuf_append(b, "%s=0x%x", name, val);
1147 else if ((flags & SRFL_PRSIGN)
1148 && (val & (1 << (width - 1))))
1149 varbuf_append(b, "%s=%d", name,
1150 (int)(val | (~0 << width)));
1151 else
1152 varbuf_append(b, "%s=%u", name, val);
1153 }
1154 }
1155
1156 if (sromrev >= 4) {
1157 /* Do per-path variables */
1158 uint p, pb, psz;
1159
1160 if (sromrev >= 8) {
1161 pb = SROM8_PATH0;
1162 psz = SROM8_PATH1 - SROM8_PATH0;
1163 } else {
1164 pb = SROM4_PATH0;
1165 psz = SROM4_PATH1 - SROM4_PATH0;
1166 }
1167
1168 for (p = 0; p < MAX_PATH_SROM; p++) {
1169 for (srv = perpath_pci_sromvars; srv->name != NULL;
1170 srv++) {
1171 if ((srv->revmask & sr) == 0)
1172 continue;
1173
1174 if (pb + srv->off < off)
1175 continue;
1176
1177 /* This entry is for mfgc only. Don't generate param for it, */
1178 if (srv->flags & SRFL_NOVAR)
1179 continue;
1180
1181 w = srom[pb + srv->off - off];
1182 val = (w & srv->mask) >> mask_shift(srv->mask);
1183 width = mask_width(srv->mask);
1184
1185 /* Cheating: no per-path var is more than 1 word */
1186
1187 if ((srv->flags & SRFL_NOFFS)
1188 && ((int)val == (1 << width) - 1))
1189 continue;
1190
1191 if (srv->flags & SRFL_PRHEX)
1192 varbuf_append(b, "%s%d=0x%x", srv->name,
1193 p, val);
1194 else
1195 varbuf_append(b, "%s%d=%d", srv->name,
1196 p, val);
1197 }
1198 pb += psz;
1199 }
1200 }
1201 }
1202
1203 /*
1204 * Initialize nonvolatile variable table from sprom.
1205 * Return 0 on success, nonzero on error.
1206 */
1207 static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
1208 uint *count)
1209 {
1210 u16 *srom, *sromwindow;
1211 u8 sromrev = 0;
1212 u32 sr;
1213 varbuf_t b;
1214 char *vp, *base = NULL;
1215 bool flash = false;
1216 int err = 0;
1217
1218 /*
1219 * Apply CRC over SROM content regardless SROM is present or not,
1220 * and use variable <devpath>sromrev's existence in flash to decide
1221 * if we should return an error when CRC fails or read SROM variables
1222 * from flash.
1223 */
1224 srom = kmalloc(SROM_MAX, GFP_ATOMIC);
1225 if (!srom)
1226 return -2;
1227
1228 sromwindow = (u16 *) SROM_OFFSET(sih);
1229 if (ai_is_sprom_available(sih)) {
1230 err =
1231 sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
1232 true);
1233
1234 if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) ||
1235 (((sih->buscoretype == PCIE_CORE_ID)
1236 && (sih->buscorerev >= 6))
1237 || ((sih->buscoretype == PCI_CORE_ID)
1238 && (sih->buscorerev >= 0xe)))) {
1239 /* sromrev >= 4, read more */
1240 err =
1241 sprom_read_pci(sih, sromwindow, 0, srom,
1242 SROM4_WORDS, true);
1243 sromrev = srom[SROM4_CRCREV] & 0xff;
1244 } else if (err == 0) {
1245 /* srom is good and is rev < 4 */
1246 /* top word of sprom contains version and crc8 */
1247 sromrev = srom[SROM_CRCREV] & 0xff;
1248 /* bcm4401 sroms misprogrammed */
1249 if (sromrev == 0x10)
1250 sromrev = 1;
1251 }
1252 }
1253 #if defined(BCMNVRAMR)
1254 /* Use OTP if SPROM not available */
1255 else {
1256 err = otp_read_pci(sih, srom, SROM_MAX);
1257 if (err == 0)
1258 /* OTP only contain SROM rev8/rev9 for now */
1259 sromrev = srom[SROM4_CRCREV] & 0xff;
1260 else
1261 err = 1;
1262 }
1263 #else
1264 else
1265 err = 1;
1266 #endif
1267
1268 /*
1269 * We want internal/wltest driver to come up with default
1270 * sromvars so we can program a blank SPROM/OTP.
1271 */
1272 if (err) {
1273 char *value;
1274 u32 val;
1275 val = 0;
1276
1277 value = ai_getdevpathvar(sih, "sromrev");
1278 if (value) {
1279 sromrev = (u8) simple_strtoul(value, NULL, 0);
1280 flash = true;
1281 goto varscont;
1282 }
1283
1284 value = ai_getnvramflvar(sih, "sromrev");
1285 if (value) {
1286 err = 0;
1287 goto errout;
1288 }
1289
1290 {
1291 err = -1;
1292 goto errout;
1293 }
1294 }
1295
1296 varscont:
1297 /* Bitmask for the sromrev */
1298 sr = 1 << sromrev;
1299
1300 /* srom version check: Current valid versions: 1, 2, 3, 4, 5, 8, 9 */
1301 if ((sr & 0x33e) == 0) {
1302 err = -2;
1303 goto errout;
1304 }
1305
1306 base = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC);
1307 if (!base) {
1308 err = -2;
1309 goto errout;
1310 }
1311
1312 varbuf_init(&b, base, MAXSZ_NVRAM_VARS);
1313
1314 /* parse SROM into name=value pairs. */
1315 _initvars_srom_pci(sromrev, srom, 0, &b);
1316
1317 /* final nullbyte terminator */
1318 vp = b.buf;
1319 *vp++ = '\0';
1320
1321 err = initvars_table(base, vp, vars, count);
1322
1323 errout:
1324 if (base)
1325 kfree(base);
1326
1327 kfree(srom);
1328 return err;
1329 }
Linux kernel - Deliverables
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