drivers/staging/comedi/comedi.h

   1 /*
   2     include/comedi.h (installed as /usr/include/comedi.h)
   3     header file for comedi
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU Lesser General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17 */
  18
  19 #ifndef _COMEDI_H
  20 #define _COMEDI_H
  21
  22 #define COMEDI_MAJORVERSION     0
  23 #define COMEDI_MINORVERSION     7
  24 #define COMEDI_MICROVERSION     76
  25 #define VERSION "0.7.76"
  26
  27 /* comedi's major device number */
  28 #define COMEDI_MAJOR 98
  29
  30 /*
  31    maximum number of minor devices.  This can be increased, although
  32    kernel structures are currently statically allocated, thus you
  33    don't want this to be much more than you actually use.
  34  */
  35 #define COMEDI_NDEVICES 16
  36
  37 /* number of config options in the config structure */
  38 #define COMEDI_NDEVCONFOPTS 32
  39
  40 /*
  41  * NOTE: 'comedi_config --init-data' is deprecated
  42  *
  43  * The following indexes in the config options were used by
  44  * comedi_config to pass firmware blobs from user space to the
  45  * comedi drivers. The request_firmware() hotplug interface is
  46  * now used by all comedi drivers instead.
  47  */
  48
  49 /* length of nth chunk of firmware data -*/
  50 #define COMEDI_DEVCONF_AUX_DATA3_LENGTH         25
  51 #define COMEDI_DEVCONF_AUX_DATA2_LENGTH         26
  52 #define COMEDI_DEVCONF_AUX_DATA1_LENGTH         27
  53 #define COMEDI_DEVCONF_AUX_DATA0_LENGTH         28
  54 /* most significant 32 bits of pointer address (if needed) */
  55 #define COMEDI_DEVCONF_AUX_DATA_HI              29
  56 /* least significant 32 bits of pointer address */
  57 #define COMEDI_DEVCONF_AUX_DATA_LO              30
  58 #define COMEDI_DEVCONF_AUX_DATA_LENGTH          31      /* total data length */
  59
  60 /* max length of device and driver names */
  61 #define COMEDI_NAMELEN 20
  62
  63 /* packs and unpacks a channel/range number */
  64
  65 #define CR_PACK(chan, rng, aref)                                        \
  66         ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan))
  67 #define CR_PACK_FLAGS(chan, range, aref, flags)                         \
  68         (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK))
  69
  70 #define CR_CHAN(a)      ((a)&0xffff)
  71 #define CR_RANGE(a)     (((a)>>16)&0xff)
  72 #define CR_AREF(a)      (((a)>>24)&0x03)
  73
  74 #define CR_FLAGS_MASK   0xfc000000
  75 #define CR_ALT_FILTER   (1<<26)
  76 #define CR_DITHER       CR_ALT_FILTER
  77 #define CR_DEGLITCH     CR_ALT_FILTER
  78 #define CR_ALT_SOURCE   (1<<27)
  79 #define CR_EDGE         (1<<30)
  80 #define CR_INVERT       (1<<31)
  81
  82 #define AREF_GROUND     0x00    /* analog ref = analog ground */
  83 #define AREF_COMMON     0x01    /* analog ref = analog common */
  84 #define AREF_DIFF       0x02    /* analog ref = differential */
  85 #define AREF_OTHER      0x03    /* analog ref = other (undefined) */
  86
  87 /* counters -- these are arbitrary values */
  88 #define GPCT_RESET              0x0001
  89 #define GPCT_SET_SOURCE         0x0002
  90 #define GPCT_SET_GATE           0x0004
  91 #define GPCT_SET_DIRECTION      0x0008
  92 #define GPCT_SET_OPERATION      0x0010
  93 #define GPCT_ARM                0x0020
  94 #define GPCT_DISARM             0x0040
  95 #define GPCT_GET_INT_CLK_FRQ    0x0080
  96
  97 #define GPCT_INT_CLOCK          0x0001
  98 #define GPCT_EXT_PIN            0x0002
  99 #define GPCT_NO_GATE            0x0004
 100 #define GPCT_UP                 0x0008
 101 #define GPCT_DOWN               0x0010
 102 #define GPCT_HWUD               0x0020
 103 #define GPCT_SIMPLE_EVENT       0x0040
 104 #define GPCT_SINGLE_PERIOD      0x0080
 105 #define GPCT_SINGLE_PW          0x0100
 106 #define GPCT_CONT_PULSE_OUT     0x0200
 107 #define GPCT_SINGLE_PULSE_OUT   0x0400
 108
 109 /* instructions */
 110
 111 #define INSN_MASK_WRITE         0x8000000
 112 #define INSN_MASK_READ          0x4000000
 113 #define INSN_MASK_SPECIAL       0x2000000
 114
 115 #define INSN_READ               (0 | INSN_MASK_READ)
 116 #define INSN_WRITE              (1 | INSN_MASK_WRITE)
 117 #define INSN_BITS               (2 | INSN_MASK_READ|INSN_MASK_WRITE)
 118 #define INSN_CONFIG             (3 | INSN_MASK_READ|INSN_MASK_WRITE)
 119 #define INSN_GTOD               (4 | INSN_MASK_READ|INSN_MASK_SPECIAL)
 120 #define INSN_WAIT               (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
 121 #define INSN_INTTRIG            (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
 122
 123 /* trigger flags */
 124 /* These flags are used in comedi_trig structures */
 125
 126 #define TRIG_DITHER     0x0002  /* enable dithering */
 127 #define TRIG_DEGLITCH   0x0004  /* enable deglitching */
 128 #define TRIG_CONFIG     0x0010  /* perform configuration, not triggering */
 129
 130 /* command flags */
 131 /* These flags are used in comedi_cmd structures */
 132
 133 #define CMDF_BOGUS              0x00000001      /* do the motions */
 134
 135 /* try to use a real-time interrupt while performing command */
 136 #define CMDF_PRIORITY           0x00000008
 137
 138 /* wake up on end-of-scan events */
 139 #define CMDF_WAKE_EOS           0x00000020
 140
 141 #define CMDF_WRITE              0x00000040
 142
 143 #define CMDF_RAWDATA            0x00000080
 144
 145 /* timer rounding definitions */
 146 #define CMDF_ROUND_MASK         0x00030000
 147 #define CMDF_ROUND_NEAREST      0x00000000
 148 #define CMDF_ROUND_DOWN         0x00010000
 149 #define CMDF_ROUND_UP           0x00020000
 150 #define CMDF_ROUND_UP_NEXT      0x00030000
 151
 152 #define COMEDI_EV_START         0x00040000
 153 #define COMEDI_EV_SCAN_BEGIN    0x00080000
 154 #define COMEDI_EV_CONVERT       0x00100000
 155 #define COMEDI_EV_SCAN_END      0x00200000
 156 #define COMEDI_EV_STOP          0x00400000
 157
 158 /* compatibility definitions */
 159 #define TRIG_BOGUS              CMDF_BOGUS
 160 #define TRIG_RT                 CMDF_PRIORITY
 161 #define TRIG_WAKE_EOS           CMDF_WAKE_EOS
 162 #define TRIG_WRITE              CMDF_WRITE
 163 #define TRIG_ROUND_MASK         CMDF_ROUND_MASK
 164 #define TRIG_ROUND_NEAREST      CMDF_ROUND_NEAREST
 165 #define TRIG_ROUND_DOWN         CMDF_ROUND_DOWN
 166 #define TRIG_ROUND_UP           CMDF_ROUND_UP
 167 #define TRIG_ROUND_UP_NEXT      CMDF_ROUND_UP_NEXT
 168
 169 /* trigger sources */
 170
 171 #define TRIG_ANY        0xffffffff
 172 #define TRIG_INVALID    0x00000000
 173
 174 #define TRIG_NONE       0x00000001 /* never trigger */
 175 #define TRIG_NOW        0x00000002 /* trigger now + N ns */
 176 #define TRIG_FOLLOW     0x00000004 /* trigger on next lower level trig */
 177 #define TRIG_TIME       0x00000008 /* trigger at time N ns */
 178 #define TRIG_TIMER      0x00000010 /* trigger at rate N ns */
 179 #define TRIG_COUNT      0x00000020 /* trigger when count reaches N */
 180 #define TRIG_EXT        0x00000040 /* trigger on external signal N */
 181 #define TRIG_INT        0x00000080 /* trigger on comedi-internal signal N */
 182 #define TRIG_OTHER      0x00000100 /* driver defined */
 183
 184 /* subdevice flags */
 185
 186 #define SDF_BUSY        0x0001  /* device is busy */
 187 #define SDF_BUSY_OWNER  0x0002  /* device is busy with your job */
 188 #define SDF_LOCKED      0x0004  /* subdevice is locked */
 189 #define SDF_LOCK_OWNER  0x0008  /* you own lock */
 190 #define SDF_MAXDATA     0x0010  /* maxdata depends on channel */
 191 #define SDF_FLAGS       0x0020  /* flags depend on channel */
 192 #define SDF_RANGETYPE   0x0040  /* range type depends on channel */
 193 #define SDF_MODE0       0x0080  /* can do mode 0 */
 194 #define SDF_MODE1       0x0100  /* can do mode 1 */
 195 #define SDF_MODE2       0x0200  /* can do mode 2 */
 196 #define SDF_MODE3       0x0400  /* can do mode 3 */
 197 #define SDF_MODE4       0x0800  /* can do mode 4 */
 198 #define SDF_CMD         0x1000  /* can do commands (deprecated) */
 199 #define SDF_SOFT_CALIBRATED     0x2000 /* subdevice uses software calibration */
 200 #define SDF_CMD_WRITE           0x4000 /* can do output commands */
 201 #define SDF_CMD_READ            0x8000 /* can do input commands */
 202
 203 /* subdevice can be read (e.g. analog input) */
 204 #define SDF_READABLE    0x00010000
 205 /* subdevice can be written (e.g. analog output) */
 206 #define SDF_WRITABLE    0x00020000
 207 #define SDF_WRITEABLE   SDF_WRITABLE    /* spelling error in API */
 208 /* subdevice does not have externally visible lines */
 209 #define SDF_INTERNAL    0x00040000
 210 #define SDF_GROUND      0x00100000      /* can do aref=ground */
 211 #define SDF_COMMON      0x00200000      /* can do aref=common */
 212 #define SDF_DIFF        0x00400000      /* can do aref=diff */
 213 #define SDF_OTHER       0x00800000      /* can do aref=other */
 214 #define SDF_DITHER      0x01000000      /* can do dithering */
 215 #define SDF_DEGLITCH    0x02000000      /* can do deglitching */
 216 #define SDF_MMAP        0x04000000      /* can do mmap() */
 217 #define SDF_RUNNING     0x08000000      /* subdevice is acquiring data */
 218 #define SDF_LSAMPL      0x10000000      /* subdevice uses 32-bit samples */
 219 #define SDF_PACKED      0x20000000      /* subdevice can do packed DIO */
 220 /* re recycle these flags for PWM */
 221 #define SDF_PWM_COUNTER SDF_MODE0       /* PWM can automatically switch off */
 222 #define SDF_PWM_HBRIDGE SDF_MODE1       /* PWM is signed (H-bridge) */
 223
 224 /* subdevice types */
 225
 226 enum comedi_subdevice_type {
 227         COMEDI_SUBD_UNUSED,     /* unused by driver */
 228         COMEDI_SUBD_AI,         /* analog input */
 229         COMEDI_SUBD_AO,         /* analog output */
 230         COMEDI_SUBD_DI,         /* digital input */
 231         COMEDI_SUBD_DO,         /* digital output */
 232         COMEDI_SUBD_DIO,        /* digital input/output */
 233         COMEDI_SUBD_COUNTER,    /* counter */
 234         COMEDI_SUBD_TIMER,      /* timer */
 235         COMEDI_SUBD_MEMORY,     /* memory, EEPROM, DPRAM */
 236         COMEDI_SUBD_CALIB,      /* calibration DACs */
 237         COMEDI_SUBD_PROC,       /* processor, DSP */
 238         COMEDI_SUBD_SERIAL,     /* serial IO */
 239         COMEDI_SUBD_PWM         /* PWM */
 240 };
 241
 242 /* configuration instructions */
 243
 244 enum configuration_ids {
 245         INSN_CONFIG_DIO_INPUT = 0,
 246         INSN_CONFIG_DIO_OUTPUT = 1,
 247         INSN_CONFIG_DIO_OPENDRAIN = 2,
 248         INSN_CONFIG_ANALOG_TRIG = 16,
 249 /*      INSN_CONFIG_WAVEFORM = 17, */
 250 /*      INSN_CONFIG_TRIG = 18, */
 251 /*      INSN_CONFIG_COUNTER = 19, */
 252         INSN_CONFIG_ALT_SOURCE = 20,
 253         INSN_CONFIG_DIGITAL_TRIG = 21,
 254         INSN_CONFIG_BLOCK_SIZE = 22,
 255         INSN_CONFIG_TIMER_1 = 23,
 256         INSN_CONFIG_FILTER = 24,
 257         INSN_CONFIG_CHANGE_NOTIFY = 25,
 258
 259         INSN_CONFIG_SERIAL_CLOCK = 26,  /*ALPHA*/
 260         INSN_CONFIG_BIDIRECTIONAL_DATA = 27,
 261         INSN_CONFIG_DIO_QUERY = 28,
 262         INSN_CONFIG_PWM_OUTPUT = 29,
 263         INSN_CONFIG_GET_PWM_OUTPUT = 30,
 264         INSN_CONFIG_ARM = 31,
 265         INSN_CONFIG_DISARM = 32,
 266         INSN_CONFIG_GET_COUNTER_STATUS = 33,
 267         INSN_CONFIG_RESET = 34,
 268         /* Use CTR as single pulsegenerator */
 269         INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001,
 270         /* Use CTR as pulsetraingenerator */
 271         INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002,
 272         /* Use the counter as encoder */
 273         INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003,
 274         INSN_CONFIG_SET_GATE_SRC = 2001,        /* Set gate source */
 275         INSN_CONFIG_GET_GATE_SRC = 2002,        /* Get gate source */
 276         /* Set master clock source */
 277         INSN_CONFIG_SET_CLOCK_SRC = 2003,
 278         INSN_CONFIG_GET_CLOCK_SRC = 2004, /* Get master clock source */
 279         INSN_CONFIG_SET_OTHER_SRC = 2005, /* Set other source */
 280         /* INSN_CONFIG_GET_OTHER_SRC = 2006,*//* Get other source */
 281         /* Get size in bytes of subdevice's on-board fifos used during
 282          * streaming input/output */
 283         INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006,
 284         INSN_CONFIG_SET_COUNTER_MODE = 4097,
 285         /* INSN_CONFIG_8254_SET_MODE is deprecated */
 286         INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE,
 287         INSN_CONFIG_8254_READ_STATUS = 4098,
 288         INSN_CONFIG_SET_ROUTING = 4099,
 289         INSN_CONFIG_GET_ROUTING = 4109,
 290         /* PWM */
 291         INSN_CONFIG_PWM_SET_PERIOD = 5000,      /* sets frequency */
 292         INSN_CONFIG_PWM_GET_PERIOD = 5001,      /* gets frequency */
 293         INSN_CONFIG_GET_PWM_STATUS = 5002,      /* is it running? */
 294         /* sets H bridge: duty cycle and sign bit for a relay at the
 295          * same time */
 296         INSN_CONFIG_PWM_SET_H_BRIDGE = 5003,
 297         /* gets H bridge data: duty cycle and the sign bit */
 298         INSN_CONFIG_PWM_GET_H_BRIDGE = 5004
 299 };
 300
 301 /*
 302  * Settings for INSN_CONFIG_DIGITAL_TRIG:
 303  * data[0] = INSN_CONFIG_DIGITAL_TRIG
 304  * data[1] = trigger ID
 305  * data[2] = configuration operation
 306  * data[3] = configuration parameter 1
 307  * data[4] = configuration parameter 2
 308  * data[5] = configuration parameter 3
 309  *
 310  * operation                           parameter 1   parameter 2   parameter 3
 311  * ---------------------------------   -----------   -----------   -----------
 312  * COMEDI_DIGITAL_TRIG_DISABLE
 313  * COMEDI_DIGITAL_TRIG_ENABLE_EDGES    left-shift    rising-edges  falling-edges
 314  * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS   left-shift    high-levels   low-levels
 315  *
 316  * COMEDI_DIGITAL_TRIG_DISABLE returns the trigger to its default, inactive,
 317  * unconfigured state.
 318  *
 319  * COMEDI_DIGITAL_TRIG_ENABLE_EDGES sets the rising and/or falling edge inputs
 320  * that each can fire the trigger.
 321  *
 322  * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS sets a combination of high and/or low
 323  * level inputs that can fire the trigger.
 324  *
 325  * "left-shift" is useful if the trigger has more than 32 inputs to specify the
 326  * first input for this configuration.
 327  *
 328  * Some sequences of INSN_CONFIG_DIGITAL_TRIG instructions may have a (partly)
 329  * accumulative effect, depending on the low-level driver.  This is useful
 330  * when setting up a trigger that has more than 32 inputs or has a combination
 331  * of edge and level triggered inputs.
 332  */
 333 enum comedi_digital_trig_op {
 334         COMEDI_DIGITAL_TRIG_DISABLE = 0,
 335         COMEDI_DIGITAL_TRIG_ENABLE_EDGES = 1,
 336         COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = 2
 337 };
 338
 339 enum comedi_io_direction {
 340         COMEDI_INPUT = 0,
 341         COMEDI_OUTPUT = 1,
 342         COMEDI_OPENDRAIN = 2
 343 };
 344
 345 enum comedi_support_level {
 346         COMEDI_UNKNOWN_SUPPORT = 0,
 347         COMEDI_SUPPORTED,
 348         COMEDI_UNSUPPORTED
 349 };
 350
 351 /* ioctls */
 352
 353 #define CIO 'd'
 354 #define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig)
 355 #define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo)
 356 #define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo)
 357 #define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo)
 358 #define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig)
 359 #define COMEDI_LOCK _IO(CIO, 5)
 360 #define COMEDI_UNLOCK _IO(CIO, 6)
 361 #define COMEDI_CANCEL _IO(CIO, 7)
 362 #define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo)
 363 #define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd)
 364 #define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd)
 365 #define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist)
 366 #define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn)
 367 #define COMEDI_BUFCONFIG _IOR(CIO, 13, struct comedi_bufconfig)
 368 #define COMEDI_BUFINFO _IOWR(CIO, 14, struct comedi_bufinfo)
 369 #define COMEDI_POLL _IO(CIO, 15)
 370 #define COMEDI_SETRSUBD _IO(CIO, 16)
 371 #define COMEDI_SETWSUBD _IO(CIO, 17)
 372
 373 /* structures */
 374
 375 struct comedi_trig {
 376         unsigned int subdev;    /* subdevice */
 377         unsigned int mode;      /* mode */
 378         unsigned int flags;
 379         unsigned int n_chan;    /* number of channels */
 380         unsigned int *chanlist; /* channel/range list */
 381         short *data;            /* data list, size depends on subd flags */
 382         unsigned int n;         /* number of scans */
 383         unsigned int trigsrc;
 384         unsigned int trigvar;
 385         unsigned int trigvar1;
 386         unsigned int data_len;
 387         unsigned int unused[3];
 388 };
 389
 390 struct comedi_insn {
 391         unsigned int insn;
 392         unsigned int n;
 393         unsigned int __user *data;
 394         unsigned int subdev;
 395         unsigned int chanspec;
 396         unsigned int unused[3];
 397 };
 398
 399 struct comedi_insnlist {
 400         unsigned int n_insns;
 401         struct comedi_insn __user *insns;
 402 };
 403
 404 struct comedi_cmd {
 405         unsigned int subdev;
 406         unsigned int flags;
 407
 408         unsigned int start_src;
 409         unsigned int start_arg;
 410
 411         unsigned int scan_begin_src;
 412         unsigned int scan_begin_arg;
 413
 414         unsigned int convert_src;
 415         unsigned int convert_arg;
 416
 417         unsigned int scan_end_src;
 418         unsigned int scan_end_arg;
 419
 420         unsigned int stop_src;
 421         unsigned int stop_arg;
 422
 423         unsigned int *chanlist; /* channel/range list */
 424         unsigned int chanlist_len;
 425
 426         short __user *data; /* data list, size depends on subd flags */
 427         unsigned int data_len;
 428 };
 429
 430 struct comedi_chaninfo {
 431         unsigned int subdev;
 432         unsigned int __user *maxdata_list;
 433         unsigned int __user *flaglist;
 434         unsigned int __user *rangelist;
 435         unsigned int unused[4];
 436 };
 437
 438 struct comedi_rangeinfo {
 439         unsigned int range_type;
 440         void __user *range_ptr;
 441 };
 442
 443 struct comedi_krange {
 444         int min;        /* fixed point, multiply by 1e-6 */
 445         int max;        /* fixed point, multiply by 1e-6 */
 446         unsigned int flags;
 447 };
 448
 449 struct comedi_subdinfo {
 450         unsigned int type;
 451         unsigned int n_chan;
 452         unsigned int subd_flags;
 453         unsigned int timer_type;
 454         unsigned int len_chanlist;
 455         unsigned int maxdata;
 456         unsigned int flags;             /* channel flags */
 457         unsigned int range_type;        /* lookup in kernel */
 458         unsigned int settling_time_0;
 459         /* see support_level enum for values */
 460         unsigned insn_bits_support;
 461         unsigned int unused[8];
 462 };
 463
 464 struct comedi_devinfo {
 465         unsigned int version_code;
 466         unsigned int n_subdevs;
 467         char driver_name[COMEDI_NAMELEN];
 468         char board_name[COMEDI_NAMELEN];
 469         int read_subdevice;
 470         int write_subdevice;
 471         int unused[30];
 472 };
 473
 474 struct comedi_devconfig {
 475         char board_name[COMEDI_NAMELEN];
 476         int options[COMEDI_NDEVCONFOPTS];
 477 };
 478
 479 struct comedi_bufconfig {
 480         unsigned int subdevice;
 481         unsigned int flags;
 482
 483         unsigned int maximum_size;
 484         unsigned int size;
 485
 486         unsigned int unused[4];
 487 };
 488
 489 struct comedi_bufinfo {
 490         unsigned int subdevice;
 491         unsigned int bytes_read;
 492
 493         unsigned int buf_write_ptr;
 494         unsigned int buf_read_ptr;
 495         unsigned int buf_write_count;
 496         unsigned int buf_read_count;
 497
 498         unsigned int bytes_written;
 499
 500         unsigned int unused[4];
 501 };
 502
 503 /* range stuff */
 504
 505 #define __RANGE(a, b)   ((((a)&0xffff)<<16)|((b)&0xffff))
 506
 507 #define RANGE_OFFSET(a)         (((a)>>16)&0xffff)
 508 #define RANGE_LENGTH(b)         ((b)&0xffff)
 509
 510 #define RF_UNIT(flags)          ((flags)&0xff)
 511 #define RF_EXTERNAL             (1<<8)
 512
 513 #define UNIT_volt               0
 514 #define UNIT_mA                 1
 515 #define UNIT_none               2
 516
 517 #define COMEDI_MIN_SPEED        ((unsigned int)0xffffffff)
 518
 519 /**********************************************************/
 520 /* everything after this line is ALPHA */
 521 /**********************************************************/
 522
 523 /*
 524   8254 specific configuration.
 525
 526   It supports two config commands:
 527
 528   0 ID: INSN_CONFIG_SET_COUNTER_MODE
 529   1 8254 Mode
 530     I8254_MODE0, I8254_MODE1, ..., I8254_MODE5
 531     OR'ed with:
 532     I8254_BCD, I8254_BINARY
 533
 534   0 ID: INSN_CONFIG_8254_READ_STATUS
 535   1 <-- Status byte returned here.
 536     B7 = Output
 537     B6 = NULL Count
 538     B5 - B0 Current mode.
 539
 540 */
 541
 542 enum i8254_mode {
 543         I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */
 544         I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */
 545         I8254_MODE2 = (2 << 1), /* Rate generator */
 546         I8254_MODE3 = (3 << 1), /* Square wave mode */
 547         I8254_MODE4 = (4 << 1), /* Software triggered strobe */
 548         I8254_MODE5 = (5 << 1), /* Hardware triggered strobe
 549                                  * (retriggerable) */
 550         I8254_BCD = 1,          /* use binary-coded decimal instead of binary
 551                                  * (pretty useless) */
 552         I8254_BINARY = 0
 553 };
 554
 555 #define NI_USUAL_PFI_SELECT(x)  (((x) < 10) ? (0x1 + (x)) : (0xb + (x)))
 556 #define NI_USUAL_RTSI_SELECT(x) (((x) < 7) ? (0xb + (x)) : 0x1b)
 557
 558 /* mode bits for NI general-purpose counters, set with
 559  * INSN_CONFIG_SET_COUNTER_MODE */
 560 #define NI_GPCT_COUNTING_MODE_SHIFT 16
 561 #define NI_GPCT_INDEX_PHASE_BITSHIFT 20
 562 #define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
 563 enum ni_gpct_mode_bits {
 564         NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4,
 565         NI_GPCT_EDGE_GATE_MODE_MASK = 0x18,
 566         NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0,
 567         NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8,
 568         NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10,
 569         NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18,
 570         NI_GPCT_STOP_MODE_MASK = 0x60,
 571         NI_GPCT_STOP_ON_GATE_BITS = 0x00,
 572         NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20,
 573         NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40,
 574         NI_GPCT_LOAD_B_SELECT_BIT = 0x80,
 575         NI_GPCT_OUTPUT_MODE_MASK = 0x300,
 576         NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100,
 577         NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200,
 578         NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300,
 579         NI_GPCT_HARDWARE_DISARM_MASK = 0xc00,
 580         NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000,
 581         NI_GPCT_DISARM_AT_TC_BITS = 0x400,
 582         NI_GPCT_DISARM_AT_GATE_BITS = 0x800,
 583         NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00,
 584         NI_GPCT_LOADING_ON_TC_BIT = 0x1000,
 585         NI_GPCT_LOADING_ON_GATE_BIT = 0x4000,
 586         NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT,
 587         NI_GPCT_COUNTING_MODE_NORMAL_BITS =
 588                 0x0 << NI_GPCT_COUNTING_MODE_SHIFT,
 589         NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS =
 590                 0x1 << NI_GPCT_COUNTING_MODE_SHIFT,
 591         NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS =
 592                 0x2 << NI_GPCT_COUNTING_MODE_SHIFT,
 593         NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS =
 594                 0x3 << NI_GPCT_COUNTING_MODE_SHIFT,
 595         NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS =
 596                 0x4 << NI_GPCT_COUNTING_MODE_SHIFT,
 597         NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS =
 598                 0x6 << NI_GPCT_COUNTING_MODE_SHIFT,
 599         NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 600         NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS =
 601                 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 602         NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS =
 603                 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 604         NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS =
 605                 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 606         NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS =
 607                 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 608         NI_GPCT_INDEX_ENABLE_BIT = 0x400000,
 609         NI_GPCT_COUNTING_DIRECTION_MASK =
 610                 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 611         NI_GPCT_COUNTING_DIRECTION_DOWN_BITS =
 612                 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 613         NI_GPCT_COUNTING_DIRECTION_UP_BITS =
 614                 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 615         NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS =
 616                 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 617         NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS =
 618                 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 619         NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000,
 620         NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0,
 621         NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000,
 622         NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000,
 623         NI_GPCT_OR_GATE_BIT = 0x10000000,
 624         NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000
 625 };
 626
 627 /* Bits for setting a clock source with
 628  * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */
 629 enum ni_gpct_clock_source_bits {
 630         NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f,
 631         NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0,
 632         NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1,
 633         NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2,
 634         NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3,
 635         NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4,
 636         NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5,
 637         /* NI 660x-specific */
 638         NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6,
 639         NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7,
 640         NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8,
 641         NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9,
 642         NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000,
 643         NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0,
 644         /* divide source by 2 */
 645         NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000,
 646         /* divide source by 8 */
 647         NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000,
 648         NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000
 649 };
 650
 651 /* NI 660x-specific */
 652 #define NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(x)    (0x10 + (x))
 653
 654 #define NI_GPCT_RTSI_CLOCK_SRC_BITS(x)          (0x18 + (x))
 655
 656 /* no pfi on NI 660x */
 657 #define NI_GPCT_PFI_CLOCK_SRC_BITS(x)           (0x20 + (x))
 658
 659 /* Possibilities for setting a gate source with
 660 INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
 661 May be bitwise-or'd with CR_EDGE or CR_INVERT. */
 662 enum ni_gpct_gate_select {
 663         /* m-series gates */
 664         NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0,
 665         NI_GPCT_AI_START2_GATE_SELECT = 0x12,
 666         NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13,
 667         NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14,
 668         NI_GPCT_AI_START1_GATE_SELECT = 0x1c,
 669         NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d,
 670         NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e,
 671         NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f,
 672         /* more gates for 660x */
 673         NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100,
 674         NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101,
 675         /* more gates for 660x "second gate" */
 676         NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201,
 677         NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e,
 678         /* m-series "second gate" sources are unknown,
 679          * we should add them here with an offset of 0x300 when
 680          * known. */
 681         NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
 682 };
 683
 684 #define NI_GPCT_GATE_PIN_GATE_SELECT(x)         (0x102 + (x))
 685 #define NI_GPCT_RTSI_GATE_SELECT(x)             NI_USUAL_RTSI_SELECT(x)
 686 #define NI_GPCT_PFI_GATE_SELECT(x)              NI_USUAL_PFI_SELECT(x)
 687 #define NI_GPCT_UP_DOWN_PIN_GATE_SELECT(x)      (0x202 + (x))
 688
 689 /* Possibilities for setting a source with
 690 INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */
 691 enum ni_gpct_other_index {
 692         NI_GPCT_SOURCE_ENCODER_A,
 693         NI_GPCT_SOURCE_ENCODER_B,
 694         NI_GPCT_SOURCE_ENCODER_Z
 695 };
 696
 697 enum ni_gpct_other_select {
 698         /* m-series gates */
 699         /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */
 700         NI_GPCT_DISABLED_OTHER_SELECT = 0x8000,
 701 };
 702
 703 #define NI_GPCT_PFI_OTHER_SELECT(x)     NI_USUAL_PFI_SELECT(x)
 704
 705 /* start sources for ni general-purpose counters for use with
 706 INSN_CONFIG_ARM */
 707 enum ni_gpct_arm_source {
 708         NI_GPCT_ARM_IMMEDIATE = 0x0,
 709         NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter
 710                                              * and the adjacent paired
 711                                              * counter simultaneously */
 712         /* NI doesn't document bits for selecting hardware arm triggers.
 713          * If the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least
 714          * significant bits (3 bits for 660x or 5 bits for m-series)
 715          * through to the hardware.  This will at least allow someone to
 716          * figure out what the bits do later. */
 717         NI_GPCT_ARM_UNKNOWN = 0x1000,
 718 };
 719
 720 /* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */
 721 enum ni_gpct_filter_select {
 722         NI_GPCT_FILTER_OFF = 0x0,
 723         NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1,
 724         NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2,
 725         NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3,
 726         NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4,
 727         NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5,
 728         NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6
 729 };
 730
 731 /* PFI digital filtering options for ni m-series for use with
 732  * INSN_CONFIG_FILTER. */
 733 enum ni_pfi_filter_select {
 734         NI_PFI_FILTER_OFF = 0x0,
 735         NI_PFI_FILTER_125ns = 0x1,
 736         NI_PFI_FILTER_6425ns = 0x2,
 737         NI_PFI_FILTER_2550us = 0x3
 738 };
 739
 740 /* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */
 741 enum ni_mio_clock_source {
 742         NI_MIO_INTERNAL_CLOCK = 0,
 743         NI_MIO_RTSI_CLOCK = 1,  /* doesn't work for m-series, use
 744                                    NI_MIO_PLL_RTSI_CLOCK() */
 745         /* the NI_MIO_PLL_* sources are m-series only */
 746         NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2,
 747         NI_MIO_PLL_PXI10_CLOCK = 3,
 748         NI_MIO_PLL_RTSI0_CLOCK = 4
 749 };
 750
 751 #define NI_MIO_PLL_RTSI_CLOCK(x)        (NI_MIO_PLL_RTSI0_CLOCK + (x))
 752
 753 /* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING.
 754  The numbers assigned are not arbitrary, they correspond to the bits required
 755  to program the board. */
 756 enum ni_rtsi_routing {
 757         NI_RTSI_OUTPUT_ADR_START1 = 0,
 758         NI_RTSI_OUTPUT_ADR_START2 = 1,
 759         NI_RTSI_OUTPUT_SCLKG = 2,
 760         NI_RTSI_OUTPUT_DACUPDN = 3,
 761         NI_RTSI_OUTPUT_DA_START1 = 4,
 762         NI_RTSI_OUTPUT_G_SRC0 = 5,
 763         NI_RTSI_OUTPUT_G_GATE0 = 6,
 764         NI_RTSI_OUTPUT_RGOUT0 = 7,
 765         NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
 766         NI_RTSI_OUTPUT_RTSI_OSC = 12    /* pre-m-series always have RTSI
 767                                          * clock on line 7 */
 768 };
 769
 770 #define NI_RTSI_OUTPUT_RTSI_BRD(x)      (NI_RTSI_OUTPUT_RTSI_BRD_0 + (x))
 771
 772 /* Signals which can be routed to an NI PFI pin on an m-series board with
 773  * INSN_CONFIG_SET_ROUTING.  These numbers are also returned by
 774  * INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing
 775  * cannot be changed.  The numbers assigned are not arbitrary, they correspond
 776  * to the bits required to program the board. */
 777 enum ni_pfi_routing {
 778         NI_PFI_OUTPUT_PFI_DEFAULT = 0,
 779         NI_PFI_OUTPUT_AI_START1 = 1,
 780         NI_PFI_OUTPUT_AI_START2 = 2,
 781         NI_PFI_OUTPUT_AI_CONVERT = 3,
 782         NI_PFI_OUTPUT_G_SRC1 = 4,
 783         NI_PFI_OUTPUT_G_GATE1 = 5,
 784         NI_PFI_OUTPUT_AO_UPDATE_N = 6,
 785         NI_PFI_OUTPUT_AO_START1 = 7,
 786         NI_PFI_OUTPUT_AI_START_PULSE = 8,
 787         NI_PFI_OUTPUT_G_SRC0 = 9,
 788         NI_PFI_OUTPUT_G_GATE0 = 10,
 789         NI_PFI_OUTPUT_EXT_STROBE = 11,
 790         NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12,
 791         NI_PFI_OUTPUT_GOUT0 = 13,
 792         NI_PFI_OUTPUT_GOUT1 = 14,
 793         NI_PFI_OUTPUT_FREQ_OUT = 15,
 794         NI_PFI_OUTPUT_PFI_DO = 16,
 795         NI_PFI_OUTPUT_I_ATRIG = 17,
 796         NI_PFI_OUTPUT_RTSI0 = 18,
 797         NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26,
 798         NI_PFI_OUTPUT_SCXI_TRIG1 = 27,
 799         NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28,
 800         NI_PFI_OUTPUT_CDI_SAMPLE = 29,
 801         NI_PFI_OUTPUT_CDO_UPDATE = 30
 802 };
 803
 804 #define NI_PFI_OUTPUT_RTSI(x)           (NI_PFI_OUTPUT_RTSI0 + (x))
 805
 806 /* Signals which can be routed to output on a NI PFI pin on a 660x board
 807  with INSN_CONFIG_SET_ROUTING.  The numbers assigned are
 808  not arbitrary, they correspond to the bits required
 809  to program the board.  Lines 0 to 7 can only be set to
 810  NI_660X_PFI_OUTPUT_DIO.  Lines 32 to 39 can only be set to
 811  NI_660X_PFI_OUTPUT_COUNTER. */
 812 enum ni_660x_pfi_routing {
 813         NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */
 814         NI_660X_PFI_OUTPUT_DIO = 2,     /* static digital output */
 815 };
 816
 817 /* NI External Trigger lines.  These values are not arbitrary, but are related
 818  * to the bits required to program the board (offset by 1 for historical
 819  * reasons). */
 820 #define NI_EXT_PFI(x)                   (NI_USUAL_PFI_SELECT(x) - 1)
 821 #define NI_EXT_RTSI(x)                  (NI_USUAL_RTSI_SELECT(x) - 1)
 822
 823 /* status bits for INSN_CONFIG_GET_COUNTER_STATUS */
 824 enum comedi_counter_status_flags {
 825         COMEDI_COUNTER_ARMED = 0x1,
 826         COMEDI_COUNTER_COUNTING = 0x2,
 827         COMEDI_COUNTER_TERMINAL_COUNT = 0x4,
 828 };
 829
 830 /* Clock sources for CDIO subdevice on NI m-series boards.  Used as the
 831  * scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd
 832  * with CR_INVERT to change polarity. */
 833 enum ni_m_series_cdio_scan_begin_src {
 834         NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0,
 835         NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18,
 836         NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19,
 837         NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20,
 838         NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28,
 839         NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29,
 840         NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30,
 841         NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31,
 842         NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32,
 843         NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33
 844 };
 845
 846 #define NI_CDIO_SCAN_BEGIN_SRC_PFI(x)   NI_USUAL_PFI_SELECT(x)
 847 #define NI_CDIO_SCAN_BEGIN_SRC_RTSI(x)  NI_USUAL_RTSI_SELECT(x)
 848
 849 /* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI
 850  * boards.  These scan begin sources can also be bitwise-or'd with CR_INVERT to
 851  * change polarity. */
 852 #define NI_AO_SCAN_BEGIN_SRC_PFI(x)     NI_USUAL_PFI_SELECT(x)
 853 #define NI_AO_SCAN_BEGIN_SRC_RTSI(x)    NI_USUAL_RTSI_SELECT(x)
 854
 855 /* Bits for setting a clock source with
 856  * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */
 857 enum ni_freq_out_clock_source_bits {
 858         NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */
 859         NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC        /* 100 KHz */
 860 };
 861
 862 /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
 863  * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
 864 enum amplc_dio_clock_source {
 865         AMPLC_DIO_CLK_CLKN,     /* per channel external clock
 866                                    input/output pin (pin is only an
 867                                    input when clock source set to this
 868                                    value, otherwise it is an output) */
 869         AMPLC_DIO_CLK_10MHZ,    /* 10 MHz internal clock */
 870         AMPLC_DIO_CLK_1MHZ,     /* 1 MHz internal clock */
 871         AMPLC_DIO_CLK_100KHZ,   /* 100 kHz internal clock */
 872         AMPLC_DIO_CLK_10KHZ,    /* 10 kHz internal clock */
 873         AMPLC_DIO_CLK_1KHZ,     /* 1 kHz internal clock */
 874         AMPLC_DIO_CLK_OUTNM1,   /* output of preceding counter channel
 875                                    (for channel 0, preceding counter
 876                                    channel is channel 2 on preceding
 877                                    counter subdevice, for first counter
 878                                    subdevice, preceding counter
 879                                    subdevice is the last counter
 880                                    subdevice) */
 881         AMPLC_DIO_CLK_EXT,      /* per chip external input pin */
 882         /* the following are "enhanced" clock sources for PCIe models */
 883         AMPLC_DIO_CLK_VCC,      /* clock input HIGH */
 884         AMPLC_DIO_CLK_GND,      /* clock input LOW */
 885         AMPLC_DIO_CLK_PAT_PRESENT, /* "pattern present" signal */
 886         AMPLC_DIO_CLK_20MHZ     /* 20 MHz internal clock */
 887 };
 888
 889 /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
 890  * timer subdevice on some Amplicon DIO PCIe boards (amplc_dio200 driver). */
 891 enum amplc_dio_ts_clock_src {
 892         AMPLC_DIO_TS_CLK_1GHZ,  /* 1 ns period with 20 ns granularity */
 893         AMPLC_DIO_TS_CLK_1MHZ,  /* 1 us period */
 894         AMPLC_DIO_TS_CLK_1KHZ   /* 1 ms period */
 895 };
 896
 897 /* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for
 898  * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
 899 enum amplc_dio_gate_source {
 900         AMPLC_DIO_GAT_VCC,      /* internal high logic level */
 901         AMPLC_DIO_GAT_GND,      /* internal low logic level */
 902         AMPLC_DIO_GAT_GATN,     /* per channel external gate input */
 903         AMPLC_DIO_GAT_NOUTNM2,  /* negated output of counter channel
 904                                    minus 2 (for channels 0 or 1,
 905                                    channel minus 2 is channel 1 or 2 on
 906                                    the preceding counter subdevice, for
 907                                    the first counter subdevice the
 908                                    preceding counter subdevice is the
 909                                    last counter subdevice) */
 910         AMPLC_DIO_GAT_RESERVED4,
 911         AMPLC_DIO_GAT_RESERVED5,
 912         AMPLC_DIO_GAT_RESERVED6,
 913         AMPLC_DIO_GAT_RESERVED7,
 914         /* the following are "enhanced" gate sources for PCIe models */
 915         AMPLC_DIO_GAT_NGATN = 6, /* negated per channel gate input */
 916         AMPLC_DIO_GAT_OUTNM2,   /* non-negated output of counter
 917                                    channel minus 2 */
 918         AMPLC_DIO_GAT_PAT_PRESENT, /* "pattern present" signal */
 919         AMPLC_DIO_GAT_PAT_OCCURRED, /* "pattern occurred" latched */
 920         AMPLC_DIO_GAT_PAT_GONE, /* "pattern gone away" latched */
 921         AMPLC_DIO_GAT_NPAT_PRESENT, /* negated "pattern present" */
 922         AMPLC_DIO_GAT_NPAT_OCCURRED, /* negated "pattern occurred" */
 923         AMPLC_DIO_GAT_NPAT_GONE /* negated "pattern gone away" */
 924 };
 925
 926 /*
 927  * Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
 928  * the counter subdevice on the Kolter Electronic PCI-Counter board
 929  * (ke_counter driver).
 930  */
 931 enum ke_counter_clock_source {
 932         KE_CLK_20MHZ,   /* internal 20MHz (default) */
 933         KE_CLK_4MHZ,    /* internal 4MHz (option) */
 934         KE_CLK_EXT      /* external clock on pin 21 of D-Sub */
 935 };
 936
 937 #endif /* _COMEDI_H */