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Merge 3.9-rc5 into staging-next
[deliverable/linux.git] / drivers / staging / comedi / drivers / adv_pci_dio.c
1 /*
2 * comedi/drivers/adv_pci_dio.c
3 *
4 * Author: Michal Dobes <dobes@tesnet.cz>
5 *
6 * Hardware driver for Advantech PCI DIO cards.
7 */
8 /*
9 Driver: adv_pci_dio
10 Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U,
11 PCI-1736UP, PCI-1739U, PCI-1750, PCI-1751, PCI-1752,
12 PCI-1753/E, PCI-1754, PCI-1756, PCI-1760, PCI-1762
13 Author: Michal Dobes <dobes@tesnet.cz>
14 Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
15 PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
16 PCI-1751, PCI-1752, PCI-1753,
17 PCI-1753+PCI-1753E, PCI-1754, PCI-1756,
18 PCI-1760, PCI-1762
19 Status: untested
20 Updated: Mon, 09 Jan 2012 12:40:46 +0000
21
22 This driver supports now only insn interface for DI/DO/DIO.
23
24 Configuration options:
25 [0] - PCI bus of device (optional)
26 [1] - PCI slot of device (optional)
27 If bus/slot is not specified, the first available PCI
28 device will be used.
29
30 */
31
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34
35 #include "../comedidev.h"
36
37 #include "8255.h"
38 #include "8253.h"
39
40 /* hardware types of the cards */
41 enum hw_cards_id {
42 TYPE_PCI1730, TYPE_PCI1733, TYPE_PCI1734, TYPE_PCI1735, TYPE_PCI1736,
43 TYPE_PCI1739,
44 TYPE_PCI1750,
45 TYPE_PCI1751,
46 TYPE_PCI1752,
47 TYPE_PCI1753, TYPE_PCI1753E,
48 TYPE_PCI1754, TYPE_PCI1756,
49 TYPE_PCI1760,
50 TYPE_PCI1762
51 };
52
53 /* which I/O instructions to use */
54 enum hw_io_access {
55 IO_8b, IO_16b
56 };
57
58 #define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */
59 #define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */
60 #define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per
61 * card */
62 #define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per
63 * card */
64 /* (could be more than one 8254 per
65 * subdevice) */
66
67 #define SIZE_8254 4 /* 8254 IO space length */
68 #define SIZE_8255 4 /* 8255 IO space length */
69
70 #define PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */
71
72 /* Register offset definitions */
73 /* Advantech PCI-1730/3/4 */
74 #define PCI1730_IDI 0 /* R: Isolated digital input 0-15 */
75 #define PCI1730_IDO 0 /* W: Isolated digital output 0-15 */
76 #define PCI1730_DI 2 /* R: Digital input 0-15 */
77 #define PCI1730_DO 2 /* W: Digital output 0-15 */
78 #define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */
79 #define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
80 #define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for
81 * interrupts */
82 #define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */
83 #define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */
84 #define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */
85
86 /* Advantech PCI-1735U */
87 #define PCI1735_DI 0 /* R: Digital input 0-31 */
88 #define PCI1735_DO 0 /* W: Digital output 0-31 */
89 #define PCI1735_C8254 4 /* R/W: 8254 counter */
90 #define PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */
91
92 /* Advantech PCI-1736UP */
93 #define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */
94 #define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */
95 #define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
96 #define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for
97 * interrupts */
98 #define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */
99 #define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */
100 #define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */
101
102 /* Advantech PCI-1739U */
103 #define PCI1739_DIO 0 /* R/W: begin of 8255 registers block */
104 #define PCI1739_ICR 32 /* W: Interrupt control register */
105 #define PCI1739_ISR 32 /* R: Interrupt status register */
106 #define PCI1739_BOARDID 8 /* R: Board I/D switch for 1739U */
107
108 /* Advantech PCI-1750 */
109 #define PCI1750_IDI 0 /* R: Isolated digital input 0-15 */
110 #define PCI1750_IDO 0 /* W: Isolated digital output 0-15 */
111 #define PCI1750_ICR 32 /* W: Interrupt control register */
112 #define PCI1750_ISR 32 /* R: Interrupt status register */
113
114 /* Advantech PCI-1751/3/3E */
115 #define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */
116 #define PCI1751_CNT 24 /* R/W: begin of 8254 registers block */
117 #define PCI1751_ICR 32 /* W: Interrupt control register */
118 #define PCI1751_ISR 32 /* R: Interrupt status register */
119 #define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */
120 #define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */
121 #define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */
122 #define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */
123 #define PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */
124 #define PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */
125 #define PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */
126 #define PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */
127 #define PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */
128 #define PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */
129
130 /* Advantech PCI-1752/4/6 */
131 #define PCI1752_IDO 0 /* R/W: Digital output 0-31 */
132 #define PCI1752_IDO2 4 /* R/W: Digital output 32-63 */
133 #define PCI1754_IDI 0 /* R: Digital input 0-31 */
134 #define PCI1754_IDI2 4 /* R: Digital input 32-64 */
135 #define PCI1756_IDI 0 /* R: Digital input 0-31 */
136 #define PCI1756_IDO 4 /* R/W: Digital output 0-31 */
137 #define PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */
138 #define PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */
139 #define PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */
140 #define PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */
141 #define PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */
142 #define PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */
143
144 /* Advantech PCI-1762 registers */
145 #define PCI1762_RO 0 /* R/W: Relays status/output */
146 #define PCI1762_IDI 2 /* R: Isolated input status */
147 #define PCI1762_BOARDID 4 /* R: Board I/D switch */
148 #define PCI1762_ICR 6 /* W: Interrupt control register */
149 #define PCI1762_ISR 6 /* R: Interrupt status register */
150
151 /* Advantech PCI-1760 registers */
152 #define OMB0 0x0c /* W: Mailbox outgoing registers */
153 #define OMB1 0x0d
154 #define OMB2 0x0e
155 #define OMB3 0x0f
156 #define IMB0 0x1c /* R: Mailbox incoming registers */
157 #define IMB1 0x1d
158 #define IMB2 0x1e
159 #define IMB3 0x1f
160 #define INTCSR0 0x38 /* R/W: Interrupt control registers */
161 #define INTCSR1 0x39
162 #define INTCSR2 0x3a
163 #define INTCSR3 0x3b
164
165 /* PCI-1760 mailbox commands */
166 #define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actual
167 * DI status in IMB3 */
168 #define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */
169 #define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */
170 #define CMD_ReadCurrentStatus 0x07 /* Read the current status of the
171 * register in OMB0, result in IMB0 */
172 #define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in
173 * IMB1.IMB0 */
174 #define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in
175 * IMB1.IMB0 */
176 #define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in
177 * OMB0 */
178 #define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on
179 * bits in OMB0 */
180 #define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on
181 * bits in OMB0 */
182 #define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in
183 * OMB0 */
184 #define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in
185 * OMB0 to its reset values */
186 #define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow
187 * interrupts based on bits in OMB0 */
188 #define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value
189 * interrupts based on bits in OMB0 */
190 #define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0
191 * - rising, =1 - falling) */
192 #define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current
193 * value */
194 #define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value
195 * 256*OMB1+OMB0 */
196 #define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value
197 * 256*OMB1+OMB0 */
198 #define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value
199 * 256*OMB1+OMB0 */
200 #define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value
201 * 256*OMB1+OMB0 */
202 #define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value
203 * 256*OMB1+OMB0 */
204 #define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value
205 * 256*OMB1+OMB0 */
206 #define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value
207 * 256*OMB1+OMB0 */
208 #define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value
209 * 256*OMB1+OMB0 */
210 #define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value
211 * 256*OMB1+OMB0 */
212 #define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value
213 * 256*OMB1+OMB0 */
214 #define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value
215 * 256*OMB1+OMB0 */
216 #define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value
217 * 256*OMB1+OMB0 */
218 #define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value
219 * 256*OMB1+OMB0 */
220 #define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value
221 * 256*OMB1+OMB0 */
222 #define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value
223 * 256*OMB1+OMB0 */
224 #define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value
225 * 256*OMB1+OMB0 */
226
227 #define OMBCMD_RETRY 0x03 /* 3 times try request before error */
228
229 struct diosubd_data {
230 int chans; /* num of chans */
231 int addr; /* PCI address ofset */
232 int regs; /* number of registers to read or 8255
233 subdevices or 8254 chips */
234 unsigned int specflags; /* addon subdevice flags */
235 };
236
237 struct dio_boardtype {
238 const char *name; /* board name */
239 int main_pci_region; /* main I/O PCI region */
240 enum hw_cards_id cardtype;
241 int nsubdevs;
242 struct diosubd_data sdi[MAX_DI_SUBDEVS]; /* DI chans */
243 struct diosubd_data sdo[MAX_DO_SUBDEVS]; /* DO chans */
244 struct diosubd_data sdio[MAX_DIO_SUBDEVG]; /* DIO 8255 chans */
245 struct diosubd_data boardid; /* card supports board ID switch */
246 struct diosubd_data s8254[MAX_8254_SUBDEVS]; /* 8254 subdevices */
247 enum hw_io_access io_access;
248 };
249
250 static const struct dio_boardtype boardtypes[] = {
251 [TYPE_PCI1730] = {
252 .name = "pci1730",
253 .main_pci_region = PCIDIO_MAINREG,
254 .cardtype = TYPE_PCI1730,
255 .nsubdevs = 5,
256 .sdi[0] = { 16, PCI1730_DI, 2, 0, },
257 .sdi[1] = { 16, PCI1730_IDI, 2, 0, },
258 .sdo[0] = { 16, PCI1730_DO, 2, 0, },
259 .sdo[1] = { 16, PCI1730_IDO, 2, 0, },
260 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
261 .io_access = IO_8b,
262 },
263 [TYPE_PCI1733] = {
264 .name = "pci1733",
265 .main_pci_region = PCIDIO_MAINREG,
266 .cardtype = TYPE_PCI1733,
267 .nsubdevs = 2,
268 .sdi[1] = { 32, PCI1733_IDI, 4, 0, },
269 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
270 .io_access = IO_8b,
271 },
272 [TYPE_PCI1734] = {
273 .name = "pci1734",
274 .main_pci_region = PCIDIO_MAINREG,
275 .cardtype = TYPE_PCI1734,
276 .nsubdevs = 2,
277 .sdo[1] = { 32, PCI1734_IDO, 4, 0, },
278 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
279 .io_access = IO_8b,
280 },
281 [TYPE_PCI1735] = {
282 .name = "pci1735",
283 .main_pci_region = PCIDIO_MAINREG,
284 .cardtype = TYPE_PCI1735,
285 .nsubdevs = 4,
286 .sdi[0] = { 32, PCI1735_DI, 4, 0, },
287 .sdo[0] = { 32, PCI1735_DO, 4, 0, },
288 .boardid = { 4, PCI1735_BOARDID, 1, SDF_INTERNAL, },
289 .s8254[0] = { 3, PCI1735_C8254, 1, 0, },
290 .io_access = IO_8b,
291 },
292 [TYPE_PCI1736] = {
293 .name = "pci1736",
294 .main_pci_region = PCI1736_MAINREG,
295 .cardtype = TYPE_PCI1736,
296 .nsubdevs = 3,
297 .sdi[1] = { 16, PCI1736_IDI, 2, 0, },
298 .sdo[1] = { 16, PCI1736_IDO, 2, 0, },
299 .boardid = { 4, PCI1736_BOARDID, 1, SDF_INTERNAL, },
300 .io_access = IO_8b,
301 },
302 [TYPE_PCI1739] = {
303 .name = "pci1739",
304 .main_pci_region = PCIDIO_MAINREG,
305 .cardtype = TYPE_PCI1739,
306 .nsubdevs = 2,
307 .sdio[0] = { 48, PCI1739_DIO, 2, 0, },
308 .io_access = IO_8b,
309 },
310 [TYPE_PCI1750] = {
311 .name = "pci1750",
312 .main_pci_region = PCIDIO_MAINREG,
313 .cardtype = TYPE_PCI1750,
314 .nsubdevs = 2,
315 .sdi[1] = { 16, PCI1750_IDI, 2, 0, },
316 .sdo[1] = { 16, PCI1750_IDO, 2, 0, },
317 .io_access = IO_8b,
318 },
319 [TYPE_PCI1751] = {
320 .name = "pci1751",
321 .main_pci_region = PCIDIO_MAINREG,
322 .cardtype = TYPE_PCI1751,
323 .nsubdevs = 3,
324 .sdio[0] = { 48, PCI1751_DIO, 2, 0, },
325 .s8254[0] = { 3, PCI1751_CNT, 1, 0, },
326 .io_access = IO_8b,
327 },
328 [TYPE_PCI1752] = {
329 .name = "pci1752",
330 .main_pci_region = PCIDIO_MAINREG,
331 .cardtype = TYPE_PCI1752,
332 .nsubdevs = 3,
333 .sdo[0] = { 32, PCI1752_IDO, 2, 0, },
334 .sdo[1] = { 32, PCI1752_IDO2, 2, 0, },
335 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
336 .io_access = IO_16b,
337 },
338 [TYPE_PCI1753] = {
339 .name = "pci1753",
340 .main_pci_region = PCIDIO_MAINREG,
341 .cardtype = TYPE_PCI1753,
342 .nsubdevs = 4,
343 .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
344 .io_access = IO_8b,
345 },
346 [TYPE_PCI1753E] = {
347 .name = "pci1753e",
348 .main_pci_region = PCIDIO_MAINREG,
349 .cardtype = TYPE_PCI1753E,
350 .nsubdevs = 8,
351 .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
352 .sdio[1] = { 96, PCI1753E_DIO, 4, 0, },
353 .io_access = IO_8b,
354 },
355 [TYPE_PCI1754] = {
356 .name = "pci1754",
357 .main_pci_region = PCIDIO_MAINREG,
358 .cardtype = TYPE_PCI1754,
359 .nsubdevs = 3,
360 .sdi[0] = { 32, PCI1754_IDI, 2, 0, },
361 .sdi[1] = { 32, PCI1754_IDI2, 2, 0, },
362 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
363 .io_access = IO_16b,
364 },
365 [TYPE_PCI1756] = {
366 .name = "pci1756",
367 .main_pci_region = PCIDIO_MAINREG,
368 .cardtype = TYPE_PCI1756,
369 .nsubdevs = 3,
370 .sdi[1] = { 32, PCI1756_IDI, 2, 0, },
371 .sdo[1] = { 32, PCI1756_IDO, 2, 0, },
372 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
373 .io_access = IO_16b,
374 },
375 [TYPE_PCI1760] = {
376 /* This card has its own 'attach' */
377 .name = "pci1760",
378 .main_pci_region = 0,
379 .cardtype = TYPE_PCI1760,
380 .nsubdevs = 4,
381 .io_access = IO_8b,
382 },
383 [TYPE_PCI1762] = {
384 .name = "pci1762",
385 .main_pci_region = PCIDIO_MAINREG,
386 .cardtype = TYPE_PCI1762,
387 .nsubdevs = 3,
388 .sdi[1] = { 16, PCI1762_IDI, 1, 0, },
389 .sdo[1] = { 16, PCI1762_RO, 1, 0, },
390 .boardid = { 4, PCI1762_BOARDID, 1, SDF_INTERNAL, },
391 .io_access = IO_16b,
392 },
393 };
394
395 struct pci_dio_private {
396 char valid; /* card is usable */
397 char GlobalIrqEnabled; /* 1= any IRQ source is enabled */
398 /* PCI-1760 specific data */
399 unsigned char IDICntEnable; /* counter's counting enable status */
400 unsigned char IDICntOverEnable; /* counter's overflow interrupts enable
401 * status */
402 unsigned char IDICntMatchEnable; /* counter's match interrupts
403 * enable status */
404 unsigned char IDICntEdge; /* counter's count edge value
405 * (bit=0 - rising, =1 - falling) */
406 unsigned short CntResValue[8]; /* counters' reset value */
407 unsigned short CntMatchValue[8]; /* counters' match interrupt value */
408 unsigned char IDIFiltersEn; /* IDI's digital filters enable status */
409 unsigned char IDIPatMatchEn; /* IDI's pattern match enable status */
410 unsigned char IDIPatMatchValue; /* IDI's pattern match value */
411 unsigned short IDIFiltrLow[8]; /* IDI's filter value low signal */
412 unsigned short IDIFiltrHigh[8]; /* IDI's filter value high signal */
413 };
414
415 /*
416 ==============================================================================
417 */
418 static int pci_dio_insn_bits_di_b(struct comedi_device *dev,
419 struct comedi_subdevice *s,
420 struct comedi_insn *insn, unsigned int *data)
421 {
422 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
423 int i;
424
425 data[1] = 0;
426 for (i = 0; i < d->regs; i++)
427 data[1] |= inb(dev->iobase + d->addr + i) << (8 * i);
428
429
430 return insn->n;
431 }
432
433 /*
434 ==============================================================================
435 */
436 static int pci_dio_insn_bits_di_w(struct comedi_device *dev,
437 struct comedi_subdevice *s,
438 struct comedi_insn *insn, unsigned int *data)
439 {
440 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
441 int i;
442
443 data[1] = 0;
444 for (i = 0; i < d->regs; i++)
445 data[1] |= inw(dev->iobase + d->addr + 2 * i) << (16 * i);
446
447 return insn->n;
448 }
449
450 /*
451 ==============================================================================
452 */
453 static int pci_dio_insn_bits_do_b(struct comedi_device *dev,
454 struct comedi_subdevice *s,
455 struct comedi_insn *insn, unsigned int *data)
456 {
457 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
458 int i;
459
460 if (data[0]) {
461 s->state &= ~data[0];
462 s->state |= (data[0] & data[1]);
463 for (i = 0; i < d->regs; i++)
464 outb((s->state >> (8 * i)) & 0xff,
465 dev->iobase + d->addr + i);
466 }
467 data[1] = s->state;
468
469 return insn->n;
470 }
471
472 /*
473 ==============================================================================
474 */
475 static int pci_dio_insn_bits_do_w(struct comedi_device *dev,
476 struct comedi_subdevice *s,
477 struct comedi_insn *insn, unsigned int *data)
478 {
479 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
480 int i;
481
482 if (data[0]) {
483 s->state &= ~data[0];
484 s->state |= (data[0] & data[1]);
485 for (i = 0; i < d->regs; i++)
486 outw((s->state >> (16 * i)) & 0xffff,
487 dev->iobase + d->addr + 2 * i);
488 }
489 data[1] = s->state;
490
491 return insn->n;
492 }
493
494 /*
495 ==============================================================================
496 */
497 static int pci_8254_insn_read(struct comedi_device *dev,
498 struct comedi_subdevice *s,
499 struct comedi_insn *insn, unsigned int *data)
500 {
501 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
502 unsigned int chan, chip, chipchan;
503 unsigned long flags;
504
505 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
506 chip = chan / 3; /* chip on subdevice */
507 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
508 spin_lock_irqsave(&s->spin_lock, flags);
509 data[0] = i8254_read(dev->iobase + d->addr + (SIZE_8254 * chip),
510 0, chipchan);
511 spin_unlock_irqrestore(&s->spin_lock, flags);
512 return 1;
513 }
514
515 /*
516 ==============================================================================
517 */
518 static int pci_8254_insn_write(struct comedi_device *dev,
519 struct comedi_subdevice *s,
520 struct comedi_insn *insn, unsigned int *data)
521 {
522 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
523 unsigned int chan, chip, chipchan;
524 unsigned long flags;
525
526 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
527 chip = chan / 3; /* chip on subdevice */
528 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
529 spin_lock_irqsave(&s->spin_lock, flags);
530 i8254_write(dev->iobase + d->addr + (SIZE_8254 * chip),
531 0, chipchan, data[0]);
532 spin_unlock_irqrestore(&s->spin_lock, flags);
533 return 1;
534 }
535
536 /*
537 ==============================================================================
538 */
539 static int pci_8254_insn_config(struct comedi_device *dev,
540 struct comedi_subdevice *s,
541 struct comedi_insn *insn, unsigned int *data)
542 {
543 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
544 unsigned int chan, chip, chipchan;
545 unsigned long iobase;
546 int ret = 0;
547 unsigned long flags;
548
549 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
550 chip = chan / 3; /* chip on subdevice */
551 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
552 iobase = dev->iobase + d->addr + (SIZE_8254 * chip);
553 spin_lock_irqsave(&s->spin_lock, flags);
554 switch (data[0]) {
555 case INSN_CONFIG_SET_COUNTER_MODE:
556 ret = i8254_set_mode(iobase, 0, chipchan, data[1]);
557 if (ret < 0)
558 ret = -EINVAL;
559 break;
560 case INSN_CONFIG_8254_READ_STATUS:
561 data[1] = i8254_status(iobase, 0, chipchan);
562 break;
563 default:
564 ret = -EINVAL;
565 break;
566 }
567 spin_unlock_irqrestore(&s->spin_lock, flags);
568 return ret < 0 ? ret : insn->n;
569 }
570
571 /*
572 ==============================================================================
573 */
574 static int pci1760_unchecked_mbxrequest(struct comedi_device *dev,
575 unsigned char *omb, unsigned char *imb,
576 int repeats)
577 {
578 int cnt, tout, ok = 0;
579
580 for (cnt = 0; cnt < repeats; cnt++) {
581 outb(omb[0], dev->iobase + OMB0);
582 outb(omb[1], dev->iobase + OMB1);
583 outb(omb[2], dev->iobase + OMB2);
584 outb(omb[3], dev->iobase + OMB3);
585 for (tout = 0; tout < 251; tout++) {
586 imb[2] = inb(dev->iobase + IMB2);
587 if (imb[2] == omb[2]) {
588 imb[0] = inb(dev->iobase + IMB0);
589 imb[1] = inb(dev->iobase + IMB1);
590 imb[3] = inb(dev->iobase + IMB3);
591 ok = 1;
592 break;
593 }
594 udelay(1);
595 }
596 if (ok)
597 return 0;
598 }
599
600 comedi_error(dev, "PCI-1760 mailbox request timeout!");
601 return -ETIME;
602 }
603
604 static int pci1760_clear_imb2(struct comedi_device *dev)
605 {
606 unsigned char omb[4] = { 0x0, 0x0, CMD_ClearIMB2, 0x0 };
607 unsigned char imb[4];
608 /* check if imb2 is already clear */
609 if (inb(dev->iobase + IMB2) == CMD_ClearIMB2)
610 return 0;
611 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
612 }
613
614 static int pci1760_mbxrequest(struct comedi_device *dev,
615 unsigned char *omb, unsigned char *imb)
616 {
617 if (omb[2] == CMD_ClearIMB2) {
618 comedi_error(dev,
619 "bug! this function should not be used for CMD_ClearIMB2 command");
620 return -EINVAL;
621 }
622 if (inb(dev->iobase + IMB2) == omb[2]) {
623 int retval;
624 retval = pci1760_clear_imb2(dev);
625 if (retval < 0)
626 return retval;
627 }
628 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
629 }
630
631 /*
632 ==============================================================================
633 */
634 static int pci1760_insn_bits_di(struct comedi_device *dev,
635 struct comedi_subdevice *s,
636 struct comedi_insn *insn, unsigned int *data)
637 {
638 data[1] = inb(dev->iobase + IMB3);
639
640 return insn->n;
641 }
642
643 /*
644 ==============================================================================
645 */
646 static int pci1760_insn_bits_do(struct comedi_device *dev,
647 struct comedi_subdevice *s,
648 struct comedi_insn *insn, unsigned int *data)
649 {
650 int ret;
651 unsigned char omb[4] = {
652 0x00,
653 0x00,
654 CMD_SetRelaysOutput,
655 0x00
656 };
657 unsigned char imb[4];
658
659 if (data[0]) {
660 s->state &= ~data[0];
661 s->state |= (data[0] & data[1]);
662 omb[0] = s->state;
663 ret = pci1760_mbxrequest(dev, omb, imb);
664 if (!ret)
665 return ret;
666 }
667 data[1] = s->state;
668
669 return insn->n;
670 }
671
672 /*
673 ==============================================================================
674 */
675 static int pci1760_insn_cnt_read(struct comedi_device *dev,
676 struct comedi_subdevice *s,
677 struct comedi_insn *insn, unsigned int *data)
678 {
679 int ret, n;
680 unsigned char omb[4] = {
681 CR_CHAN(insn->chanspec) & 0x07,
682 0x00,
683 CMD_GetIDICntCurValue,
684 0x00
685 };
686 unsigned char imb[4];
687
688 for (n = 0; n < insn->n; n++) {
689 ret = pci1760_mbxrequest(dev, omb, imb);
690 if (!ret)
691 return ret;
692 data[n] = (imb[1] << 8) + imb[0];
693 }
694
695 return n;
696 }
697
698 /*
699 ==============================================================================
700 */
701 static int pci1760_insn_cnt_write(struct comedi_device *dev,
702 struct comedi_subdevice *s,
703 struct comedi_insn *insn, unsigned int *data)
704 {
705 struct pci_dio_private *devpriv = dev->private;
706 int ret;
707 unsigned char chan = CR_CHAN(insn->chanspec) & 0x07;
708 unsigned char bitmask = 1 << chan;
709 unsigned char omb[4] = {
710 data[0] & 0xff,
711 (data[0] >> 8) & 0xff,
712 CMD_SetIDI0CntResetValue + chan,
713 0x00
714 };
715 unsigned char imb[4];
716
717 /* Set reset value if different */
718 if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) {
719 ret = pci1760_mbxrequest(dev, omb, imb);
720 if (!ret)
721 return ret;
722 devpriv->CntResValue[chan] = data[0] & 0xffff;
723 }
724
725 omb[0] = bitmask; /* reset counter to it reset value */
726 omb[2] = CMD_ResetIDICounters;
727 ret = pci1760_mbxrequest(dev, omb, imb);
728 if (!ret)
729 return ret;
730
731 /* start counter if it don't run */
732 if (!(bitmask & devpriv->IDICntEnable)) {
733 omb[0] = bitmask;
734 omb[2] = CMD_EnableIDICounters;
735 ret = pci1760_mbxrequest(dev, omb, imb);
736 if (!ret)
737 return ret;
738 devpriv->IDICntEnable |= bitmask;
739 }
740 return 1;
741 }
742
743 /*
744 ==============================================================================
745 */
746 static int pci1760_reset(struct comedi_device *dev)
747 {
748 struct pci_dio_private *devpriv = dev->private;
749 int i;
750 unsigned char omb[4] = { 0x00, 0x00, 0x00, 0x00 };
751 unsigned char imb[4];
752
753 outb(0, dev->iobase + INTCSR0); /* disable IRQ */
754 outb(0, dev->iobase + INTCSR1);
755 outb(0, dev->iobase + INTCSR2);
756 outb(0, dev->iobase + INTCSR3);
757 devpriv->GlobalIrqEnabled = 0;
758
759 omb[0] = 0x00;
760 omb[2] = CMD_SetRelaysOutput; /* reset relay outputs */
761 pci1760_mbxrequest(dev, omb, imb);
762
763 omb[0] = 0x00;
764 omb[2] = CMD_EnableIDICounters; /* disable IDI up counters */
765 pci1760_mbxrequest(dev, omb, imb);
766 devpriv->IDICntEnable = 0;
767
768 omb[0] = 0x00;
769 omb[2] = CMD_OverflowIDICounters; /* disable counters overflow
770 * interrupts */
771 pci1760_mbxrequest(dev, omb, imb);
772 devpriv->IDICntOverEnable = 0;
773
774 omb[0] = 0x00;
775 omb[2] = CMD_MatchIntIDICounters; /* disable counters match value
776 * interrupts */
777 pci1760_mbxrequest(dev, omb, imb);
778 devpriv->IDICntMatchEnable = 0;
779
780 omb[0] = 0x00;
781 omb[1] = 0x80;
782 for (i = 0; i < 8; i++) { /* set IDI up counters match value */
783 omb[2] = CMD_SetIDI0CntMatchValue + i;
784 pci1760_mbxrequest(dev, omb, imb);
785 devpriv->CntMatchValue[i] = 0x8000;
786 }
787
788 omb[0] = 0x00;
789 omb[1] = 0x00;
790 for (i = 0; i < 8; i++) { /* set IDI up counters reset value */
791 omb[2] = CMD_SetIDI0CntResetValue + i;
792 pci1760_mbxrequest(dev, omb, imb);
793 devpriv->CntResValue[i] = 0x0000;
794 }
795
796 omb[0] = 0xff;
797 omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset
798 * values */
799 pci1760_mbxrequest(dev, omb, imb);
800
801 omb[0] = 0x00;
802 omb[2] = CMD_EdgeIDICounters; /* set IDI up counters count edge */
803 pci1760_mbxrequest(dev, omb, imb);
804 devpriv->IDICntEdge = 0x00;
805
806 omb[0] = 0x00;
807 omb[2] = CMD_EnableIDIFilters; /* disable all digital in filters */
808 pci1760_mbxrequest(dev, omb, imb);
809 devpriv->IDIFiltersEn = 0x00;
810
811 omb[0] = 0x00;
812 omb[2] = CMD_EnableIDIPatternMatch; /* disable pattern matching */
813 pci1760_mbxrequest(dev, omb, imb);
814 devpriv->IDIPatMatchEn = 0x00;
815
816 omb[0] = 0x00;
817 omb[2] = CMD_SetIDIPatternMatch; /* set pattern match value */
818 pci1760_mbxrequest(dev, omb, imb);
819 devpriv->IDIPatMatchValue = 0x00;
820
821 return 0;
822 }
823
824 /*
825 ==============================================================================
826 */
827 static int pci_dio_reset(struct comedi_device *dev)
828 {
829 const struct dio_boardtype *this_board = comedi_board(dev);
830
831 switch (this_board->cardtype) {
832 case TYPE_PCI1730:
833 outb(0, dev->iobase + PCI1730_DO); /* clear outputs */
834 outb(0, dev->iobase + PCI1730_DO + 1);
835 outb(0, dev->iobase + PCI1730_IDO);
836 outb(0, dev->iobase + PCI1730_IDO + 1);
837 /* NO break there! */
838 case TYPE_PCI1733:
839 /* disable interrupts */
840 outb(0, dev->iobase + PCI1730_3_INT_EN);
841 /* clear interrupts */
842 outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);
843 /* set rising edge trigger */
844 outb(0, dev->iobase + PCI1730_3_INT_RF);
845 break;
846 case TYPE_PCI1734:
847 outb(0, dev->iobase + PCI1734_IDO); /* clear outputs */
848 outb(0, dev->iobase + PCI1734_IDO + 1);
849 outb(0, dev->iobase + PCI1734_IDO + 2);
850 outb(0, dev->iobase + PCI1734_IDO + 3);
851 break;
852 case TYPE_PCI1735:
853 outb(0, dev->iobase + PCI1735_DO); /* clear outputs */
854 outb(0, dev->iobase + PCI1735_DO + 1);
855 outb(0, dev->iobase + PCI1735_DO + 2);
856 outb(0, dev->iobase + PCI1735_DO + 3);
857 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 0, I8254_MODE0);
858 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 1, I8254_MODE0);
859 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 2, I8254_MODE0);
860 break;
861
862 case TYPE_PCI1736:
863 outb(0, dev->iobase + PCI1736_IDO);
864 outb(0, dev->iobase + PCI1736_IDO + 1);
865 /* disable interrupts */
866 outb(0, dev->iobase + PCI1736_3_INT_EN);
867 /* clear interrupts */
868 outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);
869 /* set rising edge trigger */
870 outb(0, dev->iobase + PCI1736_3_INT_RF);
871 break;
872
873 case TYPE_PCI1739:
874 /* disable & clear interrupts */
875 outb(0x88, dev->iobase + PCI1739_ICR);
876 break;
877
878 case TYPE_PCI1750:
879 case TYPE_PCI1751:
880 /* disable & clear interrupts */
881 outb(0x88, dev->iobase + PCI1750_ICR);
882 break;
883 case TYPE_PCI1752:
884 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
885 * function */
886 outw(0, dev->iobase + PCI1752_IDO); /* clear outputs */
887 outw(0, dev->iobase + PCI1752_IDO + 2);
888 outw(0, dev->iobase + PCI1752_IDO2);
889 outw(0, dev->iobase + PCI1752_IDO2 + 2);
890 break;
891 case TYPE_PCI1753E:
892 outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear
893 * interrupts */
894 outb(0x80, dev->iobase + PCI1753E_ICR1);
895 outb(0x80, dev->iobase + PCI1753E_ICR2);
896 outb(0x80, dev->iobase + PCI1753E_ICR3);
897 /* NO break there! */
898 case TYPE_PCI1753:
899 outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear
900 * interrupts */
901 outb(0x80, dev->iobase + PCI1753_ICR1);
902 outb(0x80, dev->iobase + PCI1753_ICR2);
903 outb(0x80, dev->iobase + PCI1753_ICR3);
904 break;
905 case TYPE_PCI1754:
906 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
907 * interrupts */
908 outw(0x08, dev->iobase + PCI1754_6_ICR1);
909 outw(0x08, dev->iobase + PCI1754_ICR2);
910 outw(0x08, dev->iobase + PCI1754_ICR3);
911 break;
912 case TYPE_PCI1756:
913 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
914 * function */
915 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
916 * interrupts */
917 outw(0x08, dev->iobase + PCI1754_6_ICR1);
918 outw(0, dev->iobase + PCI1756_IDO); /* clear outputs */
919 outw(0, dev->iobase + PCI1756_IDO + 2);
920 break;
921 case TYPE_PCI1760:
922 pci1760_reset(dev);
923 break;
924 case TYPE_PCI1762:
925 outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear
926 * interrupts */
927 break;
928 }
929
930 return 0;
931 }
932
933 /*
934 ==============================================================================
935 */
936 static int pci1760_attach(struct comedi_device *dev)
937 {
938 struct comedi_subdevice *s;
939
940 s = &dev->subdevices[0];
941 s->type = COMEDI_SUBD_DI;
942 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON;
943 s->n_chan = 8;
944 s->maxdata = 1;
945 s->len_chanlist = 8;
946 s->range_table = &range_digital;
947 s->insn_bits = pci1760_insn_bits_di;
948
949 s = &dev->subdevices[1];
950 s->type = COMEDI_SUBD_DO;
951 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
952 s->n_chan = 8;
953 s->maxdata = 1;
954 s->len_chanlist = 8;
955 s->range_table = &range_digital;
956 s->state = 0;
957 s->insn_bits = pci1760_insn_bits_do;
958
959 s = &dev->subdevices[2];
960 s->type = COMEDI_SUBD_TIMER;
961 s->subdev_flags = SDF_WRITABLE | SDF_LSAMPL;
962 s->n_chan = 2;
963 s->maxdata = 0xffffffff;
964 s->len_chanlist = 2;
965 /* s->insn_config=pci1760_insn_pwm_cfg; */
966
967 s = &dev->subdevices[3];
968 s->type = COMEDI_SUBD_COUNTER;
969 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
970 s->n_chan = 8;
971 s->maxdata = 0xffff;
972 s->len_chanlist = 8;
973 s->insn_read = pci1760_insn_cnt_read;
974 s->insn_write = pci1760_insn_cnt_write;
975 /* s->insn_config=pci1760_insn_cnt_cfg; */
976
977 return 0;
978 }
979
980 /*
981 ==============================================================================
982 */
983 static int pci_dio_add_di(struct comedi_device *dev,
984 struct comedi_subdevice *s,
985 const struct diosubd_data *d)
986 {
987 const struct dio_boardtype *this_board = comedi_board(dev);
988
989 s->type = COMEDI_SUBD_DI;
990 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | d->specflags;
991 if (d->chans > 16)
992 s->subdev_flags |= SDF_LSAMPL;
993 s->n_chan = d->chans;
994 s->maxdata = 1;
995 s->len_chanlist = d->chans;
996 s->range_table = &range_digital;
997 switch (this_board->io_access) {
998 case IO_8b:
999 s->insn_bits = pci_dio_insn_bits_di_b;
1000 break;
1001 case IO_16b:
1002 s->insn_bits = pci_dio_insn_bits_di_w;
1003 break;
1004 }
1005 s->private = (void *)d;
1006
1007 return 0;
1008 }
1009
1010 /*
1011 ==============================================================================
1012 */
1013 static int pci_dio_add_do(struct comedi_device *dev,
1014 struct comedi_subdevice *s,
1015 const struct diosubd_data *d)
1016 {
1017 const struct dio_boardtype *this_board = comedi_board(dev);
1018
1019 s->type = COMEDI_SUBD_DO;
1020 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
1021 if (d->chans > 16)
1022 s->subdev_flags |= SDF_LSAMPL;
1023 s->n_chan = d->chans;
1024 s->maxdata = 1;
1025 s->len_chanlist = d->chans;
1026 s->range_table = &range_digital;
1027 s->state = 0;
1028 switch (this_board->io_access) {
1029 case IO_8b:
1030 s->insn_bits = pci_dio_insn_bits_do_b;
1031 break;
1032 case IO_16b:
1033 s->insn_bits = pci_dio_insn_bits_do_w;
1034 break;
1035 }
1036 s->private = (void *)d;
1037
1038 return 0;
1039 }
1040
1041 /*
1042 ==============================================================================
1043 */
1044 static int pci_dio_add_8254(struct comedi_device *dev,
1045 struct comedi_subdevice *s,
1046 const struct diosubd_data *d)
1047 {
1048 s->type = COMEDI_SUBD_COUNTER;
1049 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1050 s->n_chan = d->chans;
1051 s->maxdata = 65535;
1052 s->len_chanlist = d->chans;
1053 s->insn_read = pci_8254_insn_read;
1054 s->insn_write = pci_8254_insn_write;
1055 s->insn_config = pci_8254_insn_config;
1056 s->private = (void *)d;
1057
1058 return 0;
1059 }
1060
1061 static unsigned long pci_dio_override_cardtype(struct pci_dev *pcidev,
1062 unsigned long cardtype)
1063 {
1064 /*
1065 * Change cardtype from TYPE_PCI1753 to TYPE_PCI1753E if expansion
1066 * board available. Need to enable PCI device and request the main
1067 * registers PCI BAR temporarily to perform the test.
1068 */
1069 if (cardtype != TYPE_PCI1753)
1070 return cardtype;
1071 if (pci_enable_device(pcidev) < 0)
1072 return cardtype;
1073 if (pci_request_region(pcidev, PCIDIO_MAINREG, "adv_pci_dio") == 0) {
1074 /*
1075 * This test is based on Advantech's "advdaq" driver source
1076 * (which declares its module licence as "GPL" although the
1077 * driver source does not include a "COPYING" file).
1078 */
1079 unsigned long reg =
1080 pci_resource_start(pcidev, PCIDIO_MAINREG) + 53;
1081
1082 outb(0x05, reg);
1083 if ((inb(reg) & 0x07) == 0x02) {
1084 outb(0x02, reg);
1085 if ((inb(reg) & 0x07) == 0x05)
1086 cardtype = TYPE_PCI1753E;
1087 }
1088 pci_release_region(pcidev, PCIDIO_MAINREG);
1089 }
1090 pci_disable_device(pcidev);
1091 return cardtype;
1092 }
1093
1094 static int pci_dio_auto_attach(struct comedi_device *dev,
1095 unsigned long context)
1096 {
1097 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1098 const struct dio_boardtype *this_board = NULL;
1099 struct pci_dio_private *devpriv;
1100 struct comedi_subdevice *s;
1101 int ret, subdev, i, j;
1102
1103 if (context < ARRAY_SIZE(boardtypes))
1104 this_board = &boardtypes[context];
1105 if (!this_board)
1106 return -ENODEV;
1107 dev->board_ptr = this_board;
1108 dev->board_name = this_board->name;
1109
1110 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1111 if (!devpriv)
1112 return -ENOMEM;
1113 dev->private = devpriv;
1114
1115 ret = comedi_pci_enable(dev);
1116 if (ret)
1117 return ret;
1118 dev->iobase = pci_resource_start(pcidev, this_board->main_pci_region);
1119
1120 ret = comedi_alloc_subdevices(dev, this_board->nsubdevs);
1121 if (ret)
1122 return ret;
1123
1124 subdev = 0;
1125 for (i = 0; i < MAX_DI_SUBDEVS; i++)
1126 if (this_board->sdi[i].chans) {
1127 s = &dev->subdevices[subdev];
1128 pci_dio_add_di(dev, s, &this_board->sdi[i]);
1129 subdev++;
1130 }
1131
1132 for (i = 0; i < MAX_DO_SUBDEVS; i++)
1133 if (this_board->sdo[i].chans) {
1134 s = &dev->subdevices[subdev];
1135 pci_dio_add_do(dev, s, &this_board->sdo[i]);
1136 subdev++;
1137 }
1138
1139 for (i = 0; i < MAX_DIO_SUBDEVG; i++)
1140 for (j = 0; j < this_board->sdio[i].regs; j++) {
1141 s = &dev->subdevices[subdev];
1142 subdev_8255_init(dev, s, NULL,
1143 dev->iobase +
1144 this_board->sdio[i].addr +
1145 SIZE_8255 * j);
1146 subdev++;
1147 }
1148
1149 if (this_board->boardid.chans) {
1150 s = &dev->subdevices[subdev];
1151 s->type = COMEDI_SUBD_DI;
1152 pci_dio_add_di(dev, s, &this_board->boardid);
1153 subdev++;
1154 }
1155
1156 for (i = 0; i < MAX_8254_SUBDEVS; i++)
1157 if (this_board->s8254[i].chans) {
1158 s = &dev->subdevices[subdev];
1159 pci_dio_add_8254(dev, s, &this_board->s8254[i]);
1160 subdev++;
1161 }
1162
1163 if (this_board->cardtype == TYPE_PCI1760)
1164 pci1760_attach(dev);
1165
1166 devpriv->valid = 1;
1167
1168 pci_dio_reset(dev);
1169
1170 return 0;
1171 }
1172
1173 static void pci_dio_detach(struct comedi_device *dev)
1174 {
1175 struct pci_dio_private *devpriv = dev->private;
1176 struct comedi_subdevice *s;
1177 int i;
1178
1179 if (devpriv) {
1180 if (devpriv->valid)
1181 pci_dio_reset(dev);
1182 }
1183 if (dev->subdevices) {
1184 for (i = 0; i < dev->n_subdevices; i++) {
1185 s = &dev->subdevices[i];
1186 if (s->type == COMEDI_SUBD_DIO)
1187 subdev_8255_cleanup(dev, s);
1188 s->private = NULL;
1189 }
1190 }
1191 comedi_pci_disable(dev);
1192 }
1193
1194 static struct comedi_driver adv_pci_dio_driver = {
1195 .driver_name = "adv_pci_dio",
1196 .module = THIS_MODULE,
1197 .auto_attach = pci_dio_auto_attach,
1198 .detach = pci_dio_detach,
1199 };
1200
1201 static int adv_pci_dio_pci_probe(struct pci_dev *dev,
1202 const struct pci_device_id *id)
1203 {
1204 unsigned long cardtype;
1205
1206 cardtype = pci_dio_override_cardtype(dev, id->driver_data);
1207 return comedi_pci_auto_config(dev, &adv_pci_dio_driver, cardtype);
1208 }
1209
1210 static DEFINE_PCI_DEVICE_TABLE(adv_pci_dio_pci_table) = {
1211 { PCI_VDEVICE(ADVANTECH, 0x1730), TYPE_PCI1730 },
1212 { PCI_VDEVICE(ADVANTECH, 0x1733), TYPE_PCI1733 },
1213 { PCI_VDEVICE(ADVANTECH, 0x1734), TYPE_PCI1734 },
1214 { PCI_VDEVICE(ADVANTECH, 0x1735), TYPE_PCI1735 },
1215 { PCI_VDEVICE(ADVANTECH, 0x1736), TYPE_PCI1736 },
1216 { PCI_VDEVICE(ADVANTECH, 0x1739), TYPE_PCI1739 },
1217 { PCI_VDEVICE(ADVANTECH, 0x1750), TYPE_PCI1750 },
1218 { PCI_VDEVICE(ADVANTECH, 0x1751), TYPE_PCI1751 },
1219 { PCI_VDEVICE(ADVANTECH, 0x1752), TYPE_PCI1752 },
1220 { PCI_VDEVICE(ADVANTECH, 0x1753), TYPE_PCI1753 },
1221 { PCI_VDEVICE(ADVANTECH, 0x1754), TYPE_PCI1754 },
1222 { PCI_VDEVICE(ADVANTECH, 0x1756), TYPE_PCI1756 },
1223 { PCI_VDEVICE(ADVANTECH, 0x1760), TYPE_PCI1760 },
1224 { PCI_VDEVICE(ADVANTECH, 0x1762), TYPE_PCI1762 },
1225 { 0 }
1226 };
1227 MODULE_DEVICE_TABLE(pci, adv_pci_dio_pci_table);
1228
1229 static struct pci_driver adv_pci_dio_pci_driver = {
1230 .name = "adv_pci_dio",
1231 .id_table = adv_pci_dio_pci_table,
1232 .probe = adv_pci_dio_pci_probe,
1233 .remove = comedi_pci_auto_unconfig,
1234 };
1235 module_comedi_pci_driver(adv_pci_dio_driver, adv_pci_dio_pci_driver);
1236
1237 MODULE_AUTHOR("Comedi http://www.comedi.org");
1238 MODULE_DESCRIPTION("Comedi low-level driver");
1239 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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