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staging: comedi: adv_pci_dio: remove need for diosubd_data 'regs' member
[deliverable/linux.git] / drivers / staging / comedi / drivers / adv_pci_dio.c
1 /*
2 * comedi/drivers/adv_pci_dio.c
3 *
4 * Author: Michal Dobes <dobes@tesnet.cz>
5 *
6 * Hardware driver for Advantech PCI DIO cards.
7 */
8
9 /*
10 * Driver: adv_pci_dio
11 * Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U,
12 * PCI-1736UP, PCI-1739U, PCI-1750, PCI-1751, PCI-1752,
13 * PCI-1753/E, PCI-1754, PCI-1756, PCI-1762
14 * Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
15 * PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
16 * PCI-1751, PCI-1752, PCI-1753,
17 * PCI-1753+PCI-1753E, PCI-1754, PCI-1756,
18 * PCI-1762
19 * Author: Michal Dobes <dobes@tesnet.cz>
20 * Updated: Mon, 09 Jan 2012 12:40:46 +0000
21 * Status: untested
22 *
23 * Configuration Options: not applicable, uses PCI auto config
24 */
25
26 #include <linux/module.h>
27 #include <linux/delay.h>
28
29 #include "../comedi_pci.h"
30
31 #include "8255.h"
32 #include "comedi_8254.h"
33
34 /* hardware types of the cards */
35 enum hw_cards_id {
36 TYPE_PCI1730, TYPE_PCI1733, TYPE_PCI1734, TYPE_PCI1735, TYPE_PCI1736,
37 TYPE_PCI1739,
38 TYPE_PCI1750,
39 TYPE_PCI1751,
40 TYPE_PCI1752,
41 TYPE_PCI1753, TYPE_PCI1753E,
42 TYPE_PCI1754, TYPE_PCI1756,
43 TYPE_PCI1762
44 };
45
46 #define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */
47 #define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */
48 #define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per
49 * card */
50
51 /* Register offset definitions */
52 /* Advantech PCI-1730/3/4 */
53 #define PCI1730_IDI 0 /* R: Isolated digital input 0-15 */
54 #define PCI1730_IDO 0 /* W: Isolated digital output 0-15 */
55 #define PCI1730_DI 2 /* R: Digital input 0-15 */
56 #define PCI1730_DO 2 /* W: Digital output 0-15 */
57 #define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */
58 #define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
59 #define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for
60 * interrupts */
61 #define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */
62 #define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */
63 #define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */
64
65 /* Advantech PCI-1735U */
66 #define PCI1735_DI 0 /* R: Digital input 0-31 */
67 #define PCI1735_DO 0 /* W: Digital output 0-31 */
68 #define PCI1735_C8254 4 /* R/W: 8254 counter */
69 #define PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */
70
71 /* Advantech PCI-1736UP */
72 #define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */
73 #define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */
74 #define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
75 #define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for
76 * interrupts */
77 #define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */
78 #define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */
79
80 /* Advantech PCI-1739U */
81 #define PCI1739_DIO 0 /* R/W: begin of 8255 registers block */
82 #define PCI1739_ICR 32 /* W: Interrupt control register */
83 #define PCI1739_ISR 32 /* R: Interrupt status register */
84 #define PCI1739_BOARDID 8 /* R: Board I/D switch for 1739U */
85
86 /* Advantech PCI-1750 */
87 #define PCI1750_IDI 0 /* R: Isolated digital input 0-15 */
88 #define PCI1750_IDO 0 /* W: Isolated digital output 0-15 */
89 #define PCI1750_ICR 32 /* W: Interrupt control register */
90 #define PCI1750_ISR 32 /* R: Interrupt status register */
91
92 /* Advantech PCI-1751/3/3E */
93 #define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */
94 #define PCI1751_CNT 24 /* R/W: begin of 8254 registers block */
95 #define PCI1751_ICR 32 /* W: Interrupt control register */
96 #define PCI1751_ISR 32 /* R: Interrupt status register */
97 #define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */
98 #define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */
99 #define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */
100 #define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */
101 #define PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */
102 #define PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */
103 #define PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */
104 #define PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */
105 #define PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */
106 #define PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */
107
108 /* Advantech PCI-1752/4/6 */
109 #define PCI1752_IDO 0 /* R/W: Digital output 0-31 */
110 #define PCI1752_IDO2 4 /* R/W: Digital output 32-63 */
111 #define PCI1754_IDI 0 /* R: Digital input 0-31 */
112 #define PCI1754_IDI2 4 /* R: Digital input 32-64 */
113 #define PCI1756_IDI 0 /* R: Digital input 0-31 */
114 #define PCI1756_IDO 4 /* R/W: Digital output 0-31 */
115 #define PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */
116 #define PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */
117 #define PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */
118 #define PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */
119 #define PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */
120 #define PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */
121
122 /* Advantech PCI-1762 registers */
123 #define PCI1762_RO 0 /* R/W: Relays status/output */
124 #define PCI1762_IDI 2 /* R: Isolated input status */
125 #define PCI1762_BOARDID 4 /* R: Board I/D switch */
126 #define PCI1762_ICR 6 /* W: Interrupt control register */
127 #define PCI1762_ISR 6 /* R: Interrupt status register */
128
129 struct diosubd_data {
130 int chans; /* num of chans or 8255 devices */
131 int addr; /* PCI address ofset */
132 };
133
134 struct dio_boardtype {
135 const char *name; /* board name */
136 enum hw_cards_id cardtype;
137 int nsubdevs;
138 struct diosubd_data sdi[MAX_DI_SUBDEVS]; /* DI chans */
139 struct diosubd_data sdo[MAX_DO_SUBDEVS]; /* DO chans */
140 struct diosubd_data sdio[MAX_DIO_SUBDEVG]; /* DIO 8255 chans */
141 struct diosubd_data boardid; /* card supports board ID switch */
142 unsigned long timer_regbase;
143 unsigned int is_16bit:1;
144 };
145
146 static const struct dio_boardtype boardtypes[] = {
147 [TYPE_PCI1730] = {
148 .name = "pci1730",
149 .cardtype = TYPE_PCI1730,
150 .nsubdevs = 5,
151 .sdi[0] = { 16, PCI1730_DI, },
152 .sdi[1] = { 16, PCI1730_IDI, },
153 .sdo[0] = { 16, PCI1730_DO, },
154 .sdo[1] = { 16, PCI1730_IDO, },
155 .boardid = { 4, PCI173x_BOARDID, },
156 },
157 [TYPE_PCI1733] = {
158 .name = "pci1733",
159 .cardtype = TYPE_PCI1733,
160 .nsubdevs = 2,
161 .sdi[1] = { 32, PCI1733_IDI, },
162 .boardid = { 4, PCI173x_BOARDID, },
163 },
164 [TYPE_PCI1734] = {
165 .name = "pci1734",
166 .cardtype = TYPE_PCI1734,
167 .nsubdevs = 2,
168 .sdo[1] = { 32, PCI1734_IDO, },
169 .boardid = { 4, PCI173x_BOARDID, },
170 },
171 [TYPE_PCI1735] = {
172 .name = "pci1735",
173 .cardtype = TYPE_PCI1735,
174 .nsubdevs = 4,
175 .sdi[0] = { 32, PCI1735_DI, },
176 .sdo[0] = { 32, PCI1735_DO, },
177 .boardid = { 4, PCI1735_BOARDID, },
178 .timer_regbase = PCI1735_C8254,
179 },
180 [TYPE_PCI1736] = {
181 .name = "pci1736",
182 .cardtype = TYPE_PCI1736,
183 .nsubdevs = 3,
184 .sdi[1] = { 16, PCI1736_IDI, },
185 .sdo[1] = { 16, PCI1736_IDO, },
186 .boardid = { 4, PCI1736_BOARDID, },
187 },
188 [TYPE_PCI1739] = {
189 .name = "pci1739",
190 .cardtype = TYPE_PCI1739,
191 .nsubdevs = 2,
192 .sdio[0] = { 2, PCI1739_DIO, },
193 },
194 [TYPE_PCI1750] = {
195 .name = "pci1750",
196 .cardtype = TYPE_PCI1750,
197 .nsubdevs = 2,
198 .sdi[1] = { 16, PCI1750_IDI, },
199 .sdo[1] = { 16, PCI1750_IDO, },
200 },
201 [TYPE_PCI1751] = {
202 .name = "pci1751",
203 .cardtype = TYPE_PCI1751,
204 .nsubdevs = 3,
205 .sdio[0] = { 2, PCI1751_DIO, },
206 .timer_regbase = PCI1751_CNT,
207 },
208 [TYPE_PCI1752] = {
209 .name = "pci1752",
210 .cardtype = TYPE_PCI1752,
211 .nsubdevs = 3,
212 .sdo[0] = { 32, PCI1752_IDO, },
213 .sdo[1] = { 32, PCI1752_IDO2, },
214 .boardid = { 4, PCI175x_BOARDID, },
215 .is_16bit = 1,
216 },
217 [TYPE_PCI1753] = {
218 .name = "pci1753",
219 .cardtype = TYPE_PCI1753,
220 .nsubdevs = 4,
221 .sdio[0] = { 4, PCI1753_DIO, },
222 },
223 [TYPE_PCI1753E] = {
224 .name = "pci1753e",
225 .cardtype = TYPE_PCI1753E,
226 .nsubdevs = 8,
227 .sdio[0] = { 4, PCI1753_DIO, },
228 .sdio[1] = { 4, PCI1753E_DIO, },
229 },
230 [TYPE_PCI1754] = {
231 .name = "pci1754",
232 .cardtype = TYPE_PCI1754,
233 .nsubdevs = 3,
234 .sdi[0] = { 32, PCI1754_IDI, },
235 .sdi[1] = { 32, PCI1754_IDI2, },
236 .boardid = { 4, PCI175x_BOARDID, },
237 .is_16bit = 1,
238 },
239 [TYPE_PCI1756] = {
240 .name = "pci1756",
241 .cardtype = TYPE_PCI1756,
242 .nsubdevs = 3,
243 .sdi[1] = { 32, PCI1756_IDI, },
244 .sdo[1] = { 32, PCI1756_IDO, },
245 .boardid = { 4, PCI175x_BOARDID, },
246 .is_16bit = 1,
247 },
248 [TYPE_PCI1762] = {
249 .name = "pci1762",
250 .cardtype = TYPE_PCI1762,
251 .nsubdevs = 3,
252 .sdi[1] = { 16, PCI1762_IDI, },
253 .sdo[1] = { 16, PCI1762_RO, },
254 .boardid = { 4, PCI1762_BOARDID, },
255 .is_16bit = 1,
256 },
257 };
258
259 static int pci_dio_insn_bits_di_b(struct comedi_device *dev,
260 struct comedi_subdevice *s,
261 struct comedi_insn *insn,
262 unsigned int *data)
263 {
264 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
265 unsigned long iobase = dev->iobase + d->addr;
266
267 data[1] = inb(iobase);
268 if (s->n_chan > 8)
269 data[1] |= (inb(iobase + 1) << 8);
270 if (s->n_chan > 16)
271 data[1] |= (inb(iobase + 2) << 16);
272 if (s->n_chan > 24)
273 data[1] |= (inb(iobase + 3) << 24);
274
275 return insn->n;
276 }
277
278 static int pci_dio_insn_bits_di_w(struct comedi_device *dev,
279 struct comedi_subdevice *s,
280 struct comedi_insn *insn,
281 unsigned int *data)
282 {
283 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
284 unsigned long iobase = dev->iobase + d->addr;
285
286 data[1] = inw(iobase);
287 if (s->n_chan > 16)
288 data[1] |= (inw(iobase + 2) << 16);
289
290 return insn->n;
291 }
292
293 static int pci_dio_insn_bits_do_b(struct comedi_device *dev,
294 struct comedi_subdevice *s,
295 struct comedi_insn *insn,
296 unsigned int *data)
297 {
298 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
299 unsigned long iobase = dev->iobase + d->addr;
300
301 if (comedi_dio_update_state(s, data)) {
302 outb(s->state & 0xff, iobase);
303 if (s->n_chan > 8)
304 outb((s->state >> 8) & 0xff, iobase + 1);
305 if (s->n_chan > 16)
306 outb((s->state >> 16) & 0xff, iobase + 2);
307 if (s->n_chan > 24)
308 outb((s->state >> 24) & 0xff, iobase + 3);
309 }
310
311 data[1] = s->state;
312
313 return insn->n;
314 }
315
316 static int pci_dio_insn_bits_do_w(struct comedi_device *dev,
317 struct comedi_subdevice *s,
318 struct comedi_insn *insn,
319 unsigned int *data)
320 {
321 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
322 unsigned long iobase = dev->iobase + d->addr;
323
324 if (comedi_dio_update_state(s, data)) {
325 outw(s->state & 0xffff, iobase);
326 if (s->n_chan > 16)
327 outw((s->state >> 16) & 0xffff, iobase + 2);
328 }
329
330 data[1] = s->state;
331
332 return insn->n;
333 }
334
335 static int pci_dio_reset(struct comedi_device *dev)
336 {
337 const struct dio_boardtype *board = dev->board_ptr;
338
339 switch (board->cardtype) {
340 case TYPE_PCI1730:
341 outb(0, dev->iobase + PCI1730_DO); /* clear outputs */
342 outb(0, dev->iobase + PCI1730_DO + 1);
343 outb(0, dev->iobase + PCI1730_IDO);
344 outb(0, dev->iobase + PCI1730_IDO + 1);
345 /* fallthrough */
346 case TYPE_PCI1733:
347 /* disable interrupts */
348 outb(0, dev->iobase + PCI1730_3_INT_EN);
349 /* clear interrupts */
350 outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);
351 /* set rising edge trigger */
352 outb(0, dev->iobase + PCI1730_3_INT_RF);
353 break;
354 case TYPE_PCI1734:
355 outb(0, dev->iobase + PCI1734_IDO); /* clear outputs */
356 outb(0, dev->iobase + PCI1734_IDO + 1);
357 outb(0, dev->iobase + PCI1734_IDO + 2);
358 outb(0, dev->iobase + PCI1734_IDO + 3);
359 break;
360 case TYPE_PCI1735:
361 outb(0, dev->iobase + PCI1735_DO); /* clear outputs */
362 outb(0, dev->iobase + PCI1735_DO + 1);
363 outb(0, dev->iobase + PCI1735_DO + 2);
364 outb(0, dev->iobase + PCI1735_DO + 3);
365 break;
366
367 case TYPE_PCI1736:
368 outb(0, dev->iobase + PCI1736_IDO);
369 outb(0, dev->iobase + PCI1736_IDO + 1);
370 /* disable interrupts */
371 outb(0, dev->iobase + PCI1736_3_INT_EN);
372 /* clear interrupts */
373 outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);
374 /* set rising edge trigger */
375 outb(0, dev->iobase + PCI1736_3_INT_RF);
376 break;
377
378 case TYPE_PCI1739:
379 /* disable & clear interrupts */
380 outb(0x88, dev->iobase + PCI1739_ICR);
381 break;
382
383 case TYPE_PCI1750:
384 case TYPE_PCI1751:
385 /* disable & clear interrupts */
386 outb(0x88, dev->iobase + PCI1750_ICR);
387 break;
388 case TYPE_PCI1752:
389 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
390 * function */
391 outw(0, dev->iobase + PCI1752_IDO); /* clear outputs */
392 outw(0, dev->iobase + PCI1752_IDO + 2);
393 outw(0, dev->iobase + PCI1752_IDO2);
394 outw(0, dev->iobase + PCI1752_IDO2 + 2);
395 break;
396 case TYPE_PCI1753E:
397 outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear
398 * interrupts */
399 outb(0x80, dev->iobase + PCI1753E_ICR1);
400 outb(0x80, dev->iobase + PCI1753E_ICR2);
401 outb(0x80, dev->iobase + PCI1753E_ICR3);
402 /* fallthrough */
403 case TYPE_PCI1753:
404 outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear
405 * interrupts */
406 outb(0x80, dev->iobase + PCI1753_ICR1);
407 outb(0x80, dev->iobase + PCI1753_ICR2);
408 outb(0x80, dev->iobase + PCI1753_ICR3);
409 break;
410 case TYPE_PCI1754:
411 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
412 * interrupts */
413 outw(0x08, dev->iobase + PCI1754_6_ICR1);
414 outw(0x08, dev->iobase + PCI1754_ICR2);
415 outw(0x08, dev->iobase + PCI1754_ICR3);
416 break;
417 case TYPE_PCI1756:
418 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
419 * function */
420 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
421 * interrupts */
422 outw(0x08, dev->iobase + PCI1754_6_ICR1);
423 outw(0, dev->iobase + PCI1756_IDO); /* clear outputs */
424 outw(0, dev->iobase + PCI1756_IDO + 2);
425 break;
426 case TYPE_PCI1762:
427 outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear
428 * interrupts */
429 break;
430 }
431
432 return 0;
433 }
434
435 static unsigned long pci_dio_override_cardtype(struct pci_dev *pcidev,
436 unsigned long cardtype)
437 {
438 /*
439 * Change cardtype from TYPE_PCI1753 to TYPE_PCI1753E if expansion
440 * board available. Need to enable PCI device and request the main
441 * registers PCI BAR temporarily to perform the test.
442 */
443 if (cardtype != TYPE_PCI1753)
444 return cardtype;
445 if (pci_enable_device(pcidev) < 0)
446 return cardtype;
447 if (pci_request_region(pcidev, 2, "adv_pci_dio") == 0) {
448 /*
449 * This test is based on Advantech's "advdaq" driver source
450 * (which declares its module licence as "GPL" although the
451 * driver source does not include a "COPYING" file).
452 */
453 unsigned long reg = pci_resource_start(pcidev, 2) + 53;
454
455 outb(0x05, reg);
456 if ((inb(reg) & 0x07) == 0x02) {
457 outb(0x02, reg);
458 if ((inb(reg) & 0x07) == 0x05)
459 cardtype = TYPE_PCI1753E;
460 }
461 pci_release_region(pcidev, 2);
462 }
463 pci_disable_device(pcidev);
464 return cardtype;
465 }
466
467 static int pci_dio_auto_attach(struct comedi_device *dev,
468 unsigned long context)
469 {
470 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
471 const struct dio_boardtype *board = NULL;
472 const struct diosubd_data *d;
473 struct comedi_subdevice *s;
474 int ret, subdev, i, j;
475
476 if (context < ARRAY_SIZE(boardtypes))
477 board = &boardtypes[context];
478 if (!board)
479 return -ENODEV;
480 dev->board_ptr = board;
481 dev->board_name = board->name;
482
483 ret = comedi_pci_enable(dev);
484 if (ret)
485 return ret;
486 if (board->cardtype == TYPE_PCI1736)
487 dev->iobase = pci_resource_start(pcidev, 0);
488 else
489 dev->iobase = pci_resource_start(pcidev, 2);
490
491 ret = comedi_alloc_subdevices(dev, board->nsubdevs);
492 if (ret)
493 return ret;
494
495 subdev = 0;
496 for (i = 0; i < MAX_DI_SUBDEVS; i++) {
497 d = &board->sdi[i];
498 if (d->chans) {
499 s = &dev->subdevices[subdev++];
500 s->type = COMEDI_SUBD_DI;
501 s->subdev_flags = SDF_READABLE;
502 s->n_chan = d->chans;
503 s->maxdata = 1;
504 s->range_table = &range_digital;
505 s->insn_bits = board->is_16bit
506 ? pci_dio_insn_bits_di_w
507 : pci_dio_insn_bits_di_b;
508 s->private = (void *)d;
509 }
510 }
511
512 for (i = 0; i < MAX_DO_SUBDEVS; i++) {
513 d = &board->sdo[i];
514 if (d->chans) {
515 s = &dev->subdevices[subdev++];
516 s->type = COMEDI_SUBD_DO;
517 s->subdev_flags = SDF_WRITABLE;
518 s->n_chan = d->chans;
519 s->maxdata = 1;
520 s->range_table = &range_digital;
521 s->insn_bits = board->is_16bit
522 ? pci_dio_insn_bits_do_w
523 : pci_dio_insn_bits_do_b;
524 s->private = (void *)d;
525 }
526 }
527
528 for (i = 0; i < MAX_DIO_SUBDEVG; i++) {
529 d = &board->sdio[i];
530 for (j = 0; j < d->chans; j++) {
531 s = &dev->subdevices[subdev++];
532 ret = subdev_8255_init(dev, s, NULL,
533 d->addr + j * I8255_SIZE);
534 if (ret)
535 return ret;
536 }
537 }
538
539 d = &board->boardid;
540 if (d->chans) {
541 s = &dev->subdevices[subdev++];
542 s->type = COMEDI_SUBD_DI;
543 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
544 s->n_chan = d->chans;
545 s->maxdata = 1;
546 s->range_table = &range_digital;
547 s->insn_bits = board->is_16bit ? pci_dio_insn_bits_di_w
548 : pci_dio_insn_bits_di_b;
549 s->private = (void *)d;
550 }
551
552 if (board->timer_regbase) {
553 s = &dev->subdevices[subdev++];
554
555 dev->pacer = comedi_8254_init(dev->iobase +
556 board->timer_regbase,
557 0, I8254_IO8, 0);
558 if (!dev->pacer)
559 return -ENOMEM;
560
561 comedi_8254_subdevice_init(s, dev->pacer);
562 }
563
564 pci_dio_reset(dev);
565
566 return 0;
567 }
568
569 static void pci_dio_detach(struct comedi_device *dev)
570 {
571 if (dev->iobase)
572 pci_dio_reset(dev);
573 comedi_pci_detach(dev);
574 }
575
576 static struct comedi_driver adv_pci_dio_driver = {
577 .driver_name = "adv_pci_dio",
578 .module = THIS_MODULE,
579 .auto_attach = pci_dio_auto_attach,
580 .detach = pci_dio_detach,
581 };
582
583 static int adv_pci_dio_pci_probe(struct pci_dev *dev,
584 const struct pci_device_id *id)
585 {
586 unsigned long cardtype;
587
588 cardtype = pci_dio_override_cardtype(dev, id->driver_data);
589 return comedi_pci_auto_config(dev, &adv_pci_dio_driver, cardtype);
590 }
591
592 static const struct pci_device_id adv_pci_dio_pci_table[] = {
593 { PCI_VDEVICE(ADVANTECH, 0x1730), TYPE_PCI1730 },
594 { PCI_VDEVICE(ADVANTECH, 0x1733), TYPE_PCI1733 },
595 { PCI_VDEVICE(ADVANTECH, 0x1734), TYPE_PCI1734 },
596 { PCI_VDEVICE(ADVANTECH, 0x1735), TYPE_PCI1735 },
597 { PCI_VDEVICE(ADVANTECH, 0x1736), TYPE_PCI1736 },
598 { PCI_VDEVICE(ADVANTECH, 0x1739), TYPE_PCI1739 },
599 { PCI_VDEVICE(ADVANTECH, 0x1750), TYPE_PCI1750 },
600 { PCI_VDEVICE(ADVANTECH, 0x1751), TYPE_PCI1751 },
601 { PCI_VDEVICE(ADVANTECH, 0x1752), TYPE_PCI1752 },
602 { PCI_VDEVICE(ADVANTECH, 0x1753), TYPE_PCI1753 },
603 { PCI_VDEVICE(ADVANTECH, 0x1754), TYPE_PCI1754 },
604 { PCI_VDEVICE(ADVANTECH, 0x1756), TYPE_PCI1756 },
605 { PCI_VDEVICE(ADVANTECH, 0x1762), TYPE_PCI1762 },
606 { 0 }
607 };
608 MODULE_DEVICE_TABLE(pci, adv_pci_dio_pci_table);
609
610 static struct pci_driver adv_pci_dio_pci_driver = {
611 .name = "adv_pci_dio",
612 .id_table = adv_pci_dio_pci_table,
613 .probe = adv_pci_dio_pci_probe,
614 .remove = comedi_pci_auto_unconfig,
615 };
616 module_comedi_pci_driver(adv_pci_dio_driver, adv_pci_dio_pci_driver);
617
618 MODULE_AUTHOR("Comedi http://www.comedi.org");
619 MODULE_DESCRIPTION("Comedi low-level driver");
620 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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