2 * comedi/drivers/adv_pci_dio.c
4 * Author: Michal Dobes <dobes@tesnet.cz>
6 * Hardware driver for Advantech PCI DIO cards.
10 Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U,
11 PCI-1736UP, PCI-1739U, PCI-1750, PCI-1751, PCI-1752,
12 PCI-1753/E, PCI-1754, PCI-1756, PCI-1760, PCI-1762
13 Author: Michal Dobes <dobes@tesnet.cz>
14 Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
15 PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
16 PCI-1751, PCI-1752, PCI-1753,
17 PCI-1753+PCI-1753E, PCI-1754, PCI-1756,
20 Updated: Mon, 09 Jan 2012 12:40:46 +0000
22 This driver supports now only insn interface for DI/DO/DIO.
24 Configuration options:
25 [0] - PCI bus of device (optional)
26 [1] - PCI slot of device (optional)
27 If bus/slot is not specified, the first available PCI
32 #include "../comedidev.h"
34 #include <linux/delay.h>
39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
41 /* hardware types of the cards */
43 TYPE_PCI1730
, TYPE_PCI1733
, TYPE_PCI1734
, TYPE_PCI1735
, TYPE_PCI1736
,
48 TYPE_PCI1753
, TYPE_PCI1753E
,
49 TYPE_PCI1754
, TYPE_PCI1756
,
54 /* which I/O instructions to use */
59 #define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */
60 #define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */
61 #define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per
63 #define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per
65 /* (could be more than one 8254 per
68 #define SIZE_8254 4 /* 8254 IO space length */
69 #define SIZE_8255 4 /* 8255 IO space length */
71 #define PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */
73 /* Register offset definitions */
74 /* Advantech PCI-1730/3/4 */
75 #define PCI1730_IDI 0 /* R: Isolated digital input 0-15 */
76 #define PCI1730_IDO 0 /* W: Isolated digital output 0-15 */
77 #define PCI1730_DI 2 /* R: Digital input 0-15 */
78 #define PCI1730_DO 2 /* W: Digital output 0-15 */
79 #define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */
80 #define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
81 #define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for
83 #define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */
84 #define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */
85 #define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */
87 /* Advantech PCI-1735U */
88 #define PCI1735_DI 0 /* R: Digital input 0-31 */
89 #define PCI1735_DO 0 /* W: Digital output 0-31 */
90 #define PCI1735_C8254 4 /* R/W: 8254 counter */
91 #define PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */
93 /* Advantech PCI-1736UP */
94 #define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */
95 #define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */
96 #define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
97 #define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for
99 #define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */
100 #define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */
101 #define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */
103 /* Advantech PCI-1739U */
104 #define PCI1739_DIO 0 /* R/W: begin of 8255 registers block */
105 #define PCI1739_ICR 32 /* W: Interrupt control register */
106 #define PCI1739_ISR 32 /* R: Interrupt status register */
107 #define PCI1739_BOARDID 8 /* R: Board I/D switch for 1739U */
109 /* Advantech PCI-1750 */
110 #define PCI1750_IDI 0 /* R: Isolated digital input 0-15 */
111 #define PCI1750_IDO 0 /* W: Isolated digital output 0-15 */
112 #define PCI1750_ICR 32 /* W: Interrupt control register */
113 #define PCI1750_ISR 32 /* R: Interrupt status register */
115 /* Advantech PCI-1751/3/3E */
116 #define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */
117 #define PCI1751_CNT 24 /* R/W: begin of 8254 registers block */
118 #define PCI1751_ICR 32 /* W: Interrupt control register */
119 #define PCI1751_ISR 32 /* R: Interrupt status register */
120 #define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */
121 #define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */
122 #define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */
123 #define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */
124 #define PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */
125 #define PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */
126 #define PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */
127 #define PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */
128 #define PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */
129 #define PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */
131 /* Advantech PCI-1752/4/6 */
132 #define PCI1752_IDO 0 /* R/W: Digital output 0-31 */
133 #define PCI1752_IDO2 4 /* R/W: Digital output 32-63 */
134 #define PCI1754_IDI 0 /* R: Digital input 0-31 */
135 #define PCI1754_IDI2 4 /* R: Digital input 32-64 */
136 #define PCI1756_IDI 0 /* R: Digital input 0-31 */
137 #define PCI1756_IDO 4 /* R/W: Digital output 0-31 */
138 #define PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */
139 #define PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */
140 #define PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */
141 #define PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */
142 #define PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */
143 #define PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */
145 /* Advantech PCI-1762 registers */
146 #define PCI1762_RO 0 /* R/W: Relays status/output */
147 #define PCI1762_IDI 2 /* R: Isolated input status */
148 #define PCI1762_BOARDID 4 /* R: Board I/D switch */
149 #define PCI1762_ICR 6 /* W: Interrupt control register */
150 #define PCI1762_ISR 6 /* R: Interrupt status register */
152 /* Advantech PCI-1760 registers */
153 #define OMB0 0x0c /* W: Mailbox outgoing registers */
157 #define IMB0 0x1c /* R: Mailbox incoming registers */
161 #define INTCSR0 0x38 /* R/W: Interrupt control registers */
166 /* PCI-1760 mailbox commands */
167 #define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actual
168 * DI status in IMB3 */
169 #define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */
170 #define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */
171 #define CMD_ReadCurrentStatus 0x07 /* Read the current status of the
172 * register in OMB0, result in IMB0 */
173 #define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in
175 #define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in
177 #define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in
179 #define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on
181 #define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on
183 #define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in
185 #define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in
186 * OMB0 to its reset values */
187 #define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow
188 * interrupts based on bits in OMB0 */
189 #define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value
190 * interrupts based on bits in OMB0 */
191 #define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0
192 * - rising, =1 - falling) */
193 #define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current
195 #define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value
197 #define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value
199 #define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value
201 #define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value
203 #define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value
205 #define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value
207 #define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value
209 #define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value
211 #define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value
213 #define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value
215 #define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value
217 #define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value
219 #define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value
221 #define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value
223 #define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value
225 #define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value
228 #define OMBCMD_RETRY 0x03 /* 3 times try request before error */
230 struct diosubd_data
{
231 int chans
; /* num of chans */
232 int addr
; /* PCI address ofset */
233 int regs
; /* number of registers to read or 8255
234 subdevices or 8254 chips */
235 unsigned int specflags
; /* addon subdevice flags */
238 struct dio_boardtype
{
239 const char *name
; /* board name */
240 int vendor_id
; /* vendor/device PCI ID */
242 int main_pci_region
; /* main I/O PCI region */
243 enum hw_cards_id cardtype
;
245 struct diosubd_data sdi
[MAX_DI_SUBDEVS
]; /* DI chans */
246 struct diosubd_data sdo
[MAX_DO_SUBDEVS
]; /* DO chans */
247 struct diosubd_data sdio
[MAX_DIO_SUBDEVG
]; /* DIO 8255 chans */
248 struct diosubd_data boardid
; /* card supports board ID switch */
249 struct diosubd_data s8254
[MAX_8254_SUBDEVS
]; /* 8254 subdevices */
250 enum hw_io_access io_access
;
253 static const struct dio_boardtype boardtypes
[] = {
256 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
258 .main_pci_region
= PCIDIO_MAINREG
,
259 .cardtype
= TYPE_PCI1730
,
261 .sdi
[0] = { 16, PCI1730_DI
, 2, 0, },
262 .sdi
[1] = { 16, PCI1730_IDI
, 2, 0, },
263 .sdo
[0] = { 16, PCI1730_DO
, 2, 0, },
264 .sdo
[1] = { 16, PCI1730_IDO
, 2, 0, },
265 .boardid
= { 4, PCI173x_BOARDID
, 1, SDF_INTERNAL
, },
269 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
271 .main_pci_region
= PCIDIO_MAINREG
,
272 .cardtype
= TYPE_PCI1733
,
274 .sdi
[1] = { 32, PCI1733_IDI
, 4, 0, },
275 .boardid
= { 4, PCI173x_BOARDID
, 1, SDF_INTERNAL
, },
279 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
281 .main_pci_region
= PCIDIO_MAINREG
,
282 .cardtype
= TYPE_PCI1734
,
284 .sdo
[1] = { 32, PCI1734_IDO
, 4, 0, },
285 .boardid
= { 4, PCI173x_BOARDID
, 1, SDF_INTERNAL
, },
289 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
291 .main_pci_region
= PCIDIO_MAINREG
,
292 .cardtype
= TYPE_PCI1735
,
294 .sdi
[0] = { 32, PCI1735_DI
, 4, 0, },
295 .sdo
[0] = { 32, PCI1735_DO
, 4, 0, },
296 .boardid
= { 4, PCI1735_BOARDID
, 1, SDF_INTERNAL
, },
297 .s8254
[0] = { 3, PCI1735_C8254
, 1, 0, },
301 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
303 .main_pci_region
= PCI1736_MAINREG
,
304 .cardtype
= TYPE_PCI1736
,
306 .sdi
[1] = { 16, PCI1736_IDI
, 2, 0, },
307 .sdo
[1] = { 16, PCI1736_IDO
, 2, 0, },
308 .boardid
= { 4, PCI1736_BOARDID
, 1, SDF_INTERNAL
, },
312 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
314 .main_pci_region
= PCIDIO_MAINREG
,
315 .cardtype
= TYPE_PCI1739
,
317 .sdio
[0] = { 48, PCI1739_DIO
, 2, 0, },
321 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
323 .main_pci_region
= PCIDIO_MAINREG
,
324 .cardtype
= TYPE_PCI1750
,
326 .sdi
[1] = { 16, PCI1750_IDI
, 2, 0, },
327 .sdo
[1] = { 16, PCI1750_IDO
, 2, 0, },
331 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
333 .main_pci_region
= PCIDIO_MAINREG
,
334 .cardtype
= TYPE_PCI1751
,
336 .sdio
[0] = { 48, PCI1751_DIO
, 2, 0, },
337 .s8254
[0] = { 3, PCI1751_CNT
, 1, 0, },
341 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
343 .main_pci_region
= PCIDIO_MAINREG
,
344 .cardtype
= TYPE_PCI1752
,
346 .sdo
[0] = { 32, PCI1752_IDO
, 2, 0, },
347 .sdo
[1] = { 32, PCI1752_IDO2
, 2, 0, },
348 .boardid
= { 4, PCI175x_BOARDID
, 1, SDF_INTERNAL
, },
352 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
354 .main_pci_region
= PCIDIO_MAINREG
,
355 .cardtype
= TYPE_PCI1753
,
357 .sdio
[0] = { 96, PCI1753_DIO
, 4, 0, },
361 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
363 .main_pci_region
= PCIDIO_MAINREG
,
364 .cardtype
= TYPE_PCI1753E
,
366 .sdio
[0] = { 96, PCI1753_DIO
, 4, 0, },
367 .sdio
[1] = { 96, PCI1753E_DIO
, 4, 0, },
371 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
373 .main_pci_region
= PCIDIO_MAINREG
,
374 .cardtype
= TYPE_PCI1754
,
376 .sdi
[0] = { 32, PCI1754_IDI
, 2, 0, },
377 .sdi
[1] = { 32, PCI1754_IDI2
, 2, 0, },
378 .boardid
= { 4, PCI175x_BOARDID
, 1, SDF_INTERNAL
, },
382 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
384 .main_pci_region
= PCIDIO_MAINREG
,
385 .cardtype
= TYPE_PCI1756
,
387 .sdi
[1] = { 32, PCI1756_IDI
, 2, 0, },
388 .sdo
[1] = { 32, PCI1756_IDO
, 2, 0, },
389 .boardid
= { 4, PCI175x_BOARDID
, 1, SDF_INTERNAL
, },
392 /* This card has its own 'attach' */
394 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
396 .main_pci_region
= 0,
397 .cardtype
= TYPE_PCI1760
,
402 .vendor_id
= PCI_VENDOR_ID_ADVANTECH
,
404 .main_pci_region
= PCIDIO_MAINREG
,
405 .cardtype
= TYPE_PCI1762
,
407 .sdi
[1] = { 16, PCI1762_IDI
, 1, 0, },
408 .sdo
[1] = { 16, PCI1762_RO
, 1, 0, },
409 .boardid
= { 4, PCI1762_BOARDID
, 1, SDF_INTERNAL
, },
414 struct pci_dio_private
{
415 char valid
; /* card is usable */
416 char GlobalIrqEnabled
; /* 1= any IRQ source is enabled */
417 /* PCI-1760 specific data */
418 unsigned char IDICntEnable
; /* counter's counting enable status */
419 unsigned char IDICntOverEnable
; /* counter's overflow interrupts enable
421 unsigned char IDICntMatchEnable
; /* counter's match interrupts
423 unsigned char IDICntEdge
; /* counter's count edge value
424 * (bit=0 - rising, =1 - falling) */
425 unsigned short CntResValue
[8]; /* counters' reset value */
426 unsigned short CntMatchValue
[8]; /* counters' match interrupt value */
427 unsigned char IDIFiltersEn
; /* IDI's digital filters enable status */
428 unsigned char IDIPatMatchEn
; /* IDI's pattern match enable status */
429 unsigned char IDIPatMatchValue
; /* IDI's pattern match value */
430 unsigned short IDIFiltrLow
[8]; /* IDI's filter value low signal */
431 unsigned short IDIFiltrHigh
[8]; /* IDI's filter value high signal */
435 ==============================================================================
437 static int pci_dio_insn_bits_di_b(struct comedi_device
*dev
,
438 struct comedi_subdevice
*s
,
439 struct comedi_insn
*insn
, unsigned int *data
)
441 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
445 for (i
= 0; i
< d
->regs
; i
++)
446 data
[1] |= inb(dev
->iobase
+ d
->addr
+ i
) << (8 * i
);
453 ==============================================================================
455 static int pci_dio_insn_bits_di_w(struct comedi_device
*dev
,
456 struct comedi_subdevice
*s
,
457 struct comedi_insn
*insn
, unsigned int *data
)
459 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
463 for (i
= 0; i
< d
->regs
; i
++)
464 data
[1] |= inw(dev
->iobase
+ d
->addr
+ 2 * i
) << (16 * i
);
470 ==============================================================================
472 static int pci_dio_insn_bits_do_b(struct comedi_device
*dev
,
473 struct comedi_subdevice
*s
,
474 struct comedi_insn
*insn
, unsigned int *data
)
476 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
480 s
->state
&= ~data
[0];
481 s
->state
|= (data
[0] & data
[1]);
482 for (i
= 0; i
< d
->regs
; i
++)
483 outb((s
->state
>> (8 * i
)) & 0xff,
484 dev
->iobase
+ d
->addr
+ i
);
492 ==============================================================================
494 static int pci_dio_insn_bits_do_w(struct comedi_device
*dev
,
495 struct comedi_subdevice
*s
,
496 struct comedi_insn
*insn
, unsigned int *data
)
498 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
502 s
->state
&= ~data
[0];
503 s
->state
|= (data
[0] & data
[1]);
504 for (i
= 0; i
< d
->regs
; i
++)
505 outw((s
->state
>> (16 * i
)) & 0xffff,
506 dev
->iobase
+ d
->addr
+ 2 * i
);
514 ==============================================================================
516 static int pci_8254_insn_read(struct comedi_device
*dev
,
517 struct comedi_subdevice
*s
,
518 struct comedi_insn
*insn
, unsigned int *data
)
520 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
521 unsigned int chan
, chip
, chipchan
;
524 chan
= CR_CHAN(insn
->chanspec
); /* channel on subdevice */
525 chip
= chan
/ 3; /* chip on subdevice */
526 chipchan
= chan
- (3 * chip
); /* channel on chip on subdevice */
527 spin_lock_irqsave(&s
->spin_lock
, flags
);
528 data
[0] = i8254_read(dev
->iobase
+ d
->addr
+ (SIZE_8254
* chip
),
530 spin_unlock_irqrestore(&s
->spin_lock
, flags
);
535 ==============================================================================
537 static int pci_8254_insn_write(struct comedi_device
*dev
,
538 struct comedi_subdevice
*s
,
539 struct comedi_insn
*insn
, unsigned int *data
)
541 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
542 unsigned int chan
, chip
, chipchan
;
545 chan
= CR_CHAN(insn
->chanspec
); /* channel on subdevice */
546 chip
= chan
/ 3; /* chip on subdevice */
547 chipchan
= chan
- (3 * chip
); /* channel on chip on subdevice */
548 spin_lock_irqsave(&s
->spin_lock
, flags
);
549 i8254_write(dev
->iobase
+ d
->addr
+ (SIZE_8254
* chip
),
550 0, chipchan
, data
[0]);
551 spin_unlock_irqrestore(&s
->spin_lock
, flags
);
556 ==============================================================================
558 static int pci_8254_insn_config(struct comedi_device
*dev
,
559 struct comedi_subdevice
*s
,
560 struct comedi_insn
*insn
, unsigned int *data
)
562 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
563 unsigned int chan
, chip
, chipchan
;
564 unsigned long iobase
;
568 chan
= CR_CHAN(insn
->chanspec
); /* channel on subdevice */
569 chip
= chan
/ 3; /* chip on subdevice */
570 chipchan
= chan
- (3 * chip
); /* channel on chip on subdevice */
571 iobase
= dev
->iobase
+ d
->addr
+ (SIZE_8254
* chip
);
572 spin_lock_irqsave(&s
->spin_lock
, flags
);
574 case INSN_CONFIG_SET_COUNTER_MODE
:
575 ret
= i8254_set_mode(iobase
, 0, chipchan
, data
[1]);
579 case INSN_CONFIG_8254_READ_STATUS
:
580 data
[1] = i8254_status(iobase
, 0, chipchan
);
586 spin_unlock_irqrestore(&s
->spin_lock
, flags
);
587 return ret
< 0 ? ret
: insn
->n
;
591 ==============================================================================
593 static int pci1760_unchecked_mbxrequest(struct comedi_device
*dev
,
594 unsigned char *omb
, unsigned char *imb
,
597 int cnt
, tout
, ok
= 0;
599 for (cnt
= 0; cnt
< repeats
; cnt
++) {
600 outb(omb
[0], dev
->iobase
+ OMB0
);
601 outb(omb
[1], dev
->iobase
+ OMB1
);
602 outb(omb
[2], dev
->iobase
+ OMB2
);
603 outb(omb
[3], dev
->iobase
+ OMB3
);
604 for (tout
= 0; tout
< 251; tout
++) {
605 imb
[2] = inb(dev
->iobase
+ IMB2
);
606 if (imb
[2] == omb
[2]) {
607 imb
[0] = inb(dev
->iobase
+ IMB0
);
608 imb
[1] = inb(dev
->iobase
+ IMB1
);
609 imb
[3] = inb(dev
->iobase
+ IMB3
);
619 comedi_error(dev
, "PCI-1760 mailbox request timeout!");
623 static int pci1760_clear_imb2(struct comedi_device
*dev
)
625 unsigned char omb
[4] = { 0x0, 0x0, CMD_ClearIMB2
, 0x0 };
626 unsigned char imb
[4];
627 /* check if imb2 is already clear */
628 if (inb(dev
->iobase
+ IMB2
) == CMD_ClearIMB2
)
630 return pci1760_unchecked_mbxrequest(dev
, omb
, imb
, OMBCMD_RETRY
);
633 static int pci1760_mbxrequest(struct comedi_device
*dev
,
634 unsigned char *omb
, unsigned char *imb
)
636 if (omb
[2] == CMD_ClearIMB2
) {
638 "bug! this function should not be used for CMD_ClearIMB2 command");
641 if (inb(dev
->iobase
+ IMB2
) == omb
[2]) {
643 retval
= pci1760_clear_imb2(dev
);
647 return pci1760_unchecked_mbxrequest(dev
, omb
, imb
, OMBCMD_RETRY
);
651 ==============================================================================
653 static int pci1760_insn_bits_di(struct comedi_device
*dev
,
654 struct comedi_subdevice
*s
,
655 struct comedi_insn
*insn
, unsigned int *data
)
657 data
[1] = inb(dev
->iobase
+ IMB3
);
663 ==============================================================================
665 static int pci1760_insn_bits_do(struct comedi_device
*dev
,
666 struct comedi_subdevice
*s
,
667 struct comedi_insn
*insn
, unsigned int *data
)
670 unsigned char omb
[4] = {
676 unsigned char imb
[4];
679 s
->state
&= ~data
[0];
680 s
->state
|= (data
[0] & data
[1]);
682 ret
= pci1760_mbxrequest(dev
, omb
, imb
);
692 ==============================================================================
694 static int pci1760_insn_cnt_read(struct comedi_device
*dev
,
695 struct comedi_subdevice
*s
,
696 struct comedi_insn
*insn
, unsigned int *data
)
699 unsigned char omb
[4] = {
700 CR_CHAN(insn
->chanspec
) & 0x07,
702 CMD_GetIDICntCurValue
,
705 unsigned char imb
[4];
707 for (n
= 0; n
< insn
->n
; n
++) {
708 ret
= pci1760_mbxrequest(dev
, omb
, imb
);
711 data
[n
] = (imb
[1] << 8) + imb
[0];
718 ==============================================================================
720 static int pci1760_insn_cnt_write(struct comedi_device
*dev
,
721 struct comedi_subdevice
*s
,
722 struct comedi_insn
*insn
, unsigned int *data
)
724 struct pci_dio_private
*devpriv
= dev
->private;
726 unsigned char chan
= CR_CHAN(insn
->chanspec
) & 0x07;
727 unsigned char bitmask
= 1 << chan
;
728 unsigned char omb
[4] = {
730 (data
[0] >> 8) & 0xff,
731 CMD_SetIDI0CntResetValue
+ chan
,
734 unsigned char imb
[4];
736 /* Set reset value if different */
737 if (devpriv
->CntResValue
[chan
] != (data
[0] & 0xffff)) {
738 ret
= pci1760_mbxrequest(dev
, omb
, imb
);
741 devpriv
->CntResValue
[chan
] = data
[0] & 0xffff;
744 omb
[0] = bitmask
; /* reset counter to it reset value */
745 omb
[2] = CMD_ResetIDICounters
;
746 ret
= pci1760_mbxrequest(dev
, omb
, imb
);
750 /* start counter if it don't run */
751 if (!(bitmask
& devpriv
->IDICntEnable
)) {
753 omb
[2] = CMD_EnableIDICounters
;
754 ret
= pci1760_mbxrequest(dev
, omb
, imb
);
757 devpriv
->IDICntEnable
|= bitmask
;
763 ==============================================================================
765 static int pci1760_reset(struct comedi_device
*dev
)
767 struct pci_dio_private
*devpriv
= dev
->private;
769 unsigned char omb
[4] = { 0x00, 0x00, 0x00, 0x00 };
770 unsigned char imb
[4];
772 outb(0, dev
->iobase
+ INTCSR0
); /* disable IRQ */
773 outb(0, dev
->iobase
+ INTCSR1
);
774 outb(0, dev
->iobase
+ INTCSR2
);
775 outb(0, dev
->iobase
+ INTCSR3
);
776 devpriv
->GlobalIrqEnabled
= 0;
779 omb
[2] = CMD_SetRelaysOutput
; /* reset relay outputs */
780 pci1760_mbxrequest(dev
, omb
, imb
);
783 omb
[2] = CMD_EnableIDICounters
; /* disable IDI up counters */
784 pci1760_mbxrequest(dev
, omb
, imb
);
785 devpriv
->IDICntEnable
= 0;
788 omb
[2] = CMD_OverflowIDICounters
; /* disable counters overflow
790 pci1760_mbxrequest(dev
, omb
, imb
);
791 devpriv
->IDICntOverEnable
= 0;
794 omb
[2] = CMD_MatchIntIDICounters
; /* disable counters match value
796 pci1760_mbxrequest(dev
, omb
, imb
);
797 devpriv
->IDICntMatchEnable
= 0;
801 for (i
= 0; i
< 8; i
++) { /* set IDI up counters match value */
802 omb
[2] = CMD_SetIDI0CntMatchValue
+ i
;
803 pci1760_mbxrequest(dev
, omb
, imb
);
804 devpriv
->CntMatchValue
[i
] = 0x8000;
809 for (i
= 0; i
< 8; i
++) { /* set IDI up counters reset value */
810 omb
[2] = CMD_SetIDI0CntResetValue
+ i
;
811 pci1760_mbxrequest(dev
, omb
, imb
);
812 devpriv
->CntResValue
[i
] = 0x0000;
816 omb
[2] = CMD_ResetIDICounters
; /* reset IDI up counters to reset
818 pci1760_mbxrequest(dev
, omb
, imb
);
821 omb
[2] = CMD_EdgeIDICounters
; /* set IDI up counters count edge */
822 pci1760_mbxrequest(dev
, omb
, imb
);
823 devpriv
->IDICntEdge
= 0x00;
826 omb
[2] = CMD_EnableIDIFilters
; /* disable all digital in filters */
827 pci1760_mbxrequest(dev
, omb
, imb
);
828 devpriv
->IDIFiltersEn
= 0x00;
831 omb
[2] = CMD_EnableIDIPatternMatch
; /* disable pattern matching */
832 pci1760_mbxrequest(dev
, omb
, imb
);
833 devpriv
->IDIPatMatchEn
= 0x00;
836 omb
[2] = CMD_SetIDIPatternMatch
; /* set pattern match value */
837 pci1760_mbxrequest(dev
, omb
, imb
);
838 devpriv
->IDIPatMatchValue
= 0x00;
844 ==============================================================================
846 static int pci_dio_reset(struct comedi_device
*dev
)
848 const struct dio_boardtype
*this_board
= comedi_board(dev
);
850 switch (this_board
->cardtype
) {
852 outb(0, dev
->iobase
+ PCI1730_DO
); /* clear outputs */
853 outb(0, dev
->iobase
+ PCI1730_DO
+ 1);
854 outb(0, dev
->iobase
+ PCI1730_IDO
);
855 outb(0, dev
->iobase
+ PCI1730_IDO
+ 1);
856 /* NO break there! */
858 /* disable interrupts */
859 outb(0, dev
->iobase
+ PCI1730_3_INT_EN
);
860 /* clear interrupts */
861 outb(0x0f, dev
->iobase
+ PCI1730_3_INT_CLR
);
862 /* set rising edge trigger */
863 outb(0, dev
->iobase
+ PCI1730_3_INT_RF
);
866 outb(0, dev
->iobase
+ PCI1734_IDO
); /* clear outputs */
867 outb(0, dev
->iobase
+ PCI1734_IDO
+ 1);
868 outb(0, dev
->iobase
+ PCI1734_IDO
+ 2);
869 outb(0, dev
->iobase
+ PCI1734_IDO
+ 3);
872 outb(0, dev
->iobase
+ PCI1735_DO
); /* clear outputs */
873 outb(0, dev
->iobase
+ PCI1735_DO
+ 1);
874 outb(0, dev
->iobase
+ PCI1735_DO
+ 2);
875 outb(0, dev
->iobase
+ PCI1735_DO
+ 3);
876 i8254_set_mode(dev
->iobase
+ PCI1735_C8254
, 0, 0, I8254_MODE0
);
877 i8254_set_mode(dev
->iobase
+ PCI1735_C8254
, 0, 1, I8254_MODE0
);
878 i8254_set_mode(dev
->iobase
+ PCI1735_C8254
, 0, 2, I8254_MODE0
);
882 outb(0, dev
->iobase
+ PCI1736_IDO
);
883 outb(0, dev
->iobase
+ PCI1736_IDO
+ 1);
884 /* disable interrupts */
885 outb(0, dev
->iobase
+ PCI1736_3_INT_EN
);
886 /* clear interrupts */
887 outb(0x0f, dev
->iobase
+ PCI1736_3_INT_CLR
);
888 /* set rising edge trigger */
889 outb(0, dev
->iobase
+ PCI1736_3_INT_RF
);
893 /* disable & clear interrupts */
894 outb(0x88, dev
->iobase
+ PCI1739_ICR
);
899 /* disable & clear interrupts */
900 outb(0x88, dev
->iobase
+ PCI1750_ICR
);
903 outw(0, dev
->iobase
+ PCI1752_6_CFC
); /* disable channel freeze
905 outw(0, dev
->iobase
+ PCI1752_IDO
); /* clear outputs */
906 outw(0, dev
->iobase
+ PCI1752_IDO
+ 2);
907 outw(0, dev
->iobase
+ PCI1752_IDO2
);
908 outw(0, dev
->iobase
+ PCI1752_IDO2
+ 2);
911 outb(0x88, dev
->iobase
+ PCI1753E_ICR0
); /* disable & clear
913 outb(0x80, dev
->iobase
+ PCI1753E_ICR1
);
914 outb(0x80, dev
->iobase
+ PCI1753E_ICR2
);
915 outb(0x80, dev
->iobase
+ PCI1753E_ICR3
);
916 /* NO break there! */
918 outb(0x88, dev
->iobase
+ PCI1753_ICR0
); /* disable & clear
920 outb(0x80, dev
->iobase
+ PCI1753_ICR1
);
921 outb(0x80, dev
->iobase
+ PCI1753_ICR2
);
922 outb(0x80, dev
->iobase
+ PCI1753_ICR3
);
925 outw(0x08, dev
->iobase
+ PCI1754_6_ICR0
); /* disable and clear
927 outw(0x08, dev
->iobase
+ PCI1754_6_ICR1
);
928 outw(0x08, dev
->iobase
+ PCI1754_ICR2
);
929 outw(0x08, dev
->iobase
+ PCI1754_ICR3
);
932 outw(0, dev
->iobase
+ PCI1752_6_CFC
); /* disable channel freeze
934 outw(0x08, dev
->iobase
+ PCI1754_6_ICR0
); /* disable and clear
936 outw(0x08, dev
->iobase
+ PCI1754_6_ICR1
);
937 outw(0, dev
->iobase
+ PCI1756_IDO
); /* clear outputs */
938 outw(0, dev
->iobase
+ PCI1756_IDO
+ 2);
944 outw(0x0101, dev
->iobase
+ PCI1762_ICR
); /* disable & clear
953 ==============================================================================
955 static int pci1760_attach(struct comedi_device
*dev
)
957 struct comedi_subdevice
*s
;
959 s
= &dev
->subdevices
[0];
960 s
->type
= COMEDI_SUBD_DI
;
961 s
->subdev_flags
= SDF_READABLE
| SDF_GROUND
| SDF_COMMON
;
965 s
->range_table
= &range_digital
;
966 s
->insn_bits
= pci1760_insn_bits_di
;
968 s
= &dev
->subdevices
[1];
969 s
->type
= COMEDI_SUBD_DO
;
970 s
->subdev_flags
= SDF_WRITABLE
| SDF_GROUND
| SDF_COMMON
;
974 s
->range_table
= &range_digital
;
976 s
->insn_bits
= pci1760_insn_bits_do
;
978 s
= &dev
->subdevices
[2];
979 s
->type
= COMEDI_SUBD_TIMER
;
980 s
->subdev_flags
= SDF_WRITABLE
| SDF_LSAMPL
;
982 s
->maxdata
= 0xffffffff;
984 /* s->insn_config=pci1760_insn_pwm_cfg; */
986 s
= &dev
->subdevices
[3];
987 s
->type
= COMEDI_SUBD_COUNTER
;
988 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
;
992 s
->insn_read
= pci1760_insn_cnt_read
;
993 s
->insn_write
= pci1760_insn_cnt_write
;
994 /* s->insn_config=pci1760_insn_cnt_cfg; */
1000 ==============================================================================
1002 static int pci_dio_add_di(struct comedi_device
*dev
,
1003 struct comedi_subdevice
*s
,
1004 const struct diosubd_data
*d
)
1006 const struct dio_boardtype
*this_board
= comedi_board(dev
);
1008 s
->type
= COMEDI_SUBD_DI
;
1009 s
->subdev_flags
= SDF_READABLE
| SDF_GROUND
| SDF_COMMON
| d
->specflags
;
1011 s
->subdev_flags
|= SDF_LSAMPL
;
1012 s
->n_chan
= d
->chans
;
1014 s
->len_chanlist
= d
->chans
;
1015 s
->range_table
= &range_digital
;
1016 switch (this_board
->io_access
) {
1018 s
->insn_bits
= pci_dio_insn_bits_di_b
;
1021 s
->insn_bits
= pci_dio_insn_bits_di_w
;
1024 s
->private = (void *)d
;
1030 ==============================================================================
1032 static int pci_dio_add_do(struct comedi_device
*dev
,
1033 struct comedi_subdevice
*s
,
1034 const struct diosubd_data
*d
)
1036 const struct dio_boardtype
*this_board
= comedi_board(dev
);
1038 s
->type
= COMEDI_SUBD_DO
;
1039 s
->subdev_flags
= SDF_WRITABLE
| SDF_GROUND
| SDF_COMMON
;
1041 s
->subdev_flags
|= SDF_LSAMPL
;
1042 s
->n_chan
= d
->chans
;
1044 s
->len_chanlist
= d
->chans
;
1045 s
->range_table
= &range_digital
;
1047 switch (this_board
->io_access
) {
1049 s
->insn_bits
= pci_dio_insn_bits_do_b
;
1052 s
->insn_bits
= pci_dio_insn_bits_do_w
;
1055 s
->private = (void *)d
;
1061 ==============================================================================
1063 static int pci_dio_add_8254(struct comedi_device
*dev
,
1064 struct comedi_subdevice
*s
,
1065 const struct diosubd_data
*d
)
1067 s
->type
= COMEDI_SUBD_COUNTER
;
1068 s
->subdev_flags
= SDF_WRITABLE
| SDF_READABLE
;
1069 s
->n_chan
= d
->chans
;
1071 s
->len_chanlist
= d
->chans
;
1072 s
->insn_read
= pci_8254_insn_read
;
1073 s
->insn_write
= pci_8254_insn_write
;
1074 s
->insn_config
= pci_8254_insn_config
;
1075 s
->private = (void *)d
;
1080 static const void *pci_dio_find_boardinfo(struct comedi_device
*dev
,
1081 struct pci_dev
*pcidev
)
1083 const struct dio_boardtype
*this_board
;
1086 for (i
= 0; i
< ARRAY_SIZE(boardtypes
); ++i
) {
1087 this_board
= &boardtypes
[i
];
1088 if (this_board
->vendor_id
== pcidev
->vendor
&&
1089 this_board
->device_id
== pcidev
->device
)
1095 static int pci_dio_attach_pci(struct comedi_device
*dev
,
1096 struct pci_dev
*pcidev
)
1098 const struct dio_boardtype
*this_board
;
1099 struct pci_dio_private
*devpriv
;
1100 struct comedi_subdevice
*s
;
1101 int ret
, subdev
, i
, j
;
1103 comedi_set_hw_dev(dev
, &pcidev
->dev
);
1105 this_board
= pci_dio_find_boardinfo(dev
, pcidev
);
1108 dev
->board_ptr
= this_board
;
1109 dev
->board_name
= this_board
->name
;
1111 ret
= alloc_private(dev
, sizeof(*devpriv
));
1114 devpriv
= dev
->private;
1116 ret
= comedi_pci_enable(pcidev
, dev
->board_name
);
1119 dev
->iobase
= pci_resource_start(pcidev
, this_board
->main_pci_region
);
1121 ret
= comedi_alloc_subdevices(dev
, this_board
->nsubdevs
);
1126 for (i
= 0; i
< MAX_DI_SUBDEVS
; i
++)
1127 if (this_board
->sdi
[i
].chans
) {
1128 s
= &dev
->subdevices
[subdev
];
1129 pci_dio_add_di(dev
, s
, &this_board
->sdi
[i
]);
1133 for (i
= 0; i
< MAX_DO_SUBDEVS
; i
++)
1134 if (this_board
->sdo
[i
].chans
) {
1135 s
= &dev
->subdevices
[subdev
];
1136 pci_dio_add_do(dev
, s
, &this_board
->sdo
[i
]);
1140 for (i
= 0; i
< MAX_DIO_SUBDEVG
; i
++)
1141 for (j
= 0; j
< this_board
->sdio
[i
].regs
; j
++) {
1142 s
= &dev
->subdevices
[subdev
];
1143 subdev_8255_init(dev
, s
, NULL
,
1145 this_board
->sdio
[i
].addr
+
1150 if (this_board
->boardid
.chans
) {
1151 s
= &dev
->subdevices
[subdev
];
1152 s
->type
= COMEDI_SUBD_DI
;
1153 pci_dio_add_di(dev
, s
, &this_board
->boardid
);
1157 for (i
= 0; i
< MAX_8254_SUBDEVS
; i
++)
1158 if (this_board
->s8254
[i
].chans
) {
1159 s
= &dev
->subdevices
[subdev
];
1160 pci_dio_add_8254(dev
, s
, &this_board
->s8254
[i
]);
1164 if (this_board
->cardtype
== TYPE_PCI1760
)
1165 pci1760_attach(dev
);
1174 static void pci_dio_detach(struct comedi_device
*dev
)
1176 struct pci_dio_private
*devpriv
= dev
->private;
1177 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
1178 struct comedi_subdevice
*s
;
1185 if (dev
->subdevices
) {
1186 for (i
= 0; i
< dev
->n_subdevices
; i
++) {
1187 s
= &dev
->subdevices
[i
];
1188 if (s
->type
== COMEDI_SUBD_DIO
)
1189 subdev_8255_cleanup(dev
, s
);
1195 comedi_pci_disable(pcidev
);
1199 static struct comedi_driver adv_pci_dio_driver
= {
1200 .driver_name
= "adv_pci_dio",
1201 .module
= THIS_MODULE
,
1202 .attach_pci
= pci_dio_attach_pci
,
1203 .detach
= pci_dio_detach
,
1206 static int __devinit
adv_pci_dio_pci_probe(struct pci_dev
*dev
,
1207 const struct pci_device_id
*ent
)
1209 return comedi_pci_auto_config(dev
, &adv_pci_dio_driver
);
1212 static void __devexit
adv_pci_dio_pci_remove(struct pci_dev
*dev
)
1214 comedi_pci_auto_unconfig(dev
);
1217 static DEFINE_PCI_DEVICE_TABLE(adv_pci_dio_pci_table
) = {
1218 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1730) },
1219 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1733) },
1220 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1734) },
1221 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1735) },
1222 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1736) },
1223 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1739) },
1224 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1750) },
1225 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1751) },
1226 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1752) },
1227 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1753) },
1228 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1754) },
1229 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1756) },
1230 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1760) },
1231 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1762) },
1234 MODULE_DEVICE_TABLE(pci
, adv_pci_dio_pci_table
);
1236 static struct pci_driver adv_pci_dio_pci_driver
= {
1237 .name
= "adv_pci_dio",
1238 .id_table
= adv_pci_dio_pci_table
,
1239 .probe
= adv_pci_dio_pci_probe
,
1240 .remove
= __devexit_p(adv_pci_dio_pci_remove
),
1242 module_comedi_pci_driver(adv_pci_dio_driver
, adv_pci_dio_pci_driver
);
1244 MODULE_AUTHOR("Comedi http://www.comedi.org");
1245 MODULE_DESCRIPTION("Comedi low-level driver");
1246 MODULE_LICENSE("GPL");