2 * comedi/drivers/adv_pci_dio.c
4 * Author: Michal Dobes <dobes@tesnet.cz>
6 * Hardware driver for Advantech PCI DIO cards.
10 Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U,
11 PCI-1736UP, PCI-1739U, PCI-1750, PCI-1751, PCI-1752,
12 PCI-1753/E, PCI-1754, PCI-1756, PCI-1760, PCI-1762
13 Author: Michal Dobes <dobes@tesnet.cz>
14 Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
15 PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
16 PCI-1751, PCI-1752, PCI-1753,
17 PCI-1753+PCI-1753E, PCI-1754, PCI-1756,
20 Updated: Mon, 09 Jan 2012 12:40:46 +0000
22 This driver supports now only insn interface for DI/DO/DIO.
24 Configuration options:
25 [0] - PCI bus of device (optional)
26 [1] - PCI slot of device (optional)
27 If bus/slot is not specified, the first available PCI
32 #include "../comedidev.h"
34 #include <linux/delay.h>
39 #undef PCI_DIO_EXTDEBUG /* if defined, enable extensive debug logging */
42 #ifdef PCI_DIO_EXTDEBUG
43 #define DPRINTK(fmt, args...) printk(fmt, ## args)
45 #define DPRINTK(fmt, args...)
48 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
50 /* hardware types of the cards */
52 TYPE_PCI1730
, TYPE_PCI1733
, TYPE_PCI1734
, TYPE_PCI1735
, TYPE_PCI1736
,
57 TYPE_PCI1753
, TYPE_PCI1753E
,
58 TYPE_PCI1754
, TYPE_PCI1756
,
63 /* which I/O instructions to use */
68 #define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */
69 #define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */
70 #define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per
72 #define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per
74 /* (could be more than one 8254 per
77 #define SIZE_8254 4 /* 8254 IO space length */
78 #define SIZE_8255 4 /* 8255 IO space length */
80 #define PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */
82 /* Register offset definitions */
83 /* Advantech PCI-1730/3/4 */
84 #define PCI1730_IDI 0 /* R: Isolated digital input 0-15 */
85 #define PCI1730_IDO 0 /* W: Isolated digital output 0-15 */
86 #define PCI1730_DI 2 /* R: Digital input 0-15 */
87 #define PCI1730_DO 2 /* W: Digital output 0-15 */
88 #define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */
89 #define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
90 #define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for
92 #define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */
93 #define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */
94 #define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */
96 /* Advantech PCI-1735U */
97 #define PCI1735_DI 0 /* R: Digital input 0-31 */
98 #define PCI1735_DO 0 /* W: Digital output 0-31 */
99 #define PCI1735_C8254 4 /* R/W: 8254 counter */
100 #define PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */
102 /* Advantech PCI-1736UP */
103 #define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */
104 #define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */
105 #define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
106 #define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for
108 #define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */
109 #define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */
110 #define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */
112 /* Advantech PCI-1739U */
113 #define PCI1739_DIO 0 /* R/W: begin of 8255 registers block */
114 #define PCI1739_ICR 32 /* W: Interrupt control register */
115 #define PCI1739_ISR 32 /* R: Interrupt status register */
116 #define PCI1739_BOARDID 8 /* R: Board I/D switch for 1739U */
118 /* Advantech PCI-1750 */
119 #define PCI1750_IDI 0 /* R: Isolated digital input 0-15 */
120 #define PCI1750_IDO 0 /* W: Isolated digital output 0-15 */
121 #define PCI1750_ICR 32 /* W: Interrupt control register */
122 #define PCI1750_ISR 32 /* R: Interrupt status register */
124 /* Advantech PCI-1751/3/3E */
125 #define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */
126 #define PCI1751_CNT 24 /* R/W: begin of 8254 registers block */
127 #define PCI1751_ICR 32 /* W: Interrupt control register */
128 #define PCI1751_ISR 32 /* R: Interrupt status register */
129 #define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */
130 #define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */
131 #define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */
132 #define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */
133 #define PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */
134 #define PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */
135 #define PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */
136 #define PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */
137 #define PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */
138 #define PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */
140 /* Advantech PCI-1752/4/6 */
141 #define PCI1752_IDO 0 /* R/W: Digital output 0-31 */
142 #define PCI1752_IDO2 4 /* R/W: Digital output 32-63 */
143 #define PCI1754_IDI 0 /* R: Digital input 0-31 */
144 #define PCI1754_IDI2 4 /* R: Digital input 32-64 */
145 #define PCI1756_IDI 0 /* R: Digital input 0-31 */
146 #define PCI1756_IDO 4 /* R/W: Digital output 0-31 */
147 #define PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */
148 #define PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */
149 #define PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */
150 #define PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */
151 #define PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */
152 #define PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */
154 /* Advantech PCI-1762 registers */
155 #define PCI1762_RO 0 /* R/W: Relays status/output */
156 #define PCI1762_IDI 2 /* R: Isolated input status */
157 #define PCI1762_BOARDID 4 /* R: Board I/D switch */
158 #define PCI1762_ICR 6 /* W: Interrupt control register */
159 #define PCI1762_ISR 6 /* R: Interrupt status register */
161 /* Advantech PCI-1760 registers */
162 #define OMB0 0x0c /* W: Mailbox outgoing registers */
166 #define IMB0 0x1c /* R: Mailbox incoming registers */
170 #define INTCSR0 0x38 /* R/W: Interrupt control registers */
175 /* PCI-1760 mailbox commands */
176 #define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actual
177 * DI status in IMB3 */
178 #define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */
179 #define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */
180 #define CMD_ReadCurrentStatus 0x07 /* Read the current status of the
181 * register in OMB0, result in IMB0 */
182 #define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in
184 #define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in
186 #define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in
188 #define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on
190 #define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on
192 #define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in
194 #define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in
195 * OMB0 to its reset values */
196 #define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow
197 * interrupts based on bits in OMB0 */
198 #define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value
199 * interrupts based on bits in OMB0 */
200 #define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0
201 * - rising, =1 - falling) */
202 #define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current
204 #define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value
206 #define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value
208 #define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value
210 #define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value
212 #define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value
214 #define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value
216 #define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value
218 #define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value
220 #define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value
222 #define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value
224 #define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value
226 #define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value
228 #define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value
230 #define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value
232 #define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value
234 #define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value
237 #define OMBCMD_RETRY 0x03 /* 3 times try request before error */
239 struct diosubd_data
{
240 int chans
; /* num of chans */
241 int addr
; /* PCI address ofset */
242 int regs
; /* number of registers to read or 8255
243 subdevices or 8254 chips */
244 unsigned int specflags
; /* addon subdevice flags */
247 struct dio_boardtype
{
248 const char *name
; /* board name */
249 int vendor_id
; /* vendor/device PCI ID */
251 int main_pci_region
; /* main I/O PCI region */
252 enum hw_cards_id cardtype
;
253 struct diosubd_data sdi
[MAX_DI_SUBDEVS
]; /* DI chans */
254 struct diosubd_data sdo
[MAX_DO_SUBDEVS
]; /* DO chans */
255 struct diosubd_data sdio
[MAX_DIO_SUBDEVG
]; /* DIO 8255 chans */
256 struct diosubd_data boardid
; /* card supports board ID switch */
257 struct diosubd_data s8254
[MAX_8254_SUBDEVS
]; /* 8254 subdevices */
258 enum hw_io_access io_access
;
261 static const struct dio_boardtype boardtypes
[] = {
262 {"pci1730", PCI_VENDOR_ID_ADVANTECH
, 0x1730, PCIDIO_MAINREG
,
264 { {16, PCI1730_DI
, 2, 0}, {16, PCI1730_IDI
, 2, 0} },
265 { {16, PCI1730_DO
, 2, 0}, {16, PCI1730_IDO
, 2, 0} },
266 { {0, 0, 0, 0}, {0, 0, 0, 0} },
267 {4, PCI173x_BOARDID
, 1, SDF_INTERNAL
},
270 {"pci1733", PCI_VENDOR_ID_ADVANTECH
, 0x1733, PCIDIO_MAINREG
,
272 { {0, 0, 0, 0}, {32, PCI1733_IDI
, 4, 0} },
273 { {0, 0, 0, 0}, {0, 0, 0, 0} },
274 { {0, 0, 0, 0}, {0, 0, 0, 0} },
275 {4, PCI173x_BOARDID
, 1, SDF_INTERNAL
},
278 {"pci1734", PCI_VENDOR_ID_ADVANTECH
, 0x1734, PCIDIO_MAINREG
,
280 { {0, 0, 0, 0}, {0, 0, 0, 0} },
281 { {0, 0, 0, 0}, {32, PCI1734_IDO
, 4, 0} },
282 { {0, 0, 0, 0}, {0, 0, 0, 0} },
283 {4, PCI173x_BOARDID
, 1, SDF_INTERNAL
},
286 {"pci1735", PCI_VENDOR_ID_ADVANTECH
, 0x1735, PCIDIO_MAINREG
,
288 { {32, PCI1735_DI
, 4, 0}, {0, 0, 0, 0} },
289 { {32, PCI1735_DO
, 4, 0}, {0, 0, 0, 0} },
290 { {0, 0, 0, 0}, {0, 0, 0, 0} },
291 { 4, PCI1735_BOARDID
, 1, SDF_INTERNAL
},
292 { {3, PCI1735_C8254
, 1, 0} },
294 {"pci1736", PCI_VENDOR_ID_ADVANTECH
, 0x1736, PCI1736_MAINREG
,
296 { {0, 0, 0, 0}, {16, PCI1736_IDI
, 2, 0} },
297 { {0, 0, 0, 0}, {16, PCI1736_IDO
, 2, 0} },
298 { {0, 0, 0, 0}, {0, 0, 0, 0} },
299 {4, PCI1736_BOARDID
, 1, SDF_INTERNAL
},
302 {"pci1739", PCI_VENDOR_ID_ADVANTECH
, 0x1739, PCIDIO_MAINREG
,
304 { {0, 0, 0, 0}, {0, 0, 0, 0} },
305 { {0, 0, 0, 0}, {0, 0, 0, 0} },
306 { {48, PCI1739_DIO
, 2, 0}, {0, 0, 0, 0} },
310 {"pci1750", PCI_VENDOR_ID_ADVANTECH
, 0x1750, PCIDIO_MAINREG
,
312 { {0, 0, 0, 0}, {16, PCI1750_IDI
, 2, 0} },
313 { {0, 0, 0, 0}, {16, PCI1750_IDO
, 2, 0} },
314 { {0, 0, 0, 0}, {0, 0, 0, 0} },
318 {"pci1751", PCI_VENDOR_ID_ADVANTECH
, 0x1751, PCIDIO_MAINREG
,
320 { {0, 0, 0, 0}, {0, 0, 0, 0} },
321 { {0, 0, 0, 0}, {0, 0, 0, 0} },
322 { {48, PCI1751_DIO
, 2, 0}, {0, 0, 0, 0} },
324 { {3, PCI1751_CNT
, 1, 0} },
326 {"pci1752", PCI_VENDOR_ID_ADVANTECH
, 0x1752, PCIDIO_MAINREG
,
328 { {0, 0, 0, 0}, {0, 0, 0, 0} },
329 { {32, PCI1752_IDO
, 2, 0}, {32, PCI1752_IDO2
, 2, 0} },
330 { {0, 0, 0, 0}, {0, 0, 0, 0} },
331 {4, PCI175x_BOARDID
, 1, SDF_INTERNAL
},
334 {"pci1753", PCI_VENDOR_ID_ADVANTECH
, 0x1753, PCIDIO_MAINREG
,
336 { {0, 0, 0, 0}, {0, 0, 0, 0} },
337 { {0, 0, 0, 0}, {0, 0, 0, 0} },
338 { {96, PCI1753_DIO
, 4, 0}, {0, 0, 0, 0} },
342 {"pci1753e", PCI_VENDOR_ID_ADVANTECH
, 0x1753, PCIDIO_MAINREG
,
344 { {0, 0, 0, 0}, {0, 0, 0, 0} },
345 { {0, 0, 0, 0}, {0, 0, 0, 0} },
346 { {96, PCI1753_DIO
, 4, 0}, {96, PCI1753E_DIO
, 4, 0} },
350 {"pci1754", PCI_VENDOR_ID_ADVANTECH
, 0x1754, PCIDIO_MAINREG
,
352 { {32, PCI1754_IDI
, 2, 0}, {32, PCI1754_IDI2
, 2, 0} },
353 { {0, 0, 0, 0}, {0, 0, 0, 0} },
354 { {0, 0, 0, 0}, {0, 0, 0, 0} },
355 {4, PCI175x_BOARDID
, 1, SDF_INTERNAL
},
358 {"pci1756", PCI_VENDOR_ID_ADVANTECH
, 0x1756, PCIDIO_MAINREG
,
360 { {0, 0, 0, 0}, {32, PCI1756_IDI
, 2, 0} },
361 { {0, 0, 0, 0}, {32, PCI1756_IDO
, 2, 0} },
362 { {0, 0, 0, 0}, {0, 0, 0, 0} },
363 {4, PCI175x_BOARDID
, 1, SDF_INTERNAL
},
366 {"pci1760", PCI_VENDOR_ID_ADVANTECH
, 0x1760, 0,
368 { {0, 0, 0, 0}, {0, 0, 0, 0} }, /* This card have own setup work */
369 { {0, 0, 0, 0}, {0, 0, 0, 0} },
370 { {0, 0, 0, 0}, {0, 0, 0, 0} },
374 {"pci1762", PCI_VENDOR_ID_ADVANTECH
, 0x1762, PCIDIO_MAINREG
,
376 { {0, 0, 0, 0}, {16, PCI1762_IDI
, 1, 0} },
377 { {0, 0, 0, 0}, {16, PCI1762_RO
, 1, 0} },
378 { {0, 0, 0, 0}, {0, 0, 0, 0} },
379 {4, PCI1762_BOARDID
, 1, SDF_INTERNAL
},
384 struct pci_dio_private
{
385 char valid
; /* card is usable */
386 char GlobalIrqEnabled
; /* 1= any IRQ source is enabled */
387 /* PCI-1760 specific data */
388 unsigned char IDICntEnable
; /* counter's counting enable status */
389 unsigned char IDICntOverEnable
; /* counter's overflow interrupts enable
391 unsigned char IDICntMatchEnable
; /* counter's match interrupts
393 unsigned char IDICntEdge
; /* counter's count edge value
394 * (bit=0 - rising, =1 - falling) */
395 unsigned short CntResValue
[8]; /* counters' reset value */
396 unsigned short CntMatchValue
[8]; /* counters' match interrupt value */
397 unsigned char IDIFiltersEn
; /* IDI's digital filters enable status */
398 unsigned char IDIPatMatchEn
; /* IDI's pattern match enable status */
399 unsigned char IDIPatMatchValue
; /* IDI's pattern match value */
400 unsigned short IDIFiltrLow
[8]; /* IDI's filter value low signal */
401 unsigned short IDIFiltrHigh
[8]; /* IDI's filter value high signal */
404 #define devpriv ((struct pci_dio_private *)dev->private)
405 #define this_board ((const struct dio_boardtype *)dev->board_ptr)
408 ==============================================================================
410 static int pci_dio_insn_bits_di_b(struct comedi_device
*dev
,
411 struct comedi_subdevice
*s
,
412 struct comedi_insn
*insn
, unsigned int *data
)
414 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
418 for (i
= 0; i
< d
->regs
; i
++)
419 data
[1] |= inb(dev
->iobase
+ d
->addr
+ i
) << (8 * i
);
426 ==============================================================================
428 static int pci_dio_insn_bits_di_w(struct comedi_device
*dev
,
429 struct comedi_subdevice
*s
,
430 struct comedi_insn
*insn
, unsigned int *data
)
432 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
436 for (i
= 0; i
< d
->regs
; i
++)
437 data
[1] |= inw(dev
->iobase
+ d
->addr
+ 2 * i
) << (16 * i
);
443 ==============================================================================
445 static int pci_dio_insn_bits_do_b(struct comedi_device
*dev
,
446 struct comedi_subdevice
*s
,
447 struct comedi_insn
*insn
, unsigned int *data
)
449 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
453 s
->state
&= ~data
[0];
454 s
->state
|= (data
[0] & data
[1]);
455 for (i
= 0; i
< d
->regs
; i
++)
456 outb((s
->state
>> (8 * i
)) & 0xff,
457 dev
->iobase
+ d
->addr
+ i
);
465 ==============================================================================
467 static int pci_dio_insn_bits_do_w(struct comedi_device
*dev
,
468 struct comedi_subdevice
*s
,
469 struct comedi_insn
*insn
, unsigned int *data
)
471 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
475 s
->state
&= ~data
[0];
476 s
->state
|= (data
[0] & data
[1]);
477 for (i
= 0; i
< d
->regs
; i
++)
478 outw((s
->state
>> (16 * i
)) & 0xffff,
479 dev
->iobase
+ d
->addr
+ 2 * i
);
487 ==============================================================================
489 static int pci_8254_insn_read(struct comedi_device
*dev
,
490 struct comedi_subdevice
*s
,
491 struct comedi_insn
*insn
, unsigned int *data
)
493 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
494 unsigned int chan
, chip
, chipchan
;
497 chan
= CR_CHAN(insn
->chanspec
); /* channel on subdevice */
498 chip
= chan
/ 3; /* chip on subdevice */
499 chipchan
= chan
- (3 * chip
); /* channel on chip on subdevice */
500 spin_lock_irqsave(&s
->spin_lock
, flags
);
501 data
[0] = i8254_read(dev
->iobase
+ d
->addr
+ (SIZE_8254
* chip
),
503 spin_unlock_irqrestore(&s
->spin_lock
, flags
);
508 ==============================================================================
510 static int pci_8254_insn_write(struct comedi_device
*dev
,
511 struct comedi_subdevice
*s
,
512 struct comedi_insn
*insn
, unsigned int *data
)
514 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
515 unsigned int chan
, chip
, chipchan
;
518 chan
= CR_CHAN(insn
->chanspec
); /* channel on subdevice */
519 chip
= chan
/ 3; /* chip on subdevice */
520 chipchan
= chan
- (3 * chip
); /* channel on chip on subdevice */
521 spin_lock_irqsave(&s
->spin_lock
, flags
);
522 i8254_write(dev
->iobase
+ d
->addr
+ (SIZE_8254
* chip
),
523 0, chipchan
, data
[0]);
524 spin_unlock_irqrestore(&s
->spin_lock
, flags
);
529 ==============================================================================
531 static int pci_8254_insn_config(struct comedi_device
*dev
,
532 struct comedi_subdevice
*s
,
533 struct comedi_insn
*insn
, unsigned int *data
)
535 const struct diosubd_data
*d
= (const struct diosubd_data
*)s
->private;
536 unsigned int chan
, chip
, chipchan
;
537 unsigned long iobase
;
541 chan
= CR_CHAN(insn
->chanspec
); /* channel on subdevice */
542 chip
= chan
/ 3; /* chip on subdevice */
543 chipchan
= chan
- (3 * chip
); /* channel on chip on subdevice */
544 iobase
= dev
->iobase
+ d
->addr
+ (SIZE_8254
* chip
);
545 spin_lock_irqsave(&s
->spin_lock
, flags
);
547 case INSN_CONFIG_SET_COUNTER_MODE
:
548 ret
= i8254_set_mode(iobase
, 0, chipchan
, data
[1]);
552 case INSN_CONFIG_8254_READ_STATUS
:
553 data
[1] = i8254_status(iobase
, 0, chipchan
);
559 spin_unlock_irqrestore(&s
->spin_lock
, flags
);
560 return ret
< 0 ? ret
: insn
->n
;
564 ==============================================================================
566 static int pci1760_unchecked_mbxrequest(struct comedi_device
*dev
,
567 unsigned char *omb
, unsigned char *imb
,
570 int cnt
, tout
, ok
= 0;
572 for (cnt
= 0; cnt
< repeats
; cnt
++) {
573 outb(omb
[0], dev
->iobase
+ OMB0
);
574 outb(omb
[1], dev
->iobase
+ OMB1
);
575 outb(omb
[2], dev
->iobase
+ OMB2
);
576 outb(omb
[3], dev
->iobase
+ OMB3
);
577 for (tout
= 0; tout
< 251; tout
++) {
578 imb
[2] = inb(dev
->iobase
+ IMB2
);
579 if (imb
[2] == omb
[2]) {
580 imb
[0] = inb(dev
->iobase
+ IMB0
);
581 imb
[1] = inb(dev
->iobase
+ IMB1
);
582 imb
[3] = inb(dev
->iobase
+ IMB3
);
592 comedi_error(dev
, "PCI-1760 mailbox request timeout!");
596 static int pci1760_clear_imb2(struct comedi_device
*dev
)
598 unsigned char omb
[4] = { 0x0, 0x0, CMD_ClearIMB2
, 0x0 };
599 unsigned char imb
[4];
600 /* check if imb2 is already clear */
601 if (inb(dev
->iobase
+ IMB2
) == CMD_ClearIMB2
)
603 return pci1760_unchecked_mbxrequest(dev
, omb
, imb
, OMBCMD_RETRY
);
606 static int pci1760_mbxrequest(struct comedi_device
*dev
,
607 unsigned char *omb
, unsigned char *imb
)
609 if (omb
[2] == CMD_ClearIMB2
) {
611 "bug! this function should not be used for CMD_ClearIMB2 command");
614 if (inb(dev
->iobase
+ IMB2
) == omb
[2]) {
616 retval
= pci1760_clear_imb2(dev
);
620 return pci1760_unchecked_mbxrequest(dev
, omb
, imb
, OMBCMD_RETRY
);
624 ==============================================================================
626 static int pci1760_insn_bits_di(struct comedi_device
*dev
,
627 struct comedi_subdevice
*s
,
628 struct comedi_insn
*insn
, unsigned int *data
)
630 data
[1] = inb(dev
->iobase
+ IMB3
);
636 ==============================================================================
638 static int pci1760_insn_bits_do(struct comedi_device
*dev
,
639 struct comedi_subdevice
*s
,
640 struct comedi_insn
*insn
, unsigned int *data
)
643 unsigned char omb
[4] = {
649 unsigned char imb
[4];
652 s
->state
&= ~data
[0];
653 s
->state
|= (data
[0] & data
[1]);
655 ret
= pci1760_mbxrequest(dev
, omb
, imb
);
665 ==============================================================================
667 static int pci1760_insn_cnt_read(struct comedi_device
*dev
,
668 struct comedi_subdevice
*s
,
669 struct comedi_insn
*insn
, unsigned int *data
)
672 unsigned char omb
[4] = {
673 CR_CHAN(insn
->chanspec
) & 0x07,
675 CMD_GetIDICntCurValue
,
678 unsigned char imb
[4];
680 for (n
= 0; n
< insn
->n
; n
++) {
681 ret
= pci1760_mbxrequest(dev
, omb
, imb
);
684 data
[n
] = (imb
[1] << 8) + imb
[0];
691 ==============================================================================
693 static int pci1760_insn_cnt_write(struct comedi_device
*dev
,
694 struct comedi_subdevice
*s
,
695 struct comedi_insn
*insn
, unsigned int *data
)
698 unsigned char chan
= CR_CHAN(insn
->chanspec
) & 0x07;
699 unsigned char bitmask
= 1 << chan
;
700 unsigned char omb
[4] = {
702 (data
[0] >> 8) & 0xff,
703 CMD_SetIDI0CntResetValue
+ chan
,
706 unsigned char imb
[4];
708 /* Set reset value if different */
709 if (devpriv
->CntResValue
[chan
] != (data
[0] & 0xffff)) {
710 ret
= pci1760_mbxrequest(dev
, omb
, imb
);
713 devpriv
->CntResValue
[chan
] = data
[0] & 0xffff;
716 omb
[0] = bitmask
; /* reset counter to it reset value */
717 omb
[2] = CMD_ResetIDICounters
;
718 ret
= pci1760_mbxrequest(dev
, omb
, imb
);
722 /* start counter if it don't run */
723 if (!(bitmask
& devpriv
->IDICntEnable
)) {
725 omb
[2] = CMD_EnableIDICounters
;
726 ret
= pci1760_mbxrequest(dev
, omb
, imb
);
729 devpriv
->IDICntEnable
|= bitmask
;
735 ==============================================================================
737 static int pci1760_reset(struct comedi_device
*dev
)
740 unsigned char omb
[4] = { 0x00, 0x00, 0x00, 0x00 };
741 unsigned char imb
[4];
743 outb(0, dev
->iobase
+ INTCSR0
); /* disable IRQ */
744 outb(0, dev
->iobase
+ INTCSR1
);
745 outb(0, dev
->iobase
+ INTCSR2
);
746 outb(0, dev
->iobase
+ INTCSR3
);
747 devpriv
->GlobalIrqEnabled
= 0;
750 omb
[2] = CMD_SetRelaysOutput
; /* reset relay outputs */
751 pci1760_mbxrequest(dev
, omb
, imb
);
754 omb
[2] = CMD_EnableIDICounters
; /* disable IDI up counters */
755 pci1760_mbxrequest(dev
, omb
, imb
);
756 devpriv
->IDICntEnable
= 0;
759 omb
[2] = CMD_OverflowIDICounters
; /* disable counters overflow
761 pci1760_mbxrequest(dev
, omb
, imb
);
762 devpriv
->IDICntOverEnable
= 0;
765 omb
[2] = CMD_MatchIntIDICounters
; /* disable counters match value
767 pci1760_mbxrequest(dev
, omb
, imb
);
768 devpriv
->IDICntMatchEnable
= 0;
772 for (i
= 0; i
< 8; i
++) { /* set IDI up counters match value */
773 omb
[2] = CMD_SetIDI0CntMatchValue
+ i
;
774 pci1760_mbxrequest(dev
, omb
, imb
);
775 devpriv
->CntMatchValue
[i
] = 0x8000;
780 for (i
= 0; i
< 8; i
++) { /* set IDI up counters reset value */
781 omb
[2] = CMD_SetIDI0CntResetValue
+ i
;
782 pci1760_mbxrequest(dev
, omb
, imb
);
783 devpriv
->CntResValue
[i
] = 0x0000;
787 omb
[2] = CMD_ResetIDICounters
; /* reset IDI up counters to reset
789 pci1760_mbxrequest(dev
, omb
, imb
);
792 omb
[2] = CMD_EdgeIDICounters
; /* set IDI up counters count edge */
793 pci1760_mbxrequest(dev
, omb
, imb
);
794 devpriv
->IDICntEdge
= 0x00;
797 omb
[2] = CMD_EnableIDIFilters
; /* disable all digital in filters */
798 pci1760_mbxrequest(dev
, omb
, imb
);
799 devpriv
->IDIFiltersEn
= 0x00;
802 omb
[2] = CMD_EnableIDIPatternMatch
; /* disable pattern matching */
803 pci1760_mbxrequest(dev
, omb
, imb
);
804 devpriv
->IDIPatMatchEn
= 0x00;
807 omb
[2] = CMD_SetIDIPatternMatch
; /* set pattern match value */
808 pci1760_mbxrequest(dev
, omb
, imb
);
809 devpriv
->IDIPatMatchValue
= 0x00;
815 ==============================================================================
817 static int pci_dio_reset(struct comedi_device
*dev
)
819 DPRINTK("adv_pci_dio EDBG: BGN: pci171x_reset(...)\n");
821 switch (this_board
->cardtype
) {
823 outb(0, dev
->iobase
+ PCI1730_DO
); /* clear outputs */
824 outb(0, dev
->iobase
+ PCI1730_DO
+ 1);
825 outb(0, dev
->iobase
+ PCI1730_IDO
);
826 outb(0, dev
->iobase
+ PCI1730_IDO
+ 1);
827 /* NO break there! */
829 /* disable interrupts */
830 outb(0, dev
->iobase
+ PCI1730_3_INT_EN
);
831 /* clear interrupts */
832 outb(0x0f, dev
->iobase
+ PCI1730_3_INT_CLR
);
833 /* set rising edge trigger */
834 outb(0, dev
->iobase
+ PCI1730_3_INT_RF
);
837 outb(0, dev
->iobase
+ PCI1734_IDO
); /* clear outputs */
838 outb(0, dev
->iobase
+ PCI1734_IDO
+ 1);
839 outb(0, dev
->iobase
+ PCI1734_IDO
+ 2);
840 outb(0, dev
->iobase
+ PCI1734_IDO
+ 3);
843 outb(0, dev
->iobase
+ PCI1735_DO
); /* clear outputs */
844 outb(0, dev
->iobase
+ PCI1735_DO
+ 1);
845 outb(0, dev
->iobase
+ PCI1735_DO
+ 2);
846 outb(0, dev
->iobase
+ PCI1735_DO
+ 3);
847 i8254_set_mode(dev
->iobase
+ PCI1735_C8254
, 0, 0, I8254_MODE0
);
848 i8254_set_mode(dev
->iobase
+ PCI1735_C8254
, 0, 1, I8254_MODE0
);
849 i8254_set_mode(dev
->iobase
+ PCI1735_C8254
, 0, 2, I8254_MODE0
);
853 outb(0, dev
->iobase
+ PCI1736_IDO
);
854 outb(0, dev
->iobase
+ PCI1736_IDO
+ 1);
855 /* disable interrupts */
856 outb(0, dev
->iobase
+ PCI1736_3_INT_EN
);
857 /* clear interrupts */
858 outb(0x0f, dev
->iobase
+ PCI1736_3_INT_CLR
);
859 /* set rising edge trigger */
860 outb(0, dev
->iobase
+ PCI1736_3_INT_RF
);
864 /* disable & clear interrupts */
865 outb(0x88, dev
->iobase
+ PCI1739_ICR
);
870 /* disable & clear interrupts */
871 outb(0x88, dev
->iobase
+ PCI1750_ICR
);
874 outw(0, dev
->iobase
+ PCI1752_6_CFC
); /* disable channel freeze
876 outw(0, dev
->iobase
+ PCI1752_IDO
); /* clear outputs */
877 outw(0, dev
->iobase
+ PCI1752_IDO
+ 2);
878 outw(0, dev
->iobase
+ PCI1752_IDO2
);
879 outw(0, dev
->iobase
+ PCI1752_IDO2
+ 2);
882 outb(0x88, dev
->iobase
+ PCI1753E_ICR0
); /* disable & clear
884 outb(0x80, dev
->iobase
+ PCI1753E_ICR1
);
885 outb(0x80, dev
->iobase
+ PCI1753E_ICR2
);
886 outb(0x80, dev
->iobase
+ PCI1753E_ICR3
);
887 /* NO break there! */
889 outb(0x88, dev
->iobase
+ PCI1753_ICR0
); /* disable & clear
891 outb(0x80, dev
->iobase
+ PCI1753_ICR1
);
892 outb(0x80, dev
->iobase
+ PCI1753_ICR2
);
893 outb(0x80, dev
->iobase
+ PCI1753_ICR3
);
896 outw(0x08, dev
->iobase
+ PCI1754_6_ICR0
); /* disable and clear
898 outw(0x08, dev
->iobase
+ PCI1754_6_ICR1
);
899 outw(0x08, dev
->iobase
+ PCI1754_ICR2
);
900 outw(0x08, dev
->iobase
+ PCI1754_ICR3
);
903 outw(0, dev
->iobase
+ PCI1752_6_CFC
); /* disable channel freeze
905 outw(0x08, dev
->iobase
+ PCI1754_6_ICR0
); /* disable and clear
907 outw(0x08, dev
->iobase
+ PCI1754_6_ICR1
);
908 outw(0, dev
->iobase
+ PCI1756_IDO
); /* clear outputs */
909 outw(0, dev
->iobase
+ PCI1756_IDO
+ 2);
915 outw(0x0101, dev
->iobase
+ PCI1762_ICR
); /* disable & clear
920 DPRINTK("adv_pci_dio EDBG: END: pci171x_reset(...)\n");
926 ==============================================================================
928 static int pci1760_attach(struct comedi_device
*dev
,
929 struct comedi_devconfig
*it
)
931 struct comedi_subdevice
*s
;
934 s
= dev
->subdevices
+ subdev
;
935 s
->type
= COMEDI_SUBD_DI
;
936 s
->subdev_flags
= SDF_READABLE
| SDF_GROUND
| SDF_COMMON
;
940 s
->range_table
= &range_digital
;
941 s
->insn_bits
= pci1760_insn_bits_di
;
944 s
= dev
->subdevices
+ subdev
;
945 s
->type
= COMEDI_SUBD_DO
;
946 s
->subdev_flags
= SDF_WRITABLE
| SDF_GROUND
| SDF_COMMON
;
950 s
->range_table
= &range_digital
;
952 s
->insn_bits
= pci1760_insn_bits_do
;
955 s
= dev
->subdevices
+ subdev
;
956 s
->type
= COMEDI_SUBD_TIMER
;
957 s
->subdev_flags
= SDF_WRITABLE
| SDF_LSAMPL
;
959 s
->maxdata
= 0xffffffff;
961 /* s->insn_config=pci1760_insn_pwm_cfg; */
964 s
= dev
->subdevices
+ subdev
;
965 s
->type
= COMEDI_SUBD_COUNTER
;
966 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
;
970 s
->insn_read
= pci1760_insn_cnt_read
;
971 s
->insn_write
= pci1760_insn_cnt_write
;
972 /* s->insn_config=pci1760_insn_cnt_cfg; */
979 ==============================================================================
981 static int pci_dio_add_di(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
982 const struct diosubd_data
*d
, int subdev
)
984 s
->type
= COMEDI_SUBD_DI
;
985 s
->subdev_flags
= SDF_READABLE
| SDF_GROUND
| SDF_COMMON
| d
->specflags
;
987 s
->subdev_flags
|= SDF_LSAMPL
;
988 s
->n_chan
= d
->chans
;
990 s
->len_chanlist
= d
->chans
;
991 s
->range_table
= &range_digital
;
992 switch (this_board
->io_access
) {
994 s
->insn_bits
= pci_dio_insn_bits_di_b
;
997 s
->insn_bits
= pci_dio_insn_bits_di_w
;
1000 s
->private = (void *)d
;
1006 ==============================================================================
1008 static int pci_dio_add_do(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
1009 const struct diosubd_data
*d
, int subdev
)
1011 s
->type
= COMEDI_SUBD_DO
;
1012 s
->subdev_flags
= SDF_WRITABLE
| SDF_GROUND
| SDF_COMMON
;
1014 s
->subdev_flags
|= SDF_LSAMPL
;
1015 s
->n_chan
= d
->chans
;
1017 s
->len_chanlist
= d
->chans
;
1018 s
->range_table
= &range_digital
;
1020 switch (this_board
->io_access
) {
1022 s
->insn_bits
= pci_dio_insn_bits_do_b
;
1025 s
->insn_bits
= pci_dio_insn_bits_do_w
;
1028 s
->private = (void *)d
;
1034 ==============================================================================
1036 static int pci_dio_add_8254(struct comedi_device
*dev
,
1037 struct comedi_subdevice
*s
,
1038 const struct diosubd_data
*d
, int subdev
)
1040 s
->type
= COMEDI_SUBD_COUNTER
;
1041 s
->subdev_flags
= SDF_WRITABLE
| SDF_READABLE
;
1042 s
->n_chan
= d
->chans
;
1044 s
->len_chanlist
= d
->chans
;
1045 s
->insn_read
= pci_8254_insn_read
;
1046 s
->insn_write
= pci_8254_insn_write
;
1047 s
->insn_config
= pci_8254_insn_config
;
1048 s
->private = (void *)d
;
1053 static struct pci_dev
*pci_dio_find_pci_dev(struct comedi_device
*dev
,
1054 struct comedi_devconfig
*it
)
1056 struct pci_dev
*pcidev
= NULL
;
1057 int bus
= it
->options
[0];
1058 int slot
= it
->options
[1];
1061 for_each_pci_dev(pcidev
) {
1063 if (bus
!= pcidev
->bus
->number
||
1064 slot
!= PCI_SLOT(pcidev
->devfn
))
1067 for (i
= 0; i
< ARRAY_SIZE(boardtypes
); ++i
) {
1068 if (boardtypes
[i
].vendor_id
!= pcidev
->vendor
)
1070 if (boardtypes
[i
].device_id
!= pcidev
->device
)
1072 dev
->board_ptr
= boardtypes
+ i
;
1076 dev_err(dev
->class_dev
,
1077 "No supported board found! (req. bus %d, slot %d)\n",
1082 static int pci_dio_attach(struct comedi_device
*dev
,
1083 struct comedi_devconfig
*it
)
1085 struct pci_dev
*pcidev
;
1086 struct comedi_subdevice
*s
;
1087 int ret
, subdev
, n_subdevices
, i
, j
;
1089 ret
= alloc_private(dev
, sizeof(struct pci_dio_private
));
1093 pcidev
= pci_dio_find_pci_dev(dev
, it
);
1096 comedi_set_hw_dev(dev
, &pcidev
->dev
);
1098 if (comedi_pci_enable(pcidev
, dev
->driver
->driver_name
)) {
1099 dev_err(dev
->class_dev
,
1100 "Error: Can't enable PCI device and request regions!\n");
1104 dev
->iobase
= pci_resource_start(pcidev
, this_board
->main_pci_region
);
1105 dev
->board_name
= this_board
->name
;
1107 if (this_board
->cardtype
== TYPE_PCI1760
) {
1108 n_subdevices
= 4; /* 8 IDI, 8 IDO, 2 PWM, 8 CNT */
1111 for (i
= 0; i
< MAX_DI_SUBDEVS
; i
++)
1112 if (this_board
->sdi
[i
].chans
)
1114 for (i
= 0; i
< MAX_DO_SUBDEVS
; i
++)
1115 if (this_board
->sdo
[i
].chans
)
1117 for (i
= 0; i
< MAX_DIO_SUBDEVG
; i
++)
1118 n_subdevices
+= this_board
->sdio
[i
].regs
;
1119 if (this_board
->boardid
.chans
)
1121 for (i
= 0; i
< MAX_8254_SUBDEVS
; i
++)
1122 if (this_board
->s8254
[i
].chans
)
1126 ret
= comedi_alloc_subdevices(dev
, n_subdevices
);
1131 for (i
= 0; i
< MAX_DI_SUBDEVS
; i
++)
1132 if (this_board
->sdi
[i
].chans
) {
1133 s
= dev
->subdevices
+ subdev
;
1134 pci_dio_add_di(dev
, s
, &this_board
->sdi
[i
], subdev
);
1138 for (i
= 0; i
< MAX_DO_SUBDEVS
; i
++)
1139 if (this_board
->sdo
[i
].chans
) {
1140 s
= dev
->subdevices
+ subdev
;
1141 pci_dio_add_do(dev
, s
, &this_board
->sdo
[i
], subdev
);
1145 for (i
= 0; i
< MAX_DIO_SUBDEVG
; i
++)
1146 for (j
= 0; j
< this_board
->sdio
[i
].regs
; j
++) {
1147 s
= dev
->subdevices
+ subdev
;
1148 subdev_8255_init(dev
, s
, NULL
,
1150 this_board
->sdio
[i
].addr
+
1155 if (this_board
->boardid
.chans
) {
1156 s
= dev
->subdevices
+ subdev
;
1157 s
->type
= COMEDI_SUBD_DI
;
1158 pci_dio_add_di(dev
, s
, &this_board
->boardid
, subdev
);
1162 for (i
= 0; i
< MAX_8254_SUBDEVS
; i
++)
1163 if (this_board
->s8254
[i
].chans
) {
1164 s
= dev
->subdevices
+ subdev
;
1165 pci_dio_add_8254(dev
, s
, &this_board
->s8254
[i
], subdev
);
1169 if (this_board
->cardtype
== TYPE_PCI1760
)
1170 pci1760_attach(dev
, it
);
1179 static void pci_dio_detach(struct comedi_device
*dev
)
1181 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
1183 struct comedi_subdevice
*s
;
1190 for (i
= 0; i
< MAX_DI_SUBDEVS
; i
++) {
1191 if (this_board
->sdi
[i
].chans
)
1194 for (i
= 0; i
< MAX_DO_SUBDEVS
; i
++) {
1195 if (this_board
->sdo
[i
].chans
)
1198 for (i
= 0; i
< MAX_DIO_SUBDEVG
; i
++) {
1199 for (j
= 0; j
< this_board
->sdio
[i
].regs
; j
++) {
1200 s
= dev
->subdevices
+ subdev
;
1201 subdev_8255_cleanup(dev
, s
);
1205 if (this_board
->boardid
.chans
)
1207 for (i
= 0; i
< MAX_8254_SUBDEVS
; i
++)
1208 if (this_board
->s8254
[i
].chans
)
1210 for (i
= 0; i
< dev
->n_subdevices
; i
++) {
1211 s
= dev
->subdevices
+ i
;
1217 comedi_pci_disable(pcidev
);
1218 pci_dev_put(pcidev
);
1222 static struct comedi_driver adv_pci_dio_driver
= {
1223 .driver_name
= "adv_pci_dio",
1224 .module
= THIS_MODULE
,
1225 .attach
= pci_dio_attach
,
1226 .detach
= pci_dio_detach
1229 static int __devinit
adv_pci_dio_pci_probe(struct pci_dev
*dev
,
1230 const struct pci_device_id
*ent
)
1232 return comedi_pci_auto_config(dev
, &adv_pci_dio_driver
);
1235 static void __devexit
adv_pci_dio_pci_remove(struct pci_dev
*dev
)
1237 comedi_pci_auto_unconfig(dev
);
1240 static DEFINE_PCI_DEVICE_TABLE(adv_pci_dio_pci_table
) = {
1241 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1730) },
1242 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1733) },
1243 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1734) },
1244 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1735) },
1245 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1736) },
1246 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1739) },
1247 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1750) },
1248 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1751) },
1249 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1752) },
1250 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1753) },
1251 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1754) },
1252 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1756) },
1253 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1760) },
1254 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH
, 0x1762) },
1257 MODULE_DEVICE_TABLE(pci
, adv_pci_dio_pci_table
);
1259 static struct pci_driver adv_pci_dio_pci_driver
= {
1260 .name
= "adv_pci_dio",
1261 .id_table
= adv_pci_dio_pci_table
,
1262 .probe
= adv_pci_dio_pci_probe
,
1263 .remove
= __devexit_p(adv_pci_dio_pci_remove
),
1265 module_comedi_pci_driver(adv_pci_dio_driver
, adv_pci_dio_pci_driver
);
1267 MODULE_AUTHOR("Comedi http://www.comedi.org");
1268 MODULE_DESCRIPTION("Comedi low-level driver");
1269 MODULE_LICENSE("GPL");