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[deliverable/linux.git] / drivers / staging / comedi / drivers / amplc_dio200.c
1 /*
2 comedi/drivers/amplc_dio200.c
3 Driver for Amplicon PC272E and PCI272 DIO boards.
4 (Support for other boards in Amplicon 200 series may be added at
5 a later date, e.g. PCI215.)
6
7 Copyright (C) 2005 MEV Ltd. <http://www.mev.co.uk/>
8
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25
26 */
27 /*
28 * Driver: amplc_dio200
29 * Description: Amplicon 200 Series Digital I/O
30 * Author: Ian Abbott <abbotti@mev.co.uk>
31 * Devices: [Amplicon] PC212E (pc212e), PC214E (pc214e), PC215E (pc215e),
32 * PCI215 (pci215), PCIe215 (pcie215), PC218E (pc218e), PCIe236 (pcie236),
33 * PC272E (pc272e), PCI272 (pci272), PCIe296 (pcie296)
34 * Updated: Wed, 24 Oct 2012 16:22:34 +0100
35 * Status: works
36 *
37 * Configuration options - PC212E, PC214E, PC215E, PC218E, PC272E:
38 * [0] - I/O port base address
39 * [1] - IRQ (optional, but commands won't work without it)
40 *
41 * Manual configuration of PCI(e) cards is not supported; they are configured
42 * automatically.
43 *
44 * Passing a zero for an option is the same as leaving it unspecified.
45 *
46 * SUBDEVICES
47 *
48 * PC212E PC214E PC215E/PCI215
49 * ------------- ------------- -------------
50 * Subdevices 6 4 5
51 * 0 PPI-X PPI-X PPI-X
52 * 1 CTR-Y1 PPI-Y PPI-Y
53 * 2 CTR-Y2 CTR-Z1* CTR-Z1
54 * 3 CTR-Z1 INTERRUPT* CTR-Z2
55 * 4 CTR-Z2 INTERRUPT
56 * 5 INTERRUPT
57 *
58 * PCIe215 PC218E PCIe236
59 * ------------- ------------- -------------
60 * Subdevices 8 7 8
61 * 0 PPI-X CTR-X1 PPI-X
62 * 1 UNUSED CTR-X2 UNUSED
63 * 2 PPI-Y CTR-Y1 UNUSED
64 * 3 UNUSED CTR-Y2 UNUSED
65 * 4 CTR-Z1 CTR-Z1 CTR-Z1
66 * 5 CTR-Z2 CTR-Z2 CTR-Z2
67 * 6 TIMER INTERRUPT TIMER
68 * 7 INTERRUPT INTERRUPT
69 *
70 * PC272E/PCI272 PCIe296
71 * ------------- -------------
72 * Subdevices 4 8
73 * 0 PPI-X PPI-X1
74 * 1 PPI-Y PPI-X2
75 * 2 PPI-Z PPI-Y1
76 * 3 INTERRUPT PPI-Y2
77 * 4 CTR-Z1
78 * 5 CTR-Z2
79 * 6 TIMER
80 * 7 INTERRUPT
81 *
82 * Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels
83 * are configurable as inputs or outputs in four groups:
84 *
85 * Port A - channels 0 to 7
86 * Port B - channels 8 to 15
87 * Port CL - channels 16 to 19
88 * Port CH - channels 20 to 23
89 *
90 * Only mode 0 of the 8255 chips is supported.
91 *
92 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
93 * channel is configured individually with INSN_CONFIG instructions. The
94 * specific type of configuration instruction is specified in data[0].
95 * Some configuration instructions expect an additional parameter in
96 * data[1]; others return a value in data[1]. The following configuration
97 * instructions are supported:
98 *
99 * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
100 * BCD/binary setting specified in data[1].
101 *
102 * INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the
103 * counter channel into data[1].
104 *
105 * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
106 * specified in data[1] (this is a hardware-specific value). Not
107 * supported on PC214E. For the other boards, valid clock sources are
108 * 0 to 7 as follows:
109 *
110 * 0. CLK n, the counter channel's dedicated CLK input from the SK1
111 * connector. (N.B. for other values, the counter channel's CLKn
112 * pin on the SK1 connector is an output!)
113 * 1. Internal 10 MHz clock.
114 * 2. Internal 1 MHz clock.
115 * 3. Internal 100 kHz clock.
116 * 4. Internal 10 kHz clock.
117 * 5. Internal 1 kHz clock.
118 * 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
119 * 7. Ext Clock, the counter chip's dedicated Ext Clock input from
120 * the SK1 connector. This pin is shared by all three counter
121 * channels on the chip.
122 *
123 * For the PCIe boards, clock sources in the range 0 to 31 are allowed
124 * and the following additional clock sources are defined:
125 *
126 * 8. HIGH logic level.
127 * 9. LOW logic level.
128 * 10. "Pattern present" signal.
129 * 11. Internal 20 MHz clock.
130 *
131 * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
132 * clock source in data[1]. For internal clock sources, data[2] is set
133 * to the period in ns.
134 *
135 * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
136 * specified in data[2] (this is a hardware-specific value). Not
137 * supported on PC214E. For the other boards, valid gate sources are 0
138 * to 7 as follows:
139 *
140 * 0. VCC (internal +5V d.c.), i.e. gate permanently enabled.
141 * 1. GND (internal 0V d.c.), i.e. gate permanently disabled.
142 * 2. GAT n, the counter channel's dedicated GAT input from the SK1
143 * connector. (N.B. for other values, the counter channel's GATn
144 * pin on the SK1 connector is an output!)
145 * 3. /OUT n-2, the inverted output of counter channel n-2 (see note
146 * 2 below).
147 * 4. Reserved.
148 * 5. Reserved.
149 * 6. Reserved.
150 * 7. Reserved.
151 *
152 * For the PCIe boards, gate sources in the range 0 to 31 are allowed;
153 * the following additional clock sources and clock sources 6 and 7 are
154 * (re)defined:
155 *
156 * 6. /GAT n, negated version of the counter channel's dedicated
157 * GAT input (negated version of gate source 2).
158 * 7. OUT n-2, the non-inverted output of counter channel n-2
159 * (negated version of gate source 3).
160 * 8. "Pattern present" signal, HIGH while pattern present.
161 * 9. "Pattern occurred" latched signal, latches HIGH when pattern
162 * occurs.
163 * 10. "Pattern gone away" latched signal, latches LOW when pattern
164 * goes away after it occurred.
165 * 11. Negated "pattern present" signal, LOW while pattern present
166 * (negated version of gate source 8).
167 * 12. Negated "pattern occurred" latched signal, latches LOW when
168 * pattern occurs (negated version of gate source 9).
169 * 13. Negated "pattern gone away" latched signal, latches LOW when
170 * pattern goes away after it occurred (negated version of gate
171 * source 10).
172 *
173 * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
174 * source in data[2].
175 *
176 * Clock and gate interconnection notes:
177 *
178 * 1. Clock source OUT n-1 is the output of the preceding channel on the
179 * same counter subdevice if n > 0, or the output of channel 2 on the
180 * preceding counter subdevice (see note 3) if n = 0.
181 *
182 * 2. Gate source /OUT n-2 is the inverted output of channel 0 on the
183 * same counter subdevice if n = 2, or the inverted output of channel n+1
184 * on the preceding counter subdevice (see note 3) if n < 2.
185 *
186 * 3. The counter subdevices are connected in a ring, so the highest
187 * counter subdevice precedes the lowest.
188 *
189 * The 'TIMER' subdevice is a free-running 32-bit timer subdevice.
190 *
191 * The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The
192 * digital inputs come from the interrupt status register. The number of
193 * channels matches the number of interrupt sources. The PC214E does not
194 * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
195 * below.
196 *
197 * INTERRUPT SOURCES
198 *
199 * PC212E PC214E PC215E/PCI215
200 * ------------- ------------- -------------
201 * Sources 6 1 6
202 * 0 PPI-X-C0 JUMPER-J5 PPI-X-C0
203 * 1 PPI-X-C3 PPI-X-C3
204 * 2 CTR-Y1-OUT1 PPI-Y-C0
205 * 3 CTR-Y2-OUT1 PPI-Y-C3
206 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1
207 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1
208 *
209 * PCIe215 PC218E PCIe236
210 * ------------- ------------- -------------
211 * Sources 6 6 6
212 * 0 PPI-X-C0 CTR-X1-OUT1 PPI-X-C0
213 * 1 PPI-X-C3 CTR-X2-OUT1 PPI-X-C3
214 * 2 PPI-Y-C0 CTR-Y1-OUT1 unused
215 * 3 PPI-Y-C3 CTR-Y2-OUT1 unused
216 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1
217 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1
218 *
219 * PC272E/PCI272 PCIe296
220 * ------------- -------------
221 * Sources 6 6
222 * 0 PPI-X-C0 PPI-X1-C0
223 * 1 PPI-X-C3 PPI-X1-C3
224 * 2 PPI-Y-C0 PPI-Y1-C0
225 * 3 PPI-Y-C3 PPI-Y1-C3
226 * 4 PPI-Z-C0 CTR-Z1-OUT1
227 * 5 PPI-Z-C3 CTR-Z2-OUT1
228 *
229 * When an interrupt source is enabled in the interrupt source enable
230 * register, a rising edge on the source signal latches the corresponding
231 * bit to 1 in the interrupt status register.
232 *
233 * When the interrupt status register value as a whole (actually, just the
234 * 6 least significant bits) goes from zero to non-zero, the board will
235 * generate an interrupt. For level-triggered hardware interrupts (PCI
236 * card), the interrupt will remain asserted until the interrupt status
237 * register is cleared to zero. For edge-triggered hardware interrupts
238 * (ISA card), no further interrupts will occur until the interrupt status
239 * register is cleared to zero. To clear a bit to zero in the interrupt
240 * status register, the corresponding interrupt source must be disabled
241 * in the interrupt source enable register (there is no separate interrupt
242 * clear register).
243 *
244 * The PC214E does not have an interrupt source enable register or an
245 * interrupt status register; its 'INTERRUPT' subdevice has a single
246 * channel and its interrupt source is selected by the position of jumper
247 * J5.
248 *
249 * COMMANDS
250 *
251 * The driver supports a read streaming acquisition command on the
252 * 'INTERRUPT' subdevice. The channel list selects the interrupt sources
253 * to be enabled. All channels will be sampled together (convert_src ==
254 * TRIG_NOW). The scan begins a short time after the hardware interrupt
255 * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
256 * scan_begin_arg == 0). The value read from the interrupt status register
257 * is packed into a short value, one bit per requested channel, in the
258 * order they appear in the channel list.
259 */
260
261 #include <linux/pci.h>
262 #include <linux/interrupt.h>
263 #include <linux/slab.h>
264
265 #include "../comedidev.h"
266
267 #include "comedi_fc.h"
268 #include "8253.h"
269
270 #define DIO200_DRIVER_NAME "amplc_dio200"
271
272 #define DO_ISA IS_ENABLED(CONFIG_COMEDI_AMPLC_DIO200_ISA)
273 #define DO_PCI IS_ENABLED(CONFIG_COMEDI_AMPLC_DIO200_PCI)
274
275 /* PCI IDs */
276 #define PCI_DEVICE_ID_AMPLICON_PCI272 0x000a
277 #define PCI_DEVICE_ID_AMPLICON_PCI215 0x000b
278 #define PCI_DEVICE_ID_AMPLICON_PCIE236 0x0011
279 #define PCI_DEVICE_ID_AMPLICON_PCIE215 0x0012
280 #define PCI_DEVICE_ID_AMPLICON_PCIE296 0x0014
281
282 /* 8255 control register bits */
283 #define CR_C_LO_IO 0x01
284 #define CR_B_IO 0x02
285 #define CR_B_MODE 0x04
286 #define CR_C_HI_IO 0x08
287 #define CR_A_IO 0x10
288 #define CR_A_MODE(a) ((a)<<5)
289 #define CR_CW 0x80
290
291 /* 200 series registers */
292 #define DIO200_IO_SIZE 0x20
293 #define DIO200_PCIE_IO_SIZE 0x4000
294 #define DIO200_XCLK_SCE 0x18 /* Group X clock selection register */
295 #define DIO200_YCLK_SCE 0x19 /* Group Y clock selection register */
296 #define DIO200_ZCLK_SCE 0x1a /* Group Z clock selection register */
297 #define DIO200_XGAT_SCE 0x1b /* Group X gate selection register */
298 #define DIO200_YGAT_SCE 0x1c /* Group Y gate selection register */
299 #define DIO200_ZGAT_SCE 0x1d /* Group Z gate selection register */
300 #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */
301 /* Extra registers for new PCIe boards */
302 #define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */
303 #define DIO200_VERSION 0x24 /* Hardware version register */
304 #define DIO200_TS_CONFIG 0x600 /* Timestamp timer config register */
305 #define DIO200_TS_COUNT 0x602 /* Timestamp timer count register */
306
307 /*
308 * Functions for constructing value for DIO_200_?CLK_SCE and
309 * DIO_200_?GAT_SCE registers:
310 *
311 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
312 * 'chan' is the channel: 0, 1 or 2.
313 * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards.
314 */
315 static unsigned char clk_gat_sce(unsigned int which, unsigned int chan,
316 unsigned int source)
317 {
318 return (which << 5) | (chan << 3) |
319 ((source & 030) << 3) | (source & 007);
320 }
321
322 static unsigned char clk_sce(unsigned int which, unsigned int chan,
323 unsigned int source)
324 {
325 return clk_gat_sce(which, chan, source);
326 }
327
328 static unsigned char gat_sce(unsigned int which, unsigned int chan,
329 unsigned int source)
330 {
331 return clk_gat_sce(which, chan, source);
332 }
333
334 /*
335 * Periods of the internal clock sources in nanoseconds.
336 */
337 static const unsigned int clock_period[32] = {
338 [1] = 100, /* 10 MHz */
339 [2] = 1000, /* 1 MHz */
340 [3] = 10000, /* 100 kHz */
341 [4] = 100000, /* 10 kHz */
342 [5] = 1000000, /* 1 kHz */
343 [11] = 50, /* 20 MHz (enhanced boards) */
344 /* clock sources 12 and later reserved for enhanced boards */
345 };
346
347 /*
348 * Timestamp timer configuration register (for new PCIe boards).
349 */
350 #define TS_CONFIG_RESET 0x100 /* Reset counter to zero. */
351 #define TS_CONFIG_CLK_SRC_MASK 0x0FF /* Clock source. */
352 #define TS_CONFIG_MAX_CLK_SRC 2 /* Maximum clock source value. */
353
354 /*
355 * Periods of the timestamp timer clock sources in nanoseconds.
356 */
357 static const unsigned int ts_clock_period[TS_CONFIG_MAX_CLK_SRC + 1] = {
358 1, /* 1 nanosecond (but with 20 ns granularity). */
359 1000, /* 1 microsecond. */
360 1000000, /* 1 millisecond. */
361 };
362
363 /*
364 * Register region.
365 */
366 enum dio200_regtype { no_regtype = 0, io_regtype, mmio_regtype };
367 struct dio200_region {
368 union {
369 unsigned long iobase; /* I/O base address */
370 unsigned char __iomem *membase; /* mapped MMIO base address */
371 } u;
372 enum dio200_regtype regtype;
373 };
374
375 /*
376 * Board descriptions.
377 */
378
379 enum dio200_bustype { isa_bustype, pci_bustype };
380
381 enum dio200_model {
382 pc212e_model,
383 pc214e_model,
384 pc215e_model, pci215_model, pcie215_model,
385 pc218e_model,
386 pcie236_model,
387 pc272e_model, pci272_model,
388 pcie296_model,
389 };
390
391 enum dio200_layout_idx {
392 #if DO_ISA
393 pc212_layout,
394 pc214_layout,
395 #endif
396 pc215_layout,
397 #if DO_ISA
398 pc218_layout,
399 #endif
400 pc272_layout,
401 #if DO_PCI
402 pcie215_layout,
403 pcie236_layout,
404 pcie296_layout,
405 #endif
406 };
407
408 struct dio200_board {
409 const char *name;
410 unsigned short devid;
411 enum dio200_bustype bustype;
412 enum dio200_model model;
413 enum dio200_layout_idx layout;
414 unsigned char mainbar;
415 unsigned char mainshift;
416 unsigned int mainsize;
417 };
418
419 #if DO_ISA
420 static const struct dio200_board dio200_isa_boards[] = {
421 {
422 .name = "pc212e",
423 .bustype = isa_bustype,
424 .model = pc212e_model,
425 .layout = pc212_layout,
426 .mainsize = DIO200_IO_SIZE,
427 },
428 {
429 .name = "pc214e",
430 .bustype = isa_bustype,
431 .model = pc214e_model,
432 .layout = pc214_layout,
433 .mainsize = DIO200_IO_SIZE,
434 },
435 {
436 .name = "pc215e",
437 .bustype = isa_bustype,
438 .model = pc215e_model,
439 .layout = pc215_layout,
440 .mainsize = DIO200_IO_SIZE,
441 },
442 {
443 .name = "pc218e",
444 .bustype = isa_bustype,
445 .model = pc218e_model,
446 .layout = pc218_layout,
447 .mainsize = DIO200_IO_SIZE,
448 },
449 {
450 .name = "pc272e",
451 .bustype = isa_bustype,
452 .model = pc272e_model,
453 .layout = pc272_layout,
454 .mainsize = DIO200_IO_SIZE,
455 },
456 };
457 #endif
458
459 #if DO_PCI
460 static const struct dio200_board dio200_pci_boards[] = {
461 {
462 .name = "pci215",
463 .devid = PCI_DEVICE_ID_AMPLICON_PCI215,
464 .bustype = pci_bustype,
465 .model = pci215_model,
466 .layout = pc215_layout,
467 .mainbar = 2,
468 .mainsize = DIO200_IO_SIZE,
469 },
470 {
471 .name = "pci272",
472 .devid = PCI_DEVICE_ID_AMPLICON_PCI272,
473 .bustype = pci_bustype,
474 .model = pci272_model,
475 .layout = pc272_layout,
476 .mainbar = 2,
477 .mainsize = DIO200_IO_SIZE,
478 },
479 {
480 .name = "pcie215",
481 .devid = PCI_DEVICE_ID_AMPLICON_PCIE215,
482 .bustype = pci_bustype,
483 .model = pcie215_model,
484 .layout = pcie215_layout,
485 .mainbar = 1,
486 .mainshift = 3,
487 .mainsize = DIO200_PCIE_IO_SIZE,
488 },
489 {
490 .name = "pcie236",
491 .devid = PCI_DEVICE_ID_AMPLICON_PCIE236,
492 .bustype = pci_bustype,
493 .model = pcie236_model,
494 .layout = pcie236_layout,
495 .mainbar = 1,
496 .mainshift = 3,
497 .mainsize = DIO200_PCIE_IO_SIZE,
498 },
499 {
500 .name = "pcie296",
501 .devid = PCI_DEVICE_ID_AMPLICON_PCIE296,
502 .bustype = pci_bustype,
503 .model = pcie296_model,
504 .layout = pcie296_layout,
505 .mainbar = 1,
506 .mainshift = 3,
507 .mainsize = DIO200_PCIE_IO_SIZE,
508 },
509 };
510 #endif
511
512 /*
513 * Layout descriptions - some ISA and PCI board descriptions share the same
514 * layout.
515 */
516
517 enum dio200_sdtype { sd_none, sd_intr, sd_8255, sd_8254, sd_timer };
518
519 #define DIO200_MAX_SUBDEVS 8
520 #define DIO200_MAX_ISNS 6
521
522 struct dio200_layout {
523 unsigned short n_subdevs; /* number of subdevices */
524 unsigned char sdtype[DIO200_MAX_SUBDEVS]; /* enum dio200_sdtype */
525 unsigned char sdinfo[DIO200_MAX_SUBDEVS]; /* depends on sdtype */
526 char has_int_sce; /* has interrupt enable/status register */
527 char has_clk_gat_sce; /* has clock/gate selection registers */
528 char has_enhancements; /* has enhanced features */
529 };
530
531 static const struct dio200_layout dio200_layouts[] = {
532 #if DO_ISA
533 [pc212_layout] = {
534 .n_subdevs = 6,
535 .sdtype = {sd_8255, sd_8254, sd_8254, sd_8254,
536 sd_8254,
537 sd_intr},
538 .sdinfo = {0x00, 0x08, 0x0C, 0x10, 0x14,
539 0x3F},
540 .has_int_sce = 1,
541 .has_clk_gat_sce = 1,
542 },
543 [pc214_layout] = {
544 .n_subdevs = 4,
545 .sdtype = {sd_8255, sd_8255, sd_8254,
546 sd_intr},
547 .sdinfo = {0x00, 0x08, 0x10, 0x01},
548 .has_int_sce = 0,
549 .has_clk_gat_sce = 0,
550 },
551 #endif
552 [pc215_layout] = {
553 .n_subdevs = 5,
554 .sdtype = {sd_8255, sd_8255, sd_8254,
555 sd_8254,
556 sd_intr},
557 .sdinfo = {0x00, 0x08, 0x10, 0x14, 0x3F},
558 .has_int_sce = 1,
559 .has_clk_gat_sce = 1,
560 },
561 #if DO_ISA
562 [pc218_layout] = {
563 .n_subdevs = 7,
564 .sdtype = {sd_8254, sd_8254, sd_8255, sd_8254,
565 sd_8254,
566 sd_intr},
567 .sdinfo = {0x00, 0x04, 0x08, 0x0C, 0x10,
568 0x14,
569 0x3F},
570 .has_int_sce = 1,
571 .has_clk_gat_sce = 1,
572 },
573 #endif
574 [pc272_layout] = {
575 .n_subdevs = 4,
576 .sdtype = {sd_8255, sd_8255, sd_8255,
577 sd_intr},
578 .sdinfo = {0x00, 0x08, 0x10, 0x3F},
579 .has_int_sce = 1,
580 .has_clk_gat_sce = 0,
581 },
582 #if DO_PCI
583 [pcie215_layout] = {
584 .n_subdevs = 8,
585 .sdtype = {sd_8255, sd_none, sd_8255, sd_none,
586 sd_8254, sd_8254, sd_timer, sd_intr},
587 .sdinfo = {0x00, 0x00, 0x08, 0x00,
588 0x10, 0x14, 0x00, 0x3F},
589 .has_int_sce = 1,
590 .has_clk_gat_sce = 1,
591 .has_enhancements = 1,
592 },
593 [pcie236_layout] = {
594 .n_subdevs = 8,
595 .sdtype = {sd_8255, sd_none, sd_none, sd_none,
596 sd_8254, sd_8254, sd_timer, sd_intr},
597 .sdinfo = {0x00, 0x00, 0x00, 0x00,
598 0x10, 0x14, 0x00, 0x3F},
599 .has_int_sce = 1,
600 .has_clk_gat_sce = 1,
601 .has_enhancements = 1,
602 },
603 [pcie296_layout] = {
604 .n_subdevs = 8,
605 .sdtype = {sd_8255, sd_8255, sd_8255, sd_8255,
606 sd_8254, sd_8254, sd_timer, sd_intr},
607 .sdinfo = {0x00, 0x04, 0x08, 0x0C,
608 0x10, 0x14, 0x00, 0x3F},
609 .has_int_sce = 1,
610 .has_clk_gat_sce = 1,
611 .has_enhancements = 1,
612 },
613 #endif
614 };
615
616 /* this structure is for data unique to this hardware driver. If
617 several hardware drivers keep similar information in this structure,
618 feel free to suggest moving the variable to the struct comedi_device struct.
619 */
620 struct dio200_private {
621 struct dio200_region io; /* Register region */
622 int intr_sd;
623 };
624
625 struct dio200_subdev_8254 {
626 unsigned int ofs; /* Counter base offset */
627 unsigned int clk_sce_ofs; /* CLK_SCE base address */
628 unsigned int gat_sce_ofs; /* GAT_SCE base address */
629 int which; /* Bit 5 of CLK_SCE or GAT_SCE */
630 unsigned int clock_src[3]; /* Current clock sources */
631 unsigned int gate_src[3]; /* Current gate sources */
632 spinlock_t spinlock;
633 };
634
635 struct dio200_subdev_8255 {
636 unsigned int ofs; /* DIO base offset */
637 };
638
639 struct dio200_subdev_intr {
640 unsigned int ofs;
641 spinlock_t spinlock;
642 int active;
643 unsigned int valid_isns;
644 unsigned int enabled_isns;
645 unsigned int stopcount;
646 int continuous;
647 };
648
649 static inline const struct dio200_layout *
650 dio200_board_layout(const struct dio200_board *board)
651 {
652 return &dio200_layouts[board->layout];
653 }
654
655 static inline const struct dio200_layout *
656 dio200_dev_layout(struct comedi_device *dev)
657 {
658 return dio200_board_layout(comedi_board(dev));
659 }
660
661 static inline bool is_pci_board(const struct dio200_board *board)
662 {
663 return DO_PCI && board->bustype == pci_bustype;
664 }
665
666 static inline bool is_isa_board(const struct dio200_board *board)
667 {
668 return DO_ISA && board->bustype == isa_bustype;
669 }
670
671 /*
672 * Read 8-bit register.
673 */
674 static unsigned char dio200_read8(struct comedi_device *dev,
675 unsigned int offset)
676 {
677 const struct dio200_board *thisboard = comedi_board(dev);
678 struct dio200_private *devpriv = dev->private;
679
680 offset <<= thisboard->mainshift;
681 if (devpriv->io.regtype == io_regtype)
682 return inb(devpriv->io.u.iobase + offset);
683 else
684 return readb(devpriv->io.u.membase + offset);
685 }
686
687 /*
688 * Write 8-bit register.
689 */
690 static void dio200_write8(struct comedi_device *dev, unsigned int offset,
691 unsigned char val)
692 {
693 const struct dio200_board *thisboard = comedi_board(dev);
694 struct dio200_private *devpriv = dev->private;
695
696 offset <<= thisboard->mainshift;
697 if (devpriv->io.regtype == io_regtype)
698 outb(val, devpriv->io.u.iobase + offset);
699 else
700 writeb(val, devpriv->io.u.membase + offset);
701 }
702
703 /*
704 * Read 32-bit register.
705 */
706 static unsigned int dio200_read32(struct comedi_device *dev,
707 unsigned int offset)
708 {
709 const struct dio200_board *thisboard = comedi_board(dev);
710 struct dio200_private *devpriv = dev->private;
711
712 offset <<= thisboard->mainshift;
713 if (devpriv->io.regtype == io_regtype)
714 return inl(devpriv->io.u.iobase + offset);
715 else
716 return readl(devpriv->io.u.membase + offset);
717 }
718
719 /*
720 * Write 32-bit register.
721 */
722 static void dio200_write32(struct comedi_device *dev, unsigned int offset,
723 unsigned int val)
724 {
725 const struct dio200_board *thisboard = comedi_board(dev);
726 struct dio200_private *devpriv = dev->private;
727
728 offset <<= thisboard->mainshift;
729 if (devpriv->io.regtype == io_regtype)
730 outl(val, devpriv->io.u.iobase + offset);
731 else
732 writel(val, devpriv->io.u.membase + offset);
733 }
734
735 /*
736 * This function looks for a board matching the supplied PCI device.
737 */
738 static const struct dio200_board *
739 dio200_find_pci_board(struct pci_dev *pci_dev)
740 {
741 unsigned int i;
742
743 for (i = 0; i < ARRAY_SIZE(dio200_pci_boards); i++)
744 if (pci_dev->device == dio200_pci_boards[i].devid)
745 return &dio200_pci_boards[i];
746 return NULL;
747 }
748
749 /*
750 * This function checks and requests an I/O region, reporting an error
751 * if there is a conflict.
752 */
753 static int
754 dio200_request_region(struct comedi_device *dev,
755 unsigned long from, unsigned long extent)
756 {
757 if (!from || !request_region(from, extent, DIO200_DRIVER_NAME)) {
758 dev_err(dev->class_dev, "I/O port conflict (%#lx,%lu)!\n",
759 from, extent);
760 return -EIO;
761 }
762 return 0;
763 }
764
765 /*
766 * 'insn_bits' function for an 'INTERRUPT' subdevice.
767 */
768 static int
769 dio200_subdev_intr_insn_bits(struct comedi_device *dev,
770 struct comedi_subdevice *s,
771 struct comedi_insn *insn, unsigned int *data)
772 {
773 const struct dio200_layout *layout = dio200_dev_layout(dev);
774 struct dio200_subdev_intr *subpriv = s->private;
775
776 if (layout->has_int_sce) {
777 /* Just read the interrupt status register. */
778 data[1] = dio200_read8(dev, subpriv->ofs) & subpriv->valid_isns;
779 } else {
780 /* No interrupt status register. */
781 data[0] = 0;
782 }
783
784 return insn->n;
785 }
786
787 /*
788 * Called to stop acquisition for an 'INTERRUPT' subdevice.
789 */
790 static void dio200_stop_intr(struct comedi_device *dev,
791 struct comedi_subdevice *s)
792 {
793 const struct dio200_layout *layout = dio200_dev_layout(dev);
794 struct dio200_subdev_intr *subpriv = s->private;
795
796 subpriv->active = 0;
797 subpriv->enabled_isns = 0;
798 if (layout->has_int_sce)
799 dio200_write8(dev, subpriv->ofs, 0);
800 }
801
802 /*
803 * Called to start acquisition for an 'INTERRUPT' subdevice.
804 */
805 static int dio200_start_intr(struct comedi_device *dev,
806 struct comedi_subdevice *s)
807 {
808 unsigned int n;
809 unsigned isn_bits;
810 const struct dio200_layout *layout = dio200_dev_layout(dev);
811 struct dio200_subdev_intr *subpriv = s->private;
812 struct comedi_cmd *cmd = &s->async->cmd;
813 int retval = 0;
814
815 if (!subpriv->continuous && subpriv->stopcount == 0) {
816 /* An empty acquisition! */
817 s->async->events |= COMEDI_CB_EOA;
818 subpriv->active = 0;
819 retval = 1;
820 } else {
821 /* Determine interrupt sources to enable. */
822 isn_bits = 0;
823 if (cmd->chanlist) {
824 for (n = 0; n < cmd->chanlist_len; n++)
825 isn_bits |= (1U << CR_CHAN(cmd->chanlist[n]));
826 }
827 isn_bits &= subpriv->valid_isns;
828 /* Enable interrupt sources. */
829 subpriv->enabled_isns = isn_bits;
830 if (layout->has_int_sce)
831 dio200_write8(dev, subpriv->ofs, isn_bits);
832 }
833
834 return retval;
835 }
836
837 /*
838 * Internal trigger function to start acquisition for an 'INTERRUPT' subdevice.
839 */
840 static int
841 dio200_inttrig_start_intr(struct comedi_device *dev, struct comedi_subdevice *s,
842 unsigned int trignum)
843 {
844 struct dio200_subdev_intr *subpriv;
845 unsigned long flags;
846 int event = 0;
847
848 if (trignum != 0)
849 return -EINVAL;
850
851 subpriv = s->private;
852
853 spin_lock_irqsave(&subpriv->spinlock, flags);
854 s->async->inttrig = NULL;
855 if (subpriv->active)
856 event = dio200_start_intr(dev, s);
857
858 spin_unlock_irqrestore(&subpriv->spinlock, flags);
859
860 if (event)
861 comedi_event(dev, s);
862
863 return 1;
864 }
865
866 /*
867 * This is called from the interrupt service routine to handle a read
868 * scan on an 'INTERRUPT' subdevice.
869 */
870 static int dio200_handle_read_intr(struct comedi_device *dev,
871 struct comedi_subdevice *s)
872 {
873 const struct dio200_layout *layout = dio200_dev_layout(dev);
874 struct dio200_subdev_intr *subpriv = s->private;
875 unsigned triggered;
876 unsigned intstat;
877 unsigned cur_enabled;
878 unsigned int oldevents;
879 unsigned long flags;
880
881 triggered = 0;
882
883 spin_lock_irqsave(&subpriv->spinlock, flags);
884 oldevents = s->async->events;
885 if (layout->has_int_sce) {
886 /*
887 * Collect interrupt sources that have triggered and disable
888 * them temporarily. Loop around until no extra interrupt
889 * sources have triggered, at which point, the valid part of
890 * the interrupt status register will read zero, clearing the
891 * cause of the interrupt.
892 *
893 * Mask off interrupt sources already seen to avoid infinite
894 * loop in case of misconfiguration.
895 */
896 cur_enabled = subpriv->enabled_isns;
897 while ((intstat = (dio200_read8(dev, subpriv->ofs) &
898 subpriv->valid_isns & ~triggered)) != 0) {
899 triggered |= intstat;
900 cur_enabled &= ~triggered;
901 dio200_write8(dev, subpriv->ofs, cur_enabled);
902 }
903 } else {
904 /*
905 * No interrupt status register. Assume the single interrupt
906 * source has triggered.
907 */
908 triggered = subpriv->enabled_isns;
909 }
910
911 if (triggered) {
912 /*
913 * Some interrupt sources have triggered and have been
914 * temporarily disabled to clear the cause of the interrupt.
915 *
916 * Reenable them NOW to minimize the time they are disabled.
917 */
918 cur_enabled = subpriv->enabled_isns;
919 if (layout->has_int_sce)
920 dio200_write8(dev, subpriv->ofs, cur_enabled);
921
922 if (subpriv->active) {
923 /*
924 * The command is still active.
925 *
926 * Ignore interrupt sources that the command isn't
927 * interested in (just in case there's a race
928 * condition).
929 */
930 if (triggered & subpriv->enabled_isns) {
931 /* Collect scan data. */
932 short val;
933 unsigned int n, ch, len;
934
935 val = 0;
936 len = s->async->cmd.chanlist_len;
937 for (n = 0; n < len; n++) {
938 ch = CR_CHAN(s->async->cmd.chanlist[n]);
939 if (triggered & (1U << ch))
940 val |= (1U << n);
941 }
942 /* Write the scan to the buffer. */
943 if (comedi_buf_put(s->async, val)) {
944 s->async->events |= (COMEDI_CB_BLOCK |
945 COMEDI_CB_EOS);
946 } else {
947 /* Error! Stop acquisition. */
948 dio200_stop_intr(dev, s);
949 s->async->events |= COMEDI_CB_ERROR
950 | COMEDI_CB_OVERFLOW;
951 comedi_error(dev, "buffer overflow");
952 }
953
954 /* Check for end of acquisition. */
955 if (!subpriv->continuous) {
956 /* stop_src == TRIG_COUNT */
957 if (subpriv->stopcount > 0) {
958 subpriv->stopcount--;
959 if (subpriv->stopcount == 0) {
960 s->async->events |=
961 COMEDI_CB_EOA;
962 dio200_stop_intr(dev,
963 s);
964 }
965 }
966 }
967 }
968 }
969 }
970 spin_unlock_irqrestore(&subpriv->spinlock, flags);
971
972 if (oldevents != s->async->events)
973 comedi_event(dev, s);
974
975 return (triggered != 0);
976 }
977
978 /*
979 * 'cancel' function for an 'INTERRUPT' subdevice.
980 */
981 static int dio200_subdev_intr_cancel(struct comedi_device *dev,
982 struct comedi_subdevice *s)
983 {
984 struct dio200_subdev_intr *subpriv = s->private;
985 unsigned long flags;
986
987 spin_lock_irqsave(&subpriv->spinlock, flags);
988 if (subpriv->active)
989 dio200_stop_intr(dev, s);
990
991 spin_unlock_irqrestore(&subpriv->spinlock, flags);
992
993 return 0;
994 }
995
996 /*
997 * 'do_cmdtest' function for an 'INTERRUPT' subdevice.
998 */
999 static int
1000 dio200_subdev_intr_cmdtest(struct comedi_device *dev,
1001 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1002 {
1003 int err = 0;
1004
1005 /* Step 1 : check if triggers are trivially valid */
1006
1007 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
1008 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
1009 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
1010 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1011 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
1012
1013 if (err)
1014 return 1;
1015
1016 /* Step 2a : make sure trigger sources are unique */
1017
1018 err |= cfc_check_trigger_is_unique(cmd->start_src);
1019 err |= cfc_check_trigger_is_unique(cmd->stop_src);
1020
1021 /* Step 2b : and mutually compatible */
1022
1023 if (err)
1024 return 2;
1025
1026 /* Step 3: check if arguments are trivially valid */
1027
1028 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
1029 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
1030 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
1031 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
1032
1033 switch (cmd->stop_src) {
1034 case TRIG_COUNT:
1035 /* any count allowed */
1036 break;
1037 case TRIG_NONE:
1038 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
1039 break;
1040 default:
1041 break;
1042 }
1043
1044 if (err)
1045 return 3;
1046
1047 /* step 4: fix up any arguments */
1048
1049 /* if (err) return 4; */
1050
1051 return 0;
1052 }
1053
1054 /*
1055 * 'do_cmd' function for an 'INTERRUPT' subdevice.
1056 */
1057 static int dio200_subdev_intr_cmd(struct comedi_device *dev,
1058 struct comedi_subdevice *s)
1059 {
1060 struct comedi_cmd *cmd = &s->async->cmd;
1061 struct dio200_subdev_intr *subpriv = s->private;
1062 unsigned long flags;
1063 int event = 0;
1064
1065 spin_lock_irqsave(&subpriv->spinlock, flags);
1066 subpriv->active = 1;
1067
1068 /* Set up end of acquisition. */
1069 switch (cmd->stop_src) {
1070 case TRIG_COUNT:
1071 subpriv->continuous = 0;
1072 subpriv->stopcount = cmd->stop_arg;
1073 break;
1074 default:
1075 /* TRIG_NONE */
1076 subpriv->continuous = 1;
1077 subpriv->stopcount = 0;
1078 break;
1079 }
1080
1081 /* Set up start of acquisition. */
1082 switch (cmd->start_src) {
1083 case TRIG_INT:
1084 s->async->inttrig = dio200_inttrig_start_intr;
1085 break;
1086 default:
1087 /* TRIG_NOW */
1088 event = dio200_start_intr(dev, s);
1089 break;
1090 }
1091 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1092
1093 if (event)
1094 comedi_event(dev, s);
1095
1096 return 0;
1097 }
1098
1099 /*
1100 * This function initializes an 'INTERRUPT' subdevice.
1101 */
1102 static int
1103 dio200_subdev_intr_init(struct comedi_device *dev, struct comedi_subdevice *s,
1104 unsigned int offset, unsigned valid_isns)
1105 {
1106 const struct dio200_layout *layout = dio200_dev_layout(dev);
1107 struct dio200_subdev_intr *subpriv;
1108
1109 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1110 if (!subpriv)
1111 return -ENOMEM;
1112
1113 subpriv->ofs = offset;
1114 subpriv->valid_isns = valid_isns;
1115 spin_lock_init(&subpriv->spinlock);
1116
1117 if (layout->has_int_sce)
1118 /* Disable interrupt sources. */
1119 dio200_write8(dev, subpriv->ofs, 0);
1120
1121 s->private = subpriv;
1122 s->type = COMEDI_SUBD_DI;
1123 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
1124 if (layout->has_int_sce) {
1125 s->n_chan = DIO200_MAX_ISNS;
1126 s->len_chanlist = DIO200_MAX_ISNS;
1127 } else {
1128 /* No interrupt source register. Support single channel. */
1129 s->n_chan = 1;
1130 s->len_chanlist = 1;
1131 }
1132 s->range_table = &range_digital;
1133 s->maxdata = 1;
1134 s->insn_bits = dio200_subdev_intr_insn_bits;
1135 s->do_cmdtest = dio200_subdev_intr_cmdtest;
1136 s->do_cmd = dio200_subdev_intr_cmd;
1137 s->cancel = dio200_subdev_intr_cancel;
1138
1139 return 0;
1140 }
1141
1142 /*
1143 * This function cleans up an 'INTERRUPT' subdevice.
1144 */
1145 static void
1146 dio200_subdev_intr_cleanup(struct comedi_device *dev,
1147 struct comedi_subdevice *s)
1148 {
1149 struct dio200_subdev_intr *subpriv = s->private;
1150 kfree(subpriv);
1151 }
1152
1153 /*
1154 * Interrupt service routine.
1155 */
1156 static irqreturn_t dio200_interrupt(int irq, void *d)
1157 {
1158 struct comedi_device *dev = d;
1159 struct dio200_private *devpriv = dev->private;
1160 struct comedi_subdevice *s;
1161 int handled;
1162
1163 if (!dev->attached)
1164 return IRQ_NONE;
1165
1166 if (devpriv->intr_sd >= 0) {
1167 s = &dev->subdevices[devpriv->intr_sd];
1168 handled = dio200_handle_read_intr(dev, s);
1169 } else {
1170 handled = 0;
1171 }
1172
1173 return IRQ_RETVAL(handled);
1174 }
1175
1176 /*
1177 * Read an '8254' counter subdevice channel.
1178 */
1179 static unsigned int
1180 dio200_subdev_8254_read_chan(struct comedi_device *dev,
1181 struct comedi_subdevice *s, unsigned int chan)
1182 {
1183 struct dio200_subdev_8254 *subpriv = s->private;
1184 unsigned int val;
1185
1186 /* latch counter */
1187 val = chan << 6;
1188 dio200_write8(dev, subpriv->ofs + i8254_control_reg, val);
1189 /* read lsb, msb */
1190 val = dio200_read8(dev, subpriv->ofs + chan);
1191 val += dio200_read8(dev, subpriv->ofs + chan) << 8;
1192 return val;
1193 }
1194
1195 /*
1196 * Write an '8254' subdevice channel.
1197 */
1198 static void
1199 dio200_subdev_8254_write_chan(struct comedi_device *dev,
1200 struct comedi_subdevice *s, unsigned int chan,
1201 unsigned int count)
1202 {
1203 struct dio200_subdev_8254 *subpriv = s->private;
1204
1205 /* write lsb, msb */
1206 dio200_write8(dev, subpriv->ofs + chan, count & 0xff);
1207 dio200_write8(dev, subpriv->ofs + chan, (count >> 8) & 0xff);
1208 }
1209
1210 /*
1211 * Set mode of an '8254' subdevice channel.
1212 */
1213 static void
1214 dio200_subdev_8254_set_mode(struct comedi_device *dev,
1215 struct comedi_subdevice *s, unsigned int chan,
1216 unsigned int mode)
1217 {
1218 struct dio200_subdev_8254 *subpriv = s->private;
1219 unsigned int byte;
1220
1221 byte = chan << 6;
1222 byte |= 0x30; /* access order: lsb, msb */
1223 byte |= (mode & 0xf); /* counter mode and BCD|binary */
1224 dio200_write8(dev, subpriv->ofs + i8254_control_reg, byte);
1225 }
1226
1227 /*
1228 * Read status byte of an '8254' counter subdevice channel.
1229 */
1230 static unsigned int
1231 dio200_subdev_8254_status(struct comedi_device *dev,
1232 struct comedi_subdevice *s, unsigned int chan)
1233 {
1234 struct dio200_subdev_8254 *subpriv = s->private;
1235
1236 /* latch status */
1237 dio200_write8(dev, subpriv->ofs + i8254_control_reg,
1238 0xe0 | (2 << chan));
1239 /* read status */
1240 return dio200_read8(dev, subpriv->ofs + chan);
1241 }
1242
1243 /*
1244 * Handle 'insn_read' for an '8254' counter subdevice.
1245 */
1246 static int
1247 dio200_subdev_8254_read(struct comedi_device *dev, struct comedi_subdevice *s,
1248 struct comedi_insn *insn, unsigned int *data)
1249 {
1250 struct dio200_subdev_8254 *subpriv = s->private;
1251 int chan = CR_CHAN(insn->chanspec);
1252 unsigned int n;
1253 unsigned long flags;
1254
1255 for (n = 0; n < insn->n; n++) {
1256 spin_lock_irqsave(&subpriv->spinlock, flags);
1257 data[n] = dio200_subdev_8254_read_chan(dev, s, chan);
1258 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1259 }
1260 return insn->n;
1261 }
1262
1263 /*
1264 * Handle 'insn_write' for an '8254' counter subdevice.
1265 */
1266 static int
1267 dio200_subdev_8254_write(struct comedi_device *dev, struct comedi_subdevice *s,
1268 struct comedi_insn *insn, unsigned int *data)
1269 {
1270 struct dio200_subdev_8254 *subpriv = s->private;
1271 int chan = CR_CHAN(insn->chanspec);
1272 unsigned int n;
1273 unsigned long flags;
1274
1275 for (n = 0; n < insn->n; n++) {
1276 spin_lock_irqsave(&subpriv->spinlock, flags);
1277 dio200_subdev_8254_write_chan(dev, s, chan, data[n]);
1278 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1279 }
1280 return insn->n;
1281 }
1282
1283 /*
1284 * Set gate source for an '8254' counter subdevice channel.
1285 */
1286 static int
1287 dio200_subdev_8254_set_gate_src(struct comedi_device *dev,
1288 struct comedi_subdevice *s,
1289 unsigned int counter_number,
1290 unsigned int gate_src)
1291 {
1292 const struct dio200_layout *layout = dio200_dev_layout(dev);
1293 struct dio200_subdev_8254 *subpriv = s->private;
1294 unsigned char byte;
1295
1296 if (!layout->has_clk_gat_sce)
1297 return -1;
1298 if (counter_number > 2)
1299 return -1;
1300 if (gate_src > (layout->has_enhancements ? 31 : 7))
1301 return -1;
1302
1303 subpriv->gate_src[counter_number] = gate_src;
1304 byte = gat_sce(subpriv->which, counter_number, gate_src);
1305 dio200_write8(dev, subpriv->gat_sce_ofs, byte);
1306
1307 return 0;
1308 }
1309
1310 /*
1311 * Get gate source for an '8254' counter subdevice channel.
1312 */
1313 static int
1314 dio200_subdev_8254_get_gate_src(struct comedi_device *dev,
1315 struct comedi_subdevice *s,
1316 unsigned int counter_number)
1317 {
1318 const struct dio200_layout *layout = dio200_dev_layout(dev);
1319 struct dio200_subdev_8254 *subpriv = s->private;
1320
1321 if (!layout->has_clk_gat_sce)
1322 return -1;
1323 if (counter_number > 2)
1324 return -1;
1325
1326 return subpriv->gate_src[counter_number];
1327 }
1328
1329 /*
1330 * Set clock source for an '8254' counter subdevice channel.
1331 */
1332 static int
1333 dio200_subdev_8254_set_clock_src(struct comedi_device *dev,
1334 struct comedi_subdevice *s,
1335 unsigned int counter_number,
1336 unsigned int clock_src)
1337 {
1338 const struct dio200_layout *layout = dio200_dev_layout(dev);
1339 struct dio200_subdev_8254 *subpriv = s->private;
1340 unsigned char byte;
1341
1342 if (!layout->has_clk_gat_sce)
1343 return -1;
1344 if (counter_number > 2)
1345 return -1;
1346 if (clock_src > (layout->has_enhancements ? 31 : 7))
1347 return -1;
1348
1349 subpriv->clock_src[counter_number] = clock_src;
1350 byte = clk_sce(subpriv->which, counter_number, clock_src);
1351 dio200_write8(dev, subpriv->clk_sce_ofs, byte);
1352
1353 return 0;
1354 }
1355
1356 /*
1357 * Get clock source for an '8254' counter subdevice channel.
1358 */
1359 static int
1360 dio200_subdev_8254_get_clock_src(struct comedi_device *dev,
1361 struct comedi_subdevice *s,
1362 unsigned int counter_number,
1363 unsigned int *period_ns)
1364 {
1365 const struct dio200_layout *layout = dio200_dev_layout(dev);
1366 struct dio200_subdev_8254 *subpriv = s->private;
1367 unsigned clock_src;
1368
1369 if (!layout->has_clk_gat_sce)
1370 return -1;
1371 if (counter_number > 2)
1372 return -1;
1373
1374 clock_src = subpriv->clock_src[counter_number];
1375 *period_ns = clock_period[clock_src];
1376 return clock_src;
1377 }
1378
1379 /*
1380 * Handle 'insn_config' for an '8254' counter subdevice.
1381 */
1382 static int
1383 dio200_subdev_8254_config(struct comedi_device *dev, struct comedi_subdevice *s,
1384 struct comedi_insn *insn, unsigned int *data)
1385 {
1386 struct dio200_subdev_8254 *subpriv = s->private;
1387 int ret = 0;
1388 int chan = CR_CHAN(insn->chanspec);
1389 unsigned long flags;
1390
1391 spin_lock_irqsave(&subpriv->spinlock, flags);
1392 switch (data[0]) {
1393 case INSN_CONFIG_SET_COUNTER_MODE:
1394 if (data[1] > (I8254_MODE5 | I8254_BINARY))
1395 ret = -EINVAL;
1396 else
1397 dio200_subdev_8254_set_mode(dev, s, chan, data[1]);
1398 break;
1399 case INSN_CONFIG_8254_READ_STATUS:
1400 data[1] = dio200_subdev_8254_status(dev, s, chan);
1401 break;
1402 case INSN_CONFIG_SET_GATE_SRC:
1403 ret = dio200_subdev_8254_set_gate_src(dev, s, chan, data[2]);
1404 if (ret < 0)
1405 ret = -EINVAL;
1406 break;
1407 case INSN_CONFIG_GET_GATE_SRC:
1408 ret = dio200_subdev_8254_get_gate_src(dev, s, chan);
1409 if (ret < 0) {
1410 ret = -EINVAL;
1411 break;
1412 }
1413 data[2] = ret;
1414 break;
1415 case INSN_CONFIG_SET_CLOCK_SRC:
1416 ret = dio200_subdev_8254_set_clock_src(dev, s, chan, data[1]);
1417 if (ret < 0)
1418 ret = -EINVAL;
1419 break;
1420 case INSN_CONFIG_GET_CLOCK_SRC:
1421 ret = dio200_subdev_8254_get_clock_src(dev, s, chan, &data[2]);
1422 if (ret < 0) {
1423 ret = -EINVAL;
1424 break;
1425 }
1426 data[1] = ret;
1427 break;
1428 default:
1429 ret = -EINVAL;
1430 break;
1431 }
1432 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1433 return ret < 0 ? ret : insn->n;
1434 }
1435
1436 /*
1437 * This function initializes an '8254' counter subdevice.
1438 */
1439 static int
1440 dio200_subdev_8254_init(struct comedi_device *dev, struct comedi_subdevice *s,
1441 unsigned int offset)
1442 {
1443 const struct dio200_layout *layout = dio200_dev_layout(dev);
1444 struct dio200_subdev_8254 *subpriv;
1445 unsigned int chan;
1446
1447 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1448 if (!subpriv)
1449 return -ENOMEM;
1450
1451 s->private = subpriv;
1452 s->type = COMEDI_SUBD_COUNTER;
1453 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1454 s->n_chan = 3;
1455 s->maxdata = 0xFFFF;
1456 s->insn_read = dio200_subdev_8254_read;
1457 s->insn_write = dio200_subdev_8254_write;
1458 s->insn_config = dio200_subdev_8254_config;
1459
1460 spin_lock_init(&subpriv->spinlock);
1461 subpriv->ofs = offset;
1462 if (layout->has_clk_gat_sce) {
1463 /* Derive CLK_SCE and GAT_SCE register offsets from
1464 * 8254 offset. */
1465 subpriv->clk_sce_ofs = DIO200_XCLK_SCE + (offset >> 3);
1466 subpriv->gat_sce_ofs = DIO200_XGAT_SCE + (offset >> 3);
1467 subpriv->which = (offset >> 2) & 1;
1468 }
1469
1470 /* Initialize channels. */
1471 for (chan = 0; chan < 3; chan++) {
1472 dio200_subdev_8254_set_mode(dev, s, chan,
1473 I8254_MODE0 | I8254_BINARY);
1474 if (layout->has_clk_gat_sce) {
1475 /* Gate source 0 is VCC (logic 1). */
1476 dio200_subdev_8254_set_gate_src(dev, s, chan, 0);
1477 /* Clock source 0 is the dedicated clock input. */
1478 dio200_subdev_8254_set_clock_src(dev, s, chan, 0);
1479 }
1480 }
1481
1482 return 0;
1483 }
1484
1485 /*
1486 * This function cleans up an '8254' counter subdevice.
1487 */
1488 static void
1489 dio200_subdev_8254_cleanup(struct comedi_device *dev,
1490 struct comedi_subdevice *s)
1491 {
1492 struct dio200_subdev_intr *subpriv = s->private;
1493 kfree(subpriv);
1494 }
1495
1496 /*
1497 * This function sets I/O directions for an '8255' DIO subdevice.
1498 */
1499 static void dio200_subdev_8255_set_dir(struct comedi_device *dev,
1500 struct comedi_subdevice *s)
1501 {
1502 struct dio200_subdev_8255 *subpriv = s->private;
1503 int config;
1504
1505 config = CR_CW;
1506 /* 1 in io_bits indicates output, 1 in config indicates input */
1507 if (!(s->io_bits & 0x0000ff))
1508 config |= CR_A_IO;
1509 if (!(s->io_bits & 0x00ff00))
1510 config |= CR_B_IO;
1511 if (!(s->io_bits & 0x0f0000))
1512 config |= CR_C_LO_IO;
1513 if (!(s->io_bits & 0xf00000))
1514 config |= CR_C_HI_IO;
1515 dio200_write8(dev, subpriv->ofs + 3, config);
1516 }
1517
1518 /*
1519 * Handle 'insn_bits' for an '8255' DIO subdevice.
1520 */
1521 static int dio200_subdev_8255_bits(struct comedi_device *dev,
1522 struct comedi_subdevice *s,
1523 struct comedi_insn *insn, unsigned int *data)
1524 {
1525 struct dio200_subdev_8255 *subpriv = s->private;
1526
1527 if (data[0]) {
1528 s->state &= ~data[0];
1529 s->state |= (data[0] & data[1]);
1530 if (data[0] & 0xff)
1531 dio200_write8(dev, subpriv->ofs, s->state & 0xff);
1532 if (data[0] & 0xff00)
1533 dio200_write8(dev, subpriv->ofs + 1,
1534 (s->state >> 8) & 0xff);
1535 if (data[0] & 0xff0000)
1536 dio200_write8(dev, subpriv->ofs + 2,
1537 (s->state >> 16) & 0xff);
1538 }
1539 data[1] = dio200_read8(dev, subpriv->ofs);
1540 data[1] |= dio200_read8(dev, subpriv->ofs + 1) << 8;
1541 data[1] |= dio200_read8(dev, subpriv->ofs + 2) << 16;
1542 return 2;
1543 }
1544
1545 /*
1546 * Handle 'insn_config' for an '8255' DIO subdevice.
1547 */
1548 static int dio200_subdev_8255_config(struct comedi_device *dev,
1549 struct comedi_subdevice *s,
1550 struct comedi_insn *insn,
1551 unsigned int *data)
1552 {
1553 unsigned int mask;
1554 unsigned int bits;
1555
1556 mask = 1 << CR_CHAN(insn->chanspec);
1557 if (mask & 0x0000ff)
1558 bits = 0x0000ff;
1559 else if (mask & 0x00ff00)
1560 bits = 0x00ff00;
1561 else if (mask & 0x0f0000)
1562 bits = 0x0f0000;
1563 else
1564 bits = 0xf00000;
1565 switch (data[0]) {
1566 case INSN_CONFIG_DIO_INPUT:
1567 s->io_bits &= ~bits;
1568 break;
1569 case INSN_CONFIG_DIO_OUTPUT:
1570 s->io_bits |= bits;
1571 break;
1572 case INSN_CONFIG_DIO_QUERY:
1573 data[1] = (s->io_bits & bits) ? COMEDI_OUTPUT : COMEDI_INPUT;
1574 return insn->n;
1575 break;
1576 default:
1577 return -EINVAL;
1578 }
1579 dio200_subdev_8255_set_dir(dev, s);
1580 return 1;
1581 }
1582
1583 /*
1584 * This function initializes an '8255' DIO subdevice.
1585 *
1586 * offset is the offset to the 8255 chip.
1587 */
1588 static int dio200_subdev_8255_init(struct comedi_device *dev,
1589 struct comedi_subdevice *s,
1590 unsigned int offset)
1591 {
1592 struct dio200_subdev_8255 *subpriv;
1593
1594 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1595 if (!subpriv)
1596 return -ENOMEM;
1597 subpriv->ofs = offset;
1598 s->private = subpriv;
1599 s->type = COMEDI_SUBD_DIO;
1600 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1601 s->n_chan = 24;
1602 s->range_table = &range_digital;
1603 s->maxdata = 1;
1604 s->insn_bits = dio200_subdev_8255_bits;
1605 s->insn_config = dio200_subdev_8255_config;
1606 s->state = 0;
1607 s->io_bits = 0;
1608 dio200_subdev_8255_set_dir(dev, s);
1609 return 0;
1610 }
1611
1612 /*
1613 * This function cleans up an '8255' DIO subdevice.
1614 */
1615 static void dio200_subdev_8255_cleanup(struct comedi_device *dev,
1616 struct comedi_subdevice *s)
1617 {
1618 struct dio200_subdev_8255 *subpriv = s->private;
1619
1620 kfree(subpriv);
1621 }
1622
1623 /*
1624 * Handle 'insn_read' for a timer subdevice.
1625 */
1626 static int dio200_subdev_timer_read(struct comedi_device *dev,
1627 struct comedi_subdevice *s,
1628 struct comedi_insn *insn,
1629 unsigned int *data)
1630 {
1631 unsigned int n;
1632
1633 for (n = 0; n < insn->n; n++)
1634 data[n] = dio200_read32(dev, DIO200_TS_COUNT);
1635 return n;
1636 }
1637
1638 /*
1639 * Reset timer subdevice.
1640 */
1641 static void dio200_subdev_timer_reset(struct comedi_device *dev,
1642 struct comedi_subdevice *s)
1643 {
1644 unsigned int clock;
1645
1646 clock = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1647 dio200_write32(dev, DIO200_TS_CONFIG, clock | TS_CONFIG_RESET);
1648 dio200_write32(dev, DIO200_TS_CONFIG, clock);
1649 }
1650
1651 /*
1652 * Get timer subdevice clock source and period.
1653 */
1654 static void dio200_subdev_timer_get_clock_src(struct comedi_device *dev,
1655 struct comedi_subdevice *s,
1656 unsigned int *src,
1657 unsigned int *period)
1658 {
1659 unsigned int clk;
1660
1661 clk = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1662 *src = clk;
1663 *period = (clk < ARRAY_SIZE(ts_clock_period)) ?
1664 ts_clock_period[clk] : 0;
1665 }
1666
1667 /*
1668 * Set timer subdevice clock source.
1669 */
1670 static int dio200_subdev_timer_set_clock_src(struct comedi_device *dev,
1671 struct comedi_subdevice *s,
1672 unsigned int src)
1673 {
1674 if (src > TS_CONFIG_MAX_CLK_SRC)
1675 return -EINVAL;
1676 dio200_write32(dev, DIO200_TS_CONFIG, src);
1677 return 0;
1678 }
1679
1680 /*
1681 * Handle 'insn_config' for a timer subdevice.
1682 */
1683 static int dio200_subdev_timer_config(struct comedi_device *dev,
1684 struct comedi_subdevice *s,
1685 struct comedi_insn *insn,
1686 unsigned int *data)
1687 {
1688 int ret = 0;
1689
1690 switch (data[0]) {
1691 case INSN_CONFIG_RESET:
1692 dio200_subdev_timer_reset(dev, s);
1693 break;
1694 case INSN_CONFIG_SET_CLOCK_SRC:
1695 ret = dio200_subdev_timer_set_clock_src(dev, s, data[1]);
1696 if (ret < 0)
1697 ret = -EINVAL;
1698 break;
1699 case INSN_CONFIG_GET_CLOCK_SRC:
1700 dio200_subdev_timer_get_clock_src(dev, s, &data[1], &data[2]);
1701 break;
1702 default:
1703 ret = -EINVAL;
1704 break;
1705 }
1706 return ret < 0 ? ret : insn->n;
1707 }
1708
1709 /*
1710 * This function initializes a timer subdevice.
1711 *
1712 * Uses the timestamp timer registers. There is only one timestamp timer.
1713 */
1714 static int dio200_subdev_timer_init(struct comedi_device *dev,
1715 struct comedi_subdevice *s)
1716 {
1717 s->type = COMEDI_SUBD_TIMER;
1718 s->subdev_flags = SDF_READABLE | SDF_LSAMPL;
1719 s->n_chan = 1;
1720 s->maxdata = 0xFFFFFFFF;
1721 s->insn_read = dio200_subdev_timer_read;
1722 s->insn_config = dio200_subdev_timer_config;
1723 return 0;
1724 }
1725
1726 /*
1727 * This function cleans up a timer subdevice.
1728 */
1729 static void dio200_subdev_timer_cleanup(struct comedi_device *dev,
1730 struct comedi_subdevice *s)
1731 {
1732 /* Nothing to do. */
1733 }
1734
1735 /*
1736 * This function does some special set-up for the PCIe boards
1737 * PCIe215, PCIe236, PCIe296.
1738 */
1739 static int dio200_pcie_board_setup(struct comedi_device *dev)
1740 {
1741 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1742 void __iomem *brbase;
1743 resource_size_t brlen;
1744
1745 /*
1746 * The board uses Altera Cyclone IV with PCI-Express hard IP.
1747 * The FPGA configuration has the PCI-Express Avalon-MM Bridge
1748 * Control registers in PCI BAR 0, offset 0, and the length of
1749 * these registers is 0x4000.
1750 *
1751 * We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt
1752 * Enable" register at offset 0x50 to allow generation of PCIe
1753 * interrupts when RXmlrq_i is asserted in the SOPC Builder system.
1754 */
1755 brlen = pci_resource_len(pcidev, 0);
1756 if (brlen < 0x4000 ||
1757 !(pci_resource_flags(pcidev, 0) & IORESOURCE_MEM)) {
1758 dev_err(dev->class_dev, "error! bad PCI region!\n");
1759 return -EINVAL;
1760 }
1761 brbase = ioremap_nocache(pci_resource_start(pcidev, 0), brlen);
1762 if (!brbase) {
1763 dev_err(dev->class_dev, "error! failed to map registers!\n");
1764 return -ENOMEM;
1765 }
1766 writel(0x80, brbase + 0x50);
1767 iounmap(brbase);
1768 /* Enable "enhanced" features of board. */
1769 dio200_write8(dev, DIO200_ENHANCE, 1);
1770 return 0;
1771 }
1772
1773 static void dio200_report_attach(struct comedi_device *dev, unsigned int irq)
1774 {
1775 const struct dio200_board *thisboard = comedi_board(dev);
1776 struct dio200_private *devpriv = dev->private;
1777 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1778 char tmpbuf[60];
1779 int tmplen;
1780
1781 if (is_isa_board(thisboard))
1782 tmplen = scnprintf(tmpbuf, sizeof(tmpbuf),
1783 "(base %#lx) ", devpriv->io.u.iobase);
1784 else if (is_pci_board(thisboard))
1785 tmplen = scnprintf(tmpbuf, sizeof(tmpbuf),
1786 "(pci %s) ", pci_name(pcidev));
1787 else
1788 tmplen = 0;
1789 if (irq)
1790 tmplen += scnprintf(&tmpbuf[tmplen], sizeof(tmpbuf) - tmplen,
1791 "(irq %u%s) ", irq,
1792 (dev->irq ? "" : " UNAVAILABLE"));
1793 else
1794 tmplen += scnprintf(&tmpbuf[tmplen], sizeof(tmpbuf) - tmplen,
1795 "(no irq) ");
1796 dev_info(dev->class_dev, "%s %sattached\n", dev->board_name, tmpbuf);
1797 }
1798
1799 static int dio200_common_attach(struct comedi_device *dev, unsigned int irq,
1800 unsigned long req_irq_flags)
1801 {
1802 const struct dio200_board *thisboard = comedi_board(dev);
1803 struct dio200_private *devpriv = dev->private;
1804 const struct dio200_layout *layout = dio200_board_layout(thisboard);
1805 struct comedi_subdevice *s;
1806 int sdx;
1807 unsigned int n;
1808 int ret;
1809
1810 devpriv->intr_sd = -1;
1811 dev->board_name = thisboard->name;
1812
1813 ret = comedi_alloc_subdevices(dev, layout->n_subdevs);
1814 if (ret)
1815 return ret;
1816
1817 for (n = 0; n < dev->n_subdevices; n++) {
1818 s = &dev->subdevices[n];
1819 switch (layout->sdtype[n]) {
1820 case sd_8254:
1821 /* counter subdevice (8254) */
1822 ret = dio200_subdev_8254_init(dev, s,
1823 layout->sdinfo[n]);
1824 if (ret < 0)
1825 return ret;
1826 break;
1827 case sd_8255:
1828 /* digital i/o subdevice (8255) */
1829 ret = dio200_subdev_8255_init(dev, s,
1830 layout->sdinfo[n]);
1831 if (ret < 0)
1832 return ret;
1833 break;
1834 case sd_intr:
1835 /* 'INTERRUPT' subdevice */
1836 if (irq) {
1837 ret = dio200_subdev_intr_init(dev, s,
1838 DIO200_INT_SCE,
1839 layout->sdinfo[n]
1840 );
1841 if (ret < 0)
1842 return ret;
1843 devpriv->intr_sd = n;
1844 } else {
1845 s->type = COMEDI_SUBD_UNUSED;
1846 }
1847 break;
1848 case sd_timer:
1849 /* Only on PCIe boards. */
1850 if (DO_PCI) {
1851 ret = dio200_subdev_timer_init(dev, s);
1852 if (ret < 0)
1853 return ret;
1854 } else {
1855 s->type = COMEDI_SUBD_UNUSED;
1856 }
1857 break;
1858 default:
1859 s->type = COMEDI_SUBD_UNUSED;
1860 break;
1861 }
1862 }
1863 sdx = devpriv->intr_sd;
1864 if (sdx >= 0 && sdx < dev->n_subdevices)
1865 dev->read_subdev = &dev->subdevices[sdx];
1866 if (irq) {
1867 if (request_irq(irq, dio200_interrupt, req_irq_flags,
1868 DIO200_DRIVER_NAME, dev) >= 0) {
1869 dev->irq = irq;
1870 } else {
1871 dev_warn(dev->class_dev,
1872 "warning! irq %u unavailable!\n", irq);
1873 }
1874 }
1875 dio200_report_attach(dev, irq);
1876 return 1;
1877 }
1878
1879 /* Only called for ISA boards. */
1880 static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1881 {
1882 const struct dio200_board *thisboard = comedi_board(dev);
1883 struct dio200_private *devpriv;
1884 unsigned long iobase;
1885 unsigned int irq;
1886 int ret;
1887
1888 if (!DO_ISA)
1889 return -EINVAL;
1890
1891 dev_info(dev->class_dev, DIO200_DRIVER_NAME ": attach\n");
1892
1893 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1894 if (!devpriv)
1895 return -ENOMEM;
1896 dev->private = devpriv;
1897
1898 iobase = it->options[0];
1899 irq = it->options[1];
1900 ret = dio200_request_region(dev, iobase, thisboard->mainsize);
1901 if (ret < 0)
1902 return ret;
1903 devpriv->io.u.iobase = iobase;
1904 devpriv->io.regtype = io_regtype;
1905 return dio200_common_attach(dev, irq, 0);
1906 }
1907
1908 /*
1909 * The auto_attach hook is called at PCI probe time via
1910 * comedi_pci_auto_config(). dev->board_ptr is NULL on entry.
1911 * There should be a board entry matching the supplied PCI device.
1912 */
1913 static int dio200_auto_attach(struct comedi_device *dev,
1914 unsigned long context_unused)
1915 {
1916 struct pci_dev *pci_dev = comedi_to_pci_dev(dev);
1917 const struct dio200_board *thisboard;
1918 struct dio200_private *devpriv;
1919 resource_size_t base, len;
1920 unsigned int bar;
1921 int ret;
1922
1923 if (!DO_PCI)
1924 return -EINVAL;
1925
1926 dev_info(dev->class_dev, DIO200_DRIVER_NAME ": attach pci %s\n",
1927 pci_name(pci_dev));
1928
1929 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1930 if (!devpriv)
1931 return -ENOMEM;
1932 dev->private = devpriv;
1933
1934 dev->board_ptr = dio200_find_pci_board(pci_dev);
1935 if (dev->board_ptr == NULL) {
1936 dev_err(dev->class_dev, "BUG! cannot determine board type!\n");
1937 return -EINVAL;
1938 }
1939 thisboard = comedi_board(dev);
1940
1941 ret = comedi_pci_enable(dev);
1942 if (ret)
1943 return ret;
1944
1945 bar = thisboard->mainbar;
1946 base = pci_resource_start(pci_dev, bar);
1947 len = pci_resource_len(pci_dev, bar);
1948 if (len < thisboard->mainsize) {
1949 dev_err(dev->class_dev, "error! PCI region size too small!\n");
1950 return -EINVAL;
1951 }
1952 if ((pci_resource_flags(pci_dev, bar) & IORESOURCE_MEM) != 0) {
1953 devpriv->io.u.membase = ioremap_nocache(base, len);
1954 if (!devpriv->io.u.membase) {
1955 dev_err(dev->class_dev,
1956 "error! cannot remap registers\n");
1957 return -ENOMEM;
1958 }
1959 devpriv->io.regtype = mmio_regtype;
1960 } else {
1961 devpriv->io.u.iobase = (unsigned long)base;
1962 devpriv->io.regtype = io_regtype;
1963 }
1964 switch (thisboard->model) {
1965 case pcie215_model:
1966 case pcie236_model:
1967 case pcie296_model:
1968 ret = dio200_pcie_board_setup(dev);
1969 if (ret < 0)
1970 return ret;
1971 break;
1972 default:
1973 break;
1974 }
1975 return dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED);
1976 }
1977
1978 static void dio200_detach(struct comedi_device *dev)
1979 {
1980 const struct dio200_board *thisboard = comedi_board(dev);
1981 struct dio200_private *devpriv = dev->private;
1982 const struct dio200_layout *layout;
1983 unsigned n;
1984
1985 if (!thisboard || !devpriv)
1986 return;
1987 if (dev->irq)
1988 free_irq(dev->irq, dev);
1989 if (dev->subdevices) {
1990 layout = dio200_board_layout(thisboard);
1991 for (n = 0; n < dev->n_subdevices; n++) {
1992 struct comedi_subdevice *s = &dev->subdevices[n];
1993 switch (layout->sdtype[n]) {
1994 case sd_8254:
1995 dio200_subdev_8254_cleanup(dev, s);
1996 break;
1997 case sd_8255:
1998 dio200_subdev_8255_cleanup(dev, s);
1999 break;
2000 case sd_intr:
2001 dio200_subdev_intr_cleanup(dev, s);
2002 break;
2003 case sd_timer:
2004 /* Only on PCIe boards. */
2005 if (DO_PCI)
2006 dio200_subdev_timer_cleanup(dev, s);
2007 break;
2008 default:
2009 break;
2010 }
2011 }
2012 }
2013 if (is_isa_board(thisboard)) {
2014 if (devpriv->io.regtype == io_regtype)
2015 release_region(devpriv->io.u.iobase,
2016 thisboard->mainsize);
2017 } else if (is_pci_board(thisboard)) {
2018 if (devpriv->io.regtype == mmio_regtype)
2019 iounmap(devpriv->io.u.membase);
2020 comedi_pci_disable(dev);
2021 }
2022 }
2023
2024 /*
2025 * The struct comedi_driver structure tells the Comedi core module
2026 * which functions to call to configure/deconfigure (attach/detach)
2027 * the board, and also about the kernel module that contains
2028 * the device code.
2029 */
2030 static struct comedi_driver amplc_dio200_driver = {
2031 .driver_name = DIO200_DRIVER_NAME,
2032 .module = THIS_MODULE,
2033 .attach = dio200_attach,
2034 .auto_attach = dio200_auto_attach,
2035 .detach = dio200_detach,
2036 #if DO_ISA
2037 .board_name = &dio200_isa_boards[0].name,
2038 .offset = sizeof(struct dio200_board),
2039 .num_names = ARRAY_SIZE(dio200_isa_boards),
2040 #endif
2041 };
2042
2043 #if DO_PCI
2044 static DEFINE_PCI_DEVICE_TABLE(dio200_pci_table) = {
2045 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI215) },
2046 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI272) },
2047 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE236) },
2048 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE215) },
2049 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE296) },
2050 {0}
2051 };
2052
2053 MODULE_DEVICE_TABLE(pci, dio200_pci_table);
2054
2055 static int amplc_dio200_pci_probe(struct pci_dev *dev,
2056 const struct pci_device_id *id)
2057 {
2058 return comedi_pci_auto_config(dev, &amplc_dio200_driver,
2059 id->driver_data);
2060 }
2061
2062 static struct pci_driver amplc_dio200_pci_driver = {
2063 .name = DIO200_DRIVER_NAME,
2064 .id_table = dio200_pci_table,
2065 .probe = &amplc_dio200_pci_probe,
2066 .remove = comedi_pci_auto_unconfig,
2067 };
2068 module_comedi_pci_driver(amplc_dio200_driver, amplc_dio200_pci_driver);
2069 #else
2070 module_comedi_driver(amplc_dio200_driver);
2071 #endif
2072
2073 MODULE_AUTHOR("Comedi http://www.comedi.org");
2074 MODULE_DESCRIPTION("Comedi low-level driver");
2075 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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