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staging: comedi: amplc_dio200: set board_name before common attach
[deliverable/linux.git] / drivers / staging / comedi / drivers / amplc_dio200.c
1 /*
2 comedi/drivers/amplc_dio200.c
3 Driver for Amplicon PC272E and PCI272 DIO boards.
4 (Support for other boards in Amplicon 200 series may be added at
5 a later date, e.g. PCI215.)
6
7 Copyright (C) 2005 MEV Ltd. <http://www.mev.co.uk/>
8
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25
26 */
27 /*
28 * Driver: amplc_dio200
29 * Description: Amplicon 200 Series Digital I/O
30 * Author: Ian Abbott <abbotti@mev.co.uk>
31 * Devices: [Amplicon] PC212E (pc212e), PC214E (pc214e), PC215E (pc215e),
32 * PCI215 (pci215), PCIe215 (pcie215), PC218E (pc218e), PCIe236 (pcie236),
33 * PC272E (pc272e), PCI272 (pci272), PCIe296 (pcie296)
34 * Updated: Wed, 24 Oct 2012 16:22:34 +0100
35 * Status: works
36 *
37 * Configuration options - PC212E, PC214E, PC215E, PC218E, PC272E:
38 * [0] - I/O port base address
39 * [1] - IRQ (optional, but commands won't work without it)
40 *
41 * Manual configuration of PCI(e) cards is not supported; they are configured
42 * automatically.
43 *
44 * Passing a zero for an option is the same as leaving it unspecified.
45 *
46 * SUBDEVICES
47 *
48 * PC212E PC214E PC215E/PCI215
49 * ------------- ------------- -------------
50 * Subdevices 6 4 5
51 * 0 PPI-X PPI-X PPI-X
52 * 1 CTR-Y1 PPI-Y PPI-Y
53 * 2 CTR-Y2 CTR-Z1* CTR-Z1
54 * 3 CTR-Z1 INTERRUPT* CTR-Z2
55 * 4 CTR-Z2 INTERRUPT
56 * 5 INTERRUPT
57 *
58 * PCIe215 PC218E PCIe236
59 * ------------- ------------- -------------
60 * Subdevices 8 7 8
61 * 0 PPI-X CTR-X1 PPI-X
62 * 1 UNUSED CTR-X2 UNUSED
63 * 2 PPI-Y CTR-Y1 UNUSED
64 * 3 UNUSED CTR-Y2 UNUSED
65 * 4 CTR-Z1 CTR-Z1 CTR-Z1
66 * 5 CTR-Z2 CTR-Z2 CTR-Z2
67 * 6 TIMER INTERRUPT TIMER
68 * 7 INTERRUPT INTERRUPT
69 *
70 * PC272E/PCI272 PCIe296
71 * ------------- -------------
72 * Subdevices 4 8
73 * 0 PPI-X PPI-X1
74 * 1 PPI-Y PPI-X2
75 * 2 PPI-Z PPI-Y1
76 * 3 INTERRUPT PPI-Y2
77 * 4 CTR-Z1
78 * 5 CTR-Z2
79 * 6 TIMER
80 * 7 INTERRUPT
81 *
82 * Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels
83 * are configurable as inputs or outputs in four groups:
84 *
85 * Port A - channels 0 to 7
86 * Port B - channels 8 to 15
87 * Port CL - channels 16 to 19
88 * Port CH - channels 20 to 23
89 *
90 * Only mode 0 of the 8255 chips is supported.
91 *
92 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
93 * channel is configured individually with INSN_CONFIG instructions. The
94 * specific type of configuration instruction is specified in data[0].
95 * Some configuration instructions expect an additional parameter in
96 * data[1]; others return a value in data[1]. The following configuration
97 * instructions are supported:
98 *
99 * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
100 * BCD/binary setting specified in data[1].
101 *
102 * INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the
103 * counter channel into data[1].
104 *
105 * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
106 * specified in data[1] (this is a hardware-specific value). Not
107 * supported on PC214E. For the other boards, valid clock sources are
108 * 0 to 7 as follows:
109 *
110 * 0. CLK n, the counter channel's dedicated CLK input from the SK1
111 * connector. (N.B. for other values, the counter channel's CLKn
112 * pin on the SK1 connector is an output!)
113 * 1. Internal 10 MHz clock.
114 * 2. Internal 1 MHz clock.
115 * 3. Internal 100 kHz clock.
116 * 4. Internal 10 kHz clock.
117 * 5. Internal 1 kHz clock.
118 * 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
119 * 7. Ext Clock, the counter chip's dedicated Ext Clock input from
120 * the SK1 connector. This pin is shared by all three counter
121 * channels on the chip.
122 *
123 * For the PCIe boards, clock sources in the range 0 to 31 are allowed
124 * and the following additional clock sources are defined:
125 *
126 * 8. HIGH logic level.
127 * 9. LOW logic level.
128 * 10. "Pattern present" signal.
129 * 11. Internal 20 MHz clock.
130 *
131 * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
132 * clock source in data[1]. For internal clock sources, data[2] is set
133 * to the period in ns.
134 *
135 * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
136 * specified in data[2] (this is a hardware-specific value). Not
137 * supported on PC214E. For the other boards, valid gate sources are 0
138 * to 7 as follows:
139 *
140 * 0. VCC (internal +5V d.c.), i.e. gate permanently enabled.
141 * 1. GND (internal 0V d.c.), i.e. gate permanently disabled.
142 * 2. GAT n, the counter channel's dedicated GAT input from the SK1
143 * connector. (N.B. for other values, the counter channel's GATn
144 * pin on the SK1 connector is an output!)
145 * 3. /OUT n-2, the inverted output of counter channel n-2 (see note
146 * 2 below).
147 * 4. Reserved.
148 * 5. Reserved.
149 * 6. Reserved.
150 * 7. Reserved.
151 *
152 * For the PCIe boards, gate sources in the range 0 to 31 are allowed;
153 * the following additional clock sources and clock sources 6 and 7 are
154 * (re)defined:
155 *
156 * 6. /GAT n, negated version of the counter channel's dedicated
157 * GAT input (negated version of gate source 2).
158 * 7. OUT n-2, the non-inverted output of counter channel n-2
159 * (negated version of gate source 3).
160 * 8. "Pattern present" signal, HIGH while pattern present.
161 * 9. "Pattern occurred" latched signal, latches HIGH when pattern
162 * occurs.
163 * 10. "Pattern gone away" latched signal, latches LOW when pattern
164 * goes away after it occurred.
165 * 11. Negated "pattern present" signal, LOW while pattern present
166 * (negated version of gate source 8).
167 * 12. Negated "pattern occurred" latched signal, latches LOW when
168 * pattern occurs (negated version of gate source 9).
169 * 13. Negated "pattern gone away" latched signal, latches LOW when
170 * pattern goes away after it occurred (negated version of gate
171 * source 10).
172 *
173 * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
174 * source in data[2].
175 *
176 * Clock and gate interconnection notes:
177 *
178 * 1. Clock source OUT n-1 is the output of the preceding channel on the
179 * same counter subdevice if n > 0, or the output of channel 2 on the
180 * preceding counter subdevice (see note 3) if n = 0.
181 *
182 * 2. Gate source /OUT n-2 is the inverted output of channel 0 on the
183 * same counter subdevice if n = 2, or the inverted output of channel n+1
184 * on the preceding counter subdevice (see note 3) if n < 2.
185 *
186 * 3. The counter subdevices are connected in a ring, so the highest
187 * counter subdevice precedes the lowest.
188 *
189 * The 'TIMER' subdevice is a free-running 32-bit timer subdevice.
190 *
191 * The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The
192 * digital inputs come from the interrupt status register. The number of
193 * channels matches the number of interrupt sources. The PC214E does not
194 * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
195 * below.
196 *
197 * INTERRUPT SOURCES
198 *
199 * PC212E PC214E PC215E/PCI215
200 * ------------- ------------- -------------
201 * Sources 6 1 6
202 * 0 PPI-X-C0 JUMPER-J5 PPI-X-C0
203 * 1 PPI-X-C3 PPI-X-C3
204 * 2 CTR-Y1-OUT1 PPI-Y-C0
205 * 3 CTR-Y2-OUT1 PPI-Y-C3
206 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1
207 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1
208 *
209 * PCIe215 PC218E PCIe236
210 * ------------- ------------- -------------
211 * Sources 6 6 6
212 * 0 PPI-X-C0 CTR-X1-OUT1 PPI-X-C0
213 * 1 PPI-X-C3 CTR-X2-OUT1 PPI-X-C3
214 * 2 PPI-Y-C0 CTR-Y1-OUT1 unused
215 * 3 PPI-Y-C3 CTR-Y2-OUT1 unused
216 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1
217 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1
218 *
219 * PC272E/PCI272 PCIe296
220 * ------------- -------------
221 * Sources 6 6
222 * 0 PPI-X-C0 PPI-X1-C0
223 * 1 PPI-X-C3 PPI-X1-C3
224 * 2 PPI-Y-C0 PPI-Y1-C0
225 * 3 PPI-Y-C3 PPI-Y1-C3
226 * 4 PPI-Z-C0 CTR-Z1-OUT1
227 * 5 PPI-Z-C3 CTR-Z2-OUT1
228 *
229 * When an interrupt source is enabled in the interrupt source enable
230 * register, a rising edge on the source signal latches the corresponding
231 * bit to 1 in the interrupt status register.
232 *
233 * When the interrupt status register value as a whole (actually, just the
234 * 6 least significant bits) goes from zero to non-zero, the board will
235 * generate an interrupt. For level-triggered hardware interrupts (PCI
236 * card), the interrupt will remain asserted until the interrupt status
237 * register is cleared to zero. For edge-triggered hardware interrupts
238 * (ISA card), no further interrupts will occur until the interrupt status
239 * register is cleared to zero. To clear a bit to zero in the interrupt
240 * status register, the corresponding interrupt source must be disabled
241 * in the interrupt source enable register (there is no separate interrupt
242 * clear register).
243 *
244 * The PC214E does not have an interrupt source enable register or an
245 * interrupt status register; its 'INTERRUPT' subdevice has a single
246 * channel and its interrupt source is selected by the position of jumper
247 * J5.
248 *
249 * COMMANDS
250 *
251 * The driver supports a read streaming acquisition command on the
252 * 'INTERRUPT' subdevice. The channel list selects the interrupt sources
253 * to be enabled. All channels will be sampled together (convert_src ==
254 * TRIG_NOW). The scan begins a short time after the hardware interrupt
255 * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
256 * scan_begin_arg == 0). The value read from the interrupt status register
257 * is packed into a short value, one bit per requested channel, in the
258 * order they appear in the channel list.
259 */
260
261 #include <linux/pci.h>
262 #include <linux/interrupt.h>
263 #include <linux/slab.h>
264
265 #include "../comedidev.h"
266
267 #include "comedi_fc.h"
268 #include "8253.h"
269
270 #define DIO200_DRIVER_NAME "amplc_dio200"
271
272 #define DO_ISA IS_ENABLED(CONFIG_COMEDI_AMPLC_DIO200_ISA)
273 #define DO_PCI IS_ENABLED(CONFIG_COMEDI_AMPLC_DIO200_PCI)
274
275 /* PCI IDs */
276 #define PCI_DEVICE_ID_AMPLICON_PCI272 0x000a
277 #define PCI_DEVICE_ID_AMPLICON_PCI215 0x000b
278 #define PCI_DEVICE_ID_AMPLICON_PCIE236 0x0011
279 #define PCI_DEVICE_ID_AMPLICON_PCIE215 0x0012
280 #define PCI_DEVICE_ID_AMPLICON_PCIE296 0x0014
281
282 /* 8255 control register bits */
283 #define CR_C_LO_IO 0x01
284 #define CR_B_IO 0x02
285 #define CR_B_MODE 0x04
286 #define CR_C_HI_IO 0x08
287 #define CR_A_IO 0x10
288 #define CR_A_MODE(a) ((a)<<5)
289 #define CR_CW 0x80
290
291 /* 200 series registers */
292 #define DIO200_IO_SIZE 0x20
293 #define DIO200_PCIE_IO_SIZE 0x4000
294 #define DIO200_XCLK_SCE 0x18 /* Group X clock selection register */
295 #define DIO200_YCLK_SCE 0x19 /* Group Y clock selection register */
296 #define DIO200_ZCLK_SCE 0x1a /* Group Z clock selection register */
297 #define DIO200_XGAT_SCE 0x1b /* Group X gate selection register */
298 #define DIO200_YGAT_SCE 0x1c /* Group Y gate selection register */
299 #define DIO200_ZGAT_SCE 0x1d /* Group Z gate selection register */
300 #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */
301 /* Extra registers for new PCIe boards */
302 #define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */
303 #define DIO200_VERSION 0x24 /* Hardware version register */
304 #define DIO200_TS_CONFIG 0x600 /* Timestamp timer config register */
305 #define DIO200_TS_COUNT 0x602 /* Timestamp timer count register */
306
307 /*
308 * Functions for constructing value for DIO_200_?CLK_SCE and
309 * DIO_200_?GAT_SCE registers:
310 *
311 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
312 * 'chan' is the channel: 0, 1 or 2.
313 * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards.
314 */
315 static unsigned char clk_gat_sce(unsigned int which, unsigned int chan,
316 unsigned int source)
317 {
318 return (which << 5) | (chan << 3) |
319 ((source & 030) << 3) | (source & 007);
320 }
321
322 static unsigned char clk_sce(unsigned int which, unsigned int chan,
323 unsigned int source)
324 {
325 return clk_gat_sce(which, chan, source);
326 }
327
328 static unsigned char gat_sce(unsigned int which, unsigned int chan,
329 unsigned int source)
330 {
331 return clk_gat_sce(which, chan, source);
332 }
333
334 /*
335 * Periods of the internal clock sources in nanoseconds.
336 */
337 static const unsigned int clock_period[32] = {
338 [1] = 100, /* 10 MHz */
339 [2] = 1000, /* 1 MHz */
340 [3] = 10000, /* 100 kHz */
341 [4] = 100000, /* 10 kHz */
342 [5] = 1000000, /* 1 kHz */
343 [11] = 50, /* 20 MHz (enhanced boards) */
344 /* clock sources 12 and later reserved for enhanced boards */
345 };
346
347 /*
348 * Timestamp timer configuration register (for new PCIe boards).
349 */
350 #define TS_CONFIG_RESET 0x100 /* Reset counter to zero. */
351 #define TS_CONFIG_CLK_SRC_MASK 0x0FF /* Clock source. */
352 #define TS_CONFIG_MAX_CLK_SRC 2 /* Maximum clock source value. */
353
354 /*
355 * Periods of the timestamp timer clock sources in nanoseconds.
356 */
357 static const unsigned int ts_clock_period[TS_CONFIG_MAX_CLK_SRC + 1] = {
358 1, /* 1 nanosecond (but with 20 ns granularity). */
359 1000, /* 1 microsecond. */
360 1000000, /* 1 millisecond. */
361 };
362
363 /*
364 * Register region.
365 */
366 enum dio200_regtype { no_regtype = 0, io_regtype, mmio_regtype };
367 struct dio200_region {
368 union {
369 unsigned long iobase; /* I/O base address */
370 unsigned char __iomem *membase; /* mapped MMIO base address */
371 } u;
372 enum dio200_regtype regtype;
373 };
374
375 /*
376 * Subdevice types.
377 */
378 enum dio200_sdtype { sd_none, sd_intr, sd_8255, sd_8254, sd_timer };
379
380 #define DIO200_MAX_SUBDEVS 8
381 #define DIO200_MAX_ISNS 6
382
383 struct dio200_layout {
384 unsigned short n_subdevs; /* number of subdevices */
385 unsigned char sdtype[DIO200_MAX_SUBDEVS]; /* enum dio200_sdtype */
386 unsigned char sdinfo[DIO200_MAX_SUBDEVS]; /* depends on sdtype */
387 bool has_int_sce:1; /* has interrupt enable/status reg */
388 bool has_clk_gat_sce:1; /* has clock/gate selection registers */
389 bool has_enhancements:1; /* has enhanced features */
390 };
391
392 /*
393 * Board descriptions.
394 */
395
396 enum dio200_bustype { isa_bustype, pci_bustype };
397
398 enum dio200_pci_model {
399 pci215_model,
400 pci272_model,
401 pcie215_model,
402 pcie236_model,
403 pcie296_model
404 };
405
406 struct dio200_board {
407 const char *name;
408 struct dio200_layout layout;
409 enum dio200_bustype bustype;
410 unsigned char mainbar;
411 unsigned char mainshift;
412 unsigned int mainsize;
413 };
414
415 #if DO_ISA
416 static const struct dio200_board dio200_isa_boards[] = {
417 {
418 .name = "pc212e",
419 .bustype = isa_bustype,
420 .mainsize = DIO200_IO_SIZE,
421 .layout = {
422 .n_subdevs = 6,
423 .sdtype = {sd_8255, sd_8254, sd_8254, sd_8254, sd_8254,
424 sd_intr},
425 .sdinfo = {0x00, 0x08, 0x0C, 0x10, 0x14, 0x3F},
426 .has_int_sce = true,
427 .has_clk_gat_sce = true,
428 },
429 },
430 {
431 .name = "pc214e",
432 .bustype = isa_bustype,
433 .mainsize = DIO200_IO_SIZE,
434 .layout = {
435 .n_subdevs = 4,
436 .sdtype = {sd_8255, sd_8255, sd_8254, sd_intr},
437 .sdinfo = {0x00, 0x08, 0x10, 0x01},
438 },
439 },
440 {
441 .name = "pc215e",
442 .bustype = isa_bustype,
443 .mainsize = DIO200_IO_SIZE,
444 .layout = {
445 .n_subdevs = 5,
446 .sdtype = {sd_8255, sd_8255, sd_8254, sd_8254, sd_intr},
447 .sdinfo = {0x00, 0x08, 0x10, 0x14, 0x3F},
448 .has_int_sce = true,
449 .has_clk_gat_sce = true,
450 },
451 },
452 {
453 .name = "pc218e",
454 .bustype = isa_bustype,
455 .mainsize = DIO200_IO_SIZE,
456 .layout = {
457 .n_subdevs = 7,
458 .sdtype = {sd_8254, sd_8254, sd_8255, sd_8254, sd_8254,
459 sd_intr},
460 .sdinfo = {0x00, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x3F},
461 .has_int_sce = true,
462 .has_clk_gat_sce = true,
463 },
464 },
465 {
466 .name = "pc272e",
467 .bustype = isa_bustype,
468 .mainsize = DIO200_IO_SIZE,
469 .layout = {
470 .n_subdevs = 4,
471 .sdtype = {sd_8255, sd_8255, sd_8255, sd_intr},
472 .sdinfo = {0x00, 0x08, 0x10, 0x3F},
473 .has_int_sce = true,
474 },
475 },
476 };
477 #endif
478
479 #if DO_PCI
480 static const struct dio200_board dio200_pci_boards[] = {
481 [pci215_model] {
482 .name = "pci215",
483 .bustype = pci_bustype,
484 .mainbar = 2,
485 .mainsize = DIO200_IO_SIZE,
486 .layout = {
487 .n_subdevs = 5,
488 .sdtype = {sd_8255, sd_8255, sd_8254, sd_8254, sd_intr},
489 .sdinfo = {0x00, 0x08, 0x10, 0x14, 0x3F},
490 .has_int_sce = true,
491 .has_clk_gat_sce = true,
492 },
493 },
494 [pci272_model] {
495 .name = "pci272",
496 .bustype = pci_bustype,
497 .mainbar = 2,
498 .mainsize = DIO200_IO_SIZE,
499 .layout = {
500 .n_subdevs = 4,
501 .sdtype = {sd_8255, sd_8255, sd_8255, sd_intr},
502 .sdinfo = {0x00, 0x08, 0x10, 0x3F},
503 .has_int_sce = true,
504 },
505 },
506 [pcie215_model] {
507 .name = "pcie215",
508 .bustype = pci_bustype,
509 .mainbar = 1,
510 .mainshift = 3,
511 .mainsize = DIO200_PCIE_IO_SIZE,
512 .layout = {
513 .n_subdevs = 8,
514 .sdtype = {sd_8255, sd_none, sd_8255, sd_none,
515 sd_8254, sd_8254, sd_timer, sd_intr},
516 .sdinfo = {0x00, 0x00, 0x08, 0x00,
517 0x10, 0x14, 0x00, 0x3F},
518 .has_int_sce = true,
519 .has_clk_gat_sce = true,
520 .has_enhancements = true,
521 },
522 },
523 [pcie236_model] {
524 .name = "pcie236",
525 .bustype = pci_bustype,
526 .mainbar = 1,
527 .mainshift = 3,
528 .mainsize = DIO200_PCIE_IO_SIZE,
529 .layout = {
530 .n_subdevs = 8,
531 .sdtype = {sd_8255, sd_none, sd_none, sd_none,
532 sd_8254, sd_8254, sd_timer, sd_intr},
533 .sdinfo = {0x00, 0x00, 0x00, 0x00,
534 0x10, 0x14, 0x00, 0x3F},
535 .has_int_sce = true,
536 .has_clk_gat_sce = true,
537 .has_enhancements = true,
538 },
539 },
540 [pcie296_model] {
541 .name = "pcie296",
542 .bustype = pci_bustype,
543 .mainbar = 1,
544 .mainshift = 3,
545 .mainsize = DIO200_PCIE_IO_SIZE,
546 .layout = {
547 .n_subdevs = 8,
548 .sdtype = {sd_8255, sd_8255, sd_8255, sd_8255,
549 sd_8254, sd_8254, sd_timer, sd_intr},
550 .sdinfo = {0x00, 0x04, 0x08, 0x0C,
551 0x10, 0x14, 0x00, 0x3F},
552 .has_int_sce = true,
553 .has_clk_gat_sce = true,
554 .has_enhancements = true,
555 },
556 },
557 };
558 #endif
559
560 /* this structure is for data unique to this hardware driver. If
561 several hardware drivers keep similar information in this structure,
562 feel free to suggest moving the variable to the struct comedi_device struct.
563 */
564 struct dio200_private {
565 struct dio200_region io; /* Register region */
566 int intr_sd;
567 };
568
569 struct dio200_subdev_8254 {
570 unsigned int ofs; /* Counter base offset */
571 unsigned int clk_sce_ofs; /* CLK_SCE base address */
572 unsigned int gat_sce_ofs; /* GAT_SCE base address */
573 int which; /* Bit 5 of CLK_SCE or GAT_SCE */
574 unsigned int clock_src[3]; /* Current clock sources */
575 unsigned int gate_src[3]; /* Current gate sources */
576 spinlock_t spinlock;
577 };
578
579 struct dio200_subdev_8255 {
580 unsigned int ofs; /* DIO base offset */
581 };
582
583 struct dio200_subdev_intr {
584 spinlock_t spinlock;
585 unsigned int ofs;
586 unsigned int valid_isns;
587 unsigned int enabled_isns;
588 unsigned int stopcount;
589 bool active:1;
590 bool continuous:1;
591 };
592
593 static inline const struct dio200_layout *
594 dio200_board_layout(const struct dio200_board *board)
595 {
596 return &board->layout;
597 }
598
599 static inline const struct dio200_layout *
600 dio200_dev_layout(struct comedi_device *dev)
601 {
602 return dio200_board_layout(comedi_board(dev));
603 }
604
605 static inline bool is_pci_board(const struct dio200_board *board)
606 {
607 return DO_PCI && board->bustype == pci_bustype;
608 }
609
610 static inline bool is_isa_board(const struct dio200_board *board)
611 {
612 return DO_ISA && board->bustype == isa_bustype;
613 }
614
615 /*
616 * Read 8-bit register.
617 */
618 static unsigned char dio200_read8(struct comedi_device *dev,
619 unsigned int offset)
620 {
621 const struct dio200_board *thisboard = comedi_board(dev);
622 struct dio200_private *devpriv = dev->private;
623
624 offset <<= thisboard->mainshift;
625 if (devpriv->io.regtype == io_regtype)
626 return inb(devpriv->io.u.iobase + offset);
627 else
628 return readb(devpriv->io.u.membase + offset);
629 }
630
631 /*
632 * Write 8-bit register.
633 */
634 static void dio200_write8(struct comedi_device *dev, unsigned int offset,
635 unsigned char val)
636 {
637 const struct dio200_board *thisboard = comedi_board(dev);
638 struct dio200_private *devpriv = dev->private;
639
640 offset <<= thisboard->mainshift;
641 if (devpriv->io.regtype == io_regtype)
642 outb(val, devpriv->io.u.iobase + offset);
643 else
644 writeb(val, devpriv->io.u.membase + offset);
645 }
646
647 /*
648 * Read 32-bit register.
649 */
650 static unsigned int dio200_read32(struct comedi_device *dev,
651 unsigned int offset)
652 {
653 const struct dio200_board *thisboard = comedi_board(dev);
654 struct dio200_private *devpriv = dev->private;
655
656 offset <<= thisboard->mainshift;
657 if (devpriv->io.regtype == io_regtype)
658 return inl(devpriv->io.u.iobase + offset);
659 else
660 return readl(devpriv->io.u.membase + offset);
661 }
662
663 /*
664 * Write 32-bit register.
665 */
666 static void dio200_write32(struct comedi_device *dev, unsigned int offset,
667 unsigned int val)
668 {
669 const struct dio200_board *thisboard = comedi_board(dev);
670 struct dio200_private *devpriv = dev->private;
671
672 offset <<= thisboard->mainshift;
673 if (devpriv->io.regtype == io_regtype)
674 outl(val, devpriv->io.u.iobase + offset);
675 else
676 writel(val, devpriv->io.u.membase + offset);
677 }
678
679 /*
680 * This function checks and requests an I/O region, reporting an error
681 * if there is a conflict.
682 */
683 static int
684 dio200_request_region(struct comedi_device *dev,
685 unsigned long from, unsigned long extent)
686 {
687 if (!from || !request_region(from, extent, DIO200_DRIVER_NAME)) {
688 dev_err(dev->class_dev, "I/O port conflict (%#lx,%lu)!\n",
689 from, extent);
690 return -EIO;
691 }
692 return 0;
693 }
694
695 /*
696 * 'insn_bits' function for an 'INTERRUPT' subdevice.
697 */
698 static int
699 dio200_subdev_intr_insn_bits(struct comedi_device *dev,
700 struct comedi_subdevice *s,
701 struct comedi_insn *insn, unsigned int *data)
702 {
703 const struct dio200_layout *layout = dio200_dev_layout(dev);
704 struct dio200_subdev_intr *subpriv = s->private;
705
706 if (layout->has_int_sce) {
707 /* Just read the interrupt status register. */
708 data[1] = dio200_read8(dev, subpriv->ofs) & subpriv->valid_isns;
709 } else {
710 /* No interrupt status register. */
711 data[0] = 0;
712 }
713
714 return insn->n;
715 }
716
717 /*
718 * Called to stop acquisition for an 'INTERRUPT' subdevice.
719 */
720 static void dio200_stop_intr(struct comedi_device *dev,
721 struct comedi_subdevice *s)
722 {
723 const struct dio200_layout *layout = dio200_dev_layout(dev);
724 struct dio200_subdev_intr *subpriv = s->private;
725
726 subpriv->active = false;
727 subpriv->enabled_isns = 0;
728 if (layout->has_int_sce)
729 dio200_write8(dev, subpriv->ofs, 0);
730 }
731
732 /*
733 * Called to start acquisition for an 'INTERRUPT' subdevice.
734 */
735 static int dio200_start_intr(struct comedi_device *dev,
736 struct comedi_subdevice *s)
737 {
738 unsigned int n;
739 unsigned isn_bits;
740 const struct dio200_layout *layout = dio200_dev_layout(dev);
741 struct dio200_subdev_intr *subpriv = s->private;
742 struct comedi_cmd *cmd = &s->async->cmd;
743 int retval = 0;
744
745 if (!subpriv->continuous && subpriv->stopcount == 0) {
746 /* An empty acquisition! */
747 s->async->events |= COMEDI_CB_EOA;
748 subpriv->active = false;
749 retval = 1;
750 } else {
751 /* Determine interrupt sources to enable. */
752 isn_bits = 0;
753 if (cmd->chanlist) {
754 for (n = 0; n < cmd->chanlist_len; n++)
755 isn_bits |= (1U << CR_CHAN(cmd->chanlist[n]));
756 }
757 isn_bits &= subpriv->valid_isns;
758 /* Enable interrupt sources. */
759 subpriv->enabled_isns = isn_bits;
760 if (layout->has_int_sce)
761 dio200_write8(dev, subpriv->ofs, isn_bits);
762 }
763
764 return retval;
765 }
766
767 /*
768 * Internal trigger function to start acquisition for an 'INTERRUPT' subdevice.
769 */
770 static int
771 dio200_inttrig_start_intr(struct comedi_device *dev, struct comedi_subdevice *s,
772 unsigned int trignum)
773 {
774 struct dio200_subdev_intr *subpriv;
775 unsigned long flags;
776 int event = 0;
777
778 if (trignum != 0)
779 return -EINVAL;
780
781 subpriv = s->private;
782
783 spin_lock_irqsave(&subpriv->spinlock, flags);
784 s->async->inttrig = NULL;
785 if (subpriv->active)
786 event = dio200_start_intr(dev, s);
787
788 spin_unlock_irqrestore(&subpriv->spinlock, flags);
789
790 if (event)
791 comedi_event(dev, s);
792
793 return 1;
794 }
795
796 /*
797 * This is called from the interrupt service routine to handle a read
798 * scan on an 'INTERRUPT' subdevice.
799 */
800 static int dio200_handle_read_intr(struct comedi_device *dev,
801 struct comedi_subdevice *s)
802 {
803 const struct dio200_layout *layout = dio200_dev_layout(dev);
804 struct dio200_subdev_intr *subpriv = s->private;
805 unsigned triggered;
806 unsigned intstat;
807 unsigned cur_enabled;
808 unsigned int oldevents;
809 unsigned long flags;
810
811 triggered = 0;
812
813 spin_lock_irqsave(&subpriv->spinlock, flags);
814 oldevents = s->async->events;
815 if (layout->has_int_sce) {
816 /*
817 * Collect interrupt sources that have triggered and disable
818 * them temporarily. Loop around until no extra interrupt
819 * sources have triggered, at which point, the valid part of
820 * the interrupt status register will read zero, clearing the
821 * cause of the interrupt.
822 *
823 * Mask off interrupt sources already seen to avoid infinite
824 * loop in case of misconfiguration.
825 */
826 cur_enabled = subpriv->enabled_isns;
827 while ((intstat = (dio200_read8(dev, subpriv->ofs) &
828 subpriv->valid_isns & ~triggered)) != 0) {
829 triggered |= intstat;
830 cur_enabled &= ~triggered;
831 dio200_write8(dev, subpriv->ofs, cur_enabled);
832 }
833 } else {
834 /*
835 * No interrupt status register. Assume the single interrupt
836 * source has triggered.
837 */
838 triggered = subpriv->enabled_isns;
839 }
840
841 if (triggered) {
842 /*
843 * Some interrupt sources have triggered and have been
844 * temporarily disabled to clear the cause of the interrupt.
845 *
846 * Reenable them NOW to minimize the time they are disabled.
847 */
848 cur_enabled = subpriv->enabled_isns;
849 if (layout->has_int_sce)
850 dio200_write8(dev, subpriv->ofs, cur_enabled);
851
852 if (subpriv->active) {
853 /*
854 * The command is still active.
855 *
856 * Ignore interrupt sources that the command isn't
857 * interested in (just in case there's a race
858 * condition).
859 */
860 if (triggered & subpriv->enabled_isns) {
861 /* Collect scan data. */
862 short val;
863 unsigned int n, ch, len;
864
865 val = 0;
866 len = s->async->cmd.chanlist_len;
867 for (n = 0; n < len; n++) {
868 ch = CR_CHAN(s->async->cmd.chanlist[n]);
869 if (triggered & (1U << ch))
870 val |= (1U << n);
871 }
872 /* Write the scan to the buffer. */
873 if (comedi_buf_put(s->async, val)) {
874 s->async->events |= (COMEDI_CB_BLOCK |
875 COMEDI_CB_EOS);
876 } else {
877 /* Error! Stop acquisition. */
878 dio200_stop_intr(dev, s);
879 s->async->events |= COMEDI_CB_ERROR
880 | COMEDI_CB_OVERFLOW;
881 comedi_error(dev, "buffer overflow");
882 }
883
884 /* Check for end of acquisition. */
885 if (!subpriv->continuous) {
886 /* stop_src == TRIG_COUNT */
887 if (subpriv->stopcount > 0) {
888 subpriv->stopcount--;
889 if (subpriv->stopcount == 0) {
890 s->async->events |=
891 COMEDI_CB_EOA;
892 dio200_stop_intr(dev,
893 s);
894 }
895 }
896 }
897 }
898 }
899 }
900 spin_unlock_irqrestore(&subpriv->spinlock, flags);
901
902 if (oldevents != s->async->events)
903 comedi_event(dev, s);
904
905 return (triggered != 0);
906 }
907
908 /*
909 * 'cancel' function for an 'INTERRUPT' subdevice.
910 */
911 static int dio200_subdev_intr_cancel(struct comedi_device *dev,
912 struct comedi_subdevice *s)
913 {
914 struct dio200_subdev_intr *subpriv = s->private;
915 unsigned long flags;
916
917 spin_lock_irqsave(&subpriv->spinlock, flags);
918 if (subpriv->active)
919 dio200_stop_intr(dev, s);
920
921 spin_unlock_irqrestore(&subpriv->spinlock, flags);
922
923 return 0;
924 }
925
926 /*
927 * 'do_cmdtest' function for an 'INTERRUPT' subdevice.
928 */
929 static int
930 dio200_subdev_intr_cmdtest(struct comedi_device *dev,
931 struct comedi_subdevice *s, struct comedi_cmd *cmd)
932 {
933 int err = 0;
934
935 /* Step 1 : check if triggers are trivially valid */
936
937 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
938 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
939 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
940 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
941 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
942
943 if (err)
944 return 1;
945
946 /* Step 2a : make sure trigger sources are unique */
947
948 err |= cfc_check_trigger_is_unique(cmd->start_src);
949 err |= cfc_check_trigger_is_unique(cmd->stop_src);
950
951 /* Step 2b : and mutually compatible */
952
953 if (err)
954 return 2;
955
956 /* Step 3: check if arguments are trivially valid */
957
958 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
959 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
960 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
961 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
962
963 switch (cmd->stop_src) {
964 case TRIG_COUNT:
965 /* any count allowed */
966 break;
967 case TRIG_NONE:
968 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
969 break;
970 default:
971 break;
972 }
973
974 if (err)
975 return 3;
976
977 /* step 4: fix up any arguments */
978
979 /* if (err) return 4; */
980
981 return 0;
982 }
983
984 /*
985 * 'do_cmd' function for an 'INTERRUPT' subdevice.
986 */
987 static int dio200_subdev_intr_cmd(struct comedi_device *dev,
988 struct comedi_subdevice *s)
989 {
990 struct comedi_cmd *cmd = &s->async->cmd;
991 struct dio200_subdev_intr *subpriv = s->private;
992 unsigned long flags;
993 int event = 0;
994
995 spin_lock_irqsave(&subpriv->spinlock, flags);
996 subpriv->active = 1;
997
998 /* Set up end of acquisition. */
999 switch (cmd->stop_src) {
1000 case TRIG_COUNT:
1001 subpriv->continuous = false;
1002 subpriv->stopcount = cmd->stop_arg;
1003 break;
1004 default:
1005 /* TRIG_NONE */
1006 subpriv->continuous = true;
1007 subpriv->stopcount = 0;
1008 break;
1009 }
1010
1011 /* Set up start of acquisition. */
1012 switch (cmd->start_src) {
1013 case TRIG_INT:
1014 s->async->inttrig = dio200_inttrig_start_intr;
1015 break;
1016 default:
1017 /* TRIG_NOW */
1018 event = dio200_start_intr(dev, s);
1019 break;
1020 }
1021 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1022
1023 if (event)
1024 comedi_event(dev, s);
1025
1026 return 0;
1027 }
1028
1029 /*
1030 * This function initializes an 'INTERRUPT' subdevice.
1031 */
1032 static int
1033 dio200_subdev_intr_init(struct comedi_device *dev, struct comedi_subdevice *s,
1034 unsigned int offset, unsigned valid_isns)
1035 {
1036 const struct dio200_layout *layout = dio200_dev_layout(dev);
1037 struct dio200_subdev_intr *subpriv;
1038
1039 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1040 if (!subpriv)
1041 return -ENOMEM;
1042
1043 subpriv->ofs = offset;
1044 subpriv->valid_isns = valid_isns;
1045 spin_lock_init(&subpriv->spinlock);
1046
1047 if (layout->has_int_sce)
1048 /* Disable interrupt sources. */
1049 dio200_write8(dev, subpriv->ofs, 0);
1050
1051 s->private = subpriv;
1052 s->type = COMEDI_SUBD_DI;
1053 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
1054 if (layout->has_int_sce) {
1055 s->n_chan = DIO200_MAX_ISNS;
1056 s->len_chanlist = DIO200_MAX_ISNS;
1057 } else {
1058 /* No interrupt source register. Support single channel. */
1059 s->n_chan = 1;
1060 s->len_chanlist = 1;
1061 }
1062 s->range_table = &range_digital;
1063 s->maxdata = 1;
1064 s->insn_bits = dio200_subdev_intr_insn_bits;
1065 s->do_cmdtest = dio200_subdev_intr_cmdtest;
1066 s->do_cmd = dio200_subdev_intr_cmd;
1067 s->cancel = dio200_subdev_intr_cancel;
1068
1069 return 0;
1070 }
1071
1072 /*
1073 * This function cleans up an 'INTERRUPT' subdevice.
1074 */
1075 static void
1076 dio200_subdev_intr_cleanup(struct comedi_device *dev,
1077 struct comedi_subdevice *s)
1078 {
1079 struct dio200_subdev_intr *subpriv = s->private;
1080 kfree(subpriv);
1081 }
1082
1083 /*
1084 * Interrupt service routine.
1085 */
1086 static irqreturn_t dio200_interrupt(int irq, void *d)
1087 {
1088 struct comedi_device *dev = d;
1089 struct dio200_private *devpriv = dev->private;
1090 struct comedi_subdevice *s;
1091 int handled;
1092
1093 if (!dev->attached)
1094 return IRQ_NONE;
1095
1096 if (devpriv->intr_sd >= 0) {
1097 s = &dev->subdevices[devpriv->intr_sd];
1098 handled = dio200_handle_read_intr(dev, s);
1099 } else {
1100 handled = 0;
1101 }
1102
1103 return IRQ_RETVAL(handled);
1104 }
1105
1106 /*
1107 * Read an '8254' counter subdevice channel.
1108 */
1109 static unsigned int
1110 dio200_subdev_8254_read_chan(struct comedi_device *dev,
1111 struct comedi_subdevice *s, unsigned int chan)
1112 {
1113 struct dio200_subdev_8254 *subpriv = s->private;
1114 unsigned int val;
1115
1116 /* latch counter */
1117 val = chan << 6;
1118 dio200_write8(dev, subpriv->ofs + i8254_control_reg, val);
1119 /* read lsb, msb */
1120 val = dio200_read8(dev, subpriv->ofs + chan);
1121 val += dio200_read8(dev, subpriv->ofs + chan) << 8;
1122 return val;
1123 }
1124
1125 /*
1126 * Write an '8254' subdevice channel.
1127 */
1128 static void
1129 dio200_subdev_8254_write_chan(struct comedi_device *dev,
1130 struct comedi_subdevice *s, unsigned int chan,
1131 unsigned int count)
1132 {
1133 struct dio200_subdev_8254 *subpriv = s->private;
1134
1135 /* write lsb, msb */
1136 dio200_write8(dev, subpriv->ofs + chan, count & 0xff);
1137 dio200_write8(dev, subpriv->ofs + chan, (count >> 8) & 0xff);
1138 }
1139
1140 /*
1141 * Set mode of an '8254' subdevice channel.
1142 */
1143 static void
1144 dio200_subdev_8254_set_mode(struct comedi_device *dev,
1145 struct comedi_subdevice *s, unsigned int chan,
1146 unsigned int mode)
1147 {
1148 struct dio200_subdev_8254 *subpriv = s->private;
1149 unsigned int byte;
1150
1151 byte = chan << 6;
1152 byte |= 0x30; /* access order: lsb, msb */
1153 byte |= (mode & 0xf); /* counter mode and BCD|binary */
1154 dio200_write8(dev, subpriv->ofs + i8254_control_reg, byte);
1155 }
1156
1157 /*
1158 * Read status byte of an '8254' counter subdevice channel.
1159 */
1160 static unsigned int
1161 dio200_subdev_8254_status(struct comedi_device *dev,
1162 struct comedi_subdevice *s, unsigned int chan)
1163 {
1164 struct dio200_subdev_8254 *subpriv = s->private;
1165
1166 /* latch status */
1167 dio200_write8(dev, subpriv->ofs + i8254_control_reg,
1168 0xe0 | (2 << chan));
1169 /* read status */
1170 return dio200_read8(dev, subpriv->ofs + chan);
1171 }
1172
1173 /*
1174 * Handle 'insn_read' for an '8254' counter subdevice.
1175 */
1176 static int
1177 dio200_subdev_8254_read(struct comedi_device *dev, struct comedi_subdevice *s,
1178 struct comedi_insn *insn, unsigned int *data)
1179 {
1180 struct dio200_subdev_8254 *subpriv = s->private;
1181 int chan = CR_CHAN(insn->chanspec);
1182 unsigned int n;
1183 unsigned long flags;
1184
1185 for (n = 0; n < insn->n; n++) {
1186 spin_lock_irqsave(&subpriv->spinlock, flags);
1187 data[n] = dio200_subdev_8254_read_chan(dev, s, chan);
1188 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1189 }
1190 return insn->n;
1191 }
1192
1193 /*
1194 * Handle 'insn_write' for an '8254' counter subdevice.
1195 */
1196 static int
1197 dio200_subdev_8254_write(struct comedi_device *dev, struct comedi_subdevice *s,
1198 struct comedi_insn *insn, unsigned int *data)
1199 {
1200 struct dio200_subdev_8254 *subpriv = s->private;
1201 int chan = CR_CHAN(insn->chanspec);
1202 unsigned int n;
1203 unsigned long flags;
1204
1205 for (n = 0; n < insn->n; n++) {
1206 spin_lock_irqsave(&subpriv->spinlock, flags);
1207 dio200_subdev_8254_write_chan(dev, s, chan, data[n]);
1208 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1209 }
1210 return insn->n;
1211 }
1212
1213 /*
1214 * Set gate source for an '8254' counter subdevice channel.
1215 */
1216 static int
1217 dio200_subdev_8254_set_gate_src(struct comedi_device *dev,
1218 struct comedi_subdevice *s,
1219 unsigned int counter_number,
1220 unsigned int gate_src)
1221 {
1222 const struct dio200_layout *layout = dio200_dev_layout(dev);
1223 struct dio200_subdev_8254 *subpriv = s->private;
1224 unsigned char byte;
1225
1226 if (!layout->has_clk_gat_sce)
1227 return -1;
1228 if (counter_number > 2)
1229 return -1;
1230 if (gate_src > (layout->has_enhancements ? 31 : 7))
1231 return -1;
1232
1233 subpriv->gate_src[counter_number] = gate_src;
1234 byte = gat_sce(subpriv->which, counter_number, gate_src);
1235 dio200_write8(dev, subpriv->gat_sce_ofs, byte);
1236
1237 return 0;
1238 }
1239
1240 /*
1241 * Get gate source for an '8254' counter subdevice channel.
1242 */
1243 static int
1244 dio200_subdev_8254_get_gate_src(struct comedi_device *dev,
1245 struct comedi_subdevice *s,
1246 unsigned int counter_number)
1247 {
1248 const struct dio200_layout *layout = dio200_dev_layout(dev);
1249 struct dio200_subdev_8254 *subpriv = s->private;
1250
1251 if (!layout->has_clk_gat_sce)
1252 return -1;
1253 if (counter_number > 2)
1254 return -1;
1255
1256 return subpriv->gate_src[counter_number];
1257 }
1258
1259 /*
1260 * Set clock source for an '8254' counter subdevice channel.
1261 */
1262 static int
1263 dio200_subdev_8254_set_clock_src(struct comedi_device *dev,
1264 struct comedi_subdevice *s,
1265 unsigned int counter_number,
1266 unsigned int clock_src)
1267 {
1268 const struct dio200_layout *layout = dio200_dev_layout(dev);
1269 struct dio200_subdev_8254 *subpriv = s->private;
1270 unsigned char byte;
1271
1272 if (!layout->has_clk_gat_sce)
1273 return -1;
1274 if (counter_number > 2)
1275 return -1;
1276 if (clock_src > (layout->has_enhancements ? 31 : 7))
1277 return -1;
1278
1279 subpriv->clock_src[counter_number] = clock_src;
1280 byte = clk_sce(subpriv->which, counter_number, clock_src);
1281 dio200_write8(dev, subpriv->clk_sce_ofs, byte);
1282
1283 return 0;
1284 }
1285
1286 /*
1287 * Get clock source for an '8254' counter subdevice channel.
1288 */
1289 static int
1290 dio200_subdev_8254_get_clock_src(struct comedi_device *dev,
1291 struct comedi_subdevice *s,
1292 unsigned int counter_number,
1293 unsigned int *period_ns)
1294 {
1295 const struct dio200_layout *layout = dio200_dev_layout(dev);
1296 struct dio200_subdev_8254 *subpriv = s->private;
1297 unsigned clock_src;
1298
1299 if (!layout->has_clk_gat_sce)
1300 return -1;
1301 if (counter_number > 2)
1302 return -1;
1303
1304 clock_src = subpriv->clock_src[counter_number];
1305 *period_ns = clock_period[clock_src];
1306 return clock_src;
1307 }
1308
1309 /*
1310 * Handle 'insn_config' for an '8254' counter subdevice.
1311 */
1312 static int
1313 dio200_subdev_8254_config(struct comedi_device *dev, struct comedi_subdevice *s,
1314 struct comedi_insn *insn, unsigned int *data)
1315 {
1316 struct dio200_subdev_8254 *subpriv = s->private;
1317 int ret = 0;
1318 int chan = CR_CHAN(insn->chanspec);
1319 unsigned long flags;
1320
1321 spin_lock_irqsave(&subpriv->spinlock, flags);
1322 switch (data[0]) {
1323 case INSN_CONFIG_SET_COUNTER_MODE:
1324 if (data[1] > (I8254_MODE5 | I8254_BINARY))
1325 ret = -EINVAL;
1326 else
1327 dio200_subdev_8254_set_mode(dev, s, chan, data[1]);
1328 break;
1329 case INSN_CONFIG_8254_READ_STATUS:
1330 data[1] = dio200_subdev_8254_status(dev, s, chan);
1331 break;
1332 case INSN_CONFIG_SET_GATE_SRC:
1333 ret = dio200_subdev_8254_set_gate_src(dev, s, chan, data[2]);
1334 if (ret < 0)
1335 ret = -EINVAL;
1336 break;
1337 case INSN_CONFIG_GET_GATE_SRC:
1338 ret = dio200_subdev_8254_get_gate_src(dev, s, chan);
1339 if (ret < 0) {
1340 ret = -EINVAL;
1341 break;
1342 }
1343 data[2] = ret;
1344 break;
1345 case INSN_CONFIG_SET_CLOCK_SRC:
1346 ret = dio200_subdev_8254_set_clock_src(dev, s, chan, data[1]);
1347 if (ret < 0)
1348 ret = -EINVAL;
1349 break;
1350 case INSN_CONFIG_GET_CLOCK_SRC:
1351 ret = dio200_subdev_8254_get_clock_src(dev, s, chan, &data[2]);
1352 if (ret < 0) {
1353 ret = -EINVAL;
1354 break;
1355 }
1356 data[1] = ret;
1357 break;
1358 default:
1359 ret = -EINVAL;
1360 break;
1361 }
1362 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1363 return ret < 0 ? ret : insn->n;
1364 }
1365
1366 /*
1367 * This function initializes an '8254' counter subdevice.
1368 */
1369 static int
1370 dio200_subdev_8254_init(struct comedi_device *dev, struct comedi_subdevice *s,
1371 unsigned int offset)
1372 {
1373 const struct dio200_layout *layout = dio200_dev_layout(dev);
1374 struct dio200_subdev_8254 *subpriv;
1375 unsigned int chan;
1376
1377 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1378 if (!subpriv)
1379 return -ENOMEM;
1380
1381 s->private = subpriv;
1382 s->type = COMEDI_SUBD_COUNTER;
1383 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1384 s->n_chan = 3;
1385 s->maxdata = 0xFFFF;
1386 s->insn_read = dio200_subdev_8254_read;
1387 s->insn_write = dio200_subdev_8254_write;
1388 s->insn_config = dio200_subdev_8254_config;
1389
1390 spin_lock_init(&subpriv->spinlock);
1391 subpriv->ofs = offset;
1392 if (layout->has_clk_gat_sce) {
1393 /* Derive CLK_SCE and GAT_SCE register offsets from
1394 * 8254 offset. */
1395 subpriv->clk_sce_ofs = DIO200_XCLK_SCE + (offset >> 3);
1396 subpriv->gat_sce_ofs = DIO200_XGAT_SCE + (offset >> 3);
1397 subpriv->which = (offset >> 2) & 1;
1398 }
1399
1400 /* Initialize channels. */
1401 for (chan = 0; chan < 3; chan++) {
1402 dio200_subdev_8254_set_mode(dev, s, chan,
1403 I8254_MODE0 | I8254_BINARY);
1404 if (layout->has_clk_gat_sce) {
1405 /* Gate source 0 is VCC (logic 1). */
1406 dio200_subdev_8254_set_gate_src(dev, s, chan, 0);
1407 /* Clock source 0 is the dedicated clock input. */
1408 dio200_subdev_8254_set_clock_src(dev, s, chan, 0);
1409 }
1410 }
1411
1412 return 0;
1413 }
1414
1415 /*
1416 * This function cleans up an '8254' counter subdevice.
1417 */
1418 static void
1419 dio200_subdev_8254_cleanup(struct comedi_device *dev,
1420 struct comedi_subdevice *s)
1421 {
1422 struct dio200_subdev_intr *subpriv = s->private;
1423 kfree(subpriv);
1424 }
1425
1426 /*
1427 * This function sets I/O directions for an '8255' DIO subdevice.
1428 */
1429 static void dio200_subdev_8255_set_dir(struct comedi_device *dev,
1430 struct comedi_subdevice *s)
1431 {
1432 struct dio200_subdev_8255 *subpriv = s->private;
1433 int config;
1434
1435 config = CR_CW;
1436 /* 1 in io_bits indicates output, 1 in config indicates input */
1437 if (!(s->io_bits & 0x0000ff))
1438 config |= CR_A_IO;
1439 if (!(s->io_bits & 0x00ff00))
1440 config |= CR_B_IO;
1441 if (!(s->io_bits & 0x0f0000))
1442 config |= CR_C_LO_IO;
1443 if (!(s->io_bits & 0xf00000))
1444 config |= CR_C_HI_IO;
1445 dio200_write8(dev, subpriv->ofs + 3, config);
1446 }
1447
1448 /*
1449 * Handle 'insn_bits' for an '8255' DIO subdevice.
1450 */
1451 static int dio200_subdev_8255_bits(struct comedi_device *dev,
1452 struct comedi_subdevice *s,
1453 struct comedi_insn *insn, unsigned int *data)
1454 {
1455 struct dio200_subdev_8255 *subpriv = s->private;
1456
1457 if (data[0]) {
1458 s->state &= ~data[0];
1459 s->state |= (data[0] & data[1]);
1460 if (data[0] & 0xff)
1461 dio200_write8(dev, subpriv->ofs, s->state & 0xff);
1462 if (data[0] & 0xff00)
1463 dio200_write8(dev, subpriv->ofs + 1,
1464 (s->state >> 8) & 0xff);
1465 if (data[0] & 0xff0000)
1466 dio200_write8(dev, subpriv->ofs + 2,
1467 (s->state >> 16) & 0xff);
1468 }
1469 data[1] = dio200_read8(dev, subpriv->ofs);
1470 data[1] |= dio200_read8(dev, subpriv->ofs + 1) << 8;
1471 data[1] |= dio200_read8(dev, subpriv->ofs + 2) << 16;
1472 return 2;
1473 }
1474
1475 /*
1476 * Handle 'insn_config' for an '8255' DIO subdevice.
1477 */
1478 static int dio200_subdev_8255_config(struct comedi_device *dev,
1479 struct comedi_subdevice *s,
1480 struct comedi_insn *insn,
1481 unsigned int *data)
1482 {
1483 unsigned int mask;
1484 unsigned int bits;
1485
1486 mask = 1 << CR_CHAN(insn->chanspec);
1487 if (mask & 0x0000ff)
1488 bits = 0x0000ff;
1489 else if (mask & 0x00ff00)
1490 bits = 0x00ff00;
1491 else if (mask & 0x0f0000)
1492 bits = 0x0f0000;
1493 else
1494 bits = 0xf00000;
1495 switch (data[0]) {
1496 case INSN_CONFIG_DIO_INPUT:
1497 s->io_bits &= ~bits;
1498 break;
1499 case INSN_CONFIG_DIO_OUTPUT:
1500 s->io_bits |= bits;
1501 break;
1502 case INSN_CONFIG_DIO_QUERY:
1503 data[1] = (s->io_bits & bits) ? COMEDI_OUTPUT : COMEDI_INPUT;
1504 return insn->n;
1505 break;
1506 default:
1507 return -EINVAL;
1508 }
1509 dio200_subdev_8255_set_dir(dev, s);
1510 return 1;
1511 }
1512
1513 /*
1514 * This function initializes an '8255' DIO subdevice.
1515 *
1516 * offset is the offset to the 8255 chip.
1517 */
1518 static int dio200_subdev_8255_init(struct comedi_device *dev,
1519 struct comedi_subdevice *s,
1520 unsigned int offset)
1521 {
1522 struct dio200_subdev_8255 *subpriv;
1523
1524 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1525 if (!subpriv)
1526 return -ENOMEM;
1527 subpriv->ofs = offset;
1528 s->private = subpriv;
1529 s->type = COMEDI_SUBD_DIO;
1530 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1531 s->n_chan = 24;
1532 s->range_table = &range_digital;
1533 s->maxdata = 1;
1534 s->insn_bits = dio200_subdev_8255_bits;
1535 s->insn_config = dio200_subdev_8255_config;
1536 s->state = 0;
1537 s->io_bits = 0;
1538 dio200_subdev_8255_set_dir(dev, s);
1539 return 0;
1540 }
1541
1542 /*
1543 * This function cleans up an '8255' DIO subdevice.
1544 */
1545 static void dio200_subdev_8255_cleanup(struct comedi_device *dev,
1546 struct comedi_subdevice *s)
1547 {
1548 struct dio200_subdev_8255 *subpriv = s->private;
1549
1550 kfree(subpriv);
1551 }
1552
1553 /*
1554 * Handle 'insn_read' for a timer subdevice.
1555 */
1556 static int dio200_subdev_timer_read(struct comedi_device *dev,
1557 struct comedi_subdevice *s,
1558 struct comedi_insn *insn,
1559 unsigned int *data)
1560 {
1561 unsigned int n;
1562
1563 for (n = 0; n < insn->n; n++)
1564 data[n] = dio200_read32(dev, DIO200_TS_COUNT);
1565 return n;
1566 }
1567
1568 /*
1569 * Reset timer subdevice.
1570 */
1571 static void dio200_subdev_timer_reset(struct comedi_device *dev,
1572 struct comedi_subdevice *s)
1573 {
1574 unsigned int clock;
1575
1576 clock = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1577 dio200_write32(dev, DIO200_TS_CONFIG, clock | TS_CONFIG_RESET);
1578 dio200_write32(dev, DIO200_TS_CONFIG, clock);
1579 }
1580
1581 /*
1582 * Get timer subdevice clock source and period.
1583 */
1584 static void dio200_subdev_timer_get_clock_src(struct comedi_device *dev,
1585 struct comedi_subdevice *s,
1586 unsigned int *src,
1587 unsigned int *period)
1588 {
1589 unsigned int clk;
1590
1591 clk = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1592 *src = clk;
1593 *period = (clk < ARRAY_SIZE(ts_clock_period)) ?
1594 ts_clock_period[clk] : 0;
1595 }
1596
1597 /*
1598 * Set timer subdevice clock source.
1599 */
1600 static int dio200_subdev_timer_set_clock_src(struct comedi_device *dev,
1601 struct comedi_subdevice *s,
1602 unsigned int src)
1603 {
1604 if (src > TS_CONFIG_MAX_CLK_SRC)
1605 return -EINVAL;
1606 dio200_write32(dev, DIO200_TS_CONFIG, src);
1607 return 0;
1608 }
1609
1610 /*
1611 * Handle 'insn_config' for a timer subdevice.
1612 */
1613 static int dio200_subdev_timer_config(struct comedi_device *dev,
1614 struct comedi_subdevice *s,
1615 struct comedi_insn *insn,
1616 unsigned int *data)
1617 {
1618 int ret = 0;
1619
1620 switch (data[0]) {
1621 case INSN_CONFIG_RESET:
1622 dio200_subdev_timer_reset(dev, s);
1623 break;
1624 case INSN_CONFIG_SET_CLOCK_SRC:
1625 ret = dio200_subdev_timer_set_clock_src(dev, s, data[1]);
1626 if (ret < 0)
1627 ret = -EINVAL;
1628 break;
1629 case INSN_CONFIG_GET_CLOCK_SRC:
1630 dio200_subdev_timer_get_clock_src(dev, s, &data[1], &data[2]);
1631 break;
1632 default:
1633 ret = -EINVAL;
1634 break;
1635 }
1636 return ret < 0 ? ret : insn->n;
1637 }
1638
1639 /*
1640 * This function initializes a timer subdevice.
1641 *
1642 * Uses the timestamp timer registers. There is only one timestamp timer.
1643 */
1644 static int dio200_subdev_timer_init(struct comedi_device *dev,
1645 struct comedi_subdevice *s)
1646 {
1647 s->type = COMEDI_SUBD_TIMER;
1648 s->subdev_flags = SDF_READABLE | SDF_LSAMPL;
1649 s->n_chan = 1;
1650 s->maxdata = 0xFFFFFFFF;
1651 s->insn_read = dio200_subdev_timer_read;
1652 s->insn_config = dio200_subdev_timer_config;
1653 return 0;
1654 }
1655
1656 /*
1657 * This function cleans up a timer subdevice.
1658 */
1659 static void dio200_subdev_timer_cleanup(struct comedi_device *dev,
1660 struct comedi_subdevice *s)
1661 {
1662 /* Nothing to do. */
1663 }
1664
1665 /*
1666 * This function does some special set-up for the PCIe boards
1667 * PCIe215, PCIe236, PCIe296.
1668 */
1669 static int dio200_pcie_board_setup(struct comedi_device *dev)
1670 {
1671 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1672 void __iomem *brbase;
1673 resource_size_t brlen;
1674
1675 /*
1676 * The board uses Altera Cyclone IV with PCI-Express hard IP.
1677 * The FPGA configuration has the PCI-Express Avalon-MM Bridge
1678 * Control registers in PCI BAR 0, offset 0, and the length of
1679 * these registers is 0x4000.
1680 *
1681 * We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt
1682 * Enable" register at offset 0x50 to allow generation of PCIe
1683 * interrupts when RXmlrq_i is asserted in the SOPC Builder system.
1684 */
1685 brlen = pci_resource_len(pcidev, 0);
1686 if (brlen < 0x4000 ||
1687 !(pci_resource_flags(pcidev, 0) & IORESOURCE_MEM)) {
1688 dev_err(dev->class_dev, "error! bad PCI region!\n");
1689 return -EINVAL;
1690 }
1691 brbase = ioremap_nocache(pci_resource_start(pcidev, 0), brlen);
1692 if (!brbase) {
1693 dev_err(dev->class_dev, "error! failed to map registers!\n");
1694 return -ENOMEM;
1695 }
1696 writel(0x80, brbase + 0x50);
1697 iounmap(brbase);
1698 /* Enable "enhanced" features of board. */
1699 dio200_write8(dev, DIO200_ENHANCE, 1);
1700 return 0;
1701 }
1702
1703 static void dio200_report_attach(struct comedi_device *dev, unsigned int irq)
1704 {
1705 const struct dio200_board *thisboard = comedi_board(dev);
1706 struct dio200_private *devpriv = dev->private;
1707 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1708 char tmpbuf[60];
1709 int tmplen;
1710
1711 if (is_isa_board(thisboard))
1712 tmplen = scnprintf(tmpbuf, sizeof(tmpbuf),
1713 "(base %#lx) ", devpriv->io.u.iobase);
1714 else if (is_pci_board(thisboard))
1715 tmplen = scnprintf(tmpbuf, sizeof(tmpbuf),
1716 "(pci %s) ", pci_name(pcidev));
1717 else
1718 tmplen = 0;
1719 if (irq)
1720 tmplen += scnprintf(&tmpbuf[tmplen], sizeof(tmpbuf) - tmplen,
1721 "(irq %u%s) ", irq,
1722 (dev->irq ? "" : " UNAVAILABLE"));
1723 else
1724 tmplen += scnprintf(&tmpbuf[tmplen], sizeof(tmpbuf) - tmplen,
1725 "(no irq) ");
1726 dev_info(dev->class_dev, "%s %sattached\n", dev->board_name, tmpbuf);
1727 }
1728
1729 static int dio200_common_attach(struct comedi_device *dev, unsigned int irq,
1730 unsigned long req_irq_flags)
1731 {
1732 const struct dio200_board *thisboard = comedi_board(dev);
1733 struct dio200_private *devpriv = dev->private;
1734 const struct dio200_layout *layout = dio200_board_layout(thisboard);
1735 struct comedi_subdevice *s;
1736 int sdx;
1737 unsigned int n;
1738 int ret;
1739
1740 devpriv->intr_sd = -1;
1741
1742 ret = comedi_alloc_subdevices(dev, layout->n_subdevs);
1743 if (ret)
1744 return ret;
1745
1746 for (n = 0; n < dev->n_subdevices; n++) {
1747 s = &dev->subdevices[n];
1748 switch (layout->sdtype[n]) {
1749 case sd_8254:
1750 /* counter subdevice (8254) */
1751 ret = dio200_subdev_8254_init(dev, s,
1752 layout->sdinfo[n]);
1753 if (ret < 0)
1754 return ret;
1755 break;
1756 case sd_8255:
1757 /* digital i/o subdevice (8255) */
1758 ret = dio200_subdev_8255_init(dev, s,
1759 layout->sdinfo[n]);
1760 if (ret < 0)
1761 return ret;
1762 break;
1763 case sd_intr:
1764 /* 'INTERRUPT' subdevice */
1765 if (irq) {
1766 ret = dio200_subdev_intr_init(dev, s,
1767 DIO200_INT_SCE,
1768 layout->sdinfo[n]
1769 );
1770 if (ret < 0)
1771 return ret;
1772 devpriv->intr_sd = n;
1773 } else {
1774 s->type = COMEDI_SUBD_UNUSED;
1775 }
1776 break;
1777 case sd_timer:
1778 /* Only on PCIe boards. */
1779 if (DO_PCI) {
1780 ret = dio200_subdev_timer_init(dev, s);
1781 if (ret < 0)
1782 return ret;
1783 } else {
1784 s->type = COMEDI_SUBD_UNUSED;
1785 }
1786 break;
1787 default:
1788 s->type = COMEDI_SUBD_UNUSED;
1789 break;
1790 }
1791 }
1792 sdx = devpriv->intr_sd;
1793 if (sdx >= 0 && sdx < dev->n_subdevices)
1794 dev->read_subdev = &dev->subdevices[sdx];
1795 if (irq) {
1796 if (request_irq(irq, dio200_interrupt, req_irq_flags,
1797 DIO200_DRIVER_NAME, dev) >= 0) {
1798 dev->irq = irq;
1799 } else {
1800 dev_warn(dev->class_dev,
1801 "warning! irq %u unavailable!\n", irq);
1802 }
1803 }
1804 dio200_report_attach(dev, irq);
1805 return 0;
1806 }
1807
1808 /* Only called for ISA boards. */
1809 static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1810 {
1811 const struct dio200_board *thisboard = comedi_board(dev);
1812 struct dio200_private *devpriv;
1813 unsigned long iobase;
1814 unsigned int irq;
1815 int ret;
1816
1817 if (!DO_ISA)
1818 return -EINVAL;
1819
1820 dev->board_name = thisboard->name;
1821 dev_info(dev->class_dev, DIO200_DRIVER_NAME ": attach\n");
1822
1823 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1824 if (!devpriv)
1825 return -ENOMEM;
1826 dev->private = devpriv;
1827
1828 iobase = it->options[0];
1829 irq = it->options[1];
1830 ret = dio200_request_region(dev, iobase, thisboard->mainsize);
1831 if (ret < 0)
1832 return ret;
1833 devpriv->io.u.iobase = iobase;
1834 devpriv->io.regtype = io_regtype;
1835 return dio200_common_attach(dev, irq, 0);
1836 }
1837
1838 /*
1839 * The auto_attach hook is called at PCI probe time via
1840 * comedi_pci_auto_config(). dev->board_ptr is NULL on entry.
1841 * The context should be an index into dio200_pci_boards[].
1842 */
1843 static int dio200_auto_attach(struct comedi_device *dev,
1844 unsigned long context_model)
1845 {
1846 struct pci_dev *pci_dev = comedi_to_pci_dev(dev);
1847 const struct dio200_board *thisboard = NULL;
1848 struct dio200_private *devpriv;
1849 resource_size_t base, len;
1850 unsigned int bar;
1851 int ret;
1852
1853 if (!DO_PCI)
1854 return -EINVAL;
1855
1856 if (context_model < ARRAY_SIZE(dio200_pci_boards))
1857 thisboard = &dio200_pci_boards[context_model];
1858 if (!thisboard)
1859 return -EINVAL;
1860 dev->board_ptr = thisboard;
1861 dev->board_name = thisboard->name;
1862
1863 dev_info(dev->class_dev, DIO200_DRIVER_NAME ": attach pci %s\n",
1864 pci_name(pci_dev));
1865
1866 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1867 if (!devpriv)
1868 return -ENOMEM;
1869 dev->private = devpriv;
1870
1871 ret = comedi_pci_enable(dev);
1872 if (ret)
1873 return ret;
1874
1875 bar = thisboard->mainbar;
1876 base = pci_resource_start(pci_dev, bar);
1877 len = pci_resource_len(pci_dev, bar);
1878 if (len < thisboard->mainsize) {
1879 dev_err(dev->class_dev, "error! PCI region size too small!\n");
1880 return -EINVAL;
1881 }
1882 if ((pci_resource_flags(pci_dev, bar) & IORESOURCE_MEM) != 0) {
1883 devpriv->io.u.membase = ioremap_nocache(base, len);
1884 if (!devpriv->io.u.membase) {
1885 dev_err(dev->class_dev,
1886 "error! cannot remap registers\n");
1887 return -ENOMEM;
1888 }
1889 devpriv->io.regtype = mmio_regtype;
1890 } else {
1891 devpriv->io.u.iobase = (unsigned long)base;
1892 devpriv->io.regtype = io_regtype;
1893 }
1894 switch (context_model) {
1895 case pcie215_model:
1896 case pcie236_model:
1897 case pcie296_model:
1898 ret = dio200_pcie_board_setup(dev);
1899 if (ret < 0)
1900 return ret;
1901 break;
1902 default:
1903 break;
1904 }
1905 return dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED);
1906 }
1907
1908 static void dio200_detach(struct comedi_device *dev)
1909 {
1910 const struct dio200_board *thisboard = comedi_board(dev);
1911 struct dio200_private *devpriv = dev->private;
1912 const struct dio200_layout *layout;
1913 unsigned n;
1914
1915 if (!thisboard || !devpriv)
1916 return;
1917 if (dev->irq)
1918 free_irq(dev->irq, dev);
1919 if (dev->subdevices) {
1920 layout = dio200_board_layout(thisboard);
1921 for (n = 0; n < dev->n_subdevices; n++) {
1922 struct comedi_subdevice *s = &dev->subdevices[n];
1923 switch (layout->sdtype[n]) {
1924 case sd_8254:
1925 dio200_subdev_8254_cleanup(dev, s);
1926 break;
1927 case sd_8255:
1928 dio200_subdev_8255_cleanup(dev, s);
1929 break;
1930 case sd_intr:
1931 dio200_subdev_intr_cleanup(dev, s);
1932 break;
1933 case sd_timer:
1934 /* Only on PCIe boards. */
1935 if (DO_PCI)
1936 dio200_subdev_timer_cleanup(dev, s);
1937 break;
1938 default:
1939 break;
1940 }
1941 }
1942 }
1943 if (is_isa_board(thisboard)) {
1944 if (devpriv->io.regtype == io_regtype)
1945 release_region(devpriv->io.u.iobase,
1946 thisboard->mainsize);
1947 } else if (is_pci_board(thisboard)) {
1948 if (devpriv->io.regtype == mmio_regtype)
1949 iounmap(devpriv->io.u.membase);
1950 comedi_pci_disable(dev);
1951 }
1952 }
1953
1954 /*
1955 * The struct comedi_driver structure tells the Comedi core module
1956 * which functions to call to configure/deconfigure (attach/detach)
1957 * the board, and also about the kernel module that contains
1958 * the device code.
1959 */
1960 static struct comedi_driver amplc_dio200_driver = {
1961 .driver_name = DIO200_DRIVER_NAME,
1962 .module = THIS_MODULE,
1963 .attach = dio200_attach,
1964 .auto_attach = dio200_auto_attach,
1965 .detach = dio200_detach,
1966 #if DO_ISA
1967 .board_name = &dio200_isa_boards[0].name,
1968 .offset = sizeof(struct dio200_board),
1969 .num_names = ARRAY_SIZE(dio200_isa_boards),
1970 #endif
1971 };
1972
1973 #if DO_PCI
1974 static DEFINE_PCI_DEVICE_TABLE(dio200_pci_table) = {
1975 {
1976 PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI215),
1977 pci215_model
1978 }, {
1979 PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI272),
1980 pci272_model
1981 }, {
1982 PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE236),
1983 pcie236_model
1984 }, {
1985 PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE215),
1986 pcie215_model
1987 }, {
1988 PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE296),
1989 pcie296_model
1990 },
1991 {0}
1992 };
1993
1994 MODULE_DEVICE_TABLE(pci, dio200_pci_table);
1995
1996 static int amplc_dio200_pci_probe(struct pci_dev *dev,
1997 const struct pci_device_id *id)
1998 {
1999 return comedi_pci_auto_config(dev, &amplc_dio200_driver,
2000 id->driver_data);
2001 }
2002
2003 static struct pci_driver amplc_dio200_pci_driver = {
2004 .name = DIO200_DRIVER_NAME,
2005 .id_table = dio200_pci_table,
2006 .probe = &amplc_dio200_pci_probe,
2007 .remove = comedi_pci_auto_unconfig,
2008 };
2009 module_comedi_pci_driver(amplc_dio200_driver, amplc_dio200_pci_driver);
2010 #else
2011 module_comedi_driver(amplc_dio200_driver);
2012 #endif
2013
2014 MODULE_AUTHOR("Comedi http://www.comedi.org");
2015 MODULE_DESCRIPTION("Comedi low-level driver");
2016 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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