2 comedi/drivers/cb_pcidas64.c
3 This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
4 64xx, 60xx, and 4020 cards.
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2001, 2002 Frank Mori Hess
9 Thanks also go to the following people:
11 Steve Rosenbluth, for providing the source code for
12 his pci-das6402 driver, and source code for working QNX pci-6402
13 drivers by Greg Laird and Mariusz Bogacz. None of the code was
14 used directly here, but it was useful as an additional source of
15 documentation on how to program the boards.
17 John Sims, for much testing and feedback on pcidas-4020 support.
19 COMEDI - Linux Control and Measurement Device Interface
20 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
22 This program is free software; you can redistribute it and/or modify
23 it under the terms of the GNU General Public License as published by
24 the Free Software Foundation; either version 2 of the License, or
25 (at your option) any later version.
27 This program is distributed in the hope that it will be useful,
28 but WITHOUT ANY WARRANTY; without even the implied warranty of
29 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 GNU General Public License for more details.
32 You should have received a copy of the GNU General Public License
33 along with this program; if not, write to the Free Software
34 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
36 ************************************************************************/
41 Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series with the PLX 9080 PCI controller
42 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
45 Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
46 PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
47 PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
48 PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
49 PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
50 PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
51 PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
52 PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
53 PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
55 Configuration options:
56 [0] - PCI bus of device (optional)
57 [1] - PCI slot of device (optional)
59 These boards may be autocalibrated with the comedi_calibrate utility.
61 To select the bnc trigger input on the 4020 (instead of the dio input),
62 specify a nonzero channel in the chanspec. If you wish to use an external
63 master clock on the 4020, you may do so by setting the scan_begin_src
64 to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
65 to configure the divisor to use for the external clock.
67 Some devices are not identified because the PCI device IDs are not yet
68 known. If you have such a board, please file a bug report at
69 https://bugs.comedi.org.
76 make it return error if user attempts an ai command that uses the
77 external queue, and an ao command simultaneously
78 user counter subdevice
79 there are a number of boards this driver will support when they are
80 fully released, but does not yet since the pci device id numbers
81 are not yet available.
82 support prescaled 100khz clock for slow pacing (not available on 6000 series?)
83 make ao fifo size adjustable like ai fifo
86 #include "../comedidev.h"
87 #include <linux/delay.h>
88 #include <linux/interrupt.h>
93 #include "comedi_fc.h"
95 #undef PCIDAS64_DEBUG /* disable debugging code */
96 /* #define PCIDAS64_DEBUG enable debugging code */
99 #define DEBUG_PRINT(format, args...) printk(format , ## args)
101 #define DEBUG_PRINT(format, args...)
104 #define TIMER_BASE 25 /* 40MHz master clock */
105 #define PRESCALED_TIMER_BASE 10000 /* 100kHz 'prescaled' clock for slow acquisition, maybe I'll support this someday */
106 #define DMA_BUFFER_SIZE 0x1000
108 #define PCI_VENDOR_ID_COMPUTERBOARDS 0x1307
110 /* maximum value that can be loaded into board's 24-bit counters*/
111 static const int max_counter_value
= 0xffffff;
113 /* PCI-DAS64xxx base addresses */
115 /* indices of base address regions */
116 enum base_address_regions
{
117 PLX9080_BADDRINDEX
= 0,
119 DIO_COUNTER_BADDRINDEX
= 3,
122 /* devpriv->main_iobase registers */
123 enum write_only_registers
{
124 INTR_ENABLE_REG
= 0x0, /* interrupt enable register */
125 HW_CONFIG_REG
= 0x2, /* hardware config register */
127 DAQ_ATRIG_LOW_4020_REG
= 0xc,
128 ADC_CONTROL0_REG
= 0x10, /* adc control register 0 */
129 ADC_CONTROL1_REG
= 0x12, /* adc control register 1 */
130 CALIBRATION_REG
= 0x14,
131 ADC_SAMPLE_INTERVAL_LOWER_REG
= 0x16, /* lower 16 bits of adc sample interval counter */
132 ADC_SAMPLE_INTERVAL_UPPER_REG
= 0x18, /* upper 8 bits of adc sample interval counter */
133 ADC_DELAY_INTERVAL_LOWER_REG
= 0x1a, /* lower 16 bits of delay interval counter */
134 ADC_DELAY_INTERVAL_UPPER_REG
= 0x1c, /* upper 8 bits of delay interval counter */
135 ADC_COUNT_LOWER_REG
= 0x1e, /* lower 16 bits of hardware conversion/scan counter */
136 ADC_COUNT_UPPER_REG
= 0x20, /* upper 8 bits of hardware conversion/scan counter */
137 ADC_START_REG
= 0x22, /* software trigger to start acquisition */
138 ADC_CONVERT_REG
= 0x24, /* initiates single conversion */
139 ADC_QUEUE_CLEAR_REG
= 0x26, /* clears adc queue */
140 ADC_QUEUE_LOAD_REG
= 0x28, /* loads adc queue */
141 ADC_BUFFER_CLEAR_REG
= 0x2a,
142 ADC_QUEUE_HIGH_REG
= 0x2c, /* high channel for internal queue, use adc_chan_bits() inline above */
143 DAC_CONTROL0_REG
= 0x50, /* dac control register 0 */
144 DAC_CONTROL1_REG
= 0x52, /* dac control register 0 */
145 DAC_SAMPLE_INTERVAL_LOWER_REG
= 0x54, /* lower 16 bits of dac sample interval counter */
146 DAC_SAMPLE_INTERVAL_UPPER_REG
= 0x56, /* upper 8 bits of dac sample interval counter */
147 DAC_SELECT_REG
= 0x60,
148 DAC_START_REG
= 0x64,
149 DAC_BUFFER_CLEAR_REG
= 0x66, /* clear dac buffer */
151 static inline unsigned int dac_convert_reg(unsigned int channel
)
153 return 0x70 + (2 * (channel
& 0x1));
156 static inline unsigned int dac_lsb_4020_reg(unsigned int channel
)
158 return 0x70 + (4 * (channel
& 0x1));
161 static inline unsigned int dac_msb_4020_reg(unsigned int channel
)
163 return 0x72 + (4 * (channel
& 0x1));
166 enum read_only_registers
{
167 HW_STATUS_REG
= 0x0, /* hardware status register, reading this apparently clears pending interrupts as well */
168 PIPE1_READ_REG
= 0x4,
169 ADC_READ_PNTR_REG
= 0x8,
170 LOWER_XFER_REG
= 0x10,
171 ADC_WRITE_PNTR_REG
= 0xc,
175 enum read_write_registers
{
176 I8255_4020_REG
= 0x48, /* 8255 offset, for 4020 only */
177 ADC_QUEUE_FIFO_REG
= 0x100, /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
178 ADC_FIFO_REG
= 0x200, /* adc data fifo */
179 DAC_FIFO_REG
= 0x300, /* dac data fifo, has weird interactions with external channel queue */
182 /* devpriv->dio_counter_iobase registers */
183 enum dio_counter_registers
{
184 DIO_8255_OFFSET
= 0x0,
187 DIO_DIRECTION_60XX_REG
= 0x40,
188 DIO_DATA_60XX_REG
= 0x48,
191 /* bit definitions for write-only registers */
193 enum intr_enable_contents
{
194 ADC_INTR_SRC_MASK
= 0x3, /* bits that set adc interrupt source */
195 ADC_INTR_QFULL_BITS
= 0x0, /* interrupt fifo quater full */
196 ADC_INTR_EOC_BITS
= 0x1, /* interrupt end of conversion */
197 ADC_INTR_EOSCAN_BITS
= 0x2, /* interrupt end of scan */
198 ADC_INTR_EOSEQ_BITS
= 0x3, /* interrupt end of sequence (probably wont use this it's pretty fancy) */
199 EN_ADC_INTR_SRC_BIT
= 0x4, /* enable adc interrupt source */
200 EN_ADC_DONE_INTR_BIT
= 0x8, /* enable adc acquisition done interrupt */
201 DAC_INTR_SRC_MASK
= 0x30,
202 DAC_INTR_QEMPTY_BITS
= 0x0,
203 DAC_INTR_HIGH_CHAN_BITS
= 0x10,
204 EN_DAC_INTR_SRC_BIT
= 0x40, /* enable dac interrupt source */
205 EN_DAC_DONE_INTR_BIT
= 0x80,
206 EN_ADC_ACTIVE_INTR_BIT
= 0x200, /* enable adc active interrupt */
207 EN_ADC_STOP_INTR_BIT
= 0x400, /* enable adc stop trigger interrupt */
208 EN_DAC_ACTIVE_INTR_BIT
= 0x800, /* enable dac active interrupt */
209 EN_DAC_UNDERRUN_BIT
= 0x4000, /* enable dac underrun status bit */
210 EN_ADC_OVERRUN_BIT
= 0x8000, /* enable adc overrun status bit */
213 enum hw_config_contents
{
214 MASTER_CLOCK_4020_MASK
= 0x3, /* bits that specify master clock source for 4020 */
215 INTERNAL_CLOCK_4020_BITS
= 0x1, /* use 40 MHz internal master clock for 4020 */
216 BNC_CLOCK_4020_BITS
= 0x2, /* use BNC input for master clock */
217 EXT_CLOCK_4020_BITS
= 0x3, /* use dio input for master clock */
218 EXT_QUEUE_BIT
= 0x200, /* use external channel/gain queue (more versatile than internal queue) */
219 SLOW_DAC_BIT
= 0x400, /* use 225 nanosec strobe when loading dac instead of 50 nanosec */
220 HW_CONFIG_DUMMY_BITS
= 0x2000, /* bit with unknown function yet given as default value in pci-das64 manual */
221 DMA_CH_SELECT_BIT
= 0x8000, /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */
222 FIFO_SIZE_REG
= 0x4, /* allows adjustment of fifo sizes */
223 DAC_FIFO_SIZE_MASK
= 0xff00, /* bits that set dac fifo size */
224 DAC_FIFO_BITS
= 0xf800, /* 8k sample ao fifo */
226 #define DAC_FIFO_SIZE 0x2000
228 enum daq_atrig_low_4020_contents
{
229 EXT_AGATE_BNC_BIT
= 0x8000, /* use trig/ext clk bnc input for analog gate signal */
230 EXT_STOP_TRIG_BNC_BIT
= 0x4000, /* use trig/ext clk bnc input for external stop trigger signal */
231 EXT_START_TRIG_BNC_BIT
= 0x2000, /* use trig/ext clk bnc input for external start trigger signal */
233 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold
)
235 return threshold
& 0xfff;
238 enum adc_control0_contents
{
239 ADC_GATE_SRC_MASK
= 0x3, /* bits that select gate */
240 ADC_SOFT_GATE_BITS
= 0x1, /* software gate */
241 ADC_EXT_GATE_BITS
= 0x2, /* external digital gate */
242 ADC_ANALOG_GATE_BITS
= 0x3, /* analog level gate */
243 ADC_GATE_LEVEL_BIT
= 0x4, /* level-sensitive gate (for digital) */
244 ADC_GATE_POLARITY_BIT
= 0x8, /* gate active low */
245 ADC_START_TRIG_SOFT_BITS
= 0x10,
246 ADC_START_TRIG_EXT_BITS
= 0x20,
247 ADC_START_TRIG_ANALOG_BITS
= 0x30,
248 ADC_START_TRIG_MASK
= 0x30,
249 ADC_START_TRIG_FALLING_BIT
= 0x40, /* trig 1 uses falling edge */
250 ADC_EXT_CONV_FALLING_BIT
= 0x800, /* external pacing uses falling edge */
251 ADC_SAMPLE_COUNTER_EN_BIT
= 0x1000, /* enable hardware scan counter */
252 ADC_DMA_DISABLE_BIT
= 0x4000, /* disables dma */
253 ADC_ENABLE_BIT
= 0x8000, /* master adc enable */
256 enum adc_control1_contents
{
257 ADC_QUEUE_CONFIG_BIT
= 0x1, /* should be set for boards with > 16 channels */
258 CONVERT_POLARITY_BIT
= 0x10,
259 EOC_POLARITY_BIT
= 0x20,
260 ADC_SW_GATE_BIT
= 0x40, /* software gate of adc */
261 ADC_DITHER_BIT
= 0x200, /* turn on extra noise for dithering */
262 RETRIGGER_BIT
= 0x800,
263 ADC_LO_CHANNEL_4020_MASK
= 0x300,
264 ADC_HI_CHANNEL_4020_MASK
= 0xc00,
265 TWO_CHANNEL_4020_BITS
= 0x1000, /* two channel mode for 4020 */
266 FOUR_CHANNEL_4020_BITS
= 0x2000, /* four channel mode for 4020 */
267 CHANNEL_MODE_4020_MASK
= 0x3000,
268 ADC_MODE_MASK
= 0xf000,
270 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel
)
272 return (channel
& 0x3) << 8;
275 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel
)
277 return (channel
& 0x3) << 10;
280 static inline uint16_t adc_mode_bits(unsigned int mode
)
282 return (mode
& 0xf) << 12;
285 enum calibration_contents
{
286 SELECT_8800_BIT
= 0x1,
287 SELECT_8402_64XX_BIT
= 0x2,
288 SELECT_1590_60XX_BIT
= 0x2,
289 CAL_EN_64XX_BIT
= 0x40, /* calibration enable for 64xx series */
290 SERIAL_DATA_IN_BIT
= 0x80,
291 SERIAL_CLOCK_BIT
= 0x100,
292 CAL_EN_60XX_BIT
= 0x200, /* calibration enable for 60xx series */
293 CAL_GAIN_BIT
= 0x800,
295 /* calibration sources for 6025 are:
305 static inline uint16_t adc_src_bits(unsigned int source
)
307 return (source
& 0xf) << 3;
310 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel
)
312 return (channel
& 0x3) << 8;
315 enum adc_queue_load_contents
{
316 UNIP_BIT
= 0x800, /* unipolar/bipolar bit */
317 ADC_SE_DIFF_BIT
= 0x1000, /* single-ended/ differential bit */
318 ADC_COMMON_BIT
= 0x2000, /* non-referenced single-ended (common-mode input) */
319 QUEUE_EOSEQ_BIT
= 0x4000, /* queue end of sequence */
320 QUEUE_EOSCAN_BIT
= 0x8000, /* queue end of scan */
322 static inline uint16_t adc_chan_bits(unsigned int channel
)
324 return channel
& 0x3f;
327 enum dac_control0_contents
{
328 DAC_ENABLE_BIT
= 0x8000, /* dac controller enable bit */
329 DAC_CYCLIC_STOP_BIT
= 0x4000,
330 DAC_WAVEFORM_MODE_BIT
= 0x100,
331 DAC_EXT_UPDATE_FALLING_BIT
= 0x80,
332 DAC_EXT_UPDATE_ENABLE_BIT
= 0x40,
333 WAVEFORM_TRIG_MASK
= 0x30,
334 WAVEFORM_TRIG_DISABLED_BITS
= 0x0,
335 WAVEFORM_TRIG_SOFT_BITS
= 0x10,
336 WAVEFORM_TRIG_EXT_BITS
= 0x20,
337 WAVEFORM_TRIG_ADC1_BITS
= 0x30,
338 WAVEFORM_TRIG_FALLING_BIT
= 0x8,
339 WAVEFORM_GATE_LEVEL_BIT
= 0x4,
340 WAVEFORM_GATE_ENABLE_BIT
= 0x2,
341 WAVEFORM_GATE_SELECT_BIT
= 0x1,
344 enum dac_control1_contents
{
345 DAC_WRITE_POLARITY_BIT
= 0x800, /* board-dependent setting */
346 DAC1_EXT_REF_BIT
= 0x200,
347 DAC0_EXT_REF_BIT
= 0x100,
348 DAC_OUTPUT_ENABLE_BIT
= 0x80, /* dac output enable bit */
349 DAC_UPDATE_POLARITY_BIT
= 0x40, /* board-dependent setting */
350 DAC_SW_GATE_BIT
= 0x20,
351 DAC1_UNIPOLAR_BIT
= 0x8,
352 DAC0_UNIPOLAR_BIT
= 0x2,
355 /* bit definitions for read-only registers */
356 enum hw_status_contents
{
357 DAC_UNDERRUN_BIT
= 0x1,
358 ADC_OVERRUN_BIT
= 0x2,
359 DAC_ACTIVE_BIT
= 0x4,
360 ADC_ACTIVE_BIT
= 0x8,
361 DAC_INTR_PENDING_BIT
= 0x10,
362 ADC_INTR_PENDING_BIT
= 0x20,
365 EXT_INTR_PENDING_BIT
= 0x100,
366 ADC_STOP_BIT
= 0x200,
368 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits
)
370 return (hw_status_bits
>> 10) & 0x3;
373 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits
)
375 return (prepost_bits
>> 6) & 0x3;
378 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits
)
380 return (prepost_bits
>> 12) & 0x3;
383 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits
)
385 return (prepost_bits
>> 14) & 0x3;
388 /* I2C addresses for 4020 */
390 RANGE_CAL_I2C_ADDR
= 0x20,
391 CALDAC0_I2C_ADDR
= 0xc,
392 CALDAC1_I2C_ADDR
= 0xd,
395 enum range_cal_i2c_contents
{
396 ADC_SRC_4020_MASK
= 0x70, /* bits that set what source the adc converter measures */
397 BNC_TRIG_THRESHOLD_0V_BIT
= 0x80, /* make bnc trig/ext clock threshold 0V instead of 2.5V */
399 static inline uint8_t adc_src_4020_bits(unsigned int source
)
401 return (source
<< 4) & ADC_SRC_4020_MASK
;
404 static inline uint8_t attenuate_bit(unsigned int channel
)
406 /* attenuate channel (+-5V input range) */
407 return 1 << (channel
& 0x3);
410 /* analog input ranges for 64xx boards */
411 static const struct comedi_lrange ai_ranges_64xx
= {
425 /* analog input ranges for 60xx boards */
426 static const struct comedi_lrange ai_ranges_60xx
= {
436 /* analog input ranges for 6030, etc boards */
437 static const struct comedi_lrange ai_ranges_6030
= {
457 /* analog input ranges for 6052, etc boards */
458 static const struct comedi_lrange ai_ranges_6052
= {
479 /* analog input ranges for 4020 board */
480 static const struct comedi_lrange ai_ranges_4020
= {
488 /* analog output ranges */
489 static const struct comedi_lrange ao_ranges_64xx
= {
499 static const int ao_range_code_64xx
[] = {
506 static const struct comedi_lrange ao_ranges_60xx
= {
513 static const int ao_range_code_60xx
[] = {
517 static const struct comedi_lrange ao_ranges_6030
= {
525 static const int ao_range_code_6030
[] = {
530 static const struct comedi_lrange ao_ranges_4020
= {
538 static const int ao_range_code_4020
[] = {
543 enum register_layout
{
549 struct hw_fifo_info
{
550 unsigned int num_segments
;
551 unsigned int max_segment_length
;
552 unsigned int sample_packing_ratio
;
553 uint16_t fifo_size_reg_mask
;
556 struct pcidas64_board
{
558 int device_id
; /* pci device id */
559 int ai_se_chans
; /* number of ai inputs in single-ended mode */
560 int ai_bits
; /* analog input resolution */
561 int ai_speed
; /* fastest conversion period in ns */
562 const struct comedi_lrange
*ai_range_table
;
563 int ao_nchan
; /* number of analog out channels */
564 int ao_bits
; /* analog output resolution */
565 int ao_scan_speed
; /* analog output speed (for a scan, not conversion) */
566 const struct comedi_lrange
*ao_range_table
;
567 const int *ao_range_code
;
568 const struct hw_fifo_info
*const ai_fifo
;
569 enum register_layout layout
; /* different board families have slightly different registers */
573 static const struct hw_fifo_info ai_fifo_4020
= {
575 .max_segment_length
= 0x8000,
576 .sample_packing_ratio
= 2,
577 .fifo_size_reg_mask
= 0x7f,
580 static const struct hw_fifo_info ai_fifo_64xx
= {
582 .max_segment_length
= 0x800,
583 .sample_packing_ratio
= 1,
584 .fifo_size_reg_mask
= 0x3f,
587 static const struct hw_fifo_info ai_fifo_60xx
= {
589 .max_segment_length
= 0x800,
590 .sample_packing_ratio
= 1,
591 .fifo_size_reg_mask
= 0x7f,
594 /* maximum number of dma transfers we will chain together into a ring
595 * (and the maximum number of dma buffers we maintain) */
596 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
597 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
598 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
599 static inline unsigned int ai_dma_ring_count(struct pcidas64_board
*board
)
601 if (board
->layout
== LAYOUT_4020
)
602 return MAX_AI_DMA_RING_COUNT
;
604 return MIN_AI_DMA_RING_COUNT
;
607 static const int bytes_in_sample
= 2;
609 static const struct pcidas64_board pcidas64_boards
[] = {
611 .name
= "pci-das6402/16",
618 .ao_scan_speed
= 10000,
619 .layout
= LAYOUT_64XX
,
620 .ai_range_table
= &ai_ranges_64xx
,
621 .ao_range_table
= &ao_ranges_64xx
,
622 .ao_range_code
= ao_range_code_64xx
,
623 .ai_fifo
= &ai_fifo_64xx
,
627 .name
= "pci-das6402/12", /* XXX check */
634 .ao_scan_speed
= 10000,
635 .layout
= LAYOUT_64XX
,
636 .ai_range_table
= &ai_ranges_64xx
,
637 .ao_range_table
= &ao_ranges_64xx
,
638 .ao_range_code
= ao_range_code_64xx
,
639 .ai_fifo
= &ai_fifo_64xx
,
643 .name
= "pci-das64/m1/16",
650 .ao_scan_speed
= 10000,
651 .layout
= LAYOUT_64XX
,
652 .ai_range_table
= &ai_ranges_64xx
,
653 .ao_range_table
= &ao_ranges_64xx
,
654 .ao_range_code
= ao_range_code_64xx
,
655 .ai_fifo
= &ai_fifo_64xx
,
659 .name
= "pci-das64/m2/16",
666 .ao_scan_speed
= 10000,
667 .layout
= LAYOUT_64XX
,
668 .ai_range_table
= &ai_ranges_64xx
,
669 .ao_range_table
= &ao_ranges_64xx
,
670 .ao_range_code
= ao_range_code_64xx
,
671 .ai_fifo
= &ai_fifo_64xx
,
675 .name
= "pci-das64/m3/16",
682 .ao_scan_speed
= 10000,
683 .layout
= LAYOUT_64XX
,
684 .ai_range_table
= &ai_ranges_64xx
,
685 .ao_range_table
= &ao_ranges_64xx
,
686 .ao_range_code
= ao_range_code_64xx
,
687 .ai_fifo
= &ai_fifo_64xx
,
691 .name
= "pci-das6013",
698 .layout
= LAYOUT_60XX
,
699 .ai_range_table
= &ai_ranges_60xx
,
700 .ao_range_table
= &ao_ranges_60xx
,
701 .ao_range_code
= ao_range_code_60xx
,
702 .ai_fifo
= &ai_fifo_60xx
,
706 .name
= "pci-das6014",
713 .ao_scan_speed
= 100000,
714 .layout
= LAYOUT_60XX
,
715 .ai_range_table
= &ai_ranges_60xx
,
716 .ao_range_table
= &ao_ranges_60xx
,
717 .ao_range_code
= ao_range_code_60xx
,
718 .ai_fifo
= &ai_fifo_60xx
,
722 .name
= "pci-das6023",
728 .ao_scan_speed
= 100000,
729 .layout
= LAYOUT_60XX
,
730 .ai_range_table
= &ai_ranges_60xx
,
731 .ao_range_table
= &ao_ranges_60xx
,
732 .ao_range_code
= ao_range_code_60xx
,
733 .ai_fifo
= &ai_fifo_60xx
,
737 .name
= "pci-das6025",
744 .ao_scan_speed
= 100000,
745 .layout
= LAYOUT_60XX
,
746 .ai_range_table
= &ai_ranges_60xx
,
747 .ao_range_table
= &ao_ranges_60xx
,
748 .ao_range_code
= ao_range_code_60xx
,
749 .ai_fifo
= &ai_fifo_60xx
,
753 .name
= "pci-das6030",
760 .ao_scan_speed
= 10000,
761 .layout
= LAYOUT_60XX
,
762 .ai_range_table
= &ai_ranges_6030
,
763 .ao_range_table
= &ao_ranges_6030
,
764 .ao_range_code
= ao_range_code_6030
,
765 .ai_fifo
= &ai_fifo_60xx
,
769 .name
= "pci-das6031",
776 .ao_scan_speed
= 10000,
777 .layout
= LAYOUT_60XX
,
778 .ai_range_table
= &ai_ranges_6030
,
779 .ao_range_table
= &ao_ranges_6030
,
780 .ao_range_code
= ao_range_code_6030
,
781 .ai_fifo
= &ai_fifo_60xx
,
785 .name
= "pci-das6032",
791 .layout
= LAYOUT_60XX
,
792 .ai_range_table
= &ai_ranges_6030
,
793 .ai_fifo
= &ai_fifo_60xx
,
797 .name
= "pci-das6033",
803 .layout
= LAYOUT_60XX
,
804 .ai_range_table
= &ai_ranges_6030
,
805 .ai_fifo
= &ai_fifo_60xx
,
809 .name
= "pci-das6034",
816 .layout
= LAYOUT_60XX
,
817 .ai_range_table
= &ai_ranges_60xx
,
818 .ai_fifo
= &ai_fifo_60xx
,
822 .name
= "pci-das6035",
829 .ao_scan_speed
= 100000,
830 .layout
= LAYOUT_60XX
,
831 .ai_range_table
= &ai_ranges_60xx
,
832 .ao_range_table
= &ao_ranges_60xx
,
833 .ao_range_code
= ao_range_code_60xx
,
834 .ai_fifo
= &ai_fifo_60xx
,
838 .name
= "pci-das6036",
845 .ao_scan_speed
= 100000,
846 .layout
= LAYOUT_60XX
,
847 .ai_range_table
= &ai_ranges_60xx
,
848 .ao_range_table
= &ao_ranges_60xx
,
849 .ao_range_code
= ao_range_code_60xx
,
850 .ai_fifo
= &ai_fifo_60xx
,
854 .name
= "pci-das6040",
861 .ao_scan_speed
= 1000,
862 .layout
= LAYOUT_60XX
,
863 .ai_range_table
= &ai_ranges_6052
,
864 .ao_range_table
= &ao_ranges_6030
,
865 .ao_range_code
= ao_range_code_6030
,
866 .ai_fifo
= &ai_fifo_60xx
,
870 .name
= "pci-das6052",
877 .ao_scan_speed
= 3333,
878 .layout
= LAYOUT_60XX
,
879 .ai_range_table
= &ai_ranges_6052
,
880 .ao_range_table
= &ao_ranges_6030
,
881 .ao_range_code
= ao_range_code_6030
,
882 .ai_fifo
= &ai_fifo_60xx
,
886 .name
= "pci-das6070",
893 .ao_scan_speed
= 1000,
894 .layout
= LAYOUT_60XX
,
895 .ai_range_table
= &ai_ranges_6052
,
896 .ao_range_table
= &ao_ranges_6030
,
897 .ao_range_code
= ao_range_code_6030
,
898 .ai_fifo
= &ai_fifo_60xx
,
902 .name
= "pci-das6071",
909 .ao_scan_speed
= 1000,
910 .layout
= LAYOUT_60XX
,
911 .ai_range_table
= &ai_ranges_6052
,
912 .ao_range_table
= &ao_ranges_6030
,
913 .ao_range_code
= ao_range_code_6030
,
914 .ai_fifo
= &ai_fifo_60xx
,
918 .name
= "pci-das4020/12",
925 .ao_scan_speed
= 0, /* no hardware pacing on ao */
926 .layout
= LAYOUT_4020
,
927 .ai_range_table
= &ai_ranges_4020
,
928 .ao_range_table
= &ao_ranges_4020
,
929 .ao_range_code
= ao_range_code_4020
,
930 .ai_fifo
= &ai_fifo_4020
,
935 .name
= "pci-das6402/16/jr",
936 .device_id
= 0 /* XXX, */
941 .ao_scan_speed
= 10000,
942 .layout
= LAYOUT_64XX
,
943 .ai_range_table
= &ai_ranges_64xx
,
944 .ai_fifo
= ai_fifo_64xx
,
948 .name
= "pci-das64/m1/16/jr",
949 .device_id
= 0 /* XXX, */
954 .ao_scan_speed
= 10000,
955 .layout
= LAYOUT_64XX
,
956 .ai_range_table
= &ai_ranges_64xx
,
957 .ai_fifo
= ai_fifo_64xx
,
961 .name
= "pci-das64/m2/16/jr",
962 .device_id
= 0 /* XXX, */
967 .ao_scan_speed
= 10000,
968 .layout
= LAYOUT_64XX
,
969 .ai_range_table
= &ai_ranges_64xx
,
970 .ai_fifo
= ai_fifo_64xx
,
974 .name
= "pci-das64/m3/16/jr",
975 .device_id
= 0 /* XXX, */
980 .ao_scan_speed
= 10000,
981 .layout
= LAYOUT_64XX
,
982 .ai_range_table
= &ai_ranges_64xx
,
983 .ai_fifo
= ai_fifo_64xx
,
987 .name
= "pci-das64/m1/14",
988 .device_id
= 0, /* XXX */
993 .ao_scan_speed
= 10000,
994 .layout
= LAYOUT_64XX
,
995 .ai_range_table
= &ai_ranges_64xx
,
996 .ai_fifo
= ai_fifo_64xx
,
1000 .name
= "pci-das64/m2/14",
1001 .device_id
= 0, /* XXX */
1006 .ao_scan_speed
= 10000,
1007 .layout
= LAYOUT_64XX
,
1008 .ai_range_table
= &ai_ranges_64xx
,
1009 .ai_fifo
= ai_fifo_64xx
,
1013 .name
= "pci-das64/m3/14",
1014 .device_id
= 0, /* XXX */
1019 .ao_scan_speed
= 10000,
1020 .layout
= LAYOUT_64XX
,
1021 .ai_range_table
= &ai_ranges_64xx
,
1022 .ai_fifo
= ai_fifo_64xx
,
1028 static inline struct pcidas64_board
*board(const struct comedi_device
*dev
)
1030 return (struct pcidas64_board
*)dev
->board_ptr
;
1033 static inline unsigned short se_diff_bit_6xxx(struct comedi_device
*dev
,
1034 int use_differential
)
1036 if ((board(dev
)->layout
== LAYOUT_64XX
&& !use_differential
) ||
1037 (board(dev
)->layout
== LAYOUT_60XX
&& use_differential
))
1038 return ADC_SE_DIFF_BIT
;
1043 struct ext_clock_info
{
1044 unsigned int divisor
; /* master clock divisor to use for scans with external master clock */
1045 unsigned int chanspec
; /* chanspec for master clock input when used as scan begin src */
1048 /* this structure is for data unique to this hardware driver. */
1049 struct pcidas64_private
{
1050 /* base addresses (physical) */
1051 resource_size_t plx9080_phys_iobase
;
1052 resource_size_t main_phys_iobase
;
1053 resource_size_t dio_counter_phys_iobase
;
1054 /* base addresses (ioremapped) */
1055 void __iomem
*plx9080_iobase
;
1056 void __iomem
*main_iobase
;
1057 void __iomem
*dio_counter_iobase
;
1058 /* local address (used by dma controller) */
1059 uint32_t local0_iobase
;
1060 uint32_t local1_iobase
;
1061 volatile unsigned int ai_count
; /* number of analog input samples remaining */
1062 uint16_t *ai_buffer
[MAX_AI_DMA_RING_COUNT
]; /* dma buffers for analog input */
1063 dma_addr_t ai_buffer_bus_addr
[MAX_AI_DMA_RING_COUNT
]; /* physical addresses of ai dma buffers */
1064 struct plx_dma_desc
*ai_dma_desc
; /* array of ai dma descriptors read by plx9080, allocated to get proper alignment */
1065 dma_addr_t ai_dma_desc_bus_addr
; /* physical address of ai dma descriptor array */
1066 volatile unsigned int ai_dma_index
; /* index of the ai dma descriptor/buffer that is currently being used */
1067 uint16_t *ao_buffer
[AO_DMA_RING_COUNT
]; /* dma buffers for analog output */
1068 dma_addr_t ao_buffer_bus_addr
[AO_DMA_RING_COUNT
]; /* physical addresses of ao dma buffers */
1069 struct plx_dma_desc
*ao_dma_desc
;
1070 dma_addr_t ao_dma_desc_bus_addr
;
1071 volatile unsigned int ao_dma_index
; /* keeps track of buffer where the next ao sample should go */
1072 volatile unsigned long ao_count
; /* number of analog output samples remaining */
1073 volatile unsigned int ao_value
[2]; /* remember what the analog outputs are set to, to allow readback */
1074 unsigned int hw_revision
; /* stc chip hardware revision number */
1075 volatile unsigned int intr_enable_bits
; /* last bits sent to INTR_ENABLE_REG register */
1076 volatile uint16_t adc_control1_bits
; /* last bits sent to ADC_CONTROL1_REG register */
1077 volatile uint16_t fifo_size_bits
; /* last bits sent to FIFO_SIZE_REG register */
1078 volatile uint16_t hw_config_bits
; /* last bits sent to HW_CONFIG_REG register */
1079 volatile uint16_t dac_control1_bits
;
1080 volatile uint32_t plx_control_bits
; /* last bits written to plx9080 control register */
1081 volatile uint32_t plx_intcsr_bits
; /* last bits written to plx interrupt control and status register */
1082 volatile int calibration_source
; /* index of calibration source readable through ai ch0 */
1083 volatile uint8_t i2c_cal_range_bits
; /* bits written to i2c calibration/range register */
1084 volatile unsigned int ext_trig_falling
; /* configure digital triggers to trigger on falling edge */
1085 /* states of various devices stored to enable read-back */
1086 unsigned int ad8402_state
[2];
1087 unsigned int caldac_state
[8];
1088 volatile short ai_cmd_running
;
1089 unsigned int ai_fifo_segment_length
;
1090 struct ext_clock_info ext_clock
;
1091 short ao_bounce_buffer
[DAC_FIFO_SIZE
];
1094 static int ai_rinsn(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
1095 struct comedi_insn
*insn
, unsigned int *data
);
1096 static int ai_config_insn(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
1097 struct comedi_insn
*insn
, unsigned int *data
);
1098 static int ao_winsn(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
1099 struct comedi_insn
*insn
, unsigned int *data
);
1100 static int ao_readback_insn(struct comedi_device
*dev
,
1101 struct comedi_subdevice
*s
,
1102 struct comedi_insn
*insn
, unsigned int *data
);
1103 static int ai_cmd(struct comedi_device
*dev
, struct comedi_subdevice
*s
);
1104 static int ai_cmdtest(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
1105 struct comedi_cmd
*cmd
);
1106 static int ao_cmd(struct comedi_device
*dev
, struct comedi_subdevice
*s
);
1107 static int ao_inttrig(struct comedi_device
*dev
,
1108 struct comedi_subdevice
*subdev
, unsigned int trig_num
);
1109 static int ao_cmdtest(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
1110 struct comedi_cmd
*cmd
);
1111 static irqreturn_t
handle_interrupt(int irq
, void *d
);
1112 static int ai_cancel(struct comedi_device
*dev
, struct comedi_subdevice
*s
);
1113 static int ao_cancel(struct comedi_device
*dev
, struct comedi_subdevice
*s
);
1114 static int dio_callback(int dir
, int port
, int data
, unsigned long arg
);
1115 static int dio_callback_4020(int dir
, int port
, int data
, unsigned long arg
);
1116 static int di_rbits(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
1117 struct comedi_insn
*insn
, unsigned int *data
);
1118 static int do_wbits(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
1119 struct comedi_insn
*insn
, unsigned int *data
);
1120 static int dio_60xx_config_insn(struct comedi_device
*dev
,
1121 struct comedi_subdevice
*s
,
1122 struct comedi_insn
*insn
, unsigned int *data
);
1123 static int dio_60xx_wbits(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
1124 struct comedi_insn
*insn
, unsigned int *data
);
1125 static int calib_read_insn(struct comedi_device
*dev
,
1126 struct comedi_subdevice
*s
, struct comedi_insn
*insn
,
1127 unsigned int *data
);
1128 static int calib_write_insn(struct comedi_device
*dev
,
1129 struct comedi_subdevice
*s
,
1130 struct comedi_insn
*insn
, unsigned int *data
);
1131 static int ad8402_read_insn(struct comedi_device
*dev
,
1132 struct comedi_subdevice
*s
,
1133 struct comedi_insn
*insn
, unsigned int *data
);
1134 static void ad8402_write(struct comedi_device
*dev
, unsigned int channel
,
1135 unsigned int value
);
1136 static int ad8402_write_insn(struct comedi_device
*dev
,
1137 struct comedi_subdevice
*s
,
1138 struct comedi_insn
*insn
, unsigned int *data
);
1139 static int eeprom_read_insn(struct comedi_device
*dev
,
1140 struct comedi_subdevice
*s
,
1141 struct comedi_insn
*insn
, unsigned int *data
);
1142 static void check_adc_timing(struct comedi_device
*dev
, struct comedi_cmd
*cmd
);
1143 static unsigned int get_divisor(unsigned int ns
, unsigned int flags
);
1144 static void i2c_write(struct comedi_device
*dev
, unsigned int address
,
1145 const uint8_t *data
, unsigned int length
);
1146 static void caldac_write(struct comedi_device
*dev
, unsigned int channel
,
1147 unsigned int value
);
1148 static int caldac_8800_write(struct comedi_device
*dev
, unsigned int address
,
1150 /* static int dac_1590_write(struct comedi_device *dev, unsigned int dac_a, unsigned int dac_b); */
1151 static int caldac_i2c_write(struct comedi_device
*dev
,
1152 unsigned int caldac_channel
, unsigned int value
);
1153 static void abort_dma(struct comedi_device
*dev
, unsigned int channel
);
1154 static void disable_plx_interrupts(struct comedi_device
*dev
);
1155 static int set_ai_fifo_size(struct comedi_device
*dev
,
1156 unsigned int num_samples
);
1157 static unsigned int ai_fifo_size(struct comedi_device
*dev
);
1158 static int set_ai_fifo_segment_length(struct comedi_device
*dev
,
1159 unsigned int num_entries
);
1160 static void disable_ai_pacing(struct comedi_device
*dev
);
1161 static void disable_ai_interrupts(struct comedi_device
*dev
);
1162 static void enable_ai_interrupts(struct comedi_device
*dev
,
1163 const struct comedi_cmd
*cmd
);
1164 static unsigned int get_ao_divisor(unsigned int ns
, unsigned int flags
);
1165 static void load_ao_dma(struct comedi_device
*dev
,
1166 const struct comedi_cmd
*cmd
);
1168 static unsigned int ai_range_bits_6xxx(const struct comedi_device
*dev
,
1169 unsigned int range_index
)
1171 const struct comedi_krange
*range
=
1172 &board(dev
)->ai_range_table
->range
[range_index
];
1173 unsigned int bits
= 0;
1175 switch (range
->max
) {
1204 comedi_error(dev
, "bug! in ai_range_bits_6xxx");
1207 if (range
->min
== 0)
1212 static unsigned int hw_revision(const struct comedi_device
*dev
,
1213 uint16_t hw_status_bits
)
1215 if (board(dev
)->layout
== LAYOUT_4020
)
1216 return (hw_status_bits
>> 13) & 0x7;
1218 return (hw_status_bits
>> 12) & 0xf;
1221 static void set_dac_range_bits(struct comedi_device
*dev
,
1222 volatile uint16_t *bits
, unsigned int channel
,
1225 unsigned int code
= board(dev
)->ao_range_code
[range
];
1228 comedi_error(dev
, "bug! bad channel?");
1230 comedi_error(dev
, "bug! bad range code?");
1232 *bits
&= ~(0x3 << (2 * channel
));
1233 *bits
|= code
<< (2 * channel
);
1236 static inline int ao_cmd_is_supported(const struct pcidas64_board
*board
)
1238 return board
->ao_nchan
&& board
->layout
!= LAYOUT_4020
;
1241 /* initialize plx9080 chip */
1242 static void init_plx9080(struct comedi_device
*dev
)
1244 struct pcidas64_private
*devpriv
= dev
->private;
1246 void __iomem
*plx_iobase
= devpriv
->plx9080_iobase
;
1248 devpriv
->plx_control_bits
=
1249 readl(devpriv
->plx9080_iobase
+ PLX_CONTROL_REG
);
1252 DEBUG_PRINT(" plx interrupt status 0x%x\n",
1253 readl(plx_iobase
+ PLX_INTRCS_REG
));
1254 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase
+ PLX_ID_REG
));
1255 DEBUG_PRINT(" plx control reg 0x%x\n", devpriv
->plx_control_bits
);
1256 DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1257 readl(plx_iobase
+ PLX_MARB_REG
));
1258 DEBUG_PRINT(" plx region0 reg 0x%x\n",
1259 readl(plx_iobase
+ PLX_REGION0_REG
));
1260 DEBUG_PRINT(" plx region1 reg 0x%x\n",
1261 readl(plx_iobase
+ PLX_REGION1_REG
));
1263 DEBUG_PRINT(" plx revision 0x%x\n",
1264 readl(plx_iobase
+ PLX_REVISION_REG
));
1265 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1266 readl(plx_iobase
+ PLX_DMA0_MODE_REG
));
1267 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1268 readl(plx_iobase
+ PLX_DMA1_MODE_REG
));
1269 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1270 readl(plx_iobase
+ PLX_DMA0_PCI_ADDRESS_REG
));
1271 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1272 readl(plx_iobase
+ PLX_DMA0_LOCAL_ADDRESS_REG
));
1273 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1274 readl(plx_iobase
+ PLX_DMA0_TRANSFER_SIZE_REG
));
1275 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1276 readl(plx_iobase
+ PLX_DMA0_DESCRIPTOR_REG
));
1277 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1278 readb(plx_iobase
+ PLX_DMA0_CS_REG
));
1279 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1280 readl(plx_iobase
+ PLX_DMA0_THRESHOLD_REG
));
1281 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase
+ PLX_BIGEND_REG
));
1284 bits
= BIGEND_DMA0
| BIGEND_DMA1
;
1288 writel(bits
, devpriv
->plx9080_iobase
+ PLX_BIGEND_REG
);
1290 disable_plx_interrupts(dev
);
1295 /* configure dma0 mode */
1297 /* enable ready input, not sure if this is necessary */
1298 bits
|= PLX_DMA_EN_READYIN_BIT
;
1299 /* enable bterm, not sure if this is necessary */
1300 bits
|= PLX_EN_BTERM_BIT
;
1301 /* enable dma chaining */
1302 bits
|= PLX_EN_CHAIN_BIT
;
1303 /* enable interrupt on dma done (probably don't need this, since chain never finishes) */
1304 bits
|= PLX_EN_DMA_DONE_INTR_BIT
;
1305 /* don't increment local address during transfers (we are transferring from a fixed fifo register) */
1306 bits
|= PLX_LOCAL_ADDR_CONST_BIT
;
1307 /* route dma interrupt to pci bus */
1308 bits
|= PLX_DMA_INTR_PCI_BIT
;
1309 /* enable demand mode */
1310 bits
|= PLX_DEMAND_MODE_BIT
;
1311 /* enable local burst mode */
1312 bits
|= PLX_DMA_LOCAL_BURST_EN_BIT
;
1313 /* 4020 uses 32 bit dma */
1314 if (board(dev
)->layout
== LAYOUT_4020
) {
1315 bits
|= PLX_LOCAL_BUS_32_WIDE_BITS
;
1316 } else { /* localspace0 bus is 16 bits wide */
1317 bits
|= PLX_LOCAL_BUS_16_WIDE_BITS
;
1319 writel(bits
, plx_iobase
+ PLX_DMA1_MODE_REG
);
1320 if (ao_cmd_is_supported(board(dev
)))
1321 writel(bits
, plx_iobase
+ PLX_DMA0_MODE_REG
);
1323 /* enable interrupts on plx 9080 */
1324 devpriv
->plx_intcsr_bits
|=
1325 ICS_AERR
| ICS_PERR
| ICS_PIE
| ICS_PLIE
| ICS_PAIE
| ICS_LIE
|
1326 ICS_DMA0_E
| ICS_DMA1_E
;
1327 writel(devpriv
->plx_intcsr_bits
,
1328 devpriv
->plx9080_iobase
+ PLX_INTRCS_REG
);
1331 /* Allocate and initialize the subdevice structures.
1333 static int setup_subdevices(struct comedi_device
*dev
)
1335 struct pcidas64_private
*devpriv
= dev
->private;
1336 struct comedi_subdevice
*s
;
1337 void __iomem
*dio_8255_iobase
;
1341 ret
= comedi_alloc_subdevices(dev
, 10);
1345 s
= &dev
->subdevices
[0];
1346 /* analog input subdevice */
1347 dev
->read_subdev
= s
;
1348 s
->type
= COMEDI_SUBD_AI
;
1349 s
->subdev_flags
= SDF_READABLE
| SDF_GROUND
| SDF_DITHER
| SDF_CMD_READ
;
1350 if (board(dev
)->layout
== LAYOUT_60XX
)
1351 s
->subdev_flags
|= SDF_COMMON
| SDF_DIFF
;
1352 else if (board(dev
)->layout
== LAYOUT_64XX
)
1353 s
->subdev_flags
|= SDF_DIFF
;
1354 /* XXX Number of inputs in differential mode is ignored */
1355 s
->n_chan
= board(dev
)->ai_se_chans
;
1356 s
->len_chanlist
= 0x2000;
1357 s
->maxdata
= (1 << board(dev
)->ai_bits
) - 1;
1358 s
->range_table
= board(dev
)->ai_range_table
;
1359 s
->insn_read
= ai_rinsn
;
1360 s
->insn_config
= ai_config_insn
;
1362 s
->do_cmdtest
= ai_cmdtest
;
1363 s
->cancel
= ai_cancel
;
1364 if (board(dev
)->layout
== LAYOUT_4020
) {
1366 /* set adc to read from inputs (not internal calibration sources) */
1367 devpriv
->i2c_cal_range_bits
= adc_src_4020_bits(4);
1368 /* set channels to +-5 volt input ranges */
1369 for (i
= 0; i
< s
->n_chan
; i
++)
1370 devpriv
->i2c_cal_range_bits
|= attenuate_bit(i
);
1371 data
= devpriv
->i2c_cal_range_bits
;
1372 i2c_write(dev
, RANGE_CAL_I2C_ADDR
, &data
, sizeof(data
));
1375 /* analog output subdevice */
1376 s
= &dev
->subdevices
[1];
1377 if (board(dev
)->ao_nchan
) {
1378 s
->type
= COMEDI_SUBD_AO
;
1380 SDF_READABLE
| SDF_WRITABLE
| SDF_GROUND
| SDF_CMD_WRITE
;
1381 s
->n_chan
= board(dev
)->ao_nchan
;
1382 s
->maxdata
= (1 << board(dev
)->ao_bits
) - 1;
1383 s
->range_table
= board(dev
)->ao_range_table
;
1384 s
->insn_read
= ao_readback_insn
;
1385 s
->insn_write
= ao_winsn
;
1386 if (ao_cmd_is_supported(board(dev
))) {
1387 dev
->write_subdev
= s
;
1388 s
->do_cmdtest
= ao_cmdtest
;
1390 s
->len_chanlist
= board(dev
)->ao_nchan
;
1391 s
->cancel
= ao_cancel
;
1394 s
->type
= COMEDI_SUBD_UNUSED
;
1398 s
= &dev
->subdevices
[2];
1399 if (board(dev
)->layout
== LAYOUT_64XX
) {
1400 s
->type
= COMEDI_SUBD_DI
;
1401 s
->subdev_flags
= SDF_READABLE
;
1404 s
->range_table
= &range_digital
;
1405 s
->insn_bits
= di_rbits
;
1407 s
->type
= COMEDI_SUBD_UNUSED
;
1409 /* digital output */
1410 if (board(dev
)->layout
== LAYOUT_64XX
) {
1411 s
= &dev
->subdevices
[3];
1412 s
->type
= COMEDI_SUBD_DO
;
1413 s
->subdev_flags
= SDF_WRITABLE
| SDF_READABLE
;
1416 s
->range_table
= &range_digital
;
1417 s
->insn_bits
= do_wbits
;
1419 s
->type
= COMEDI_SUBD_UNUSED
;
1422 s
= &dev
->subdevices
[4];
1423 if (board(dev
)->has_8255
) {
1424 if (board(dev
)->layout
== LAYOUT_4020
) {
1426 devpriv
->main_iobase
+ I8255_4020_REG
;
1427 subdev_8255_init(dev
, s
, dio_callback_4020
,
1428 (unsigned long)dio_8255_iobase
);
1431 devpriv
->dio_counter_iobase
+ DIO_8255_OFFSET
;
1432 subdev_8255_init(dev
, s
, dio_callback
,
1433 (unsigned long)dio_8255_iobase
);
1436 s
->type
= COMEDI_SUBD_UNUSED
;
1438 /* 8 channel dio for 60xx */
1439 s
= &dev
->subdevices
[5];
1440 if (board(dev
)->layout
== LAYOUT_60XX
) {
1441 s
->type
= COMEDI_SUBD_DIO
;
1442 s
->subdev_flags
= SDF_WRITABLE
| SDF_READABLE
;
1445 s
->range_table
= &range_digital
;
1446 s
->insn_config
= dio_60xx_config_insn
;
1447 s
->insn_bits
= dio_60xx_wbits
;
1449 s
->type
= COMEDI_SUBD_UNUSED
;
1452 s
= &dev
->subdevices
[6];
1453 s
->type
= COMEDI_SUBD_CALIB
;
1454 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
| SDF_INTERNAL
;
1456 if (board(dev
)->layout
== LAYOUT_4020
)
1460 s
->insn_read
= calib_read_insn
;
1461 s
->insn_write
= calib_write_insn
;
1462 for (i
= 0; i
< s
->n_chan
; i
++)
1463 caldac_write(dev
, i
, s
->maxdata
/ 2);
1465 /* 2 channel ad8402 potentiometer */
1466 s
= &dev
->subdevices
[7];
1467 if (board(dev
)->layout
== LAYOUT_64XX
) {
1468 s
->type
= COMEDI_SUBD_CALIB
;
1469 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
| SDF_INTERNAL
;
1471 s
->insn_read
= ad8402_read_insn
;
1472 s
->insn_write
= ad8402_write_insn
;
1474 for (i
= 0; i
< s
->n_chan
; i
++)
1475 ad8402_write(dev
, i
, s
->maxdata
/ 2);
1477 s
->type
= COMEDI_SUBD_UNUSED
;
1479 /* serial EEPROM, if present */
1480 s
= &dev
->subdevices
[8];
1481 if (readl(devpriv
->plx9080_iobase
+ PLX_CONTROL_REG
) & CTL_EECHK
) {
1482 s
->type
= COMEDI_SUBD_MEMORY
;
1483 s
->subdev_flags
= SDF_READABLE
| SDF_INTERNAL
;
1485 s
->maxdata
= 0xffff;
1486 s
->insn_read
= eeprom_read_insn
;
1488 s
->type
= COMEDI_SUBD_UNUSED
;
1490 /* user counter subd XXX */
1491 s
= &dev
->subdevices
[9];
1492 s
->type
= COMEDI_SUBD_UNUSED
;
1497 static void disable_plx_interrupts(struct comedi_device
*dev
)
1499 struct pcidas64_private
*devpriv
= dev
->private;
1501 devpriv
->plx_intcsr_bits
= 0;
1502 writel(devpriv
->plx_intcsr_bits
,
1503 devpriv
->plx9080_iobase
+ PLX_INTRCS_REG
);
1506 static void init_stc_registers(struct comedi_device
*dev
)
1508 struct pcidas64_private
*devpriv
= dev
->private;
1510 unsigned long flags
;
1512 spin_lock_irqsave(&dev
->spinlock
, flags
);
1514 /* bit should be set for 6025, although docs say boards with <= 16 chans should be cleared XXX */
1516 devpriv
->adc_control1_bits
|= ADC_QUEUE_CONFIG_BIT
;
1517 writew(devpriv
->adc_control1_bits
,
1518 devpriv
->main_iobase
+ ADC_CONTROL1_REG
);
1520 /* 6402/16 manual says this register must be initialized to 0xff? */
1521 writew(0xff, devpriv
->main_iobase
+ ADC_SAMPLE_INTERVAL_UPPER_REG
);
1523 bits
= SLOW_DAC_BIT
| DMA_CH_SELECT_BIT
;
1524 if (board(dev
)->layout
== LAYOUT_4020
)
1525 bits
|= INTERNAL_CLOCK_4020_BITS
;
1526 devpriv
->hw_config_bits
|= bits
;
1527 writew(devpriv
->hw_config_bits
,
1528 devpriv
->main_iobase
+ HW_CONFIG_REG
);
1530 writew(0, devpriv
->main_iobase
+ DAQ_SYNC_REG
);
1531 writew(0, devpriv
->main_iobase
+ CALIBRATION_REG
);
1533 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
1535 /* set fifos to maximum size */
1536 devpriv
->fifo_size_bits
|= DAC_FIFO_BITS
;
1537 set_ai_fifo_segment_length(dev
,
1538 board(dev
)->ai_fifo
->max_segment_length
);
1540 devpriv
->dac_control1_bits
= DAC_OUTPUT_ENABLE_BIT
;
1541 devpriv
->intr_enable_bits
= /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1542 EN_DAC_DONE_INTR_BIT
| EN_DAC_UNDERRUN_BIT
;
1543 writew(devpriv
->intr_enable_bits
,
1544 devpriv
->main_iobase
+ INTR_ENABLE_REG
);
1546 disable_ai_pacing(dev
);
1549 static int alloc_and_init_dma_members(struct comedi_device
*dev
)
1551 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
1552 struct pcidas64_private
*devpriv
= dev
->private;
1555 /* alocate pci dma buffers */
1556 for (i
= 0; i
< ai_dma_ring_count(board(dev
)); i
++) {
1557 devpriv
->ai_buffer
[i
] =
1558 pci_alloc_consistent(pcidev
, DMA_BUFFER_SIZE
,
1559 &devpriv
->ai_buffer_bus_addr
[i
]);
1560 if (devpriv
->ai_buffer
[i
] == NULL
)
1564 for (i
= 0; i
< AO_DMA_RING_COUNT
; i
++) {
1565 if (ao_cmd_is_supported(board(dev
))) {
1566 devpriv
->ao_buffer
[i
] =
1567 pci_alloc_consistent(pcidev
,
1570 ao_buffer_bus_addr
[i
]);
1571 if (devpriv
->ao_buffer
[i
] == NULL
)
1576 /* allocate dma descriptors */
1577 devpriv
->ai_dma_desc
=
1578 pci_alloc_consistent(pcidev
,
1579 sizeof(struct plx_dma_desc
) *
1580 ai_dma_ring_count(board(dev
)),
1581 &devpriv
->ai_dma_desc_bus_addr
);
1582 if (devpriv
->ai_dma_desc
== NULL
)
1585 DEBUG_PRINT("ai dma descriptors start at bus addr 0x%x\n",
1586 devpriv
->ai_dma_desc_bus_addr
);
1587 if (ao_cmd_is_supported(board(dev
))) {
1588 devpriv
->ao_dma_desc
=
1589 pci_alloc_consistent(pcidev
,
1590 sizeof(struct plx_dma_desc
) *
1592 &devpriv
->ao_dma_desc_bus_addr
);
1593 if (devpriv
->ao_dma_desc
== NULL
)
1596 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%x\n",
1597 devpriv
->ao_dma_desc_bus_addr
);
1599 /* initialize dma descriptors */
1600 for (i
= 0; i
< ai_dma_ring_count(board(dev
)); i
++) {
1601 devpriv
->ai_dma_desc
[i
].pci_start_addr
=
1602 cpu_to_le32(devpriv
->ai_buffer_bus_addr
[i
]);
1603 if (board(dev
)->layout
== LAYOUT_4020
)
1604 devpriv
->ai_dma_desc
[i
].local_start_addr
=
1605 cpu_to_le32(devpriv
->local1_iobase
+
1608 devpriv
->ai_dma_desc
[i
].local_start_addr
=
1609 cpu_to_le32(devpriv
->local0_iobase
+
1611 devpriv
->ai_dma_desc
[i
].transfer_size
= cpu_to_le32(0);
1612 devpriv
->ai_dma_desc
[i
].next
=
1613 cpu_to_le32((devpriv
->ai_dma_desc_bus_addr
+ ((i
+
1618 sizeof(devpriv
->ai_dma_desc
[0])) |
1619 PLX_DESC_IN_PCI_BIT
| PLX_INTR_TERM_COUNT
|
1620 PLX_XFER_LOCAL_TO_PCI
);
1622 if (ao_cmd_is_supported(board(dev
))) {
1623 for (i
= 0; i
< AO_DMA_RING_COUNT
; i
++) {
1624 devpriv
->ao_dma_desc
[i
].pci_start_addr
=
1625 cpu_to_le32(devpriv
->ao_buffer_bus_addr
[i
]);
1626 devpriv
->ao_dma_desc
[i
].local_start_addr
=
1627 cpu_to_le32(devpriv
->local0_iobase
+
1629 devpriv
->ao_dma_desc
[i
].transfer_size
=
1631 devpriv
->ao_dma_desc
[i
].next
=
1632 cpu_to_le32((devpriv
->ao_dma_desc_bus_addr
+
1633 ((i
+ 1) % (AO_DMA_RING_COUNT
)) *
1634 sizeof(devpriv
->ao_dma_desc
[0])) |
1635 PLX_DESC_IN_PCI_BIT
|
1636 PLX_INTR_TERM_COUNT
);
1642 static inline void warn_external_queue(struct comedi_device
*dev
)
1645 "AO command and AI external channel queue cannot be used simultaneously.");
1647 "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1650 static struct pci_dev
*cb_pcidas64_find_pci_dev(struct comedi_device
*dev
,
1651 struct comedi_devconfig
*it
)
1653 struct pci_dev
*pcidev
= NULL
;
1654 int bus
= it
->options
[0];
1655 int slot
= it
->options
[1];
1658 for_each_pci_dev(pcidev
) {
1660 if (bus
!= pcidev
->bus
->number
||
1661 slot
!= PCI_SLOT(pcidev
->devfn
))
1664 if (pcidev
->vendor
!= PCI_VENDOR_ID_COMPUTERBOARDS
)
1667 for (i
= 0; i
< ARRAY_SIZE(pcidas64_boards
); i
++) {
1668 if (pcidas64_boards
[i
].device_id
!= pcidev
->device
)
1670 dev
->board_ptr
= pcidas64_boards
+ i
;
1674 dev_err(dev
->class_dev
,
1675 "No supported board found! (req. bus %d, slot %d)\n",
1681 * Attach is called by the Comedi core to configure the driver
1682 * for a particular board.
1684 static int attach(struct comedi_device
*dev
, struct comedi_devconfig
*it
)
1686 struct pcidas64_private
*devpriv
;
1687 struct pci_dev
*pcidev
;
1688 uint32_t local_range
, local_decode
;
1691 retval
= alloc_private(dev
, sizeof(*devpriv
));
1694 devpriv
= dev
->private;
1696 pcidev
= cb_pcidas64_find_pci_dev(dev
, it
);
1699 comedi_set_hw_dev(dev
, &pcidev
->dev
);
1701 if (comedi_pci_enable(pcidev
, dev
->driver
->driver_name
)) {
1702 dev_warn(dev
->class_dev
,
1703 "failed to enable PCI device and request regions\n");
1706 pci_set_master(pcidev
);
1708 /* Initialize dev->board_name */
1709 dev
->board_name
= board(dev
)->name
;
1711 dev
->iobase
= pci_resource_start(pcidev
, MAIN_BADDRINDEX
);
1713 devpriv
->plx9080_phys_iobase
=
1714 pci_resource_start(pcidev
, PLX9080_BADDRINDEX
);
1715 devpriv
->main_phys_iobase
= dev
->iobase
;
1716 devpriv
->dio_counter_phys_iobase
=
1717 pci_resource_start(pcidev
, DIO_COUNTER_BADDRINDEX
);
1719 /* remap, won't work with 2.0 kernels but who cares */
1720 devpriv
->plx9080_iobase
= ioremap(devpriv
->plx9080_phys_iobase
,
1721 pci_resource_len(pcidev
,
1722 PLX9080_BADDRINDEX
));
1723 devpriv
->main_iobase
=
1724 ioremap(devpriv
->main_phys_iobase
,
1725 pci_resource_len(pcidev
, MAIN_BADDRINDEX
));
1726 devpriv
->dio_counter_iobase
=
1727 ioremap(devpriv
->dio_counter_phys_iobase
,
1728 pci_resource_len(pcidev
, DIO_COUNTER_BADDRINDEX
));
1730 if (!devpriv
->plx9080_iobase
|| !devpriv
->main_iobase
1731 || !devpriv
->dio_counter_iobase
) {
1732 dev_warn(dev
->class_dev
, "failed to remap io memory\n");
1736 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", devpriv
->plx9080_iobase
);
1737 DEBUG_PRINT(" main remapped to 0x%p\n", devpriv
->main_iobase
);
1738 DEBUG_PRINT(" diocounter remapped to 0x%p\n",
1739 devpriv
->dio_counter_iobase
);
1741 /* figure out what local addresses are */
1743 readl(devpriv
->plx9080_iobase
+ PLX_LAS0RNG_REG
) & LRNG_MEM_MASK
;
1745 readl(devpriv
->plx9080_iobase
+
1746 PLX_LAS0MAP_REG
) & local_range
& LMAP_MEM_MASK
;
1747 devpriv
->local0_iobase
=
1748 ((uint32_t) devpriv
->main_phys_iobase
& ~local_range
) |
1751 readl(devpriv
->plx9080_iobase
+ PLX_LAS1RNG_REG
) & LRNG_MEM_MASK
;
1753 readl(devpriv
->plx9080_iobase
+
1754 PLX_LAS1MAP_REG
) & local_range
& LMAP_MEM_MASK
;
1755 devpriv
->local1_iobase
=
1756 ((uint32_t) devpriv
->dio_counter_phys_iobase
& ~local_range
) |
1759 DEBUG_PRINT(" local 0 io addr 0x%x\n", devpriv
->local0_iobase
);
1760 DEBUG_PRINT(" local 1 io addr 0x%x\n", devpriv
->local1_iobase
);
1762 retval
= alloc_and_init_dma_members(dev
);
1766 devpriv
->hw_revision
=
1767 hw_revision(dev
, readw(devpriv
->main_iobase
+ HW_STATUS_REG
));
1768 dev_dbg(dev
->class_dev
, "stc hardware revision %i\n",
1769 devpriv
->hw_revision
);
1771 init_stc_registers(dev
);
1773 if (request_irq(pcidev
->irq
, handle_interrupt
, IRQF_SHARED
,
1774 "cb_pcidas64", dev
)) {
1775 dev_dbg(dev
->class_dev
, "unable to allocate irq %u\n",
1779 dev
->irq
= pcidev
->irq
;
1780 dev_dbg(dev
->class_dev
, "irq %u\n", dev
->irq
);
1782 retval
= setup_subdevices(dev
);
1790 static void detach(struct comedi_device
*dev
)
1792 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
1793 struct pcidas64_private
*devpriv
= dev
->private;
1797 free_irq(dev
->irq
, dev
);
1800 if (devpriv
->plx9080_iobase
) {
1801 disable_plx_interrupts(dev
);
1802 iounmap(devpriv
->plx9080_iobase
);
1804 if (devpriv
->main_iobase
)
1805 iounmap(devpriv
->main_iobase
);
1806 if (devpriv
->dio_counter_iobase
)
1807 iounmap(devpriv
->dio_counter_iobase
);
1808 /* free pci dma buffers */
1809 for (i
= 0; i
< ai_dma_ring_count(board(dev
)); i
++) {
1810 if (devpriv
->ai_buffer
[i
])
1811 pci_free_consistent(pcidev
,
1813 devpriv
->ai_buffer
[i
],
1814 devpriv
->ai_buffer_bus_addr
[i
]);
1816 for (i
= 0; i
< AO_DMA_RING_COUNT
; i
++) {
1817 if (devpriv
->ao_buffer
[i
])
1818 pci_free_consistent(pcidev
,
1820 devpriv
->ao_buffer
[i
],
1821 devpriv
->ao_buffer_bus_addr
[i
]);
1823 /* free dma descriptors */
1824 if (devpriv
->ai_dma_desc
)
1825 pci_free_consistent(pcidev
,
1826 sizeof(struct plx_dma_desc
) *
1827 ai_dma_ring_count(board(dev
)),
1828 devpriv
->ai_dma_desc
,
1829 devpriv
->ai_dma_desc_bus_addr
);
1830 if (devpriv
->ao_dma_desc
)
1831 pci_free_consistent(pcidev
,
1832 sizeof(struct plx_dma_desc
) *
1834 devpriv
->ao_dma_desc
,
1835 devpriv
->ao_dma_desc_bus_addr
);
1838 if (dev
->subdevices
)
1839 subdev_8255_cleanup(dev
, &dev
->subdevices
[4]);
1842 comedi_pci_disable(pcidev
);
1844 pci_dev_put(pcidev
);
1848 static int ai_rinsn(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
1849 struct comedi_insn
*insn
, unsigned int *data
)
1851 struct pcidas64_private
*devpriv
= dev
->private;
1852 unsigned int bits
= 0, n
, i
;
1853 unsigned int channel
, range
, aref
;
1854 unsigned long flags
;
1855 static const int timeout
= 100;
1857 DEBUG_PRINT("chanspec 0x%x\n", insn
->chanspec
);
1858 channel
= CR_CHAN(insn
->chanspec
);
1859 range
= CR_RANGE(insn
->chanspec
);
1860 aref
= CR_AREF(insn
->chanspec
);
1862 /* disable card's analog input interrupt sources and pacing */
1863 /* 4020 generates dac done interrupts even though they are disabled */
1864 disable_ai_pacing(dev
);
1866 spin_lock_irqsave(&dev
->spinlock
, flags
);
1867 if (insn
->chanspec
& CR_ALT_FILTER
)
1868 devpriv
->adc_control1_bits
|= ADC_DITHER_BIT
;
1870 devpriv
->adc_control1_bits
&= ~ADC_DITHER_BIT
;
1871 writew(devpriv
->adc_control1_bits
,
1872 devpriv
->main_iobase
+ ADC_CONTROL1_REG
);
1873 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
1875 if (board(dev
)->layout
!= LAYOUT_4020
) {
1876 /* use internal queue */
1877 devpriv
->hw_config_bits
&= ~EXT_QUEUE_BIT
;
1878 writew(devpriv
->hw_config_bits
,
1879 devpriv
->main_iobase
+ HW_CONFIG_REG
);
1881 /* ALT_SOURCE is internal calibration reference */
1882 if (insn
->chanspec
& CR_ALT_SOURCE
) {
1883 unsigned int cal_en_bit
;
1885 DEBUG_PRINT("reading calibration source\n");
1886 if (board(dev
)->layout
== LAYOUT_60XX
)
1887 cal_en_bit
= CAL_EN_60XX_BIT
;
1889 cal_en_bit
= CAL_EN_64XX_BIT
;
1890 /* select internal reference source to connect to channel 0 */
1892 adc_src_bits(devpriv
->calibration_source
),
1893 devpriv
->main_iobase
+ CALIBRATION_REG
);
1895 /* make sure internal calibration source is turned off */
1896 writew(0, devpriv
->main_iobase
+ CALIBRATION_REG
);
1898 /* load internal queue */
1901 bits
|= ai_range_bits_6xxx(dev
, CR_RANGE(insn
->chanspec
));
1902 /* set single-ended / differential */
1903 bits
|= se_diff_bit_6xxx(dev
, aref
== AREF_DIFF
);
1904 if (aref
== AREF_COMMON
)
1905 bits
|= ADC_COMMON_BIT
;
1906 bits
|= adc_chan_bits(channel
);
1907 /* set stop channel */
1908 writew(adc_chan_bits(channel
),
1909 devpriv
->main_iobase
+ ADC_QUEUE_HIGH_REG
);
1910 /* set start channel, and rest of settings */
1911 writew(bits
, devpriv
->main_iobase
+ ADC_QUEUE_LOAD_REG
);
1913 uint8_t old_cal_range_bits
= devpriv
->i2c_cal_range_bits
;
1915 devpriv
->i2c_cal_range_bits
&= ~ADC_SRC_4020_MASK
;
1916 if (insn
->chanspec
& CR_ALT_SOURCE
) {
1917 DEBUG_PRINT("reading calibration source\n");
1918 devpriv
->i2c_cal_range_bits
|=
1919 adc_src_4020_bits(devpriv
->calibration_source
);
1920 } else { /* select BNC inputs */
1921 devpriv
->i2c_cal_range_bits
|= adc_src_4020_bits(4);
1925 devpriv
->i2c_cal_range_bits
|= attenuate_bit(channel
);
1927 devpriv
->i2c_cal_range_bits
&=
1928 ~attenuate_bit(channel
);
1929 /* update calibration/range i2c register only if necessary, as it is very slow */
1930 if (old_cal_range_bits
!= devpriv
->i2c_cal_range_bits
) {
1931 uint8_t i2c_data
= devpriv
->i2c_cal_range_bits
;
1932 i2c_write(dev
, RANGE_CAL_I2C_ADDR
, &i2c_data
,
1936 /* 4020 manual asks that sample interval register to be set before writing to convert register.
1937 * Using somewhat arbitrary setting of 4 master clock ticks = 0.1 usec */
1939 devpriv
->main_iobase
+ ADC_SAMPLE_INTERVAL_UPPER_REG
);
1941 devpriv
->main_iobase
+ ADC_SAMPLE_INTERVAL_LOWER_REG
);
1944 for (n
= 0; n
< insn
->n
; n
++) {
1946 /* clear adc buffer (inside loop for 4020 sake) */
1947 writew(0, devpriv
->main_iobase
+ ADC_BUFFER_CLEAR_REG
);
1949 /* trigger conversion, bits sent only matter for 4020 */
1950 writew(adc_convert_chan_4020_bits(CR_CHAN(insn
->chanspec
)),
1951 devpriv
->main_iobase
+ ADC_CONVERT_REG
);
1954 for (i
= 0; i
< timeout
; i
++) {
1955 bits
= readw(devpriv
->main_iobase
+ HW_STATUS_REG
);
1956 DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits
));
1957 if (board(dev
)->layout
== LAYOUT_4020
) {
1958 if (readw(devpriv
->main_iobase
+
1959 ADC_WRITE_PNTR_REG
))
1962 if (pipe_full_bits(bits
))
1967 DEBUG_PRINT(" looped %i times waiting for data\n", i
);
1969 comedi_error(dev
, " analog input read insn timed out");
1970 printk(" status 0x%x\n", bits
);
1973 if (board(dev
)->layout
== LAYOUT_4020
)
1975 readl(devpriv
->dio_counter_iobase
+
1976 ADC_FIFO_REG
) & 0xffff;
1979 readw(devpriv
->main_iobase
+ PIPE1_READ_REG
);
1985 static int ai_config_calibration_source(struct comedi_device
*dev
,
1988 struct pcidas64_private
*devpriv
= dev
->private;
1989 unsigned int source
= data
[1];
1990 int num_calibration_sources
;
1992 if (board(dev
)->layout
== LAYOUT_60XX
)
1993 num_calibration_sources
= 16;
1995 num_calibration_sources
= 8;
1996 if (source
>= num_calibration_sources
) {
1997 dev_dbg(dev
->class_dev
, "invalid calibration source: %i\n",
2002 DEBUG_PRINT("setting calibration source to %i\n", source
);
2003 devpriv
->calibration_source
= source
;
2008 static int ai_config_block_size(struct comedi_device
*dev
, unsigned int *data
)
2011 const struct hw_fifo_info
*const fifo
= board(dev
)->ai_fifo
;
2012 unsigned int block_size
, requested_block_size
;
2015 requested_block_size
= data
[1];
2017 if (requested_block_size
) {
2019 requested_block_size
* fifo
->num_segments
/ bytes_in_sample
;
2021 retval
= set_ai_fifo_size(dev
, fifo_size
);
2027 block_size
= ai_fifo_size(dev
) / fifo
->num_segments
* bytes_in_sample
;
2029 data
[1] = block_size
;
2034 static int ai_config_master_clock_4020(struct comedi_device
*dev
,
2037 struct pcidas64_private
*devpriv
= dev
->private;
2038 unsigned int divisor
= data
[4];
2047 case COMEDI_EV_SCAN_BEGIN
:
2048 devpriv
->ext_clock
.divisor
= divisor
;
2049 devpriv
->ext_clock
.chanspec
= data
[2];
2058 return retval
? retval
: 5;
2061 /* XXX could add support for 60xx series */
2062 static int ai_config_master_clock(struct comedi_device
*dev
, unsigned int *data
)
2065 switch (board(dev
)->layout
) {
2067 return ai_config_master_clock_4020(dev
, data
);
2077 static int ai_config_insn(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2078 struct comedi_insn
*insn
, unsigned int *data
)
2083 case INSN_CONFIG_ALT_SOURCE
:
2084 return ai_config_calibration_source(dev
, data
);
2086 case INSN_CONFIG_BLOCK_SIZE
:
2087 return ai_config_block_size(dev
, data
);
2089 case INSN_CONFIG_TIMER_1
:
2090 return ai_config_master_clock(dev
, data
);
2099 static int ai_cmdtest(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2100 struct comedi_cmd
*cmd
)
2103 unsigned int tmp_arg
, tmp_arg2
;
2106 unsigned int triggers
;
2108 /* Step 1 : check if triggers are trivially valid */
2110 err
|= cfc_check_trigger_src(&cmd
->start_src
, TRIG_NOW
| TRIG_EXT
);
2112 triggers
= TRIG_TIMER
;
2113 if (board(dev
)->layout
== LAYOUT_4020
)
2114 triggers
|= TRIG_OTHER
;
2116 triggers
|= TRIG_FOLLOW
;
2117 err
|= cfc_check_trigger_src(&cmd
->scan_begin_src
, triggers
);
2119 triggers
= TRIG_TIMER
;
2120 if (board(dev
)->layout
== LAYOUT_4020
)
2121 triggers
|= TRIG_NOW
;
2123 triggers
|= TRIG_EXT
;
2124 err
|= cfc_check_trigger_src(&cmd
->convert_src
, triggers
);
2126 err
|= cfc_check_trigger_src(&cmd
->scan_end_src
, TRIG_COUNT
);
2127 err
|= cfc_check_trigger_src(&cmd
->stop_src
,
2128 TRIG_COUNT
| TRIG_EXT
| TRIG_NONE
);
2133 /* Step 2a : make sure trigger sources are unique */
2135 err
|= cfc_check_trigger_is_unique(cmd
->start_src
);
2136 err
|= cfc_check_trigger_is_unique(cmd
->scan_begin_src
);
2137 err
|= cfc_check_trigger_is_unique(cmd
->convert_src
);
2138 err
|= cfc_check_trigger_is_unique(cmd
->stop_src
);
2140 /* Step 2b : and mutually compatible */
2142 if (cmd
->convert_src
== TRIG_EXT
&& cmd
->scan_begin_src
== TRIG_TIMER
)
2144 if (cmd
->stop_src
!= TRIG_COUNT
&&
2145 cmd
->stop_src
!= TRIG_NONE
&& cmd
->stop_src
!= TRIG_EXT
)
2151 /* step 3: make sure arguments are trivially compatible */
2153 if (cmd
->convert_src
== TRIG_TIMER
) {
2154 if (board(dev
)->layout
== LAYOUT_4020
) {
2155 if (cmd
->convert_arg
) {
2156 cmd
->convert_arg
= 0;
2160 if (cmd
->convert_arg
< board(dev
)->ai_speed
) {
2161 cmd
->convert_arg
= board(dev
)->ai_speed
;
2164 if (cmd
->scan_begin_src
== TRIG_TIMER
) {
2165 /* if scans are timed faster than conversion rate allows */
2166 if (cmd
->convert_arg
* cmd
->chanlist_len
>
2167 cmd
->scan_begin_arg
) {
2168 cmd
->scan_begin_arg
=
2177 if (!cmd
->chanlist_len
) {
2178 cmd
->chanlist_len
= 1;
2181 if (cmd
->scan_end_arg
!= cmd
->chanlist_len
) {
2182 cmd
->scan_end_arg
= cmd
->chanlist_len
;
2186 switch (cmd
->stop_src
) {
2190 if (!cmd
->stop_arg
) {
2196 if (cmd
->stop_arg
!= 0) {
2208 /* step 4: fix up any arguments */
2210 if (cmd
->convert_src
== TRIG_TIMER
) {
2211 tmp_arg
= cmd
->convert_arg
;
2212 tmp_arg2
= cmd
->scan_begin_arg
;
2213 check_adc_timing(dev
, cmd
);
2214 if (tmp_arg
!= cmd
->convert_arg
)
2216 if (tmp_arg2
!= cmd
->scan_begin_arg
)
2223 /* make sure user is doesn't change analog reference mid chanlist */
2224 if (cmd
->chanlist
) {
2225 aref
= CR_AREF(cmd
->chanlist
[0]);
2226 for (i
= 1; i
< cmd
->chanlist_len
; i
++) {
2227 if (aref
!= CR_AREF(cmd
->chanlist
[i
])) {
2229 "all elements in chanlist must use the same analog reference");
2234 /* check 4020 chanlist */
2235 if (board(dev
)->layout
== LAYOUT_4020
) {
2236 unsigned int first_channel
= CR_CHAN(cmd
->chanlist
[0]);
2237 for (i
= 1; i
< cmd
->chanlist_len
; i
++) {
2238 if (CR_CHAN(cmd
->chanlist
[i
]) !=
2239 first_channel
+ i
) {
2241 "chanlist must use consecutive channels");
2246 if (cmd
->chanlist_len
== 3) {
2248 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2260 static int use_hw_sample_counter(struct comedi_cmd
*cmd
)
2262 /* disable for now until I work out a race */
2265 if (cmd
->stop_src
== TRIG_COUNT
&& cmd
->stop_arg
<= max_counter_value
)
2271 static void setup_sample_counters(struct comedi_device
*dev
,
2272 struct comedi_cmd
*cmd
)
2274 struct pcidas64_private
*devpriv
= dev
->private;
2276 if (cmd
->stop_src
== TRIG_COUNT
) {
2277 /* set software count */
2278 devpriv
->ai_count
= cmd
->stop_arg
* cmd
->chanlist_len
;
2280 /* load hardware conversion counter */
2281 if (use_hw_sample_counter(cmd
)) {
2282 writew(cmd
->stop_arg
& 0xffff,
2283 devpriv
->main_iobase
+ ADC_COUNT_LOWER_REG
);
2284 writew((cmd
->stop_arg
>> 16) & 0xff,
2285 devpriv
->main_iobase
+ ADC_COUNT_UPPER_REG
);
2287 writew(1, devpriv
->main_iobase
+ ADC_COUNT_LOWER_REG
);
2291 static inline unsigned int dma_transfer_size(struct comedi_device
*dev
)
2293 struct pcidas64_private
*devpriv
= dev
->private;
2294 unsigned int num_samples
;
2297 devpriv
->ai_fifo_segment_length
*
2298 board(dev
)->ai_fifo
->sample_packing_ratio
;
2299 if (num_samples
> DMA_BUFFER_SIZE
/ sizeof(uint16_t))
2300 num_samples
= DMA_BUFFER_SIZE
/ sizeof(uint16_t);
2305 static void disable_ai_pacing(struct comedi_device
*dev
)
2307 struct pcidas64_private
*devpriv
= dev
->private;
2308 unsigned long flags
;
2310 disable_ai_interrupts(dev
);
2312 spin_lock_irqsave(&dev
->spinlock
, flags
);
2313 devpriv
->adc_control1_bits
&= ~ADC_SW_GATE_BIT
;
2314 writew(devpriv
->adc_control1_bits
,
2315 devpriv
->main_iobase
+ ADC_CONTROL1_REG
);
2316 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
2318 /* disable pacing, triggering, etc */
2319 writew(ADC_DMA_DISABLE_BIT
| ADC_SOFT_GATE_BITS
| ADC_GATE_LEVEL_BIT
,
2320 devpriv
->main_iobase
+ ADC_CONTROL0_REG
);
2323 static void disable_ai_interrupts(struct comedi_device
*dev
)
2325 struct pcidas64_private
*devpriv
= dev
->private;
2326 unsigned long flags
;
2328 spin_lock_irqsave(&dev
->spinlock
, flags
);
2329 devpriv
->intr_enable_bits
&=
2330 ~EN_ADC_INTR_SRC_BIT
& ~EN_ADC_DONE_INTR_BIT
&
2331 ~EN_ADC_ACTIVE_INTR_BIT
& ~EN_ADC_STOP_INTR_BIT
&
2332 ~EN_ADC_OVERRUN_BIT
& ~ADC_INTR_SRC_MASK
;
2333 writew(devpriv
->intr_enable_bits
,
2334 devpriv
->main_iobase
+ INTR_ENABLE_REG
);
2335 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
2337 DEBUG_PRINT("intr enable bits 0x%x\n", devpriv
->intr_enable_bits
);
2340 static void enable_ai_interrupts(struct comedi_device
*dev
,
2341 const struct comedi_cmd
*cmd
)
2343 struct pcidas64_private
*devpriv
= dev
->private;
2345 unsigned long flags
;
2347 bits
= EN_ADC_OVERRUN_BIT
| EN_ADC_DONE_INTR_BIT
|
2348 EN_ADC_ACTIVE_INTR_BIT
| EN_ADC_STOP_INTR_BIT
;
2349 /* Use pio transfer and interrupt on end of conversion if TRIG_WAKE_EOS flag is set. */
2350 if (cmd
->flags
& TRIG_WAKE_EOS
) {
2351 /* 4020 doesn't support pio transfers except for fifo dregs */
2352 if (board(dev
)->layout
!= LAYOUT_4020
)
2353 bits
|= ADC_INTR_EOSCAN_BITS
| EN_ADC_INTR_SRC_BIT
;
2355 spin_lock_irqsave(&dev
->spinlock
, flags
);
2356 devpriv
->intr_enable_bits
|= bits
;
2357 writew(devpriv
->intr_enable_bits
,
2358 devpriv
->main_iobase
+ INTR_ENABLE_REG
);
2359 DEBUG_PRINT("intr enable bits 0x%x\n", devpriv
->intr_enable_bits
);
2360 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
2363 static uint32_t ai_convert_counter_6xxx(const struct comedi_device
*dev
,
2364 const struct comedi_cmd
*cmd
)
2366 /* supposed to load counter with desired divisor minus 3 */
2367 return cmd
->convert_arg
/ TIMER_BASE
- 3;
2370 static uint32_t ai_scan_counter_6xxx(struct comedi_device
*dev
,
2371 struct comedi_cmd
*cmd
)
2374 /* figure out how long we need to delay at end of scan */
2375 switch (cmd
->scan_begin_src
) {
2377 count
= (cmd
->scan_begin_arg
-
2378 (cmd
->convert_arg
* (cmd
->chanlist_len
- 1)))
2382 count
= cmd
->convert_arg
/ TIMER_BASE
;
2391 static uint32_t ai_convert_counter_4020(struct comedi_device
*dev
,
2392 struct comedi_cmd
*cmd
)
2394 struct pcidas64_private
*devpriv
= dev
->private;
2395 unsigned int divisor
;
2397 switch (cmd
->scan_begin_src
) {
2399 divisor
= cmd
->scan_begin_arg
/ TIMER_BASE
;
2402 divisor
= devpriv
->ext_clock
.divisor
;
2404 default: /* should never happen */
2405 comedi_error(dev
, "bug! failed to set ai pacing!");
2410 /* supposed to load counter with desired divisor minus 2 for 4020 */
2414 static void select_master_clock_4020(struct comedi_device
*dev
,
2415 const struct comedi_cmd
*cmd
)
2417 struct pcidas64_private
*devpriv
= dev
->private;
2419 /* select internal/external master clock */
2420 devpriv
->hw_config_bits
&= ~MASTER_CLOCK_4020_MASK
;
2421 if (cmd
->scan_begin_src
== TRIG_OTHER
) {
2422 int chanspec
= devpriv
->ext_clock
.chanspec
;
2424 if (CR_CHAN(chanspec
))
2425 devpriv
->hw_config_bits
|= BNC_CLOCK_4020_BITS
;
2427 devpriv
->hw_config_bits
|= EXT_CLOCK_4020_BITS
;
2429 devpriv
->hw_config_bits
|= INTERNAL_CLOCK_4020_BITS
;
2431 writew(devpriv
->hw_config_bits
,
2432 devpriv
->main_iobase
+ HW_CONFIG_REG
);
2435 static void select_master_clock(struct comedi_device
*dev
,
2436 const struct comedi_cmd
*cmd
)
2438 switch (board(dev
)->layout
) {
2440 select_master_clock_4020(dev
, cmd
);
2447 static inline void dma_start_sync(struct comedi_device
*dev
,
2448 unsigned int channel
)
2450 struct pcidas64_private
*devpriv
= dev
->private;
2451 unsigned long flags
;
2453 /* spinlock for plx dma control/status reg */
2454 spin_lock_irqsave(&dev
->spinlock
, flags
);
2456 writeb(PLX_DMA_EN_BIT
| PLX_DMA_START_BIT
|
2457 PLX_CLEAR_DMA_INTR_BIT
,
2458 devpriv
->plx9080_iobase
+ PLX_DMA1_CS_REG
);
2460 writeb(PLX_DMA_EN_BIT
| PLX_DMA_START_BIT
|
2461 PLX_CLEAR_DMA_INTR_BIT
,
2462 devpriv
->plx9080_iobase
+ PLX_DMA0_CS_REG
);
2463 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
2466 static void set_ai_pacing(struct comedi_device
*dev
, struct comedi_cmd
*cmd
)
2468 struct pcidas64_private
*devpriv
= dev
->private;
2469 uint32_t convert_counter
= 0, scan_counter
= 0;
2471 check_adc_timing(dev
, cmd
);
2473 select_master_clock(dev
, cmd
);
2475 if (board(dev
)->layout
== LAYOUT_4020
) {
2476 convert_counter
= ai_convert_counter_4020(dev
, cmd
);
2478 convert_counter
= ai_convert_counter_6xxx(dev
, cmd
);
2479 scan_counter
= ai_scan_counter_6xxx(dev
, cmd
);
2482 /* load lower 16 bits of convert interval */
2483 writew(convert_counter
& 0xffff,
2484 devpriv
->main_iobase
+ ADC_SAMPLE_INTERVAL_LOWER_REG
);
2485 DEBUG_PRINT("convert counter 0x%x\n", convert_counter
);
2486 /* load upper 8 bits of convert interval */
2487 writew((convert_counter
>> 16) & 0xff,
2488 devpriv
->main_iobase
+ ADC_SAMPLE_INTERVAL_UPPER_REG
);
2489 /* load lower 16 bits of scan delay */
2490 writew(scan_counter
& 0xffff,
2491 devpriv
->main_iobase
+ ADC_DELAY_INTERVAL_LOWER_REG
);
2492 /* load upper 8 bits of scan delay */
2493 writew((scan_counter
>> 16) & 0xff,
2494 devpriv
->main_iobase
+ ADC_DELAY_INTERVAL_UPPER_REG
);
2495 DEBUG_PRINT("scan counter 0x%x\n", scan_counter
);
2498 static int use_internal_queue_6xxx(const struct comedi_cmd
*cmd
)
2501 for (i
= 0; i
+ 1 < cmd
->chanlist_len
; i
++) {
2502 if (CR_CHAN(cmd
->chanlist
[i
+ 1]) !=
2503 CR_CHAN(cmd
->chanlist
[i
]) + 1)
2505 if (CR_RANGE(cmd
->chanlist
[i
+ 1]) !=
2506 CR_RANGE(cmd
->chanlist
[i
]))
2508 if (CR_AREF(cmd
->chanlist
[i
+ 1]) != CR_AREF(cmd
->chanlist
[i
]))
2514 static int setup_channel_queue(struct comedi_device
*dev
,
2515 const struct comedi_cmd
*cmd
)
2517 struct pcidas64_private
*devpriv
= dev
->private;
2518 unsigned short bits
;
2521 if (board(dev
)->layout
!= LAYOUT_4020
) {
2522 if (use_internal_queue_6xxx(cmd
)) {
2523 devpriv
->hw_config_bits
&= ~EXT_QUEUE_BIT
;
2524 writew(devpriv
->hw_config_bits
,
2525 devpriv
->main_iobase
+ HW_CONFIG_REG
);
2528 bits
|= adc_chan_bits(CR_CHAN(cmd
->chanlist
[0]));
2530 bits
|= ai_range_bits_6xxx(dev
,
2531 CR_RANGE(cmd
->chanlist
[0]));
2532 /* set single-ended / differential */
2533 bits
|= se_diff_bit_6xxx(dev
,
2534 CR_AREF(cmd
->chanlist
[0]) ==
2536 if (CR_AREF(cmd
->chanlist
[0]) == AREF_COMMON
)
2537 bits
|= ADC_COMMON_BIT
;
2538 /* set stop channel */
2539 writew(adc_chan_bits
2540 (CR_CHAN(cmd
->chanlist
[cmd
->chanlist_len
- 1])),
2541 devpriv
->main_iobase
+ ADC_QUEUE_HIGH_REG
);
2542 /* set start channel, and rest of settings */
2544 devpriv
->main_iobase
+ ADC_QUEUE_LOAD_REG
);
2546 /* use external queue */
2547 if (dev
->write_subdev
&& dev
->write_subdev
->busy
) {
2548 warn_external_queue(dev
);
2551 devpriv
->hw_config_bits
|= EXT_QUEUE_BIT
;
2552 writew(devpriv
->hw_config_bits
,
2553 devpriv
->main_iobase
+ HW_CONFIG_REG
);
2554 /* clear DAC buffer to prevent weird interactions */
2556 devpriv
->main_iobase
+ DAC_BUFFER_CLEAR_REG
);
2557 /* clear queue pointer */
2558 writew(0, devpriv
->main_iobase
+ ADC_QUEUE_CLEAR_REG
);
2559 /* load external queue */
2560 for (i
= 0; i
< cmd
->chanlist_len
; i
++) {
2564 adc_chan_bits(CR_CHAN(cmd
->chanlist
[i
]));
2566 bits
|= ai_range_bits_6xxx(dev
,
2570 /* set single-ended / differential */
2571 bits
|= se_diff_bit_6xxx(dev
,
2575 if (CR_AREF(cmd
->chanlist
[i
]) == AREF_COMMON
)
2576 bits
|= ADC_COMMON_BIT
;
2577 /* mark end of queue */
2578 if (i
== cmd
->chanlist_len
- 1)
2579 bits
|= QUEUE_EOSCAN_BIT
|
2582 devpriv
->main_iobase
+
2583 ADC_QUEUE_FIFO_REG
);
2585 ("wrote 0x%x to external channel queue\n",
2588 /* doing a queue clear is not specified in board docs,
2589 * but required for reliable operation */
2590 writew(0, devpriv
->main_iobase
+ ADC_QUEUE_CLEAR_REG
);
2591 /* prime queue holding register */
2592 writew(0, devpriv
->main_iobase
+ ADC_QUEUE_LOAD_REG
);
2595 unsigned short old_cal_range_bits
=
2596 devpriv
->i2c_cal_range_bits
;
2598 devpriv
->i2c_cal_range_bits
&= ~ADC_SRC_4020_MASK
;
2599 /* select BNC inputs */
2600 devpriv
->i2c_cal_range_bits
|= adc_src_4020_bits(4);
2602 for (i
= 0; i
< cmd
->chanlist_len
; i
++) {
2603 unsigned int channel
= CR_CHAN(cmd
->chanlist
[i
]);
2604 unsigned int range
= CR_RANGE(cmd
->chanlist
[i
]);
2607 devpriv
->i2c_cal_range_bits
|=
2608 attenuate_bit(channel
);
2610 devpriv
->i2c_cal_range_bits
&=
2611 ~attenuate_bit(channel
);
2613 /* update calibration/range i2c register only if necessary, as it is very slow */
2614 if (old_cal_range_bits
!= devpriv
->i2c_cal_range_bits
) {
2615 uint8_t i2c_data
= devpriv
->i2c_cal_range_bits
;
2616 i2c_write(dev
, RANGE_CAL_I2C_ADDR
, &i2c_data
,
2623 static inline void load_first_dma_descriptor(struct comedi_device
*dev
,
2624 unsigned int dma_channel
,
2625 unsigned int descriptor_bits
)
2627 struct pcidas64_private
*devpriv
= dev
->private;
2629 /* The transfer size, pci address, and local address registers
2630 * are supposedly unused during chained dma,
2631 * but I have found that left over values from last operation
2632 * occasionally cause problems with transfer of first dma
2633 * block. Initializing them to zero seems to fix the problem. */
2636 devpriv
->plx9080_iobase
+ PLX_DMA1_TRANSFER_SIZE_REG
);
2637 writel(0, devpriv
->plx9080_iobase
+ PLX_DMA1_PCI_ADDRESS_REG
);
2639 devpriv
->plx9080_iobase
+ PLX_DMA1_LOCAL_ADDRESS_REG
);
2640 writel(descriptor_bits
,
2641 devpriv
->plx9080_iobase
+ PLX_DMA1_DESCRIPTOR_REG
);
2644 devpriv
->plx9080_iobase
+ PLX_DMA0_TRANSFER_SIZE_REG
);
2645 writel(0, devpriv
->plx9080_iobase
+ PLX_DMA0_PCI_ADDRESS_REG
);
2647 devpriv
->plx9080_iobase
+ PLX_DMA0_LOCAL_ADDRESS_REG
);
2648 writel(descriptor_bits
,
2649 devpriv
->plx9080_iobase
+ PLX_DMA0_DESCRIPTOR_REG
);
2653 static int ai_cmd(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
2655 struct pcidas64_private
*devpriv
= dev
->private;
2656 struct comedi_async
*async
= s
->async
;
2657 struct comedi_cmd
*cmd
= &async
->cmd
;
2660 unsigned long flags
;
2663 disable_ai_pacing(dev
);
2666 retval
= setup_channel_queue(dev
, cmd
);
2670 /* make sure internal calibration source is turned off */
2671 writew(0, devpriv
->main_iobase
+ CALIBRATION_REG
);
2673 set_ai_pacing(dev
, cmd
);
2675 setup_sample_counters(dev
, cmd
);
2677 enable_ai_interrupts(dev
, cmd
);
2679 spin_lock_irqsave(&dev
->spinlock
, flags
);
2680 /* set mode, allow conversions through software gate */
2681 devpriv
->adc_control1_bits
|= ADC_SW_GATE_BIT
;
2682 devpriv
->adc_control1_bits
&= ~ADC_DITHER_BIT
;
2683 if (board(dev
)->layout
!= LAYOUT_4020
) {
2684 devpriv
->adc_control1_bits
&= ~ADC_MODE_MASK
;
2685 if (cmd
->convert_src
== TRIG_EXT
)
2686 devpriv
->adc_control1_bits
|= adc_mode_bits(13); /* good old mode 13 */
2688 devpriv
->adc_control1_bits
|= adc_mode_bits(8); /* mode 8. What else could you need? */
2690 devpriv
->adc_control1_bits
&= ~CHANNEL_MODE_4020_MASK
;
2691 if (cmd
->chanlist_len
== 4)
2692 devpriv
->adc_control1_bits
|= FOUR_CHANNEL_4020_BITS
;
2693 else if (cmd
->chanlist_len
== 2)
2694 devpriv
->adc_control1_bits
|= TWO_CHANNEL_4020_BITS
;
2695 devpriv
->adc_control1_bits
&= ~ADC_LO_CHANNEL_4020_MASK
;
2696 devpriv
->adc_control1_bits
|=
2697 adc_lo_chan_4020_bits(CR_CHAN(cmd
->chanlist
[0]));
2698 devpriv
->adc_control1_bits
&= ~ADC_HI_CHANNEL_4020_MASK
;
2699 devpriv
->adc_control1_bits
|=
2700 adc_hi_chan_4020_bits(CR_CHAN
2702 chanlist
[cmd
->chanlist_len
- 1]));
2704 writew(devpriv
->adc_control1_bits
,
2705 devpriv
->main_iobase
+ ADC_CONTROL1_REG
);
2706 DEBUG_PRINT("control1 bits 0x%x\n", devpriv
->adc_control1_bits
);
2707 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
2709 /* clear adc buffer */
2710 writew(0, devpriv
->main_iobase
+ ADC_BUFFER_CLEAR_REG
);
2712 if ((cmd
->flags
& TRIG_WAKE_EOS
) == 0 ||
2713 board(dev
)->layout
== LAYOUT_4020
) {
2714 devpriv
->ai_dma_index
= 0;
2716 /* set dma transfer size */
2717 for (i
= 0; i
< ai_dma_ring_count(board(dev
)); i
++)
2718 devpriv
->ai_dma_desc
[i
].transfer_size
=
2719 cpu_to_le32(dma_transfer_size(dev
) *
2722 /* give location of first dma descriptor */
2723 load_first_dma_descriptor(dev
, 1,
2724 devpriv
->ai_dma_desc_bus_addr
|
2725 PLX_DESC_IN_PCI_BIT
|
2726 PLX_INTR_TERM_COUNT
|
2727 PLX_XFER_LOCAL_TO_PCI
);
2729 dma_start_sync(dev
, 1);
2732 if (board(dev
)->layout
== LAYOUT_4020
) {
2733 /* set source for external triggers */
2735 if (cmd
->start_src
== TRIG_EXT
&& CR_CHAN(cmd
->start_arg
))
2736 bits
|= EXT_START_TRIG_BNC_BIT
;
2737 if (cmd
->stop_src
== TRIG_EXT
&& CR_CHAN(cmd
->stop_arg
))
2738 bits
|= EXT_STOP_TRIG_BNC_BIT
;
2739 writew(bits
, devpriv
->main_iobase
+ DAQ_ATRIG_LOW_4020_REG
);
2742 spin_lock_irqsave(&dev
->spinlock
, flags
);
2744 /* enable pacing, triggering, etc */
2745 bits
= ADC_ENABLE_BIT
| ADC_SOFT_GATE_BITS
| ADC_GATE_LEVEL_BIT
;
2746 if (cmd
->flags
& TRIG_WAKE_EOS
)
2747 bits
|= ADC_DMA_DISABLE_BIT
;
2748 /* set start trigger */
2749 if (cmd
->start_src
== TRIG_EXT
) {
2750 bits
|= ADC_START_TRIG_EXT_BITS
;
2751 if (cmd
->start_arg
& CR_INVERT
)
2752 bits
|= ADC_START_TRIG_FALLING_BIT
;
2753 } else if (cmd
->start_src
== TRIG_NOW
)
2754 bits
|= ADC_START_TRIG_SOFT_BITS
;
2755 if (use_hw_sample_counter(cmd
))
2756 bits
|= ADC_SAMPLE_COUNTER_EN_BIT
;
2757 writew(bits
, devpriv
->main_iobase
+ ADC_CONTROL0_REG
);
2758 DEBUG_PRINT("control0 bits 0x%x\n", bits
);
2760 devpriv
->ai_cmd_running
= 1;
2762 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
2764 /* start acquisition */
2765 if (cmd
->start_src
== TRIG_NOW
) {
2766 writew(0, devpriv
->main_iobase
+ ADC_START_REG
);
2767 DEBUG_PRINT("soft trig\n");
2773 /* read num_samples from 16 bit wide ai fifo */
2774 static void pio_drain_ai_fifo_16(struct comedi_device
*dev
)
2776 struct pcidas64_private
*devpriv
= dev
->private;
2777 struct comedi_subdevice
*s
= dev
->read_subdev
;
2778 struct comedi_async
*async
= s
->async
;
2779 struct comedi_cmd
*cmd
= &async
->cmd
;
2781 uint16_t prepost_bits
;
2782 int read_segment
, read_index
, write_segment
, write_index
;
2786 /* get least significant 15 bits */
2788 readw(devpriv
->main_iobase
+ ADC_READ_PNTR_REG
) & 0x7fff;
2790 readw(devpriv
->main_iobase
+ ADC_WRITE_PNTR_REG
) & 0x7fff;
2791 /* Get most significant bits (grey code). Different boards use different code
2792 * so use a scheme that doesn't depend on encoding. This read must
2793 * occur after reading least significant 15 bits to avoid race
2794 * with fifo switching to next segment. */
2795 prepost_bits
= readw(devpriv
->main_iobase
+ PREPOST_REG
);
2797 /* if read and write pointers are not on the same fifo segment, read to the
2798 * end of the read segment */
2799 read_segment
= adc_upper_read_ptr_code(prepost_bits
);
2800 write_segment
= adc_upper_write_ptr_code(prepost_bits
);
2802 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2803 read_segment
, write_segment
, read_index
,
2806 if (read_segment
!= write_segment
)
2808 devpriv
->ai_fifo_segment_length
- read_index
;
2810 num_samples
= write_index
- read_index
;
2812 if (cmd
->stop_src
== TRIG_COUNT
) {
2813 if (devpriv
->ai_count
== 0)
2815 if (num_samples
> devpriv
->ai_count
)
2816 num_samples
= devpriv
->ai_count
;
2818 devpriv
->ai_count
-= num_samples
;
2821 if (num_samples
< 0) {
2822 dev_err(dev
->class_dev
,
2823 "cb_pcidas64: bug! num_samples < 0\n");
2827 DEBUG_PRINT(" read %i samples from fifo\n", num_samples
);
2829 for (i
= 0; i
< num_samples
; i
++) {
2830 cfc_write_to_buffer(s
,
2831 readw(devpriv
->main_iobase
+
2835 } while (read_segment
!= write_segment
);
2838 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of pointers.
2839 * The pci-4020 hardware only supports
2840 * dma transfers (it only supports the use of pio for draining the last remaining
2841 * points from the fifo when a data acquisition operation has completed).
2843 static void pio_drain_ai_fifo_32(struct comedi_device
*dev
)
2845 struct pcidas64_private
*devpriv
= dev
->private;
2846 struct comedi_subdevice
*s
= dev
->read_subdev
;
2847 struct comedi_async
*async
= s
->async
;
2848 struct comedi_cmd
*cmd
= &async
->cmd
;
2850 unsigned int max_transfer
= 100000;
2853 readw(devpriv
->main_iobase
+ ADC_WRITE_PNTR_REG
) & 0x7fff;
2855 readw(devpriv
->main_iobase
+ ADC_READ_PNTR_REG
) & 0x7fff;
2857 if (cmd
->stop_src
== TRIG_COUNT
) {
2858 if (max_transfer
> devpriv
->ai_count
)
2859 max_transfer
= devpriv
->ai_count
;
2862 for (i
= 0; read_code
!= write_code
&& i
< max_transfer
;) {
2863 fifo_data
= readl(devpriv
->dio_counter_iobase
+ ADC_FIFO_REG
);
2864 cfc_write_to_buffer(s
, fifo_data
& 0xffff);
2866 if (i
< max_transfer
) {
2867 cfc_write_to_buffer(s
, (fifo_data
>> 16) & 0xffff);
2871 readw(devpriv
->main_iobase
+ ADC_READ_PNTR_REG
) & 0x7fff;
2873 devpriv
->ai_count
-= i
;
2877 static void pio_drain_ai_fifo(struct comedi_device
*dev
)
2879 if (board(dev
)->layout
== LAYOUT_4020
)
2880 pio_drain_ai_fifo_32(dev
);
2882 pio_drain_ai_fifo_16(dev
);
2885 static void drain_dma_buffers(struct comedi_device
*dev
, unsigned int channel
)
2887 struct pcidas64_private
*devpriv
= dev
->private;
2888 struct comedi_async
*async
= dev
->read_subdev
->async
;
2889 uint32_t next_transfer_addr
;
2891 int num_samples
= 0;
2892 void __iomem
*pci_addr_reg
;
2896 devpriv
->plx9080_iobase
+ PLX_DMA1_PCI_ADDRESS_REG
;
2899 devpriv
->plx9080_iobase
+ PLX_DMA0_PCI_ADDRESS_REG
;
2901 /* loop until we have read all the full buffers */
2902 for (j
= 0, next_transfer_addr
= readl(pci_addr_reg
);
2903 (next_transfer_addr
<
2904 devpriv
->ai_buffer_bus_addr
[devpriv
->ai_dma_index
]
2905 || next_transfer_addr
>=
2906 devpriv
->ai_buffer_bus_addr
[devpriv
->ai_dma_index
] +
2907 DMA_BUFFER_SIZE
) && j
< ai_dma_ring_count(board(dev
)); j
++) {
2908 /* transfer data from dma buffer to comedi buffer */
2909 num_samples
= dma_transfer_size(dev
);
2910 if (async
->cmd
.stop_src
== TRIG_COUNT
) {
2911 if (num_samples
> devpriv
->ai_count
)
2912 num_samples
= devpriv
->ai_count
;
2913 devpriv
->ai_count
-= num_samples
;
2915 cfc_write_array_to_buffer(dev
->read_subdev
,
2916 devpriv
->ai_buffer
[devpriv
->
2918 num_samples
* sizeof(uint16_t));
2919 devpriv
->ai_dma_index
=
2920 (devpriv
->ai_dma_index
+
2921 1) % ai_dma_ring_count(board(dev
));
2923 DEBUG_PRINT("next buffer addr 0x%lx\n",
2924 (unsigned long)devpriv
->
2925 ai_buffer_bus_addr
[devpriv
->ai_dma_index
]);
2926 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr
);
2928 /* XXX check for dma ring buffer overrun (use end-of-chain bit to mark last
2932 static void handle_ai_interrupt(struct comedi_device
*dev
,
2933 unsigned short status
,
2934 unsigned int plx_status
)
2936 struct pcidas64_private
*devpriv
= dev
->private;
2937 struct comedi_subdevice
*s
= dev
->read_subdev
;
2938 struct comedi_async
*async
= s
->async
;
2939 struct comedi_cmd
*cmd
= &async
->cmd
;
2940 uint8_t dma1_status
;
2941 unsigned long flags
;
2943 /* check for fifo overrun */
2944 if (status
& ADC_OVERRUN_BIT
) {
2945 comedi_error(dev
, "fifo overrun");
2946 async
->events
|= COMEDI_CB_EOA
| COMEDI_CB_ERROR
;
2948 /* spin lock makes sure no one else changes plx dma control reg */
2949 spin_lock_irqsave(&dev
->spinlock
, flags
);
2950 dma1_status
= readb(devpriv
->plx9080_iobase
+ PLX_DMA1_CS_REG
);
2951 if (plx_status
& ICS_DMA1_A
) { /* dma chan 1 interrupt */
2952 writeb((dma1_status
& PLX_DMA_EN_BIT
) | PLX_CLEAR_DMA_INTR_BIT
,
2953 devpriv
->plx9080_iobase
+ PLX_DMA1_CS_REG
);
2954 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status
);
2956 if (dma1_status
& PLX_DMA_EN_BIT
)
2957 drain_dma_buffers(dev
, 1);
2959 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
2961 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
2963 if (status
& ADC_DONE_BIT
)
2964 DEBUG_PRINT("adc done interrupt\n");
2966 /* drain fifo with pio */
2967 if ((status
& ADC_DONE_BIT
) ||
2968 ((cmd
->flags
& TRIG_WAKE_EOS
) &&
2969 (status
& ADC_INTR_PENDING_BIT
) &&
2970 (board(dev
)->layout
!= LAYOUT_4020
))) {
2971 DEBUG_PRINT("pio fifo drain\n");
2972 spin_lock_irqsave(&dev
->spinlock
, flags
);
2973 if (devpriv
->ai_cmd_running
) {
2974 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
2975 pio_drain_ai_fifo(dev
);
2977 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
2979 /* if we are have all the data, then quit */
2980 if ((cmd
->stop_src
== TRIG_COUNT
&& (int)devpriv
->ai_count
<= 0) ||
2981 (cmd
->stop_src
== TRIG_EXT
&& (status
& ADC_STOP_BIT
))) {
2982 async
->events
|= COMEDI_CB_EOA
;
2985 cfc_handle_events(dev
, s
);
2988 static inline unsigned int prev_ao_dma_index(struct comedi_device
*dev
)
2990 struct pcidas64_private
*devpriv
= dev
->private;
2991 unsigned int buffer_index
;
2993 if (devpriv
->ao_dma_index
== 0)
2994 buffer_index
= AO_DMA_RING_COUNT
- 1;
2996 buffer_index
= devpriv
->ao_dma_index
- 1;
2997 return buffer_index
;
3000 static int last_ao_dma_load_completed(struct comedi_device
*dev
)
3002 struct pcidas64_private
*devpriv
= dev
->private;
3003 unsigned int buffer_index
;
3004 unsigned int transfer_address
;
3005 unsigned short dma_status
;
3007 buffer_index
= prev_ao_dma_index(dev
);
3008 dma_status
= readb(devpriv
->plx9080_iobase
+ PLX_DMA0_CS_REG
);
3009 if ((dma_status
& PLX_DMA_DONE_BIT
) == 0)
3013 readl(devpriv
->plx9080_iobase
+ PLX_DMA0_PCI_ADDRESS_REG
);
3014 if (transfer_address
!= devpriv
->ao_buffer_bus_addr
[buffer_index
])
3020 static int ao_stopped_by_error(struct comedi_device
*dev
,
3021 const struct comedi_cmd
*cmd
)
3023 struct pcidas64_private
*devpriv
= dev
->private;
3025 if (cmd
->stop_src
== TRIG_NONE
)
3027 if (cmd
->stop_src
== TRIG_COUNT
) {
3028 if (devpriv
->ao_count
)
3030 if (last_ao_dma_load_completed(dev
) == 0)
3036 static inline int ao_dma_needs_restart(struct comedi_device
*dev
,
3037 unsigned short dma_status
)
3039 if ((dma_status
& PLX_DMA_DONE_BIT
) == 0 ||
3040 (dma_status
& PLX_DMA_EN_BIT
) == 0)
3042 if (last_ao_dma_load_completed(dev
))
3048 static void restart_ao_dma(struct comedi_device
*dev
)
3050 struct pcidas64_private
*devpriv
= dev
->private;
3051 unsigned int dma_desc_bits
;
3054 readl(devpriv
->plx9080_iobase
+ PLX_DMA0_DESCRIPTOR_REG
);
3055 dma_desc_bits
&= ~PLX_END_OF_CHAIN_BIT
;
3056 DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits
);
3057 load_first_dma_descriptor(dev
, 0, dma_desc_bits
);
3059 dma_start_sync(dev
, 0);
3062 static void handle_ao_interrupt(struct comedi_device
*dev
,
3063 unsigned short status
, unsigned int plx_status
)
3065 struct pcidas64_private
*devpriv
= dev
->private;
3066 struct comedi_subdevice
*s
= dev
->write_subdev
;
3067 struct comedi_async
*async
;
3068 struct comedi_cmd
*cmd
;
3069 uint8_t dma0_status
;
3070 unsigned long flags
;
3072 /* board might not support ao, in which case write_subdev is NULL */
3078 /* spin lock makes sure no one else changes plx dma control reg */
3079 spin_lock_irqsave(&dev
->spinlock
, flags
);
3080 dma0_status
= readb(devpriv
->plx9080_iobase
+ PLX_DMA0_CS_REG
);
3081 if (plx_status
& ICS_DMA0_A
) { /* dma chan 0 interrupt */
3082 if ((dma0_status
& PLX_DMA_EN_BIT
)
3083 && !(dma0_status
& PLX_DMA_DONE_BIT
))
3084 writeb(PLX_DMA_EN_BIT
| PLX_CLEAR_DMA_INTR_BIT
,
3085 devpriv
->plx9080_iobase
+ PLX_DMA0_CS_REG
);
3087 writeb(PLX_CLEAR_DMA_INTR_BIT
,
3088 devpriv
->plx9080_iobase
+ PLX_DMA0_CS_REG
);
3089 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
3090 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status
);
3091 if (dma0_status
& PLX_DMA_EN_BIT
) {
3092 load_ao_dma(dev
, cmd
);
3093 /* try to recover from dma end-of-chain event */
3094 if (ao_dma_needs_restart(dev
, dma0_status
))
3095 restart_ao_dma(dev
);
3097 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3099 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
3101 if ((status
& DAC_DONE_BIT
)) {
3102 async
->events
|= COMEDI_CB_EOA
;
3103 if (ao_stopped_by_error(dev
, cmd
))
3104 async
->events
|= COMEDI_CB_ERROR
;
3105 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3106 readl(devpriv
->plx9080_iobase
+
3107 PLX_DMA0_DESCRIPTOR_REG
));
3108 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3109 readl(devpriv
->plx9080_iobase
+
3110 PLX_DMA0_PCI_ADDRESS_REG
));
3112 cfc_handle_events(dev
, s
);
3115 static irqreturn_t
handle_interrupt(int irq
, void *d
)
3117 struct comedi_device
*dev
= d
;
3118 struct pcidas64_private
*devpriv
= dev
->private;
3119 unsigned short status
;
3120 uint32_t plx_status
;
3123 plx_status
= readl(devpriv
->plx9080_iobase
+ PLX_INTRCS_REG
);
3124 status
= readw(devpriv
->main_iobase
+ HW_STATUS_REG
);
3126 DEBUG_PRINT("cb_pcidas64: hw status 0x%x ", status
);
3127 DEBUG_PRINT("plx status 0x%x\n", plx_status
);
3129 /* an interrupt before all the postconfig stuff gets done could
3130 * cause a NULL dereference if we continue through the
3131 * interrupt handler */
3132 if (dev
->attached
== 0) {
3133 DEBUG_PRINT("cb_pcidas64: premature interrupt, ignoring",
3137 handle_ai_interrupt(dev
, status
, plx_status
);
3138 handle_ao_interrupt(dev
, status
, plx_status
);
3140 /* clear possible plx9080 interrupt sources */
3141 if (plx_status
& ICS_LDIA
) { /* clear local doorbell interrupt */
3142 plx_bits
= readl(devpriv
->plx9080_iobase
+ PLX_DBR_OUT_REG
);
3143 writel(plx_bits
, devpriv
->plx9080_iobase
+ PLX_DBR_OUT_REG
);
3144 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits
);
3147 DEBUG_PRINT("exiting handler\n");
3152 static void abort_dma(struct comedi_device
*dev
, unsigned int channel
)
3154 struct pcidas64_private
*devpriv
= dev
->private;
3155 unsigned long flags
;
3157 /* spinlock for plx dma control/status reg */
3158 spin_lock_irqsave(&dev
->spinlock
, flags
);
3160 plx9080_abort_dma(devpriv
->plx9080_iobase
, channel
);
3162 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
3165 static int ai_cancel(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
3167 struct pcidas64_private
*devpriv
= dev
->private;
3168 unsigned long flags
;
3170 spin_lock_irqsave(&dev
->spinlock
, flags
);
3171 if (devpriv
->ai_cmd_running
== 0) {
3172 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
3175 devpriv
->ai_cmd_running
= 0;
3176 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
3178 disable_ai_pacing(dev
);
3182 DEBUG_PRINT("ai canceled\n");
3186 static int ao_winsn(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3187 struct comedi_insn
*insn
, unsigned int *data
)
3189 struct pcidas64_private
*devpriv
= dev
->private;
3190 int chan
= CR_CHAN(insn
->chanspec
);
3191 int range
= CR_RANGE(insn
->chanspec
);
3193 /* do some initializing */
3194 writew(0, devpriv
->main_iobase
+ DAC_CONTROL0_REG
);
3197 set_dac_range_bits(dev
, &devpriv
->dac_control1_bits
, chan
, range
);
3198 writew(devpriv
->dac_control1_bits
,
3199 devpriv
->main_iobase
+ DAC_CONTROL1_REG
);
3201 /* write to channel */
3202 if (board(dev
)->layout
== LAYOUT_4020
) {
3203 writew(data
[0] & 0xff,
3204 devpriv
->main_iobase
+ dac_lsb_4020_reg(chan
));
3205 writew((data
[0] >> 8) & 0xf,
3206 devpriv
->main_iobase
+ dac_msb_4020_reg(chan
));
3208 writew(data
[0], devpriv
->main_iobase
+ dac_convert_reg(chan
));
3211 /* remember output value */
3212 devpriv
->ao_value
[chan
] = data
[0];
3217 static int ao_readback_insn(struct comedi_device
*dev
,
3218 struct comedi_subdevice
*s
,
3219 struct comedi_insn
*insn
, unsigned int *data
)
3221 struct pcidas64_private
*devpriv
= dev
->private;
3223 data
[0] = devpriv
->ao_value
[CR_CHAN(insn
->chanspec
)];
3228 static void set_dac_control0_reg(struct comedi_device
*dev
,
3229 const struct comedi_cmd
*cmd
)
3231 struct pcidas64_private
*devpriv
= dev
->private;
3232 unsigned int bits
= DAC_ENABLE_BIT
| WAVEFORM_GATE_LEVEL_BIT
|
3233 WAVEFORM_GATE_ENABLE_BIT
| WAVEFORM_GATE_SELECT_BIT
;
3235 if (cmd
->start_src
== TRIG_EXT
) {
3236 bits
|= WAVEFORM_TRIG_EXT_BITS
;
3237 if (cmd
->start_arg
& CR_INVERT
)
3238 bits
|= WAVEFORM_TRIG_FALLING_BIT
;
3240 bits
|= WAVEFORM_TRIG_SOFT_BITS
;
3242 if (cmd
->scan_begin_src
== TRIG_EXT
) {
3243 bits
|= DAC_EXT_UPDATE_ENABLE_BIT
;
3244 if (cmd
->scan_begin_arg
& CR_INVERT
)
3245 bits
|= DAC_EXT_UPDATE_FALLING_BIT
;
3247 writew(bits
, devpriv
->main_iobase
+ DAC_CONTROL0_REG
);
3250 static void set_dac_control1_reg(struct comedi_device
*dev
,
3251 const struct comedi_cmd
*cmd
)
3253 struct pcidas64_private
*devpriv
= dev
->private;
3256 for (i
= 0; i
< cmd
->chanlist_len
; i
++) {
3259 channel
= CR_CHAN(cmd
->chanlist
[i
]);
3260 range
= CR_RANGE(cmd
->chanlist
[i
]);
3261 set_dac_range_bits(dev
, &devpriv
->dac_control1_bits
, channel
,
3264 devpriv
->dac_control1_bits
|= DAC_SW_GATE_BIT
;
3265 writew(devpriv
->dac_control1_bits
,
3266 devpriv
->main_iobase
+ DAC_CONTROL1_REG
);
3269 static void set_dac_select_reg(struct comedi_device
*dev
,
3270 const struct comedi_cmd
*cmd
)
3272 struct pcidas64_private
*devpriv
= dev
->private;
3274 unsigned int first_channel
, last_channel
;
3276 first_channel
= CR_CHAN(cmd
->chanlist
[0]);
3277 last_channel
= CR_CHAN(cmd
->chanlist
[cmd
->chanlist_len
- 1]);
3278 if (last_channel
< first_channel
)
3279 comedi_error(dev
, "bug! last ao channel < first ao channel");
3281 bits
= (first_channel
& 0x7) | (last_channel
& 0x7) << 3;
3283 writew(bits
, devpriv
->main_iobase
+ DAC_SELECT_REG
);
3286 static void set_dac_interval_regs(struct comedi_device
*dev
,
3287 const struct comedi_cmd
*cmd
)
3289 struct pcidas64_private
*devpriv
= dev
->private;
3290 unsigned int divisor
;
3292 if (cmd
->scan_begin_src
!= TRIG_TIMER
)
3295 divisor
= get_ao_divisor(cmd
->scan_begin_arg
, cmd
->flags
);
3296 if (divisor
> max_counter_value
) {
3297 comedi_error(dev
, "bug! ao divisor too big");
3298 divisor
= max_counter_value
;
3300 writew(divisor
& 0xffff,
3301 devpriv
->main_iobase
+ DAC_SAMPLE_INTERVAL_LOWER_REG
);
3302 writew((divisor
>> 16) & 0xff,
3303 devpriv
->main_iobase
+ DAC_SAMPLE_INTERVAL_UPPER_REG
);
3306 static unsigned int load_ao_dma_buffer(struct comedi_device
*dev
,
3307 const struct comedi_cmd
*cmd
)
3309 struct pcidas64_private
*devpriv
= dev
->private;
3310 unsigned int num_bytes
, buffer_index
, prev_buffer_index
;
3311 unsigned int next_bits
;
3313 buffer_index
= devpriv
->ao_dma_index
;
3314 prev_buffer_index
= prev_ao_dma_index(dev
);
3316 DEBUG_PRINT("attempting to load ao buffer %i (0x%x)\n", buffer_index
,
3317 devpriv
->ao_buffer_bus_addr
[buffer_index
]);
3319 num_bytes
= comedi_buf_read_n_available(dev
->write_subdev
->async
);
3320 if (num_bytes
> DMA_BUFFER_SIZE
)
3321 num_bytes
= DMA_BUFFER_SIZE
;
3322 if (cmd
->stop_src
== TRIG_COUNT
&& num_bytes
> devpriv
->ao_count
)
3323 num_bytes
= devpriv
->ao_count
;
3324 num_bytes
-= num_bytes
% bytes_in_sample
;
3329 DEBUG_PRINT("loading %i bytes\n", num_bytes
);
3331 num_bytes
= cfc_read_array_from_buffer(dev
->write_subdev
,
3333 ao_buffer
[buffer_index
],
3335 devpriv
->ao_dma_desc
[buffer_index
].transfer_size
=
3336 cpu_to_le32(num_bytes
);
3337 /* set end of chain bit so we catch underruns */
3338 next_bits
= le32_to_cpu(devpriv
->ao_dma_desc
[buffer_index
].next
);
3339 next_bits
|= PLX_END_OF_CHAIN_BIT
;
3340 devpriv
->ao_dma_desc
[buffer_index
].next
= cpu_to_le32(next_bits
);
3341 /* clear end of chain bit on previous buffer now that we have set it
3342 * for the last buffer */
3343 next_bits
= le32_to_cpu(devpriv
->ao_dma_desc
[prev_buffer_index
].next
);
3344 next_bits
&= ~PLX_END_OF_CHAIN_BIT
;
3345 devpriv
->ao_dma_desc
[prev_buffer_index
].next
= cpu_to_le32(next_bits
);
3347 devpriv
->ao_dma_index
= (buffer_index
+ 1) % AO_DMA_RING_COUNT
;
3348 devpriv
->ao_count
-= num_bytes
;
3353 static void load_ao_dma(struct comedi_device
*dev
, const struct comedi_cmd
*cmd
)
3355 struct pcidas64_private
*devpriv
= dev
->private;
3356 unsigned int num_bytes
;
3357 unsigned int next_transfer_addr
;
3358 void __iomem
*pci_addr_reg
=
3359 devpriv
->plx9080_iobase
+ PLX_DMA0_PCI_ADDRESS_REG
;
3360 unsigned int buffer_index
;
3363 buffer_index
= devpriv
->ao_dma_index
;
3364 /* don't overwrite data that hasn't been transferred yet */
3365 next_transfer_addr
= readl(pci_addr_reg
);
3366 if (next_transfer_addr
>=
3367 devpriv
->ao_buffer_bus_addr
[buffer_index
]
3368 && next_transfer_addr
<
3369 devpriv
->ao_buffer_bus_addr
[buffer_index
] +
3372 num_bytes
= load_ao_dma_buffer(dev
, cmd
);
3373 } while (num_bytes
>= DMA_BUFFER_SIZE
);
3376 static int prep_ao_dma(struct comedi_device
*dev
, const struct comedi_cmd
*cmd
)
3378 struct pcidas64_private
*devpriv
= dev
->private;
3379 unsigned int num_bytes
;
3382 /* clear queue pointer too, since external queue has
3383 * weird interactions with ao fifo */
3384 writew(0, devpriv
->main_iobase
+ ADC_QUEUE_CLEAR_REG
);
3385 writew(0, devpriv
->main_iobase
+ DAC_BUFFER_CLEAR_REG
);
3387 num_bytes
= (DAC_FIFO_SIZE
/ 2) * bytes_in_sample
;
3388 if (cmd
->stop_src
== TRIG_COUNT
&&
3389 num_bytes
/ bytes_in_sample
> devpriv
->ao_count
)
3390 num_bytes
= devpriv
->ao_count
* bytes_in_sample
;
3391 num_bytes
= cfc_read_array_from_buffer(dev
->write_subdev
,
3392 devpriv
->ao_bounce_buffer
,
3394 for (i
= 0; i
< num_bytes
/ bytes_in_sample
; i
++) {
3395 writew(devpriv
->ao_bounce_buffer
[i
],
3396 devpriv
->main_iobase
+ DAC_FIFO_REG
);
3398 devpriv
->ao_count
-= num_bytes
/ bytes_in_sample
;
3399 if (cmd
->stop_src
== TRIG_COUNT
&& devpriv
->ao_count
== 0)
3401 num_bytes
= load_ao_dma_buffer(dev
, cmd
);
3404 if (num_bytes
>= DMA_BUFFER_SIZE
) ;
3405 load_ao_dma(dev
, cmd
);
3407 dma_start_sync(dev
, 0);
3412 static inline int external_ai_queue_in_use(struct comedi_device
*dev
)
3414 if (dev
->read_subdev
->busy
)
3416 if (board(dev
)->layout
== LAYOUT_4020
)
3418 else if (use_internal_queue_6xxx(&dev
->read_subdev
->async
->cmd
))
3423 static int ao_cmd(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
3425 struct pcidas64_private
*devpriv
= dev
->private;
3426 struct comedi_cmd
*cmd
= &s
->async
->cmd
;
3428 if (external_ai_queue_in_use(dev
)) {
3429 warn_external_queue(dev
);
3432 /* disable analog output system during setup */
3433 writew(0x0, devpriv
->main_iobase
+ DAC_CONTROL0_REG
);
3435 devpriv
->ao_dma_index
= 0;
3436 devpriv
->ao_count
= cmd
->stop_arg
* cmd
->chanlist_len
;
3438 set_dac_select_reg(dev
, cmd
);
3439 set_dac_interval_regs(dev
, cmd
);
3440 load_first_dma_descriptor(dev
, 0, devpriv
->ao_dma_desc_bus_addr
|
3441 PLX_DESC_IN_PCI_BIT
| PLX_INTR_TERM_COUNT
);
3443 set_dac_control1_reg(dev
, cmd
);
3444 s
->async
->inttrig
= ao_inttrig
;
3449 static int ao_inttrig(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3450 unsigned int trig_num
)
3452 struct pcidas64_private
*devpriv
= dev
->private;
3453 struct comedi_cmd
*cmd
= &s
->async
->cmd
;
3459 retval
= prep_ao_dma(dev
, cmd
);
3463 set_dac_control0_reg(dev
, cmd
);
3465 if (cmd
->start_src
== TRIG_INT
)
3466 writew(0, devpriv
->main_iobase
+ DAC_START_REG
);
3468 s
->async
->inttrig
= NULL
;
3473 static int ao_cmdtest(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3474 struct comedi_cmd
*cmd
)
3477 unsigned int tmp_arg
;
3480 /* Step 1 : check if triggers are trivially valid */
3482 err
|= cfc_check_trigger_src(&cmd
->start_src
, TRIG_INT
| TRIG_EXT
);
3483 err
|= cfc_check_trigger_src(&cmd
->scan_begin_src
,
3484 TRIG_TIMER
| TRIG_EXT
);
3485 err
|= cfc_check_trigger_src(&cmd
->convert_src
, TRIG_NOW
);
3486 err
|= cfc_check_trigger_src(&cmd
->scan_end_src
, TRIG_COUNT
);
3487 err
|= cfc_check_trigger_src(&cmd
->stop_src
, TRIG_NONE
);
3492 /* Step 2a : make sure trigger sources are unique */
3494 err
|= cfc_check_trigger_is_unique(cmd
->start_src
);
3495 err
|= cfc_check_trigger_is_unique(cmd
->scan_begin_src
);
3497 /* Step 2b : and mutually compatible */
3499 if (cmd
->convert_src
== TRIG_EXT
&& cmd
->scan_begin_src
== TRIG_TIMER
)
3501 if (cmd
->stop_src
!= TRIG_COUNT
&&
3502 cmd
->stop_src
!= TRIG_NONE
&& cmd
->stop_src
!= TRIG_EXT
)
3508 /* step 3: make sure arguments are trivially compatible */
3510 if (cmd
->scan_begin_src
== TRIG_TIMER
) {
3511 if (cmd
->scan_begin_arg
< board(dev
)->ao_scan_speed
) {
3512 cmd
->scan_begin_arg
= board(dev
)->ao_scan_speed
;
3515 if (get_ao_divisor(cmd
->scan_begin_arg
,
3516 cmd
->flags
) > max_counter_value
) {
3517 cmd
->scan_begin_arg
=
3518 (max_counter_value
+ 2) * TIMER_BASE
;
3523 if (!cmd
->chanlist_len
) {
3524 cmd
->chanlist_len
= 1;
3527 if (cmd
->scan_end_arg
!= cmd
->chanlist_len
) {
3528 cmd
->scan_end_arg
= cmd
->chanlist_len
;
3535 /* step 4: fix up any arguments */
3537 if (cmd
->scan_begin_src
== TRIG_TIMER
) {
3538 tmp_arg
= cmd
->scan_begin_arg
;
3539 cmd
->scan_begin_arg
=
3540 get_divisor(cmd
->scan_begin_arg
, cmd
->flags
) * TIMER_BASE
;
3541 if (tmp_arg
!= cmd
->scan_begin_arg
)
3548 if (cmd
->chanlist
) {
3549 unsigned int first_channel
= CR_CHAN(cmd
->chanlist
[0]);
3550 for (i
= 1; i
< cmd
->chanlist_len
; i
++) {
3551 if (CR_CHAN(cmd
->chanlist
[i
]) != first_channel
+ i
) {
3553 "chanlist must use consecutive channels");
3566 static int ao_cancel(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
3568 struct pcidas64_private
*devpriv
= dev
->private;
3570 writew(0x0, devpriv
->main_iobase
+ DAC_CONTROL0_REG
);
3575 static int dio_callback(int dir
, int port
, int data
, unsigned long arg
)
3577 void __iomem
*iobase
= (void __iomem
*)arg
;
3579 writeb(data
, iobase
+ port
);
3580 DEBUG_PRINT("wrote 0x%x to port %i\n", data
, port
);
3583 return readb(iobase
+ port
);
3587 static int dio_callback_4020(int dir
, int port
, int data
, unsigned long arg
)
3589 void __iomem
*iobase
= (void __iomem
*)arg
;
3591 writew(data
, iobase
+ 2 * port
);
3594 return readw(iobase
+ 2 * port
);
3598 static int di_rbits(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3599 struct comedi_insn
*insn
, unsigned int *data
)
3601 struct pcidas64_private
*devpriv
= dev
->private;
3604 bits
= readb(devpriv
->dio_counter_iobase
+ DI_REG
);
3612 static int do_wbits(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3613 struct comedi_insn
*insn
, unsigned int *data
)
3615 struct pcidas64_private
*devpriv
= dev
->private;
3618 /* zero bits we are going to change */
3619 s
->state
&= ~data
[0];
3621 s
->state
|= data
[0] & data
[1];
3623 writeb(s
->state
, devpriv
->dio_counter_iobase
+ DO_REG
);
3630 static int dio_60xx_config_insn(struct comedi_device
*dev
,
3631 struct comedi_subdevice
*s
,
3632 struct comedi_insn
*insn
, unsigned int *data
)
3634 struct pcidas64_private
*devpriv
= dev
->private;
3637 mask
= 1 << CR_CHAN(insn
->chanspec
);
3640 case INSN_CONFIG_DIO_INPUT
:
3641 s
->io_bits
&= ~mask
;
3643 case INSN_CONFIG_DIO_OUTPUT
:
3646 case INSN_CONFIG_DIO_QUERY
:
3647 data
[1] = (s
->io_bits
& mask
) ? COMEDI_OUTPUT
: COMEDI_INPUT
;
3654 devpriv
->dio_counter_iobase
+ DIO_DIRECTION_60XX_REG
);
3659 static int dio_60xx_wbits(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3660 struct comedi_insn
*insn
, unsigned int *data
)
3662 struct pcidas64_private
*devpriv
= dev
->private;
3665 s
->state
&= ~data
[0];
3666 s
->state
|= (data
[0] & data
[1]);
3668 devpriv
->dio_counter_iobase
+ DIO_DATA_60XX_REG
);
3671 data
[1] = readb(devpriv
->dio_counter_iobase
+ DIO_DATA_60XX_REG
);
3676 static void caldac_write(struct comedi_device
*dev
, unsigned int channel
,
3679 struct pcidas64_private
*devpriv
= dev
->private;
3681 devpriv
->caldac_state
[channel
] = value
;
3683 switch (board(dev
)->layout
) {
3686 caldac_8800_write(dev
, channel
, value
);
3689 caldac_i2c_write(dev
, channel
, value
);
3696 static int calib_write_insn(struct comedi_device
*dev
,
3697 struct comedi_subdevice
*s
,
3698 struct comedi_insn
*insn
, unsigned int *data
)
3700 struct pcidas64_private
*devpriv
= dev
->private;
3701 int channel
= CR_CHAN(insn
->chanspec
);
3703 /* return immediately if setting hasn't changed, since
3704 * programming these things is slow */
3705 if (devpriv
->caldac_state
[channel
] == data
[0])
3708 caldac_write(dev
, channel
, data
[0]);
3713 static int calib_read_insn(struct comedi_device
*dev
,
3714 struct comedi_subdevice
*s
, struct comedi_insn
*insn
,
3717 struct pcidas64_private
*devpriv
= dev
->private;
3718 unsigned int channel
= CR_CHAN(insn
->chanspec
);
3720 data
[0] = devpriv
->caldac_state
[channel
];
3725 static void ad8402_write(struct comedi_device
*dev
, unsigned int channel
,
3728 struct pcidas64_private
*devpriv
= dev
->private;
3729 static const int bitstream_length
= 10;
3730 unsigned int bit
, register_bits
;
3731 unsigned int bitstream
= ((channel
& 0x3) << 8) | (value
& 0xff);
3732 static const int ad8402_udelay
= 1;
3734 devpriv
->ad8402_state
[channel
] = value
;
3736 register_bits
= SELECT_8402_64XX_BIT
;
3737 udelay(ad8402_udelay
);
3738 writew(register_bits
, devpriv
->main_iobase
+ CALIBRATION_REG
);
3740 for (bit
= 1 << (bitstream_length
- 1); bit
; bit
>>= 1) {
3741 if (bitstream
& bit
)
3742 register_bits
|= SERIAL_DATA_IN_BIT
;
3744 register_bits
&= ~SERIAL_DATA_IN_BIT
;
3745 udelay(ad8402_udelay
);
3746 writew(register_bits
, devpriv
->main_iobase
+ CALIBRATION_REG
);
3747 udelay(ad8402_udelay
);
3748 writew(register_bits
| SERIAL_CLOCK_BIT
,
3749 devpriv
->main_iobase
+ CALIBRATION_REG
);
3752 udelay(ad8402_udelay
);
3753 writew(0, devpriv
->main_iobase
+ CALIBRATION_REG
);
3756 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3757 static int ad8402_write_insn(struct comedi_device
*dev
,
3758 struct comedi_subdevice
*s
,
3759 struct comedi_insn
*insn
, unsigned int *data
)
3761 struct pcidas64_private
*devpriv
= dev
->private;
3762 int channel
= CR_CHAN(insn
->chanspec
);
3764 /* return immediately if setting hasn't changed, since
3765 * programming these things is slow */
3766 if (devpriv
->ad8402_state
[channel
] == data
[0])
3769 devpriv
->ad8402_state
[channel
] = data
[0];
3771 ad8402_write(dev
, channel
, data
[0]);
3776 static int ad8402_read_insn(struct comedi_device
*dev
,
3777 struct comedi_subdevice
*s
,
3778 struct comedi_insn
*insn
, unsigned int *data
)
3780 struct pcidas64_private
*devpriv
= dev
->private;
3781 unsigned int channel
= CR_CHAN(insn
->chanspec
);
3783 data
[0] = devpriv
->ad8402_state
[channel
];
3788 static uint16_t read_eeprom(struct comedi_device
*dev
, uint8_t address
)
3790 struct pcidas64_private
*devpriv
= dev
->private;
3791 static const int bitstream_length
= 11;
3792 static const int read_command
= 0x6;
3793 unsigned int bitstream
= (read_command
<< 8) | address
;
3795 void __iomem
* const plx_control_addr
=
3796 devpriv
->plx9080_iobase
+ PLX_CONTROL_REG
;
3798 static const int value_length
= 16;
3799 static const int eeprom_udelay
= 1;
3801 udelay(eeprom_udelay
);
3802 devpriv
->plx_control_bits
&= ~CTL_EE_CLK
& ~CTL_EE_CS
;
3803 /* make sure we don't send anything to the i2c bus on 4020 */
3804 devpriv
->plx_control_bits
|= CTL_USERO
;
3805 writel(devpriv
->plx_control_bits
, plx_control_addr
);
3806 /* activate serial eeprom */
3807 udelay(eeprom_udelay
);
3808 devpriv
->plx_control_bits
|= CTL_EE_CS
;
3809 writel(devpriv
->plx_control_bits
, plx_control_addr
);
3811 /* write read command and desired memory address */
3812 for (bit
= 1 << (bitstream_length
- 1); bit
; bit
>>= 1) {
3813 /* set bit to be written */
3814 udelay(eeprom_udelay
);
3815 if (bitstream
& bit
)
3816 devpriv
->plx_control_bits
|= CTL_EE_W
;
3818 devpriv
->plx_control_bits
&= ~CTL_EE_W
;
3819 writel(devpriv
->plx_control_bits
, plx_control_addr
);
3821 udelay(eeprom_udelay
);
3822 devpriv
->plx_control_bits
|= CTL_EE_CLK
;
3823 writel(devpriv
->plx_control_bits
, plx_control_addr
);
3824 udelay(eeprom_udelay
);
3825 devpriv
->plx_control_bits
&= ~CTL_EE_CLK
;
3826 writel(devpriv
->plx_control_bits
, plx_control_addr
);
3828 /* read back value from eeprom memory location */
3830 for (bit
= 1 << (value_length
- 1); bit
; bit
>>= 1) {
3832 udelay(eeprom_udelay
);
3833 devpriv
->plx_control_bits
|= CTL_EE_CLK
;
3834 writel(devpriv
->plx_control_bits
, plx_control_addr
);
3835 udelay(eeprom_udelay
);
3836 devpriv
->plx_control_bits
&= ~CTL_EE_CLK
;
3837 writel(devpriv
->plx_control_bits
, plx_control_addr
);
3838 udelay(eeprom_udelay
);
3839 if (readl(plx_control_addr
) & CTL_EE_R
)
3843 /* deactivate eeprom serial input */
3844 udelay(eeprom_udelay
);
3845 devpriv
->plx_control_bits
&= ~CTL_EE_CS
;
3846 writel(devpriv
->plx_control_bits
, plx_control_addr
);
3851 static int eeprom_read_insn(struct comedi_device
*dev
,
3852 struct comedi_subdevice
*s
,
3853 struct comedi_insn
*insn
, unsigned int *data
)
3855 data
[0] = read_eeprom(dev
, CR_CHAN(insn
->chanspec
));
3860 /* utility function that rounds desired timing to an achievable time, and
3861 * sets cmd members appropriately.
3862 * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
3864 static void check_adc_timing(struct comedi_device
*dev
, struct comedi_cmd
*cmd
)
3866 unsigned int convert_divisor
= 0, scan_divisor
;
3867 static const int min_convert_divisor
= 3;
3868 static const int max_convert_divisor
=
3869 max_counter_value
+ min_convert_divisor
;
3870 static const int min_scan_divisor_4020
= 2;
3871 unsigned long long max_scan_divisor
, min_scan_divisor
;
3873 if (cmd
->convert_src
== TRIG_TIMER
) {
3874 if (board(dev
)->layout
== LAYOUT_4020
) {
3875 cmd
->convert_arg
= 0;
3878 get_divisor(cmd
->convert_arg
, cmd
->flags
);
3879 if (convert_divisor
> max_convert_divisor
)
3880 convert_divisor
= max_convert_divisor
;
3881 if (convert_divisor
< min_convert_divisor
)
3882 convert_divisor
= min_convert_divisor
;
3883 cmd
->convert_arg
= convert_divisor
* TIMER_BASE
;
3885 } else if (cmd
->convert_src
== TRIG_NOW
)
3886 cmd
->convert_arg
= 0;
3888 if (cmd
->scan_begin_src
== TRIG_TIMER
) {
3889 scan_divisor
= get_divisor(cmd
->scan_begin_arg
, cmd
->flags
);
3890 if (cmd
->convert_src
== TRIG_TIMER
) {
3891 /* XXX check for integer overflows */
3892 min_scan_divisor
= convert_divisor
* cmd
->chanlist_len
;
3894 (convert_divisor
* cmd
->chanlist_len
- 1) +
3897 min_scan_divisor
= min_scan_divisor_4020
;
3898 max_scan_divisor
= max_counter_value
+ min_scan_divisor
;
3900 if (scan_divisor
> max_scan_divisor
)
3901 scan_divisor
= max_scan_divisor
;
3902 if (scan_divisor
< min_scan_divisor
)
3903 scan_divisor
= min_scan_divisor
;
3904 cmd
->scan_begin_arg
= scan_divisor
* TIMER_BASE
;
3910 /* Gets nearest achievable timing given master clock speed, does not
3911 * take into account possible minimum/maximum divisor values. Used
3912 * by other timing checking functions. */
3913 static unsigned int get_divisor(unsigned int ns
, unsigned int flags
)
3915 unsigned int divisor
;
3917 switch (flags
& TRIG_ROUND_MASK
) {
3919 divisor
= (ns
+ TIMER_BASE
- 1) / TIMER_BASE
;
3921 case TRIG_ROUND_DOWN
:
3922 divisor
= ns
/ TIMER_BASE
;
3924 case TRIG_ROUND_NEAREST
:
3926 divisor
= (ns
+ TIMER_BASE
/ 2) / TIMER_BASE
;
3932 static unsigned int get_ao_divisor(unsigned int ns
, unsigned int flags
)
3934 return get_divisor(ns
, flags
) - 2;
3937 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
3938 static int set_ai_fifo_size(struct comedi_device
*dev
, unsigned int num_samples
)
3940 unsigned int num_fifo_entries
;
3942 const struct hw_fifo_info
*const fifo
= board(dev
)->ai_fifo
;
3944 num_fifo_entries
= num_samples
/ fifo
->sample_packing_ratio
;
3946 retval
= set_ai_fifo_segment_length(dev
,
3948 fifo
->num_segments
);
3952 num_samples
= retval
* fifo
->num_segments
* fifo
->sample_packing_ratio
;
3954 DEBUG_PRINT("set hardware fifo size to %i\n", num_samples
);
3959 /* query length of fifo */
3960 static unsigned int ai_fifo_size(struct comedi_device
*dev
)
3962 struct pcidas64_private
*devpriv
= dev
->private;
3964 return devpriv
->ai_fifo_segment_length
*
3965 board(dev
)->ai_fifo
->num_segments
*
3966 board(dev
)->ai_fifo
->sample_packing_ratio
;
3969 static int set_ai_fifo_segment_length(struct comedi_device
*dev
,
3970 unsigned int num_entries
)
3972 struct pcidas64_private
*devpriv
= dev
->private;
3973 static const int increment_size
= 0x100;
3974 const struct hw_fifo_info
*const fifo
= board(dev
)->ai_fifo
;
3975 unsigned int num_increments
;
3978 if (num_entries
< increment_size
)
3979 num_entries
= increment_size
;
3980 if (num_entries
> fifo
->max_segment_length
)
3981 num_entries
= fifo
->max_segment_length
;
3983 /* 1 == 256 entries, 2 == 512 entries, etc */
3984 num_increments
= (num_entries
+ increment_size
/ 2) / increment_size
;
3986 bits
= (~(num_increments
- 1)) & fifo
->fifo_size_reg_mask
;
3987 devpriv
->fifo_size_bits
&= ~fifo
->fifo_size_reg_mask
;
3988 devpriv
->fifo_size_bits
|= bits
;
3989 writew(devpriv
->fifo_size_bits
,
3990 devpriv
->main_iobase
+ FIFO_SIZE_REG
);
3992 devpriv
->ai_fifo_segment_length
= num_increments
* increment_size
;
3994 DEBUG_PRINT("set hardware fifo segment length to %i\n",
3995 devpriv
->ai_fifo_segment_length
);
3997 return devpriv
->ai_fifo_segment_length
;
4000 /* pci-6025 8800 caldac:
4001 * address 0 == dac channel 0 offset
4002 * address 1 == dac channel 0 gain
4003 * address 2 == dac channel 1 offset
4004 * address 3 == dac channel 1 gain
4005 * address 4 == fine adc offset
4006 * address 5 == coarse adc offset
4007 * address 6 == coarse adc gain
4008 * address 7 == fine adc gain
4010 /* pci-6402/16 uses all 8 channels for dac:
4011 * address 0 == dac channel 0 fine gain
4012 * address 1 == dac channel 0 coarse gain
4013 * address 2 == dac channel 0 coarse offset
4014 * address 3 == dac channel 1 coarse offset
4015 * address 4 == dac channel 1 fine gain
4016 * address 5 == dac channel 1 coarse gain
4017 * address 6 == dac channel 0 fine offset
4018 * address 7 == dac channel 1 fine offset
4021 static int caldac_8800_write(struct comedi_device
*dev
, unsigned int address
,
4024 struct pcidas64_private
*devpriv
= dev
->private;
4025 static const int num_caldac_channels
= 8;
4026 static const int bitstream_length
= 11;
4027 unsigned int bitstream
= ((address
& 0x7) << 8) | value
;
4028 unsigned int bit
, register_bits
;
4029 static const int caldac_8800_udelay
= 1;
4031 if (address
>= num_caldac_channels
) {
4032 comedi_error(dev
, "illegal caldac channel");
4035 for (bit
= 1 << (bitstream_length
- 1); bit
; bit
>>= 1) {
4037 if (bitstream
& bit
)
4038 register_bits
|= SERIAL_DATA_IN_BIT
;
4039 udelay(caldac_8800_udelay
);
4040 writew(register_bits
, devpriv
->main_iobase
+ CALIBRATION_REG
);
4041 register_bits
|= SERIAL_CLOCK_BIT
;
4042 udelay(caldac_8800_udelay
);
4043 writew(register_bits
, devpriv
->main_iobase
+ CALIBRATION_REG
);
4045 udelay(caldac_8800_udelay
);
4046 writew(SELECT_8800_BIT
, devpriv
->main_iobase
+ CALIBRATION_REG
);
4047 udelay(caldac_8800_udelay
);
4048 writew(0, devpriv
->main_iobase
+ CALIBRATION_REG
);
4049 udelay(caldac_8800_udelay
);
4054 static int caldac_i2c_write(struct comedi_device
*dev
,
4055 unsigned int caldac_channel
, unsigned int value
)
4057 uint8_t serial_bytes
[3];
4060 /* manual has gain and offset bits switched */
4067 NOT_CLEAR_REGISTERS
= 0x20,
4070 switch (caldac_channel
) {
4071 case 0: /* chan 0 offset */
4072 i2c_addr
= CALDAC0_I2C_ADDR
;
4073 serial_bytes
[0] = OFFSET_0_2
;
4075 case 1: /* chan 1 offset */
4076 i2c_addr
= CALDAC0_I2C_ADDR
;
4077 serial_bytes
[0] = OFFSET_1_3
;
4079 case 2: /* chan 2 offset */
4080 i2c_addr
= CALDAC1_I2C_ADDR
;
4081 serial_bytes
[0] = OFFSET_0_2
;
4083 case 3: /* chan 3 offset */
4084 i2c_addr
= CALDAC1_I2C_ADDR
;
4085 serial_bytes
[0] = OFFSET_1_3
;
4087 case 4: /* chan 0 gain */
4088 i2c_addr
= CALDAC0_I2C_ADDR
;
4089 serial_bytes
[0] = GAIN_0_2
;
4091 case 5: /* chan 1 gain */
4092 i2c_addr
= CALDAC0_I2C_ADDR
;
4093 serial_bytes
[0] = GAIN_1_3
;
4095 case 6: /* chan 2 gain */
4096 i2c_addr
= CALDAC1_I2C_ADDR
;
4097 serial_bytes
[0] = GAIN_0_2
;
4099 case 7: /* chan 3 gain */
4100 i2c_addr
= CALDAC1_I2C_ADDR
;
4101 serial_bytes
[0] = GAIN_1_3
;
4104 comedi_error(dev
, "invalid caldac channel\n");
4108 serial_bytes
[1] = NOT_CLEAR_REGISTERS
| ((value
>> 8) & 0xf);
4109 serial_bytes
[2] = value
& 0xff;
4110 i2c_write(dev
, i2c_addr
, serial_bytes
, 3);
4114 /* Their i2c requires a huge delay on setting clock or data high for some reason */
4115 static const int i2c_high_udelay
= 1000;
4116 static const int i2c_low_udelay
= 10;
4118 /* set i2c data line high or low */
4119 static void i2c_set_sda(struct comedi_device
*dev
, int state
)
4121 struct pcidas64_private
*devpriv
= dev
->private;
4122 static const int data_bit
= CTL_EE_W
;
4123 void __iomem
*plx_control_addr
= devpriv
->plx9080_iobase
+
4127 /* set data line high */
4128 devpriv
->plx_control_bits
&= ~data_bit
;
4129 writel(devpriv
->plx_control_bits
, plx_control_addr
);
4130 udelay(i2c_high_udelay
);
4131 } else { /* set data line low */
4133 devpriv
->plx_control_bits
|= data_bit
;
4134 writel(devpriv
->plx_control_bits
, plx_control_addr
);
4135 udelay(i2c_low_udelay
);
4139 /* set i2c clock line high or low */
4140 static void i2c_set_scl(struct comedi_device
*dev
, int state
)
4142 struct pcidas64_private
*devpriv
= dev
->private;
4143 static const int clock_bit
= CTL_USERO
;
4144 void __iomem
*plx_control_addr
= devpriv
->plx9080_iobase
+
4148 /* set clock line high */
4149 devpriv
->plx_control_bits
&= ~clock_bit
;
4150 writel(devpriv
->plx_control_bits
, plx_control_addr
);
4151 udelay(i2c_high_udelay
);
4152 } else { /* set clock line low */
4154 devpriv
->plx_control_bits
|= clock_bit
;
4155 writel(devpriv
->plx_control_bits
, plx_control_addr
);
4156 udelay(i2c_low_udelay
);
4160 static void i2c_write_byte(struct comedi_device
*dev
, uint8_t byte
)
4163 unsigned int num_bits
= 8;
4165 DEBUG_PRINT("writing to i2c byte 0x%x\n", byte
);
4167 for (bit
= 1 << (num_bits
- 1); bit
; bit
>>= 1) {
4168 i2c_set_scl(dev
, 0);
4170 i2c_set_sda(dev
, 1);
4172 i2c_set_sda(dev
, 0);
4173 i2c_set_scl(dev
, 1);
4177 /* we can't really read the lines, so fake it */
4178 static int i2c_read_ack(struct comedi_device
*dev
)
4180 i2c_set_scl(dev
, 0);
4181 i2c_set_sda(dev
, 1);
4182 i2c_set_scl(dev
, 1);
4184 return 0; /* return fake acknowledge bit */
4187 /* send start bit */
4188 static void i2c_start(struct comedi_device
*dev
)
4190 i2c_set_scl(dev
, 1);
4191 i2c_set_sda(dev
, 1);
4192 i2c_set_sda(dev
, 0);
4196 static void i2c_stop(struct comedi_device
*dev
)
4198 i2c_set_scl(dev
, 0);
4199 i2c_set_sda(dev
, 0);
4200 i2c_set_scl(dev
, 1);
4201 i2c_set_sda(dev
, 1);
4204 static void i2c_write(struct comedi_device
*dev
, unsigned int address
,
4205 const uint8_t *data
, unsigned int length
)
4207 struct pcidas64_private
*devpriv
= dev
->private;
4210 static const int read_bit
= 0x1;
4212 /* XXX need mutex to prevent simultaneous attempts to access eeprom and i2c bus */
4214 /* make sure we dont send anything to eeprom */
4215 devpriv
->plx_control_bits
&= ~CTL_EE_CS
;
4220 /* send address and write bit */
4221 bitstream
= (address
<< 1) & ~read_bit
;
4222 i2c_write_byte(dev
, bitstream
);
4224 /* get acknowledge */
4225 if (i2c_read_ack(dev
) != 0) {
4226 comedi_error(dev
, "i2c write failed: no acknowledge");
4230 /* write data bytes */
4231 for (i
= 0; i
< length
; i
++) {
4232 i2c_write_byte(dev
, data
[i
]);
4233 if (i2c_read_ack(dev
) != 0) {
4234 comedi_error(dev
, "i2c write failed: no acknowledge");
4242 static struct comedi_driver cb_pcidas64_driver
= {
4243 .driver_name
= "cb_pcidas64",
4244 .module
= THIS_MODULE
,
4249 static int __devinit
cb_pcidas64_pci_probe(struct pci_dev
*dev
,
4250 const struct pci_device_id
*ent
)
4252 return comedi_pci_auto_config(dev
, &cb_pcidas64_driver
);
4255 static void __devexit
cb_pcidas64_pci_remove(struct pci_dev
*dev
)
4257 comedi_pci_auto_unconfig(dev
);
4260 static DEFINE_PCI_DEVICE_TABLE(cb_pcidas64_pci_table
) = {
4261 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x001d) },
4262 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x001e) },
4263 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x0035) },
4264 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x0036) },
4265 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x0037) },
4266 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x0052) },
4267 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x005d) },
4268 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x005e) },
4269 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x005f) },
4270 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x0061) },
4271 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x0062) },
4272 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x0063) },
4273 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x0064) },
4274 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x0066) },
4275 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x0067) },
4276 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x0068) },
4277 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x006f) },
4278 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x0078) },
4279 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS
, 0x0079) },
4282 MODULE_DEVICE_TABLE(pci
, cb_pcidas64_pci_table
);
4284 static struct pci_driver cb_pcidas64_pci_driver
= {
4285 .name
= "cb_pcidas64",
4286 .id_table
= cb_pcidas64_pci_table
,
4287 .probe
= cb_pcidas64_pci_probe
,
4288 .remove
= __devexit_p(cb_pcidas64_pci_remove
),
4290 module_comedi_pci_driver(cb_pcidas64_driver
, cb_pcidas64_pci_driver
);
4292 MODULE_AUTHOR("Comedi http://www.comedi.org");
4293 MODULE_DESCRIPTION("Comedi low-level driver");
4294 MODULE_LICENSE("GPL");