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[deliverable/linux.git] / drivers / staging / comedi / drivers / me4000.c
1 /*
2 comedi/drivers/me4000.c
3 Source code for the Meilhaus ME-4000 board family.
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17 */
18 /*
19 Driver: me4000
20 Description: Meilhaus ME-4000 series boards
21 Devices: [Meilhaus] ME-4650 (me4000), ME-4670i, ME-4680, ME-4680i, ME-4680is
22 Author: gg (Guenter Gebhardt <g.gebhardt@meilhaus.com>)
23 Updated: Mon, 18 Mar 2002 15:34:01 -0800
24 Status: broken (no support for loading firmware)
25
26 Supports:
27
28 - Analog Input
29 - Analog Output
30 - Digital I/O
31 - Counter
32
33 Configuration Options: not applicable, uses PCI auto config
34
35 The firmware required by these boards is available in the
36 comedi_nonfree_firmware tarball available from
37 http://www.comedi.org. However, the driver's support for
38 loading the firmware through comedi_config is currently
39 broken.
40
41 */
42
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46
47 #include "../comedi_pci.h"
48
49 #include "comedi_8254.h"
50 #include "plx9052.h"
51
52 #define ME4000_FIRMWARE "me4000_firmware.bin"
53
54 /*
55 * ME4000 Register map and bit defines
56 */
57 #define ME4000_AO_CHAN(x) ((x) * 0x18)
58
59 #define ME4000_AO_CTRL_REG(x) (0x00 + ME4000_AO_CHAN(x))
60 #define ME4000_AO_CTRL_BIT_MODE_0 (1 << 0)
61 #define ME4000_AO_CTRL_BIT_MODE_1 (1 << 1)
62 #define ME4000_AO_CTRL_MASK_MODE (3 << 0)
63 #define ME4000_AO_CTRL_BIT_STOP (1 << 2)
64 #define ME4000_AO_CTRL_BIT_ENABLE_FIFO (1 << 3)
65 #define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG (1 << 4)
66 #define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE (1 << 5)
67 #define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP (1 << 7)
68 #define ME4000_AO_CTRL_BIT_ENABLE_DO (1 << 8)
69 #define ME4000_AO_CTRL_BIT_ENABLE_IRQ (1 << 9)
70 #define ME4000_AO_CTRL_BIT_RESET_IRQ (1 << 10)
71 #define ME4000_AO_STATUS_REG(x) (0x04 + ME4000_AO_CHAN(x))
72 #define ME4000_AO_STATUS_BIT_FSM (1 << 0)
73 #define ME4000_AO_STATUS_BIT_FF (1 << 1)
74 #define ME4000_AO_STATUS_BIT_HF (1 << 2)
75 #define ME4000_AO_STATUS_BIT_EF (1 << 3)
76 #define ME4000_AO_FIFO_REG(x) (0x08 + ME4000_AO_CHAN(x))
77 #define ME4000_AO_SINGLE_REG(x) (0x0c + ME4000_AO_CHAN(x))
78 #define ME4000_AO_TIMER_REG(x) (0x10 + ME4000_AO_CHAN(x))
79 #define ME4000_AI_CTRL_REG 0x74
80 #define ME4000_AI_STATUS_REG 0x74
81 #define ME4000_AI_CTRL_BIT_MODE_0 (1 << 0)
82 #define ME4000_AI_CTRL_BIT_MODE_1 (1 << 1)
83 #define ME4000_AI_CTRL_BIT_MODE_2 (1 << 2)
84 #define ME4000_AI_CTRL_BIT_SAMPLE_HOLD (1 << 3)
85 #define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP (1 << 4)
86 #define ME4000_AI_CTRL_BIT_STOP (1 << 5)
87 #define ME4000_AI_CTRL_BIT_CHANNEL_FIFO (1 << 6)
88 #define ME4000_AI_CTRL_BIT_DATA_FIFO (1 << 7)
89 #define ME4000_AI_CTRL_BIT_FULLSCALE (1 << 8)
90 #define ME4000_AI_CTRL_BIT_OFFSET (1 << 9)
91 #define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG (1 << 10)
92 #define ME4000_AI_CTRL_BIT_EX_TRIG (1 << 11)
93 #define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING (1 << 12)
94 #define ME4000_AI_CTRL_BIT_EX_IRQ (1 << 13)
95 #define ME4000_AI_CTRL_BIT_EX_IRQ_RESET (1 << 14)
96 #define ME4000_AI_CTRL_BIT_LE_IRQ (1 << 15)
97 #define ME4000_AI_CTRL_BIT_LE_IRQ_RESET (1 << 16)
98 #define ME4000_AI_CTRL_BIT_HF_IRQ (1 << 17)
99 #define ME4000_AI_CTRL_BIT_HF_IRQ_RESET (1 << 18)
100 #define ME4000_AI_CTRL_BIT_SC_IRQ (1 << 19)
101 #define ME4000_AI_CTRL_BIT_SC_IRQ_RESET (1 << 20)
102 #define ME4000_AI_CTRL_BIT_SC_RELOAD (1 << 21)
103 #define ME4000_AI_STATUS_BIT_EF_CHANNEL (1 << 22)
104 #define ME4000_AI_STATUS_BIT_HF_CHANNEL (1 << 23)
105 #define ME4000_AI_STATUS_BIT_FF_CHANNEL (1 << 24)
106 #define ME4000_AI_STATUS_BIT_EF_DATA (1 << 25)
107 #define ME4000_AI_STATUS_BIT_HF_DATA (1 << 26)
108 #define ME4000_AI_STATUS_BIT_FF_DATA (1 << 27)
109 #define ME4000_AI_STATUS_BIT_LE (1 << 28)
110 #define ME4000_AI_STATUS_BIT_FSM (1 << 29)
111 #define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH (1 << 31)
112 #define ME4000_AI_CHANNEL_LIST_REG 0x78
113 #define ME4000_AI_LIST_INPUT_SINGLE_ENDED (0 << 5)
114 #define ME4000_AI_LIST_INPUT_DIFFERENTIAL (1 << 5)
115 #define ME4000_AI_LIST_RANGE_BIPOLAR_10 (0 << 6)
116 #define ME4000_AI_LIST_RANGE_BIPOLAR_2_5 (1 << 6)
117 #define ME4000_AI_LIST_RANGE_UNIPOLAR_10 (2 << 6)
118 #define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5 (3 << 6)
119 #define ME4000_AI_LIST_LAST_ENTRY (1 << 8)
120 #define ME4000_AI_DATA_REG 0x7c
121 #define ME4000_AI_CHAN_TIMER_REG 0x80
122 #define ME4000_AI_CHAN_PRE_TIMER_REG 0x84
123 #define ME4000_AI_SCAN_TIMER_LOW_REG 0x88
124 #define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8c
125 #define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90
126 #define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94
127 #define ME4000_AI_START_REG 0x98
128 #define ME4000_IRQ_STATUS_REG 0x9c
129 #define ME4000_IRQ_STATUS_BIT_EX (1 << 0)
130 #define ME4000_IRQ_STATUS_BIT_LE (1 << 1)
131 #define ME4000_IRQ_STATUS_BIT_AI_HF (1 << 2)
132 #define ME4000_IRQ_STATUS_BIT_AO_0_HF (1 << 3)
133 #define ME4000_IRQ_STATUS_BIT_AO_1_HF (1 << 4)
134 #define ME4000_IRQ_STATUS_BIT_AO_2_HF (1 << 5)
135 #define ME4000_IRQ_STATUS_BIT_AO_3_HF (1 << 6)
136 #define ME4000_IRQ_STATUS_BIT_SC (1 << 7)
137 #define ME4000_DIO_PORT_0_REG 0xa0
138 #define ME4000_DIO_PORT_1_REG 0xa4
139 #define ME4000_DIO_PORT_2_REG 0xa8
140 #define ME4000_DIO_PORT_3_REG 0xac
141 #define ME4000_DIO_DIR_REG 0xb0
142 #define ME4000_AO_LOADSETREG_XX 0xb4
143 #define ME4000_DIO_CTRL_REG 0xb8
144 #define ME4000_DIO_CTRL_BIT_MODE_0 (1 << 0)
145 #define ME4000_DIO_CTRL_BIT_MODE_1 (1 << 1)
146 #define ME4000_DIO_CTRL_BIT_MODE_2 (1 << 2)
147 #define ME4000_DIO_CTRL_BIT_MODE_3 (1 << 3)
148 #define ME4000_DIO_CTRL_BIT_MODE_4 (1 << 4)
149 #define ME4000_DIO_CTRL_BIT_MODE_5 (1 << 5)
150 #define ME4000_DIO_CTRL_BIT_MODE_6 (1 << 6)
151 #define ME4000_DIO_CTRL_BIT_MODE_7 (1 << 7)
152 #define ME4000_DIO_CTRL_BIT_FUNCTION_0 (1 << 8)
153 #define ME4000_DIO_CTRL_BIT_FUNCTION_1 (1 << 9)
154 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 (1 << 10)
155 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 (1 << 11)
156 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 (1 << 12)
157 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 (1 << 13)
158 #define ME4000_AO_DEMUX_ADJUST_REG 0xbc
159 #define ME4000_AO_DEMUX_ADJUST_VALUE 0x4c
160 #define ME4000_AI_SAMPLE_COUNTER_REG 0xc0
161
162 #define ME4000_AI_FIFO_COUNT 2048
163
164 #define ME4000_AI_MIN_TICKS 66
165 #define ME4000_AI_MIN_SAMPLE_TIME 2000
166
167 #define ME4000_AI_CHANNEL_LIST_COUNT 1024
168
169 struct me4000_info {
170 unsigned long plx_regbase;
171 };
172
173 enum me4000_boardid {
174 BOARD_ME4650,
175 BOARD_ME4660,
176 BOARD_ME4660I,
177 BOARD_ME4660S,
178 BOARD_ME4660IS,
179 BOARD_ME4670,
180 BOARD_ME4670I,
181 BOARD_ME4670S,
182 BOARD_ME4670IS,
183 BOARD_ME4680,
184 BOARD_ME4680I,
185 BOARD_ME4680S,
186 BOARD_ME4680IS,
187 };
188
189 struct me4000_board {
190 const char *name;
191 int ao_nchan;
192 int ao_fifo;
193 int ai_nchan;
194 int ai_diff_nchan;
195 int ai_sh_nchan;
196 unsigned int ex_trig_analog:1;
197 unsigned int has_counter:1;
198 };
199
200 static const struct me4000_board me4000_boards[] = {
201 [BOARD_ME4650] = {
202 .name = "ME-4650",
203 .ai_nchan = 16,
204 },
205 [BOARD_ME4660] = {
206 .name = "ME-4660",
207 .ai_nchan = 32,
208 .ai_diff_nchan = 16,
209 .has_counter = 1,
210 },
211 [BOARD_ME4660I] = {
212 .name = "ME-4660i",
213 .ai_nchan = 32,
214 .ai_diff_nchan = 16,
215 .has_counter = 1,
216 },
217 [BOARD_ME4660S] = {
218 .name = "ME-4660s",
219 .ai_nchan = 32,
220 .ai_diff_nchan = 16,
221 .ai_sh_nchan = 8,
222 .has_counter = 1,
223 },
224 [BOARD_ME4660IS] = {
225 .name = "ME-4660is",
226 .ai_nchan = 32,
227 .ai_diff_nchan = 16,
228 .ai_sh_nchan = 8,
229 .has_counter = 1,
230 },
231 [BOARD_ME4670] = {
232 .name = "ME-4670",
233 .ao_nchan = 4,
234 .ai_nchan = 32,
235 .ai_diff_nchan = 16,
236 .ex_trig_analog = 1,
237 .has_counter = 1,
238 },
239 [BOARD_ME4670I] = {
240 .name = "ME-4670i",
241 .ao_nchan = 4,
242 .ai_nchan = 32,
243 .ai_diff_nchan = 16,
244 .ex_trig_analog = 1,
245 .has_counter = 1,
246 },
247 [BOARD_ME4670S] = {
248 .name = "ME-4670s",
249 .ao_nchan = 4,
250 .ai_nchan = 32,
251 .ai_diff_nchan = 16,
252 .ai_sh_nchan = 8,
253 .ex_trig_analog = 1,
254 .has_counter = 1,
255 },
256 [BOARD_ME4670IS] = {
257 .name = "ME-4670is",
258 .ao_nchan = 4,
259 .ai_nchan = 32,
260 .ai_diff_nchan = 16,
261 .ai_sh_nchan = 8,
262 .ex_trig_analog = 1,
263 .has_counter = 1,
264 },
265 [BOARD_ME4680] = {
266 .name = "ME-4680",
267 .ao_nchan = 4,
268 .ao_fifo = 4,
269 .ai_nchan = 32,
270 .ai_diff_nchan = 16,
271 .ex_trig_analog = 1,
272 .has_counter = 1,
273 },
274 [BOARD_ME4680I] = {
275 .name = "ME-4680i",
276 .ao_nchan = 4,
277 .ao_fifo = 4,
278 .ai_nchan = 32,
279 .ai_diff_nchan = 16,
280 .ex_trig_analog = 1,
281 .has_counter = 1,
282 },
283 [BOARD_ME4680S] = {
284 .name = "ME-4680s",
285 .ao_nchan = 4,
286 .ao_fifo = 4,
287 .ai_nchan = 32,
288 .ai_diff_nchan = 16,
289 .ai_sh_nchan = 8,
290 .ex_trig_analog = 1,
291 .has_counter = 1,
292 },
293 [BOARD_ME4680IS] = {
294 .name = "ME-4680is",
295 .ao_nchan = 4,
296 .ao_fifo = 4,
297 .ai_nchan = 32,
298 .ai_diff_nchan = 16,
299 .ai_sh_nchan = 8,
300 .ex_trig_analog = 1,
301 .has_counter = 1,
302 },
303 };
304
305 static const struct comedi_lrange me4000_ai_range = {
306 4, {
307 UNI_RANGE(2.5),
308 UNI_RANGE(10),
309 BIP_RANGE(2.5),
310 BIP_RANGE(10)
311 }
312 };
313
314 static int me4000_xilinx_download(struct comedi_device *dev,
315 const u8 *data, size_t size,
316 unsigned long context)
317 {
318 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
319 struct me4000_info *info = dev->private;
320 unsigned long xilinx_iobase = pci_resource_start(pcidev, 5);
321 unsigned int file_length;
322 unsigned int val;
323 unsigned int i;
324
325 if (!xilinx_iobase)
326 return -ENODEV;
327
328 /*
329 * Set PLX local interrupt 2 polarity to high.
330 * Interrupt is thrown by init pin of xilinx.
331 */
332 outl(PLX9052_INTCSR_LI2POL, info->plx_regbase + PLX9052_INTCSR);
333
334 /* Set /CS and /WRITE of the Xilinx */
335 val = inl(info->plx_regbase + PLX9052_CNTRL);
336 val |= PLX9052_CNTRL_UIO2_DATA;
337 outl(val, info->plx_regbase + PLX9052_CNTRL);
338
339 /* Init Xilinx with CS1 */
340 inb(xilinx_iobase + 0xC8);
341
342 /* Wait until /INIT pin is set */
343 udelay(20);
344 val = inl(info->plx_regbase + PLX9052_INTCSR);
345 if (!(val & PLX9052_INTCSR_LI2STAT)) {
346 dev_err(dev->class_dev, "Can't init Xilinx\n");
347 return -EIO;
348 }
349
350 /* Reset /CS and /WRITE of the Xilinx */
351 val = inl(info->plx_regbase + PLX9052_CNTRL);
352 val &= ~PLX9052_CNTRL_UIO2_DATA;
353 outl(val, info->plx_regbase + PLX9052_CNTRL);
354
355 /* Download Xilinx firmware */
356 file_length = (((unsigned int)data[0] & 0xff) << 24) +
357 (((unsigned int)data[1] & 0xff) << 16) +
358 (((unsigned int)data[2] & 0xff) << 8) +
359 ((unsigned int)data[3] & 0xff);
360 udelay(10);
361
362 for (i = 0; i < file_length; i++) {
363 outb(data[16 + i], xilinx_iobase);
364 udelay(10);
365
366 /* Check if BUSY flag is low */
367 val = inl(info->plx_regbase + PLX9052_CNTRL);
368 if (val & PLX9052_CNTRL_UIO1_DATA) {
369 dev_err(dev->class_dev,
370 "Xilinx is still busy (i = %d)\n", i);
371 return -EIO;
372 }
373 }
374
375 /* If done flag is high download was successful */
376 val = inl(info->plx_regbase + PLX9052_CNTRL);
377 if (!(val & PLX9052_CNTRL_UIO0_DATA)) {
378 dev_err(dev->class_dev, "DONE flag is not set\n");
379 dev_err(dev->class_dev, "Download not successful\n");
380 return -EIO;
381 }
382
383 /* Set /CS and /WRITE */
384 val = inl(info->plx_regbase + PLX9052_CNTRL);
385 val |= PLX9052_CNTRL_UIO2_DATA;
386 outl(val, info->plx_regbase + PLX9052_CNTRL);
387
388 return 0;
389 }
390
391 static void me4000_reset(struct comedi_device *dev)
392 {
393 struct me4000_info *info = dev->private;
394 unsigned int val;
395 int chan;
396
397 /* Make a hardware reset */
398 val = inl(info->plx_regbase + PLX9052_CNTRL);
399 val |= PLX9052_CNTRL_PCI_RESET;
400 outl(val, info->plx_regbase + PLX9052_CNTRL);
401 val &= ~PLX9052_CNTRL_PCI_RESET;
402 outl(val, info->plx_regbase + PLX9052_CNTRL);
403
404 /* 0x8000 to the DACs means an output voltage of 0V */
405 for (chan = 0; chan < 4; chan++)
406 outl(0x8000, dev->iobase + ME4000_AO_SINGLE_REG(chan));
407
408 /* Set both stop bits in the analog input control register */
409 outl(ME4000_AI_CTRL_BIT_IMMEDIATE_STOP | ME4000_AI_CTRL_BIT_STOP,
410 dev->iobase + ME4000_AI_CTRL_REG);
411
412 /* Set both stop bits in the analog output control register */
413 val = ME4000_AO_CTRL_BIT_IMMEDIATE_STOP | ME4000_AO_CTRL_BIT_STOP;
414 for (chan = 0; chan < 4; chan++)
415 outl(val, dev->iobase + ME4000_AO_CTRL_REG(chan));
416
417 /* Enable interrupts on the PLX */
418 outl(PLX9052_INTCSR_LI1ENAB |
419 PLX9052_INTCSR_LI1POL |
420 PLX9052_INTCSR_PCIENAB, info->plx_regbase + PLX9052_INTCSR);
421
422 /* Set the adustment register for AO demux */
423 outl(ME4000_AO_DEMUX_ADJUST_VALUE,
424 dev->iobase + ME4000_AO_DEMUX_ADJUST_REG);
425
426 /*
427 * Set digital I/O direction for port 0
428 * to output on isolated versions
429 */
430 if (!(inl(dev->iobase + ME4000_DIO_DIR_REG) & 0x1))
431 outl(0x1, dev->iobase + ME4000_DIO_CTRL_REG);
432 }
433
434 /*=============================================================================
435 Analog input section
436 ===========================================================================*/
437
438 static int me4000_ai_insn_read(struct comedi_device *dev,
439 struct comedi_subdevice *s,
440 struct comedi_insn *insn,
441 unsigned int *data)
442 {
443 int chan = CR_CHAN(insn->chanspec);
444 int rang = CR_RANGE(insn->chanspec);
445 int aref = CR_AREF(insn->chanspec);
446
447 unsigned int entry = 0;
448 unsigned int tmp;
449 unsigned int lval;
450
451 if (insn->n == 0) {
452 return 0;
453 } else if (insn->n > 1) {
454 dev_err(dev->class_dev, "Invalid instruction length %d\n",
455 insn->n);
456 return -EINVAL;
457 }
458
459 switch (rang) {
460 case 0:
461 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
462 break;
463 case 1:
464 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
465 break;
466 case 2:
467 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
468 break;
469 case 3:
470 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
471 break;
472 default:
473 dev_err(dev->class_dev, "Invalid range specified\n");
474 return -EINVAL;
475 }
476
477 switch (aref) {
478 case AREF_GROUND:
479 case AREF_COMMON:
480 entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED | chan;
481 break;
482
483 case AREF_DIFF:
484 if (!(s->subdev_flags && SDF_DIFF)) {
485 dev_err(dev->class_dev,
486 "Differential inputs are not available\n");
487 return -EINVAL;
488 }
489
490 if (rang == 0 || rang == 1) {
491 dev_err(dev->class_dev,
492 "Range must be bipolar when aref = diff\n");
493 return -EINVAL;
494 }
495
496 if (chan >= (s->n_chan / 2)) {
497 dev_err(dev->class_dev,
498 "Analog input is not available\n");
499 return -EINVAL;
500 }
501 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL | chan;
502 break;
503 default:
504 dev_err(dev->class_dev, "Invalid aref specified\n");
505 return -EINVAL;
506 }
507
508 entry |= ME4000_AI_LIST_LAST_ENTRY;
509
510 /* Clear channel list, data fifo and both stop bits */
511 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
512 tmp &= ~(ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
513 ME4000_AI_CTRL_BIT_DATA_FIFO |
514 ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
515 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
516
517 /* Set the acquisition mode to single */
518 tmp &= ~(ME4000_AI_CTRL_BIT_MODE_0 | ME4000_AI_CTRL_BIT_MODE_1 |
519 ME4000_AI_CTRL_BIT_MODE_2);
520 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
521
522 /* Enable channel list and data fifo */
523 tmp |= ME4000_AI_CTRL_BIT_CHANNEL_FIFO | ME4000_AI_CTRL_BIT_DATA_FIFO;
524 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
525
526 /* Generate channel list entry */
527 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
528
529 /* Set the timer to maximum sample rate */
530 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
531 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
532
533 /* Start conversion by dummy read */
534 inl(dev->iobase + ME4000_AI_START_REG);
535
536 /* Wait until ready */
537 udelay(10);
538 if (!(inl(dev->iobase + ME4000_AI_STATUS_REG) &
539 ME4000_AI_STATUS_BIT_EF_DATA)) {
540 dev_err(dev->class_dev, "Value not available after wait\n");
541 return -EIO;
542 }
543
544 /* Read value from data fifo */
545 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
546 data[0] = lval ^ 0x8000;
547
548 return 1;
549 }
550
551 static int me4000_ai_cancel(struct comedi_device *dev,
552 struct comedi_subdevice *s)
553 {
554 unsigned int tmp;
555
556 /* Stop any running conversion */
557 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
558 tmp &= ~(ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
559 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
560
561 /* Clear the control register */
562 outl(0x0, dev->iobase + ME4000_AI_CTRL_REG);
563
564 return 0;
565 }
566
567 static int me4000_ai_check_chanlist(struct comedi_device *dev,
568 struct comedi_subdevice *s,
569 struct comedi_cmd *cmd)
570 {
571 unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
572 int i;
573
574 for (i = 0; i < cmd->chanlist_len; i++) {
575 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
576 unsigned int range = CR_RANGE(cmd->chanlist[i]);
577 unsigned int aref = CR_AREF(cmd->chanlist[i]);
578
579 if (aref != aref0) {
580 dev_dbg(dev->class_dev,
581 "Mode is not equal for all entries\n");
582 return -EINVAL;
583 }
584
585 if (aref == AREF_DIFF) {
586 if (!(s->subdev_flags && SDF_DIFF)) {
587 dev_err(dev->class_dev,
588 "Differential inputs are not available\n");
589 return -EINVAL;
590 }
591
592 if (chan >= (s->n_chan / 2)) {
593 dev_dbg(dev->class_dev,
594 "Channel number to high\n");
595 return -EINVAL;
596 }
597
598 if (!comedi_range_is_bipolar(s, range)) {
599 dev_dbg(dev->class_dev,
600 "Bipolar is not selected in differential mode\n");
601 return -EINVAL;
602 }
603 }
604 }
605
606 return 0;
607 }
608
609 static int ai_round_cmd_args(struct comedi_device *dev,
610 struct comedi_subdevice *s,
611 struct comedi_cmd *cmd,
612 unsigned int *init_ticks,
613 unsigned int *scan_ticks, unsigned int *chan_ticks)
614 {
615 int rest;
616
617 *init_ticks = 0;
618 *scan_ticks = 0;
619 *chan_ticks = 0;
620
621 if (cmd->start_arg) {
622 *init_ticks = (cmd->start_arg * 33) / 1000;
623 rest = (cmd->start_arg * 33) % 1000;
624
625 if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_NEAREST) {
626 if (rest > 33)
627 (*init_ticks)++;
628 } else if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_UP) {
629 if (rest)
630 (*init_ticks)++;
631 }
632 }
633
634 if (cmd->scan_begin_arg) {
635 *scan_ticks = (cmd->scan_begin_arg * 33) / 1000;
636 rest = (cmd->scan_begin_arg * 33) % 1000;
637
638 if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_NEAREST) {
639 if (rest > 33)
640 (*scan_ticks)++;
641 } else if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_UP) {
642 if (rest)
643 (*scan_ticks)++;
644 }
645 }
646
647 if (cmd->convert_arg) {
648 *chan_ticks = (cmd->convert_arg * 33) / 1000;
649 rest = (cmd->convert_arg * 33) % 1000;
650
651 if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_NEAREST) {
652 if (rest > 33)
653 (*chan_ticks)++;
654 } else if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_UP) {
655 if (rest)
656 (*chan_ticks)++;
657 }
658 }
659
660 return 0;
661 }
662
663 static void ai_write_timer(struct comedi_device *dev,
664 unsigned int init_ticks,
665 unsigned int scan_ticks, unsigned int chan_ticks)
666 {
667 outl(init_ticks - 1, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_LOW_REG);
668 outl(0x0, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_HIGH_REG);
669
670 if (scan_ticks) {
671 outl(scan_ticks - 1, dev->iobase + ME4000_AI_SCAN_TIMER_LOW_REG);
672 outl(0x0, dev->iobase + ME4000_AI_SCAN_TIMER_HIGH_REG);
673 }
674
675 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
676 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
677 }
678
679 static int ai_write_chanlist(struct comedi_device *dev,
680 struct comedi_subdevice *s, struct comedi_cmd *cmd)
681 {
682 unsigned int entry;
683 unsigned int chan;
684 unsigned int rang;
685 unsigned int aref;
686 int i;
687
688 for (i = 0; i < cmd->chanlist_len; i++) {
689 chan = CR_CHAN(cmd->chanlist[i]);
690 rang = CR_RANGE(cmd->chanlist[i]);
691 aref = CR_AREF(cmd->chanlist[i]);
692
693 entry = chan;
694
695 if (rang == 0)
696 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
697 else if (rang == 1)
698 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
699 else if (rang == 2)
700 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
701 else
702 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
703
704 if (aref == AREF_DIFF)
705 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL;
706 else
707 entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED;
708
709 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
710 }
711
712 return 0;
713 }
714
715 static int ai_prepare(struct comedi_device *dev,
716 struct comedi_subdevice *s,
717 struct comedi_cmd *cmd,
718 unsigned int init_ticks,
719 unsigned int scan_ticks, unsigned int chan_ticks)
720 {
721 unsigned int tmp = 0;
722
723 /* Write timer arguments */
724 ai_write_timer(dev, init_ticks, scan_ticks, chan_ticks);
725
726 /* Reset control register */
727 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
728
729 /* Start sources */
730 if ((cmd->start_src == TRIG_EXT &&
731 cmd->scan_begin_src == TRIG_TIMER &&
732 cmd->convert_src == TRIG_TIMER) ||
733 (cmd->start_src == TRIG_EXT &&
734 cmd->scan_begin_src == TRIG_FOLLOW &&
735 cmd->convert_src == TRIG_TIMER)) {
736 tmp = ME4000_AI_CTRL_BIT_MODE_1 |
737 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
738 ME4000_AI_CTRL_BIT_DATA_FIFO;
739 } else if (cmd->start_src == TRIG_EXT &&
740 cmd->scan_begin_src == TRIG_EXT &&
741 cmd->convert_src == TRIG_TIMER) {
742 tmp = ME4000_AI_CTRL_BIT_MODE_2 |
743 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
744 ME4000_AI_CTRL_BIT_DATA_FIFO;
745 } else if (cmd->start_src == TRIG_EXT &&
746 cmd->scan_begin_src == TRIG_EXT &&
747 cmd->convert_src == TRIG_EXT) {
748 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
749 ME4000_AI_CTRL_BIT_MODE_1 |
750 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
751 ME4000_AI_CTRL_BIT_DATA_FIFO;
752 } else {
753 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
754 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
755 ME4000_AI_CTRL_BIT_DATA_FIFO;
756 }
757
758 /* Stop triggers */
759 if (cmd->stop_src == TRIG_COUNT) {
760 outl(cmd->chanlist_len * cmd->stop_arg,
761 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
762 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
763 } else if (cmd->stop_src == TRIG_NONE &&
764 cmd->scan_end_src == TRIG_COUNT) {
765 outl(cmd->scan_end_arg,
766 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
767 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
768 } else {
769 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ;
770 }
771
772 /* Write the setup to the control register */
773 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
774
775 /* Write the channel list */
776 ai_write_chanlist(dev, s, cmd);
777
778 return 0;
779 }
780
781 static int me4000_ai_do_cmd(struct comedi_device *dev,
782 struct comedi_subdevice *s)
783 {
784 int err;
785 unsigned int init_ticks = 0;
786 unsigned int scan_ticks = 0;
787 unsigned int chan_ticks = 0;
788 struct comedi_cmd *cmd = &s->async->cmd;
789
790 /* Reset the analog input */
791 err = me4000_ai_cancel(dev, s);
792 if (err)
793 return err;
794
795 /* Round the timer arguments */
796 err = ai_round_cmd_args(dev,
797 s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
798 if (err)
799 return err;
800
801 /* Prepare the AI for acquisition */
802 err = ai_prepare(dev, s, cmd, init_ticks, scan_ticks, chan_ticks);
803 if (err)
804 return err;
805
806 /* Start acquistion by dummy read */
807 inl(dev->iobase + ME4000_AI_START_REG);
808
809 return 0;
810 }
811
812 static int me4000_ai_do_cmd_test(struct comedi_device *dev,
813 struct comedi_subdevice *s,
814 struct comedi_cmd *cmd)
815 {
816 unsigned int init_ticks;
817 unsigned int chan_ticks;
818 unsigned int scan_ticks;
819 int err = 0;
820
821 /* Round the timer arguments */
822 ai_round_cmd_args(dev, s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
823
824 /* Step 1 : check if triggers are trivially valid */
825
826 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
827 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
828 TRIG_FOLLOW | TRIG_TIMER | TRIG_EXT);
829 err |= comedi_check_trigger_src(&cmd->convert_src,
830 TRIG_TIMER | TRIG_EXT);
831 err |= comedi_check_trigger_src(&cmd->scan_end_src,
832 TRIG_NONE | TRIG_COUNT);
833 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE | TRIG_COUNT);
834
835 if (err)
836 return 1;
837
838 /* Step 2a : make sure trigger sources are unique */
839
840 err |= comedi_check_trigger_is_unique(cmd->start_src);
841 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
842 err |= comedi_check_trigger_is_unique(cmd->convert_src);
843 err |= comedi_check_trigger_is_unique(cmd->scan_end_src);
844 err |= comedi_check_trigger_is_unique(cmd->stop_src);
845
846 /* Step 2b : and mutually compatible */
847
848 if (cmd->start_src == TRIG_NOW &&
849 cmd->scan_begin_src == TRIG_TIMER &&
850 cmd->convert_src == TRIG_TIMER) {
851 } else if (cmd->start_src == TRIG_NOW &&
852 cmd->scan_begin_src == TRIG_FOLLOW &&
853 cmd->convert_src == TRIG_TIMER) {
854 } else if (cmd->start_src == TRIG_EXT &&
855 cmd->scan_begin_src == TRIG_TIMER &&
856 cmd->convert_src == TRIG_TIMER) {
857 } else if (cmd->start_src == TRIG_EXT &&
858 cmd->scan_begin_src == TRIG_FOLLOW &&
859 cmd->convert_src == TRIG_TIMER) {
860 } else if (cmd->start_src == TRIG_EXT &&
861 cmd->scan_begin_src == TRIG_EXT &&
862 cmd->convert_src == TRIG_TIMER) {
863 } else if (cmd->start_src == TRIG_EXT &&
864 cmd->scan_begin_src == TRIG_EXT &&
865 cmd->convert_src == TRIG_EXT) {
866 } else {
867 err |= -EINVAL;
868 }
869
870 if (err)
871 return 2;
872
873 /* Step 3: check if arguments are trivially valid */
874
875 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
876
877 if (cmd->chanlist_len < 1) {
878 cmd->chanlist_len = 1;
879 err |= -EINVAL;
880 }
881 if (init_ticks < 66) {
882 cmd->start_arg = 2000;
883 err |= -EINVAL;
884 }
885 if (scan_ticks && scan_ticks < 67) {
886 cmd->scan_begin_arg = 2031;
887 err |= -EINVAL;
888 }
889 if (chan_ticks < 66) {
890 cmd->convert_arg = 2000;
891 err |= -EINVAL;
892 }
893
894 if (cmd->stop_src == TRIG_COUNT)
895 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
896 else /* TRIG_NONE */
897 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
898
899 if (err)
900 return 3;
901
902 /*
903 * Stage 4. Check for argument conflicts.
904 */
905 if (cmd->start_src == TRIG_NOW &&
906 cmd->scan_begin_src == TRIG_TIMER &&
907 cmd->convert_src == TRIG_TIMER) {
908 /* Check timer arguments */
909 if (init_ticks < ME4000_AI_MIN_TICKS) {
910 dev_err(dev->class_dev, "Invalid start arg\n");
911 cmd->start_arg = 2000; /* 66 ticks at least */
912 err++;
913 }
914 if (chan_ticks < ME4000_AI_MIN_TICKS) {
915 dev_err(dev->class_dev, "Invalid convert arg\n");
916 cmd->convert_arg = 2000; /* 66 ticks at least */
917 err++;
918 }
919 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
920 dev_err(dev->class_dev, "Invalid scan end arg\n");
921
922 /* At least one tick more */
923 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
924 err++;
925 }
926 } else if (cmd->start_src == TRIG_NOW &&
927 cmd->scan_begin_src == TRIG_FOLLOW &&
928 cmd->convert_src == TRIG_TIMER) {
929 /* Check timer arguments */
930 if (init_ticks < ME4000_AI_MIN_TICKS) {
931 dev_err(dev->class_dev, "Invalid start arg\n");
932 cmd->start_arg = 2000; /* 66 ticks at least */
933 err++;
934 }
935 if (chan_ticks < ME4000_AI_MIN_TICKS) {
936 dev_err(dev->class_dev, "Invalid convert arg\n");
937 cmd->convert_arg = 2000; /* 66 ticks at least */
938 err++;
939 }
940 } else if (cmd->start_src == TRIG_EXT &&
941 cmd->scan_begin_src == TRIG_TIMER &&
942 cmd->convert_src == TRIG_TIMER) {
943 /* Check timer arguments */
944 if (init_ticks < ME4000_AI_MIN_TICKS) {
945 dev_err(dev->class_dev, "Invalid start arg\n");
946 cmd->start_arg = 2000; /* 66 ticks at least */
947 err++;
948 }
949 if (chan_ticks < ME4000_AI_MIN_TICKS) {
950 dev_err(dev->class_dev, "Invalid convert arg\n");
951 cmd->convert_arg = 2000; /* 66 ticks at least */
952 err++;
953 }
954 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
955 dev_err(dev->class_dev, "Invalid scan end arg\n");
956
957 /* At least one tick more */
958 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
959 err++;
960 }
961 } else if (cmd->start_src == TRIG_EXT &&
962 cmd->scan_begin_src == TRIG_FOLLOW &&
963 cmd->convert_src == TRIG_TIMER) {
964 /* Check timer arguments */
965 if (init_ticks < ME4000_AI_MIN_TICKS) {
966 dev_err(dev->class_dev, "Invalid start arg\n");
967 cmd->start_arg = 2000; /* 66 ticks at least */
968 err++;
969 }
970 if (chan_ticks < ME4000_AI_MIN_TICKS) {
971 dev_err(dev->class_dev, "Invalid convert arg\n");
972 cmd->convert_arg = 2000; /* 66 ticks at least */
973 err++;
974 }
975 } else if (cmd->start_src == TRIG_EXT &&
976 cmd->scan_begin_src == TRIG_EXT &&
977 cmd->convert_src == TRIG_TIMER) {
978 /* Check timer arguments */
979 if (init_ticks < ME4000_AI_MIN_TICKS) {
980 dev_err(dev->class_dev, "Invalid start arg\n");
981 cmd->start_arg = 2000; /* 66 ticks at least */
982 err++;
983 }
984 if (chan_ticks < ME4000_AI_MIN_TICKS) {
985 dev_err(dev->class_dev, "Invalid convert arg\n");
986 cmd->convert_arg = 2000; /* 66 ticks at least */
987 err++;
988 }
989 } else if (cmd->start_src == TRIG_EXT &&
990 cmd->scan_begin_src == TRIG_EXT &&
991 cmd->convert_src == TRIG_EXT) {
992 /* Check timer arguments */
993 if (init_ticks < ME4000_AI_MIN_TICKS) {
994 dev_err(dev->class_dev, "Invalid start arg\n");
995 cmd->start_arg = 2000; /* 66 ticks at least */
996 err++;
997 }
998 }
999 if (cmd->scan_end_src == TRIG_COUNT) {
1000 if (cmd->scan_end_arg == 0) {
1001 dev_err(dev->class_dev, "Invalid scan end arg\n");
1002 cmd->scan_end_arg = 1;
1003 err++;
1004 }
1005 }
1006
1007 if (err)
1008 return 4;
1009
1010 /* Step 5: check channel list if it exists */
1011 if (cmd->chanlist && cmd->chanlist_len > 0)
1012 err |= me4000_ai_check_chanlist(dev, s, cmd);
1013
1014 if (err)
1015 return 5;
1016
1017 return 0;
1018 }
1019
1020 static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
1021 {
1022 unsigned int tmp;
1023 struct comedi_device *dev = dev_id;
1024 struct comedi_subdevice *s = dev->read_subdev;
1025 int i;
1026 int c = 0;
1027 unsigned int lval;
1028
1029 if (!dev->attached)
1030 return IRQ_NONE;
1031
1032 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1033 ME4000_IRQ_STATUS_BIT_AI_HF) {
1034 /* Read status register to find out what happened */
1035 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1036
1037 if (!(tmp & ME4000_AI_STATUS_BIT_FF_DATA) &&
1038 !(tmp & ME4000_AI_STATUS_BIT_HF_DATA) &&
1039 (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1040 c = ME4000_AI_FIFO_COUNT;
1041
1042 /*
1043 * FIFO overflow, so stop conversion
1044 * and disable all interrupts
1045 */
1046 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1047 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1048 ME4000_AI_CTRL_BIT_SC_IRQ);
1049 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1050
1051 s->async->events |= COMEDI_CB_ERROR;
1052
1053 dev_err(dev->class_dev, "FIFO overflow\n");
1054 } else if ((tmp & ME4000_AI_STATUS_BIT_FF_DATA)
1055 && !(tmp & ME4000_AI_STATUS_BIT_HF_DATA)
1056 && (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1057 c = ME4000_AI_FIFO_COUNT / 2;
1058 } else {
1059 dev_err(dev->class_dev,
1060 "Can't determine state of fifo\n");
1061 c = 0;
1062
1063 /*
1064 * Undefined state, so stop conversion
1065 * and disable all interrupts
1066 */
1067 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1068 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1069 ME4000_AI_CTRL_BIT_SC_IRQ);
1070 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1071
1072 s->async->events |= COMEDI_CB_ERROR;
1073
1074 dev_err(dev->class_dev, "Undefined FIFO state\n");
1075 }
1076
1077 for (i = 0; i < c; i++) {
1078 /* Read value from data fifo */
1079 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1080 lval ^= 0x8000;
1081
1082 if (!comedi_buf_write_samples(s, &lval, 1)) {
1083 /*
1084 * Buffer overflow, so stop conversion
1085 * and disable all interrupts
1086 */
1087 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1088 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1089 ME4000_AI_CTRL_BIT_SC_IRQ);
1090 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1091 break;
1092 }
1093 }
1094
1095 /* Work is done, so reset the interrupt */
1096 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1097 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1098 tmp &= ~ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1099 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1100 }
1101
1102 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1103 ME4000_IRQ_STATUS_BIT_SC) {
1104 s->async->events |= COMEDI_CB_EOA;
1105
1106 /*
1107 * Acquisition is complete, so stop
1108 * conversion and disable all interrupts
1109 */
1110 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1111 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1112 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ);
1113 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1114
1115 /* Poll data until fifo empty */
1116 while (inl(dev->iobase + ME4000_AI_CTRL_REG) &
1117 ME4000_AI_STATUS_BIT_EF_DATA) {
1118 /* Read value from data fifo */
1119 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1120 lval ^= 0x8000;
1121
1122 if (!comedi_buf_write_samples(s, &lval, 1))
1123 break;
1124 }
1125
1126 /* Work is done, so reset the interrupt */
1127 tmp |= ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1128 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1129 tmp &= ~ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1130 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1131 }
1132
1133 comedi_handle_events(dev, s);
1134
1135 return IRQ_HANDLED;
1136 }
1137
1138 static int me4000_ao_insn_write(struct comedi_device *dev,
1139 struct comedi_subdevice *s,
1140 struct comedi_insn *insn,
1141 unsigned int *data)
1142 {
1143 int chan = CR_CHAN(insn->chanspec);
1144 unsigned int tmp;
1145
1146 /* Stop any running conversion */
1147 tmp = inl(dev->iobase + ME4000_AO_CTRL_REG(chan));
1148 tmp |= ME4000_AO_CTRL_BIT_IMMEDIATE_STOP;
1149 outl(tmp, dev->iobase + ME4000_AO_CTRL_REG(chan));
1150
1151 /* Clear control register and set to single mode */
1152 outl(0x0, dev->iobase + ME4000_AO_CTRL_REG(chan));
1153
1154 /* Write data value */
1155 outl(data[0], dev->iobase + ME4000_AO_SINGLE_REG(chan));
1156
1157 /* Store in the mirror */
1158 s->readback[chan] = data[0];
1159
1160 return 1;
1161 }
1162
1163 static int me4000_dio_insn_bits(struct comedi_device *dev,
1164 struct comedi_subdevice *s,
1165 struct comedi_insn *insn,
1166 unsigned int *data)
1167 {
1168 if (comedi_dio_update_state(s, data)) {
1169 outl((s->state >> 0) & 0xFF,
1170 dev->iobase + ME4000_DIO_PORT_0_REG);
1171 outl((s->state >> 8) & 0xFF,
1172 dev->iobase + ME4000_DIO_PORT_1_REG);
1173 outl((s->state >> 16) & 0xFF,
1174 dev->iobase + ME4000_DIO_PORT_2_REG);
1175 outl((s->state >> 24) & 0xFF,
1176 dev->iobase + ME4000_DIO_PORT_3_REG);
1177 }
1178
1179 data[1] = ((inl(dev->iobase + ME4000_DIO_PORT_0_REG) & 0xFF) << 0) |
1180 ((inl(dev->iobase + ME4000_DIO_PORT_1_REG) & 0xFF) << 8) |
1181 ((inl(dev->iobase + ME4000_DIO_PORT_2_REG) & 0xFF) << 16) |
1182 ((inl(dev->iobase + ME4000_DIO_PORT_3_REG) & 0xFF) << 24);
1183
1184 return insn->n;
1185 }
1186
1187 static int me4000_dio_insn_config(struct comedi_device *dev,
1188 struct comedi_subdevice *s,
1189 struct comedi_insn *insn,
1190 unsigned int *data)
1191 {
1192 unsigned int chan = CR_CHAN(insn->chanspec);
1193 unsigned int mask;
1194 unsigned int tmp;
1195 int ret;
1196
1197 if (chan < 8)
1198 mask = 0x000000ff;
1199 else if (chan < 16)
1200 mask = 0x0000ff00;
1201 else if (chan < 24)
1202 mask = 0x00ff0000;
1203 else
1204 mask = 0xff000000;
1205
1206 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
1207 if (ret)
1208 return ret;
1209
1210 tmp = inl(dev->iobase + ME4000_DIO_CTRL_REG);
1211 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_0 | ME4000_DIO_CTRL_BIT_MODE_1 |
1212 ME4000_DIO_CTRL_BIT_MODE_2 | ME4000_DIO_CTRL_BIT_MODE_3 |
1213 ME4000_DIO_CTRL_BIT_MODE_4 | ME4000_DIO_CTRL_BIT_MODE_5 |
1214 ME4000_DIO_CTRL_BIT_MODE_6 | ME4000_DIO_CTRL_BIT_MODE_7);
1215 if (s->io_bits & 0x000000ff)
1216 tmp |= ME4000_DIO_CTRL_BIT_MODE_0;
1217 if (s->io_bits & 0x0000ff00)
1218 tmp |= ME4000_DIO_CTRL_BIT_MODE_2;
1219 if (s->io_bits & 0x00ff0000)
1220 tmp |= ME4000_DIO_CTRL_BIT_MODE_4;
1221 if (s->io_bits & 0xff000000)
1222 tmp |= ME4000_DIO_CTRL_BIT_MODE_6;
1223
1224 /*
1225 * Check for optoisolated ME-4000 version.
1226 * If one the first port is a fixed output
1227 * port and the second is a fixed input port.
1228 */
1229 if (inl(dev->iobase + ME4000_DIO_DIR_REG)) {
1230 s->io_bits |= 0x000000ff;
1231 s->io_bits &= ~0x0000ff00;
1232 tmp |= ME4000_DIO_CTRL_BIT_MODE_0;
1233 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_2 |
1234 ME4000_DIO_CTRL_BIT_MODE_3);
1235 }
1236
1237 outl(tmp, dev->iobase + ME4000_DIO_CTRL_REG);
1238
1239 return insn->n;
1240 }
1241
1242 static int me4000_auto_attach(struct comedi_device *dev,
1243 unsigned long context)
1244 {
1245 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1246 const struct me4000_board *board = NULL;
1247 struct me4000_info *info;
1248 struct comedi_subdevice *s;
1249 int result;
1250
1251 if (context < ARRAY_SIZE(me4000_boards))
1252 board = &me4000_boards[context];
1253 if (!board)
1254 return -ENODEV;
1255 dev->board_ptr = board;
1256 dev->board_name = board->name;
1257
1258 info = comedi_alloc_devpriv(dev, sizeof(*info));
1259 if (!info)
1260 return -ENOMEM;
1261
1262 result = comedi_pci_enable(dev);
1263 if (result)
1264 return result;
1265
1266 info->plx_regbase = pci_resource_start(pcidev, 1);
1267 dev->iobase = pci_resource_start(pcidev, 2);
1268 if (!info->plx_regbase || !dev->iobase)
1269 return -ENODEV;
1270
1271 result = comedi_load_firmware(dev, &pcidev->dev, ME4000_FIRMWARE,
1272 me4000_xilinx_download, 0);
1273 if (result < 0)
1274 return result;
1275
1276 me4000_reset(dev);
1277
1278 if (pcidev->irq > 0) {
1279 result = request_irq(pcidev->irq, me4000_ai_isr, IRQF_SHARED,
1280 dev->board_name, dev);
1281 if (result == 0)
1282 dev->irq = pcidev->irq;
1283 }
1284
1285 result = comedi_alloc_subdevices(dev, 4);
1286 if (result)
1287 return result;
1288
1289 /* Analog Input subdevice */
1290 s = &dev->subdevices[0];
1291 s->type = COMEDI_SUBD_AI;
1292 s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_GROUND;
1293 if (board->ai_diff_nchan)
1294 s->subdev_flags |= SDF_DIFF;
1295 s->n_chan = board->ai_nchan;
1296 s->maxdata = 0xffff;
1297 s->len_chanlist = ME4000_AI_CHANNEL_LIST_COUNT;
1298 s->range_table = &me4000_ai_range;
1299 s->insn_read = me4000_ai_insn_read;
1300
1301 if (dev->irq) {
1302 dev->read_subdev = s;
1303 s->subdev_flags |= SDF_CMD_READ;
1304 s->cancel = me4000_ai_cancel;
1305 s->do_cmdtest = me4000_ai_do_cmd_test;
1306 s->do_cmd = me4000_ai_do_cmd;
1307 }
1308
1309 /*=========================================================================
1310 Analog output subdevice
1311 ========================================================================*/
1312
1313 s = &dev->subdevices[1];
1314
1315 if (board->ao_nchan) {
1316 s->type = COMEDI_SUBD_AO;
1317 s->subdev_flags = SDF_WRITABLE | SDF_COMMON | SDF_GROUND;
1318 s->n_chan = board->ao_nchan;
1319 s->maxdata = 0xFFFF; /* 16 bit DAC */
1320 s->range_table = &range_bipolar10;
1321 s->insn_write = me4000_ao_insn_write;
1322
1323 result = comedi_alloc_subdev_readback(s);
1324 if (result)
1325 return result;
1326 } else {
1327 s->type = COMEDI_SUBD_UNUSED;
1328 }
1329
1330 /* Digital I/O subdevice */
1331 s = &dev->subdevices[2];
1332 s->type = COMEDI_SUBD_DIO;
1333 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1334 s->n_chan = 32;
1335 s->maxdata = 1;
1336 s->range_table = &range_digital;
1337 s->insn_bits = me4000_dio_insn_bits;
1338 s->insn_config = me4000_dio_insn_config;
1339
1340 /*
1341 * Check for optoisolated ME-4000 version. If one the first
1342 * port is a fixed output port and the second is a fixed input port.
1343 */
1344 if (!inl(dev->iobase + ME4000_DIO_DIR_REG)) {
1345 s->io_bits |= 0xFF;
1346 outl(ME4000_DIO_CTRL_BIT_MODE_0,
1347 dev->iobase + ME4000_DIO_DIR_REG);
1348 }
1349
1350 /* Counter subdevice (8254) */
1351 s = &dev->subdevices[3];
1352 if (board->has_counter) {
1353 unsigned long timer_base = pci_resource_start(pcidev, 3);
1354
1355 if (!timer_base)
1356 return -ENODEV;
1357
1358 dev->pacer = comedi_8254_init(timer_base, 0, I8254_IO8, 0);
1359 if (!dev->pacer)
1360 return -ENOMEM;
1361
1362 comedi_8254_subdevice_init(s, dev->pacer);
1363 } else {
1364 s->type = COMEDI_SUBD_UNUSED;
1365 }
1366
1367 return 0;
1368 }
1369
1370 static void me4000_detach(struct comedi_device *dev)
1371 {
1372 if (dev->iobase)
1373 me4000_reset(dev);
1374 comedi_pci_detach(dev);
1375 }
1376
1377 static struct comedi_driver me4000_driver = {
1378 .driver_name = "me4000",
1379 .module = THIS_MODULE,
1380 .auto_attach = me4000_auto_attach,
1381 .detach = me4000_detach,
1382 };
1383
1384 static int me4000_pci_probe(struct pci_dev *dev,
1385 const struct pci_device_id *id)
1386 {
1387 return comedi_pci_auto_config(dev, &me4000_driver, id->driver_data);
1388 }
1389
1390 static const struct pci_device_id me4000_pci_table[] = {
1391 { PCI_VDEVICE(MEILHAUS, 0x4650), BOARD_ME4650 },
1392 { PCI_VDEVICE(MEILHAUS, 0x4660), BOARD_ME4660 },
1393 { PCI_VDEVICE(MEILHAUS, 0x4661), BOARD_ME4660I },
1394 { PCI_VDEVICE(MEILHAUS, 0x4662), BOARD_ME4660S },
1395 { PCI_VDEVICE(MEILHAUS, 0x4663), BOARD_ME4660IS },
1396 { PCI_VDEVICE(MEILHAUS, 0x4670), BOARD_ME4670 },
1397 { PCI_VDEVICE(MEILHAUS, 0x4671), BOARD_ME4670I },
1398 { PCI_VDEVICE(MEILHAUS, 0x4672), BOARD_ME4670S },
1399 { PCI_VDEVICE(MEILHAUS, 0x4673), BOARD_ME4670IS },
1400 { PCI_VDEVICE(MEILHAUS, 0x4680), BOARD_ME4680 },
1401 { PCI_VDEVICE(MEILHAUS, 0x4681), BOARD_ME4680I },
1402 { PCI_VDEVICE(MEILHAUS, 0x4682), BOARD_ME4680S },
1403 { PCI_VDEVICE(MEILHAUS, 0x4683), BOARD_ME4680IS },
1404 { 0 }
1405 };
1406 MODULE_DEVICE_TABLE(pci, me4000_pci_table);
1407
1408 static struct pci_driver me4000_pci_driver = {
1409 .name = "me4000",
1410 .id_table = me4000_pci_table,
1411 .probe = me4000_pci_probe,
1412 .remove = comedi_pci_auto_unconfig,
1413 };
1414 module_comedi_pci_driver(me4000_driver, me4000_pci_driver);
1415
1416 MODULE_AUTHOR("Comedi http://www.comedi.org");
1417 MODULE_DESCRIPTION("Comedi low-level driver");
1418 MODULE_LICENSE("GPL");
1419 MODULE_FIRMWARE(ME4000_FIRMWARE);
Linux kernel - Deliverables
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