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Staging: comedi: Remove comedi_insn typedef
[deliverable/linux.git] / drivers / staging / comedi / drivers / me_daq.c
1 /*
2
3 comedi/drivers/me_daq.c
4
5 Hardware driver for Meilhaus data acquisition cards:
6
7 ME-2000i, ME-2600i, ME-3000vm1
8
9 Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 /*
27 Driver: me_daq
28 Description: Meilhaus PCI data acquisition cards
29 Author: Michael Hillmann <hillmann@syscongroup.de>
30 Devices: [Meilhaus] ME-2600i (me_daq), ME-2000i
31 Status: experimental
32
33 Supports:
34
35 Analog Output
36
37 Configuration options:
38
39 [0] - PCI bus number (optional)
40 [1] - PCI slot number (optional)
41
42 If bus/slot is not specified, the first available PCI
43 device will be used.
44
45 The 2600 requires a firmware upload, which can be accomplished
46 using the -i or --init-data option of comedi_config.
47 The firmware can be
48 found in the comedi_nonfree_firmware tarball available
49 from http://www.comedi.org
50
51 */
52
53 #include "../comedidev.h"
54
55 #include "comedi_pci.h"
56
57 /*#include "me2600_fw.h" */
58
59 #define ME_DRIVER_NAME "me_daq"
60
61 #define ME2000_DEVICE_ID 0x2000
62 #define ME2600_DEVICE_ID 0x2600
63
64 #define PLX_INTCSR 0x4C /* PLX interrupt status register */
65 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
66
67 #define ME_CONTROL_1 0x0000 /* - | W */
68 #define INTERRUPT_ENABLE (1<<15)
69 #define COUNTER_B_IRQ (1<<12)
70 #define COUNTER_A_IRQ (1<<11)
71 #define CHANLIST_READY_IRQ (1<<10)
72 #define EXT_IRQ (1<<9)
73 #define ADFIFO_HALFFULL_IRQ (1<<8)
74 #define SCAN_COUNT_ENABLE (1<<5)
75 #define SIMULTANEOUS_ENABLE (1<<4)
76 #define TRIGGER_FALLING_EDGE (1<<3)
77 #define CONTINUOUS_MODE (1<<2)
78 #define DISABLE_ADC (0<<0)
79 #define SOFTWARE_TRIGGERED_ADC (1<<0)
80 #define SCAN_TRIGGERED_ADC (2<<0)
81 #define EXT_TRIGGERED_ADC (3<<0)
82 #define ME_ADC_START 0x0000 /* R | - */
83 #define ME_CONTROL_2 0x0002 /* - | W */
84 #define ENABLE_ADFIFO (1<<10)
85 #define ENABLE_CHANLIST (1<<9)
86 #define ENABLE_PORT_B (1<<7)
87 #define ENABLE_PORT_A (1<<6)
88 #define ENABLE_COUNTER_B (1<<4)
89 #define ENABLE_COUNTER_A (1<<3)
90 #define ENABLE_DAC (1<<1)
91 #define BUFFERED_DAC (1<<0)
92 #define ME_DAC_UPDATE 0x0002 /* R | - */
93 #define ME_STATUS 0x0004 /* R | - */
94 #define COUNTER_B_IRQ_PENDING (1<<12)
95 #define COUNTER_A_IRQ_PENDING (1<<11)
96 #define CHANLIST_READY_IRQ_PENDING (1<<10)
97 #define EXT_IRQ_PENDING (1<<9)
98 #define ADFIFO_HALFFULL_IRQ_PENDING (1<<8)
99 #define ADFIFO_FULL (1<<4)
100 #define ADFIFO_HALFFULL (1<<3)
101 #define ADFIFO_EMPTY (1<<2)
102 #define CHANLIST_FULL (1<<1)
103 #define FST_ACTIVE (1<<0)
104 #define ME_RESET_INTERRUPT 0x0004 /* - | W */
105 #define ME_DIO_PORT_A 0x0006 /* R | W */
106 #define ME_DIO_PORT_B 0x0008 /* R | W */
107 #define ME_TIMER_DATA_0 0x000A /* - | W */
108 #define ME_TIMER_DATA_1 0x000C /* - | W */
109 #define ME_TIMER_DATA_2 0x000E /* - | W */
110 #define ME_CHANNEL_LIST 0x0010 /* - | W */
111 #define ADC_UNIPOLAR (1<<6)
112 #define ADC_GAIN_0 (0<<4)
113 #define ADC_GAIN_1 (1<<4)
114 #define ADC_GAIN_2 (2<<4)
115 #define ADC_GAIN_3 (3<<4)
116 #define ME_READ_AD_FIFO 0x0010 /* R | - */
117 #define ME_DAC_CONTROL 0x0012 /* - | W */
118 #define DAC_UNIPOLAR_D (0<<4)
119 #define DAC_BIPOLAR_D (1<<4)
120 #define DAC_UNIPOLAR_C (0<<5)
121 #define DAC_BIPOLAR_C (1<<5)
122 #define DAC_UNIPOLAR_B (0<<6)
123 #define DAC_BIPOLAR_B (1<<6)
124 #define DAC_UNIPOLAR_A (0<<7)
125 #define DAC_BIPOLAR_A (1<<7)
126 #define DAC_GAIN_0_D (0<<8)
127 #define DAC_GAIN_1_D (1<<8)
128 #define DAC_GAIN_0_C (0<<9)
129 #define DAC_GAIN_1_C (1<<9)
130 #define DAC_GAIN_0_B (0<<10)
131 #define DAC_GAIN_1_B (1<<10)
132 #define DAC_GAIN_0_A (0<<11)
133 #define DAC_GAIN_1_A (1<<11)
134 #define ME_DAC_CONTROL_UPDATE 0x0012 /* R | - */
135 #define ME_DAC_DATA_A 0x0014 /* - | W */
136 #define ME_DAC_DATA_B 0x0016 /* - | W */
137 #define ME_DAC_DATA_C 0x0018 /* - | W */
138 #define ME_DAC_DATA_D 0x001A /* - | W */
139 #define ME_COUNTER_ENDDATA_A 0x001C /* - | W */
140 #define ME_COUNTER_ENDDATA_B 0x001E /* - | W */
141 #define ME_COUNTER_STARTDATA_A 0x0020 /* - | W */
142 #define ME_COUNTER_VALUE_A 0x0020 /* R | - */
143 #define ME_COUNTER_STARTDATA_B 0x0022 /* - | W */
144 #define ME_COUNTER_VALUE_B 0x0022 /* R | - */
145
146 /* Function prototypes */
147 static int me_attach(struct comedi_device *dev, comedi_devconfig *it);
148 static int me_detach(struct comedi_device *dev);
149
150 static const struct comedi_lrange me2000_ai_range = {
151 8,
152 {
153 BIP_RANGE(10),
154 BIP_RANGE(5),
155 BIP_RANGE(2.5),
156 BIP_RANGE(1.25),
157 UNI_RANGE(10),
158 UNI_RANGE(5),
159 UNI_RANGE(2.5),
160 UNI_RANGE(1.25)
161 }
162 };
163
164 static const struct comedi_lrange me2600_ai_range = {
165 8,
166 {
167 BIP_RANGE(10),
168 BIP_RANGE(5),
169 BIP_RANGE(2.5),
170 BIP_RANGE(1.25),
171 UNI_RANGE(10),
172 UNI_RANGE(5),
173 UNI_RANGE(2.5),
174 UNI_RANGE(1.25)
175 }
176 };
177
178 static const struct comedi_lrange me2600_ao_range = {
179 3,
180 {
181 BIP_RANGE(10),
182 BIP_RANGE(5),
183 UNI_RANGE(10)
184 }
185 };
186
187 static DEFINE_PCI_DEVICE_TABLE(me_pci_table) = {
188 {PCI_VENDOR_ID_MEILHAUS, ME2600_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
189 0},
190 {PCI_VENDOR_ID_MEILHAUS, ME2000_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
191 0},
192 {0}
193 };
194
195 MODULE_DEVICE_TABLE(pci, me_pci_table);
196
197 /* Board specification structure */
198 struct me_board {
199 const char *name; /* driver name */
200 int device_id;
201 int ao_channel_nbr; /* DA config */
202 int ao_resolution;
203 int ao_resolution_mask;
204 const struct comedi_lrange *ao_range_list;
205 int ai_channel_nbr; /* AD config */
206 int ai_resolution;
207 int ai_resolution_mask;
208 const struct comedi_lrange *ai_range_list;
209 int dio_channel_nbr; /* DIO config */
210 };
211
212 static const struct me_board me_boards[] = {
213 {
214 /* -- ME-2600i -- */
215 .name = ME_DRIVER_NAME,
216 .device_id = ME2600_DEVICE_ID,
217 /* Analog Output */
218 .ao_channel_nbr = 4,
219 .ao_resolution = 12,
220 .ao_resolution_mask = 0x0fff,
221 .ao_range_list = &me2600_ao_range,
222 .ai_channel_nbr = 16,
223 /* Analog Input */
224 .ai_resolution = 12,
225 .ai_resolution_mask = 0x0fff,
226 .ai_range_list = &me2600_ai_range,
227 .dio_channel_nbr = 32,
228 },
229 {
230 /* -- ME-2000i -- */
231 .name = ME_DRIVER_NAME,
232 .device_id = ME2000_DEVICE_ID,
233 /* Analog Output */
234 .ao_channel_nbr = 0,
235 .ao_resolution = 0,
236 .ao_resolution_mask = 0,
237 .ao_range_list = NULL,
238 .ai_channel_nbr = 16,
239 /* Analog Input */
240 .ai_resolution = 12,
241 .ai_resolution_mask = 0x0fff,
242 .ai_range_list = &me2000_ai_range,
243 .dio_channel_nbr = 32,
244 }
245 };
246
247 #define me_board_nbr (sizeof(me_boards)/sizeof(struct me_board))
248
249
250 static struct comedi_driver me_driver = {
251 .driver_name = ME_DRIVER_NAME,
252 .module = THIS_MODULE,
253 .attach = me_attach,
254 .detach = me_detach,
255 };
256 COMEDI_PCI_INITCLEANUP(me_driver, me_pci_table);
257
258 /* Private data structure */
259 struct me_private_data {
260 struct pci_dev *pci_device;
261 void __iomem *plx_regbase; /* PLX configuration base address */
262 void __iomem *me_regbase; /* Base address of the Meilhaus card */
263 unsigned long plx_regbase_size; /* Size of PLX configuration space */
264 unsigned long me_regbase_size; /* Size of Meilhaus space */
265
266 unsigned short control_1; /* Mirror of CONTROL_1 register */
267 unsigned short control_2; /* Mirror of CONTROL_2 register */
268 unsigned short dac_control; /* Mirror of the DAC_CONTROL register */
269 int ao_readback[4]; /* Mirror of analog output data */
270 };
271
272 #define dev_private ((struct me_private_data *)dev->private)
273
274 /*
275 * ------------------------------------------------------------------
276 *
277 * Helpful functions
278 *
279 * ------------------------------------------------------------------
280 */
281 static inline void sleep(unsigned sec)
282 {
283 current->state = TASK_INTERRUPTIBLE;
284 schedule_timeout(sec * HZ);
285 }
286
287 /*
288 * ------------------------------------------------------------------
289 *
290 * DIGITAL INPUT/OUTPUT SECTION
291 *
292 * ------------------------------------------------------------------
293 */
294 static int me_dio_insn_config(struct comedi_device *dev, struct comedi_subdevice *s,
295 struct comedi_insn *insn, unsigned int *data)
296 {
297 int bits;
298 int mask = 1 << CR_CHAN(insn->chanspec);
299
300 /* calculate port */
301 if (mask & 0x0000ffff) { /* Port A in use */
302 bits = 0x0000ffff;
303
304 /* Enable Port A */
305 dev_private->control_2 |= ENABLE_PORT_A;
306 writew(dev_private->control_2,
307 dev_private->me_regbase + ME_CONTROL_2);
308 } else { /* Port B in use */
309
310 bits = 0xffff0000;
311
312 /* Enable Port B */
313 dev_private->control_2 |= ENABLE_PORT_B;
314 writew(dev_private->control_2,
315 dev_private->me_regbase + ME_CONTROL_2);
316 }
317
318 if (data[0]) {
319 /* Config port as output */
320 s->io_bits |= bits;
321 } else {
322 /* Config port as input */
323 s->io_bits &= ~bits;
324 }
325
326 return 1;
327 }
328
329 /* Digital instant input/outputs */
330 static int me_dio_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s,
331 struct comedi_insn *insn, unsigned int *data)
332 {
333 unsigned int mask = data[0];
334 s->state &= ~mask;
335 s->state |= (mask & data[1]);
336
337 mask &= s->io_bits;
338 if (mask & 0x0000ffff) { /* Port A */
339 writew((s->state & 0xffff),
340 dev_private->me_regbase + ME_DIO_PORT_A);
341 } else {
342 data[1] &= ~0x0000ffff;
343 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_A);
344 }
345
346 if (mask & 0xffff0000) { /* Port B */
347 writew(((s->state >> 16) & 0xffff),
348 dev_private->me_regbase + ME_DIO_PORT_B);
349 } else {
350 data[1] &= ~0xffff0000;
351 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_B) << 16;
352 }
353
354 return 2;
355 }
356
357 /*
358 * ------------------------------------------------------------------
359 *
360 * ANALOG INPUT SECTION
361 *
362 * ------------------------------------------------------------------
363 */
364
365 /* Analog instant input */
366 static int me_ai_insn_read(struct comedi_device *dev, struct comedi_subdevice *subdevice,
367 struct comedi_insn *insn, unsigned int *data)
368 {
369 unsigned short value;
370 int chan = CR_CHAN((&insn->chanspec)[0]);
371 int rang = CR_RANGE((&insn->chanspec)[0]);
372 int aref = CR_AREF((&insn->chanspec)[0]);
373 int i;
374
375 /* stop any running conversion */
376 dev_private->control_1 &= 0xFFFC;
377 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
378
379 /* clear chanlist and ad fifo */
380 dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
381 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
382
383 /* reset any pending interrupt */
384 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
385
386 /* enable the chanlist and ADC fifo */
387 dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
388 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
389
390 /* write to channel list fifo */
391 /* b3:b0 are the channel number */
392 value = chan & 0x0f;
393 /* b5:b4 are the channel gain */
394 value |= (rang & 0x03) << 4;
395 /* b6 channel polarity */
396 value |= (rang & 0x04) << 4;
397 /* b7 single or differential */
398 value |= ((aref & AREF_DIFF) ? 0x80 : 0);
399 writew(value & 0xff, dev_private->me_regbase + ME_CHANNEL_LIST);
400
401 /* set ADC mode to software trigger */
402 dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
403 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
404
405 /* start conversion by reading from ADC_START */
406 readw(dev_private->me_regbase + ME_ADC_START);
407
408 /* wait for ADC fifo not empty flag */
409 for (i = 100000; i > 0; i--)
410 if (!(readw(dev_private->me_regbase + ME_STATUS) & 0x0004))
411 break;
412
413 /* get value from ADC fifo */
414 if (i) {
415 data[0] =
416 (readw(dev_private->me_regbase +
417 ME_READ_AD_FIFO) ^ 0x800) & 0x0FFF;
418 } else {
419 printk(KERN_ERR "comedi%d: Cannot get single value\n",
420 dev->minor);
421 return -EIO;
422 }
423
424 /* stop any running conversion */
425 dev_private->control_1 &= 0xFFFC;
426 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
427
428 return 1;
429 }
430
431 /*
432 * ------------------------------------------------------------------
433 *
434 * HARDWARE TRIGGERED ANALOG INPUT SECTION
435 *
436 * ------------------------------------------------------------------
437 */
438
439 /* Cancel analog input autoscan */
440 static int me_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
441 {
442 /* disable interrupts */
443
444 /* stop any running conversion */
445 dev_private->control_1 &= 0xFFFC;
446 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
447
448 return 0;
449 }
450
451 /* Test analog input command */
452 static int me_ai_do_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
453 struct comedi_cmd *cmd)
454 {
455 return 0;
456 }
457
458 /* Analog input command */
459 static int me_ai_do_cmd(struct comedi_device *dev, struct comedi_subdevice *subdevice)
460 {
461 return 0;
462 }
463
464 /*
465 * ------------------------------------------------------------------
466 *
467 * ANALOG OUTPUT SECTION
468 *
469 * ------------------------------------------------------------------
470 */
471
472 /* Analog instant output */
473 static int me_ao_insn_write(struct comedi_device *dev, struct comedi_subdevice *s,
474 struct comedi_insn *insn, unsigned int *data)
475 {
476 int chan;
477 int rang;
478 int i;
479
480 /* Enable all DAC */
481 dev_private->control_2 |= ENABLE_DAC;
482 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
483
484 /* and set DAC to "buffered" mode */
485 dev_private->control_2 |= BUFFERED_DAC;
486 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
487
488 /* Set dac-control register */
489 for (i = 0; i < insn->n; i++) {
490 chan = CR_CHAN((&insn->chanspec)[i]);
491 rang = CR_RANGE((&insn->chanspec)[i]);
492
493 /* clear bits for this channel */
494 dev_private->dac_control &= ~(0x0880 >> chan);
495 if (rang == 0)
496 dev_private->dac_control |=
497 ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
498 else if (rang == 1)
499 dev_private->dac_control |=
500 ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
501 }
502 writew(dev_private->dac_control,
503 dev_private->me_regbase + ME_DAC_CONTROL);
504
505 /* Update dac-control register */
506 readw(dev_private->me_regbase + ME_DAC_CONTROL_UPDATE);
507
508 /* Set data register */
509 for (i = 0; i < insn->n; i++) {
510 chan = CR_CHAN((&insn->chanspec)[i]);
511 writew((data[0] & s->maxdata),
512 dev_private->me_regbase + ME_DAC_DATA_A + (chan << 1));
513 dev_private->ao_readback[chan] = (data[0] & s->maxdata);
514 }
515
516 /* Update dac with data registers */
517 readw(dev_private->me_regbase + ME_DAC_UPDATE);
518
519 return i;
520 }
521
522 /* Analog output readback */
523 static int me_ao_insn_read(struct comedi_device *dev, struct comedi_subdevice *s,
524 struct comedi_insn *insn, unsigned int *data)
525 {
526 int i;
527
528 for (i = 0; i < insn->n; i++) {
529 data[i] =
530 dev_private->ao_readback[CR_CHAN((&insn->chanspec)[i])];
531 }
532
533 return 1;
534 }
535
536 /*
537 * ------------------------------------------------------------------
538 *
539 * INITIALISATION SECTION
540 *
541 * ------------------------------------------------------------------
542 */
543
544 /* Xilinx firmware download for card: ME-2600i */
545 static int me2600_xilinx_download(struct comedi_device *dev,
546 unsigned char *me2600_firmware,
547 unsigned int length)
548 {
549 unsigned int value;
550 unsigned int file_length;
551 unsigned int i;
552
553 /* disable irq's on PLX */
554 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
555
556 /* First, make a dummy read to reset xilinx */
557 value = readw(dev_private->me_regbase + XILINX_DOWNLOAD_RESET);
558
559 /* Wait until reset is over */
560 sleep(1);
561
562 /* Write a dummy value to Xilinx */
563 writeb(0x00, dev_private->me_regbase + 0x0);
564 sleep(1);
565
566 /*
567 * Format of the firmware
568 * Build longs from the byte-wise coded header
569 * Byte 1-3: length of the array
570 * Byte 4-7: version
571 * Byte 8-11: date
572 * Byte 12-15: reserved
573 */
574 if (length < 16)
575 return -EINVAL;
576 file_length = (((unsigned int)me2600_firmware[0] & 0xff) << 24) +
577 (((unsigned int)me2600_firmware[1] & 0xff) << 16) +
578 (((unsigned int)me2600_firmware[2] & 0xff) << 8) +
579 ((unsigned int)me2600_firmware[3] & 0xff);
580
581 /*
582 * Loop for writing firmware byte by byte to xilinx
583 * Firmware data start at offfset 16
584 */
585 for (i = 0; i < file_length; i++)
586 writeb((me2600_firmware[16 + i] & 0xff),
587 dev_private->me_regbase + 0x0);
588
589 /* Write 5 dummy values to xilinx */
590 for (i = 0; i < 5; i++)
591 writeb(0x00, dev_private->me_regbase + 0x0);
592
593 /* Test if there was an error during download -> INTB was thrown */
594 value = readl(dev_private->plx_regbase + PLX_INTCSR);
595 if (value & 0x20) {
596 /* Disable interrupt */
597 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
598 printk(KERN_ERR "comedi%d: Xilinx download failed\n",
599 dev->minor);
600 return -EIO;
601 }
602
603 /* Wait until the Xilinx is ready for real work */
604 sleep(1);
605
606 /* Enable PLX-Interrupts */
607 writel(0x43, dev_private->plx_regbase + PLX_INTCSR);
608
609 return 0;
610 }
611
612 /* Reset device */
613 static int me_reset(struct comedi_device *dev)
614 {
615 /* Reset board */
616 writew(0x00, dev_private->me_regbase + ME_CONTROL_1);
617 writew(0x00, dev_private->me_regbase + ME_CONTROL_2);
618 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
619 writew(0x00, dev_private->me_regbase + ME_DAC_CONTROL);
620
621 /* Save values in the board context */
622 dev_private->dac_control = 0;
623 dev_private->control_1 = 0;
624 dev_private->control_2 = 0;
625
626 return 0;
627 }
628
629 /*
630 * Attach
631 *
632 * - Register PCI device
633 * - Declare device driver capability
634 */
635 static int me_attach(struct comedi_device *dev, comedi_devconfig *it)
636 {
637 struct pci_dev *pci_device;
638 struct comedi_subdevice *subdevice;
639 struct me_board *board;
640 resource_size_t plx_regbase_tmp;
641 unsigned long plx_regbase_size_tmp;
642 resource_size_t me_regbase_tmp;
643 unsigned long me_regbase_size_tmp;
644 resource_size_t swap_regbase_tmp;
645 unsigned long swap_regbase_size_tmp;
646 resource_size_t regbase_tmp;
647 int result, error, i;
648
649 /* Allocate private memory */
650 if (alloc_private(dev, sizeof(struct me_private_data)) < 0)
651 return -ENOMEM;
652
653 /* Probe the device to determine what device in the series it is. */
654 for (pci_device = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL);
655 pci_device != NULL;
656 pci_device =
657 pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pci_device)) {
658 if (pci_device->vendor == PCI_VENDOR_ID_MEILHAUS) {
659 for (i = 0; i < me_board_nbr; i++) {
660 if (me_boards[i].device_id ==
661 pci_device->device) {
662 /*
663 * was a particular bus/slot requested?
664 */
665 if ((it->options[0] != 0)
666 || (it->options[1] != 0)) {
667 /*
668 * are we on the wrong bus/slot?
669 */
670 if (pci_device->bus->number !=
671 it->options[0]
672 || PCI_SLOT(pci_device->
673 devfn) !=
674 it->options[1]) {
675 continue;
676 }
677 }
678
679 dev->board_ptr = me_boards + i;
680 board = (struct me_board *) dev->
681 board_ptr;
682 dev_private->pci_device = pci_device;
683 goto found;
684 }
685 }
686 }
687 }
688
689 printk(KERN_ERR
690 "comedi%d: no supported board found! (req. bus/slot : %d/%d)\n",
691 dev->minor, it->options[0], it->options[1]);
692 return -EIO;
693
694 found:
695 printk(KERN_INFO "comedi%d: found %s at PCI bus %d, slot %d\n",
696 dev->minor, me_boards[i].name,
697 pci_device->bus->number, PCI_SLOT(pci_device->devfn));
698
699 /* Enable PCI device and request PCI regions */
700 if (comedi_pci_enable(pci_device, ME_DRIVER_NAME) < 0) {
701 printk(KERN_ERR "comedi%d: Failed to enable PCI device and "
702 "request regions\n", dev->minor);
703 return -EIO;
704 }
705
706 /* Set data in device structure */
707 dev->board_name = board->name;
708
709 /* Read PLX register base address [PCI_BASE_ADDRESS #0]. */
710 plx_regbase_tmp = pci_resource_start(pci_device, 0);
711 plx_regbase_size_tmp = pci_resource_len(pci_device, 0);
712 dev_private->plx_regbase =
713 ioremap(plx_regbase_tmp, plx_regbase_size_tmp);
714 dev_private->plx_regbase_size = plx_regbase_size_tmp;
715 if (!dev_private->plx_regbase) {
716 printk("comedi%d: Failed to remap I/O memory\n", dev->minor);
717 return -ENOMEM;
718 }
719
720 /* Read Swap base address [PCI_BASE_ADDRESS #5]. */
721
722 swap_regbase_tmp = pci_resource_start(pci_device, 5);
723 swap_regbase_size_tmp = pci_resource_len(pci_device, 5);
724
725 if (!swap_regbase_tmp)
726 printk(KERN_ERR "comedi%d: Swap not present\n", dev->minor);
727
728 /*---------------------------------------------- Workaround start ---*/
729 if (plx_regbase_tmp & 0x0080) {
730 printk(KERN_ERR "comedi%d: PLX-Bug detected\n", dev->minor);
731
732 if (swap_regbase_tmp) {
733 regbase_tmp = plx_regbase_tmp;
734 plx_regbase_tmp = swap_regbase_tmp;
735 swap_regbase_tmp = regbase_tmp;
736
737 result = pci_write_config_dword(pci_device,
738 PCI_BASE_ADDRESS_0, plx_regbase_tmp);
739 if (result != PCIBIOS_SUCCESSFUL)
740 return -EIO;
741
742 result = pci_write_config_dword(pci_device,
743 PCI_BASE_ADDRESS_5, swap_regbase_tmp);
744 if (result != PCIBIOS_SUCCESSFUL)
745 return -EIO;
746 } else {
747 plx_regbase_tmp -= 0x80;
748 result = pci_write_config_dword(pci_device,
749 PCI_BASE_ADDRESS_0, plx_regbase_tmp);
750 if (result != PCIBIOS_SUCCESSFUL)
751 return -EIO;
752 }
753 }
754 /*--------------------------------------------- Workaround end -----*/
755
756 /* Read Meilhaus register base address [PCI_BASE_ADDRESS #2]. */
757
758 me_regbase_tmp = pci_resource_start(pci_device, 2);
759 me_regbase_size_tmp = pci_resource_len(pci_device, 2);
760 dev_private->me_regbase_size = me_regbase_size_tmp;
761 dev_private->me_regbase = ioremap(me_regbase_tmp, me_regbase_size_tmp);
762 if (!dev_private->me_regbase) {
763 printk(KERN_ERR "comedi%d: Failed to remap I/O memory\n",
764 dev->minor);
765 return -ENOMEM;
766 }
767 /* Download firmware and reset card */
768 if (board->device_id == ME2600_DEVICE_ID) {
769 unsigned char *aux_data;
770 int aux_len;
771
772 aux_data = comedi_aux_data(it->options, 0);
773 aux_len = it->options[COMEDI_DEVCONF_AUX_DATA_LENGTH];
774
775 if (!aux_data || aux_len < 1) {
776 comedi_error(dev, "You must provide me2600 firmware "
777 "using the --init-data option of "
778 "comedi_config");
779 return -EINVAL;
780 }
781 me2600_xilinx_download(dev, aux_data, aux_len);
782 }
783
784 me_reset(dev);
785
786 /* device driver capabilities */
787 error = alloc_subdevices(dev, 3);
788 if (error < 0)
789 return error;
790
791 subdevice = dev->subdevices + 0;
792 subdevice->type = COMEDI_SUBD_AI;
793 subdevice->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_CMD_READ;
794 subdevice->n_chan = board->ai_channel_nbr;
795 subdevice->maxdata = board->ai_resolution_mask;
796 subdevice->len_chanlist = board->ai_channel_nbr;
797 subdevice->range_table = board->ai_range_list;
798 subdevice->cancel = me_ai_cancel;
799 subdevice->insn_read = me_ai_insn_read;
800 subdevice->do_cmdtest = me_ai_do_cmd_test;
801 subdevice->do_cmd = me_ai_do_cmd;
802
803 subdevice = dev->subdevices + 1;
804 subdevice->type = COMEDI_SUBD_AO;
805 subdevice->subdev_flags = SDF_WRITEABLE | SDF_COMMON;
806 subdevice->n_chan = board->ao_channel_nbr;
807 subdevice->maxdata = board->ao_resolution_mask;
808 subdevice->len_chanlist = board->ao_channel_nbr;
809 subdevice->range_table = board->ao_range_list;
810 subdevice->insn_read = me_ao_insn_read;
811 subdevice->insn_write = me_ao_insn_write;
812
813 subdevice = dev->subdevices + 2;
814 subdevice->type = COMEDI_SUBD_DIO;
815 subdevice->subdev_flags = SDF_READABLE | SDF_WRITEABLE;
816 subdevice->n_chan = board->dio_channel_nbr;
817 subdevice->maxdata = 1;
818 subdevice->len_chanlist = board->dio_channel_nbr;
819 subdevice->range_table = &range_digital;
820 subdevice->insn_bits = me_dio_insn_bits;
821 subdevice->insn_config = me_dio_insn_config;
822 subdevice->io_bits = 0;
823
824 printk(KERN_INFO "comedi%d: "ME_DRIVER_NAME" attached.\n", dev->minor);
825 return 0;
826 }
827
828 /* Detach */
829 static int me_detach(struct comedi_device *dev)
830 {
831 if (dev_private) {
832 if (dev_private->me_regbase) {
833 me_reset(dev);
834 iounmap(dev_private->me_regbase);
835 }
836 if (dev_private->plx_regbase)
837 iounmap(dev_private->plx_regbase);
838 if (dev_private->pci_device) {
839 if (dev_private->plx_regbase_size)
840 comedi_pci_disable(dev_private->pci_device);
841
842 pci_dev_put(dev_private->pci_device);
843 }
844 }
845 return 0;
846 }
Linux kernel - Deliverables
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