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[deliverable/linux.git] / drivers / staging / comedi / drivers / me_daq.c
1 /*
2
3 comedi/drivers/me_daq.c
4
5 Hardware driver for Meilhaus data acquisition cards:
6
7 ME-2000i, ME-2600i, ME-3000vm1
8
9 Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 /*
27 Driver: me_daq
28 Description: Meilhaus PCI data acquisition cards
29 Author: Michael Hillmann <hillmann@syscongroup.de>
30 Devices: [Meilhaus] ME-2600i (me_daq), ME-2000i
31 Status: experimental
32
33 Supports:
34
35 Analog Output
36
37 Configuration options:
38
39 [0] - PCI bus number (optional)
40 [1] - PCI slot number (optional)
41
42 If bus/slot is not specified, the first available PCI
43 device will be used.
44
45 The 2600 requires a firmware upload, which can be accomplished
46 using the -i or --init-data option of comedi_config.
47 The firmware can be
48 found in the comedi_nonfree_firmware tarball available
49 from http://www.comedi.org
50
51 */
52
53 #include <linux/interrupt.h>
54 #include <linux/sched.h>
55 #include "../comedidev.h"
56
57 #include "comedi_pci.h"
58
59 /*#include "me2600_fw.h" */
60
61 #define ME_DRIVER_NAME "me_daq"
62
63 #define PCI_VENDOR_ID_MEILHAUS 0x1402
64 #define ME2000_DEVICE_ID 0x2000
65 #define ME2600_DEVICE_ID 0x2600
66
67 #define PLX_INTCSR 0x4C /* PLX interrupt status register */
68 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
69
70 #define ME_CONTROL_1 0x0000 /* - | W */
71 #define INTERRUPT_ENABLE (1<<15)
72 #define COUNTER_B_IRQ (1<<12)
73 #define COUNTER_A_IRQ (1<<11)
74 #define CHANLIST_READY_IRQ (1<<10)
75 #define EXT_IRQ (1<<9)
76 #define ADFIFO_HALFFULL_IRQ (1<<8)
77 #define SCAN_COUNT_ENABLE (1<<5)
78 #define SIMULTANEOUS_ENABLE (1<<4)
79 #define TRIGGER_FALLING_EDGE (1<<3)
80 #define CONTINUOUS_MODE (1<<2)
81 #define DISABLE_ADC (0<<0)
82 #define SOFTWARE_TRIGGERED_ADC (1<<0)
83 #define SCAN_TRIGGERED_ADC (2<<0)
84 #define EXT_TRIGGERED_ADC (3<<0)
85 #define ME_ADC_START 0x0000 /* R | - */
86 #define ME_CONTROL_2 0x0002 /* - | W */
87 #define ENABLE_ADFIFO (1<<10)
88 #define ENABLE_CHANLIST (1<<9)
89 #define ENABLE_PORT_B (1<<7)
90 #define ENABLE_PORT_A (1<<6)
91 #define ENABLE_COUNTER_B (1<<4)
92 #define ENABLE_COUNTER_A (1<<3)
93 #define ENABLE_DAC (1<<1)
94 #define BUFFERED_DAC (1<<0)
95 #define ME_DAC_UPDATE 0x0002 /* R | - */
96 #define ME_STATUS 0x0004 /* R | - */
97 #define COUNTER_B_IRQ_PENDING (1<<12)
98 #define COUNTER_A_IRQ_PENDING (1<<11)
99 #define CHANLIST_READY_IRQ_PENDING (1<<10)
100 #define EXT_IRQ_PENDING (1<<9)
101 #define ADFIFO_HALFFULL_IRQ_PENDING (1<<8)
102 #define ADFIFO_FULL (1<<4)
103 #define ADFIFO_HALFFULL (1<<3)
104 #define ADFIFO_EMPTY (1<<2)
105 #define CHANLIST_FULL (1<<1)
106 #define FST_ACTIVE (1<<0)
107 #define ME_RESET_INTERRUPT 0x0004 /* - | W */
108 #define ME_DIO_PORT_A 0x0006 /* R | W */
109 #define ME_DIO_PORT_B 0x0008 /* R | W */
110 #define ME_TIMER_DATA_0 0x000A /* - | W */
111 #define ME_TIMER_DATA_1 0x000C /* - | W */
112 #define ME_TIMER_DATA_2 0x000E /* - | W */
113 #define ME_CHANNEL_LIST 0x0010 /* - | W */
114 #define ADC_UNIPOLAR (1<<6)
115 #define ADC_GAIN_0 (0<<4)
116 #define ADC_GAIN_1 (1<<4)
117 #define ADC_GAIN_2 (2<<4)
118 #define ADC_GAIN_3 (3<<4)
119 #define ME_READ_AD_FIFO 0x0010 /* R | - */
120 #define ME_DAC_CONTROL 0x0012 /* - | W */
121 #define DAC_UNIPOLAR_D (0<<4)
122 #define DAC_BIPOLAR_D (1<<4)
123 #define DAC_UNIPOLAR_C (0<<5)
124 #define DAC_BIPOLAR_C (1<<5)
125 #define DAC_UNIPOLAR_B (0<<6)
126 #define DAC_BIPOLAR_B (1<<6)
127 #define DAC_UNIPOLAR_A (0<<7)
128 #define DAC_BIPOLAR_A (1<<7)
129 #define DAC_GAIN_0_D (0<<8)
130 #define DAC_GAIN_1_D (1<<8)
131 #define DAC_GAIN_0_C (0<<9)
132 #define DAC_GAIN_1_C (1<<9)
133 #define DAC_GAIN_0_B (0<<10)
134 #define DAC_GAIN_1_B (1<<10)
135 #define DAC_GAIN_0_A (0<<11)
136 #define DAC_GAIN_1_A (1<<11)
137 #define ME_DAC_CONTROL_UPDATE 0x0012 /* R | - */
138 #define ME_DAC_DATA_A 0x0014 /* - | W */
139 #define ME_DAC_DATA_B 0x0016 /* - | W */
140 #define ME_DAC_DATA_C 0x0018 /* - | W */
141 #define ME_DAC_DATA_D 0x001A /* - | W */
142 #define ME_COUNTER_ENDDATA_A 0x001C /* - | W */
143 #define ME_COUNTER_ENDDATA_B 0x001E /* - | W */
144 #define ME_COUNTER_STARTDATA_A 0x0020 /* - | W */
145 #define ME_COUNTER_VALUE_A 0x0020 /* R | - */
146 #define ME_COUNTER_STARTDATA_B 0x0022 /* - | W */
147 #define ME_COUNTER_VALUE_B 0x0022 /* R | - */
148
149 /* Function prototypes */
150 static int me_attach(struct comedi_device *dev, struct comedi_devconfig *it);
151 static int me_detach(struct comedi_device *dev);
152
153 static const struct comedi_lrange me2000_ai_range = {
154 8,
155 {
156 BIP_RANGE(10),
157 BIP_RANGE(5),
158 BIP_RANGE(2.5),
159 BIP_RANGE(1.25),
160 UNI_RANGE(10),
161 UNI_RANGE(5),
162 UNI_RANGE(2.5),
163 UNI_RANGE(1.25)
164 }
165 };
166
167 static const struct comedi_lrange me2600_ai_range = {
168 8,
169 {
170 BIP_RANGE(10),
171 BIP_RANGE(5),
172 BIP_RANGE(2.5),
173 BIP_RANGE(1.25),
174 UNI_RANGE(10),
175 UNI_RANGE(5),
176 UNI_RANGE(2.5),
177 UNI_RANGE(1.25)
178 }
179 };
180
181 static const struct comedi_lrange me2600_ao_range = {
182 3,
183 {
184 BIP_RANGE(10),
185 BIP_RANGE(5),
186 UNI_RANGE(10)
187 }
188 };
189
190 static DEFINE_PCI_DEVICE_TABLE(me_pci_table) = {
191 {
192 PCI_VENDOR_ID_MEILHAUS, ME2600_DEVICE_ID, PCI_ANY_ID,
193 PCI_ANY_ID, 0, 0, 0}, {
194 PCI_VENDOR_ID_MEILHAUS, ME2000_DEVICE_ID, PCI_ANY_ID,
195 PCI_ANY_ID, 0, 0, 0}, {
196 0}
197 };
198
199 MODULE_DEVICE_TABLE(pci, me_pci_table);
200
201 /* Board specification structure */
202 struct me_board {
203 const char *name; /* driver name */
204 int device_id;
205 int ao_channel_nbr; /* DA config */
206 int ao_resolution;
207 int ao_resolution_mask;
208 const struct comedi_lrange *ao_range_list;
209 int ai_channel_nbr; /* AD config */
210 int ai_resolution;
211 int ai_resolution_mask;
212 const struct comedi_lrange *ai_range_list;
213 int dio_channel_nbr; /* DIO config */
214 };
215
216 static const struct me_board me_boards[] = {
217 {
218 /* -- ME-2600i -- */
219 .name = ME_DRIVER_NAME,
220 .device_id = ME2600_DEVICE_ID,
221 /* Analog Output */
222 .ao_channel_nbr = 4,
223 .ao_resolution = 12,
224 .ao_resolution_mask = 0x0fff,
225 .ao_range_list = &me2600_ao_range,
226 .ai_channel_nbr = 16,
227 /* Analog Input */
228 .ai_resolution = 12,
229 .ai_resolution_mask = 0x0fff,
230 .ai_range_list = &me2600_ai_range,
231 .dio_channel_nbr = 32,
232 },
233 {
234 /* -- ME-2000i -- */
235 .name = ME_DRIVER_NAME,
236 .device_id = ME2000_DEVICE_ID,
237 /* Analog Output */
238 .ao_channel_nbr = 0,
239 .ao_resolution = 0,
240 .ao_resolution_mask = 0,
241 .ao_range_list = NULL,
242 .ai_channel_nbr = 16,
243 /* Analog Input */
244 .ai_resolution = 12,
245 .ai_resolution_mask = 0x0fff,
246 .ai_range_list = &me2000_ai_range,
247 .dio_channel_nbr = 32,
248 }
249 };
250
251 #define me_board_nbr (sizeof(me_boards)/sizeof(struct me_board))
252
253 static struct comedi_driver me_driver = {
254 .driver_name = ME_DRIVER_NAME,
255 .module = THIS_MODULE,
256 .attach = me_attach,
257 .detach = me_detach,
258 };
259
260 COMEDI_PCI_INITCLEANUP(me_driver, me_pci_table);
261
262 /* Private data structure */
263 struct me_private_data {
264 struct pci_dev *pci_device;
265 void __iomem *plx_regbase; /* PLX configuration base address */
266 void __iomem *me_regbase; /* Base address of the Meilhaus card */
267 unsigned long plx_regbase_size; /* Size of PLX configuration space */
268 unsigned long me_regbase_size; /* Size of Meilhaus space */
269
270 unsigned short control_1; /* Mirror of CONTROL_1 register */
271 unsigned short control_2; /* Mirror of CONTROL_2 register */
272 unsigned short dac_control; /* Mirror of the DAC_CONTROL register */
273 int ao_readback[4]; /* Mirror of analog output data */
274 };
275
276 #define dev_private ((struct me_private_data *)dev->private)
277
278 /*
279 * ------------------------------------------------------------------
280 *
281 * Helpful functions
282 *
283 * ------------------------------------------------------------------
284 */
285 static inline void sleep(unsigned sec)
286 {
287 current->state = TASK_INTERRUPTIBLE;
288 schedule_timeout(sec * HZ);
289 }
290
291 /*
292 * ------------------------------------------------------------------
293 *
294 * DIGITAL INPUT/OUTPUT SECTION
295 *
296 * ------------------------------------------------------------------
297 */
298 static int me_dio_insn_config(struct comedi_device *dev,
299 struct comedi_subdevice *s,
300 struct comedi_insn *insn, unsigned int *data)
301 {
302 int bits;
303 int mask = 1 << CR_CHAN(insn->chanspec);
304
305 /* calculate port */
306 if (mask & 0x0000ffff) { /* Port A in use */
307 bits = 0x0000ffff;
308
309 /* Enable Port A */
310 dev_private->control_2 |= ENABLE_PORT_A;
311 writew(dev_private->control_2,
312 dev_private->me_regbase + ME_CONTROL_2);
313 } else { /* Port B in use */
314
315 bits = 0xffff0000;
316
317 /* Enable Port B */
318 dev_private->control_2 |= ENABLE_PORT_B;
319 writew(dev_private->control_2,
320 dev_private->me_regbase + ME_CONTROL_2);
321 }
322
323 if (data[0]) {
324 /* Config port as output */
325 s->io_bits |= bits;
326 } else {
327 /* Config port as input */
328 s->io_bits &= ~bits;
329 }
330
331 return 1;
332 }
333
334 /* Digital instant input/outputs */
335 static int me_dio_insn_bits(struct comedi_device *dev,
336 struct comedi_subdevice *s,
337 struct comedi_insn *insn, unsigned int *data)
338 {
339 unsigned int mask = data[0];
340 s->state &= ~mask;
341 s->state |= (mask & data[1]);
342
343 mask &= s->io_bits;
344 if (mask & 0x0000ffff) { /* Port A */
345 writew((s->state & 0xffff),
346 dev_private->me_regbase + ME_DIO_PORT_A);
347 } else {
348 data[1] &= ~0x0000ffff;
349 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_A);
350 }
351
352 if (mask & 0xffff0000) { /* Port B */
353 writew(((s->state >> 16) & 0xffff),
354 dev_private->me_regbase + ME_DIO_PORT_B);
355 } else {
356 data[1] &= ~0xffff0000;
357 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_B) << 16;
358 }
359
360 return 2;
361 }
362
363 /*
364 * ------------------------------------------------------------------
365 *
366 * ANALOG INPUT SECTION
367 *
368 * ------------------------------------------------------------------
369 */
370
371 /* Analog instant input */
372 static int me_ai_insn_read(struct comedi_device *dev,
373 struct comedi_subdevice *subdevice,
374 struct comedi_insn *insn, unsigned int *data)
375 {
376 unsigned short value;
377 int chan = CR_CHAN((&insn->chanspec)[0]);
378 int rang = CR_RANGE((&insn->chanspec)[0]);
379 int aref = CR_AREF((&insn->chanspec)[0]);
380 int i;
381
382 /* stop any running conversion */
383 dev_private->control_1 &= 0xFFFC;
384 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
385
386 /* clear chanlist and ad fifo */
387 dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
388 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
389
390 /* reset any pending interrupt */
391 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
392
393 /* enable the chanlist and ADC fifo */
394 dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
395 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
396
397 /* write to channel list fifo */
398 /* b3:b0 are the channel number */
399 value = chan & 0x0f;
400 /* b5:b4 are the channel gain */
401 value |= (rang & 0x03) << 4;
402 /* b6 channel polarity */
403 value |= (rang & 0x04) << 4;
404 /* b7 single or differential */
405 value |= ((aref & AREF_DIFF) ? 0x80 : 0);
406 writew(value & 0xff, dev_private->me_regbase + ME_CHANNEL_LIST);
407
408 /* set ADC mode to software trigger */
409 dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
410 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
411
412 /* start conversion by reading from ADC_START */
413 readw(dev_private->me_regbase + ME_ADC_START);
414
415 /* wait for ADC fifo not empty flag */
416 for (i = 100000; i > 0; i--)
417 if (!(readw(dev_private->me_regbase + ME_STATUS) & 0x0004))
418 break;
419
420 /* get value from ADC fifo */
421 if (i) {
422 data[0] =
423 (readw(dev_private->me_regbase +
424 ME_READ_AD_FIFO) ^ 0x800) & 0x0FFF;
425 } else {
426 printk(KERN_ERR "comedi%d: Cannot get single value\n",
427 dev->minor);
428 return -EIO;
429 }
430
431 /* stop any running conversion */
432 dev_private->control_1 &= 0xFFFC;
433 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
434
435 return 1;
436 }
437
438 /*
439 * ------------------------------------------------------------------
440 *
441 * HARDWARE TRIGGERED ANALOG INPUT SECTION
442 *
443 * ------------------------------------------------------------------
444 */
445
446 /* Cancel analog input autoscan */
447 static int me_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
448 {
449 /* disable interrupts */
450
451 /* stop any running conversion */
452 dev_private->control_1 &= 0xFFFC;
453 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
454
455 return 0;
456 }
457
458 /* Test analog input command */
459 static int me_ai_do_cmd_test(struct comedi_device *dev,
460 struct comedi_subdevice *s, struct comedi_cmd *cmd)
461 {
462 return 0;
463 }
464
465 /* Analog input command */
466 static int me_ai_do_cmd(struct comedi_device *dev,
467 struct comedi_subdevice *subdevice)
468 {
469 return 0;
470 }
471
472 /*
473 * ------------------------------------------------------------------
474 *
475 * ANALOG OUTPUT SECTION
476 *
477 * ------------------------------------------------------------------
478 */
479
480 /* Analog instant output */
481 static int me_ao_insn_write(struct comedi_device *dev,
482 struct comedi_subdevice *s,
483 struct comedi_insn *insn, unsigned int *data)
484 {
485 int chan;
486 int rang;
487 int i;
488
489 /* Enable all DAC */
490 dev_private->control_2 |= ENABLE_DAC;
491 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
492
493 /* and set DAC to "buffered" mode */
494 dev_private->control_2 |= BUFFERED_DAC;
495 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
496
497 /* Set dac-control register */
498 for (i = 0; i < insn->n; i++) {
499 chan = CR_CHAN((&insn->chanspec)[i]);
500 rang = CR_RANGE((&insn->chanspec)[i]);
501
502 /* clear bits for this channel */
503 dev_private->dac_control &= ~(0x0880 >> chan);
504 if (rang == 0)
505 dev_private->dac_control |=
506 ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
507 else if (rang == 1)
508 dev_private->dac_control |=
509 ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
510 }
511 writew(dev_private->dac_control,
512 dev_private->me_regbase + ME_DAC_CONTROL);
513
514 /* Update dac-control register */
515 readw(dev_private->me_regbase + ME_DAC_CONTROL_UPDATE);
516
517 /* Set data register */
518 for (i = 0; i < insn->n; i++) {
519 chan = CR_CHAN((&insn->chanspec)[i]);
520 writew((data[0] & s->maxdata),
521 dev_private->me_regbase + ME_DAC_DATA_A + (chan << 1));
522 dev_private->ao_readback[chan] = (data[0] & s->maxdata);
523 }
524
525 /* Update dac with data registers */
526 readw(dev_private->me_regbase + ME_DAC_UPDATE);
527
528 return i;
529 }
530
531 /* Analog output readback */
532 static int me_ao_insn_read(struct comedi_device *dev,
533 struct comedi_subdevice *s, struct comedi_insn *insn,
534 unsigned int *data)
535 {
536 int i;
537
538 for (i = 0; i < insn->n; i++) {
539 data[i] =
540 dev_private->ao_readback[CR_CHAN((&insn->chanspec)[i])];
541 }
542
543 return 1;
544 }
545
546 /*
547 * ------------------------------------------------------------------
548 *
549 * INITIALISATION SECTION
550 *
551 * ------------------------------------------------------------------
552 */
553
554 /* Xilinx firmware download for card: ME-2600i */
555 static int me2600_xilinx_download(struct comedi_device *dev,
556 unsigned char *me2600_firmware,
557 unsigned int length)
558 {
559 unsigned int value;
560 unsigned int file_length;
561 unsigned int i;
562
563 /* disable irq's on PLX */
564 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
565
566 /* First, make a dummy read to reset xilinx */
567 value = readw(dev_private->me_regbase + XILINX_DOWNLOAD_RESET);
568
569 /* Wait until reset is over */
570 sleep(1);
571
572 /* Write a dummy value to Xilinx */
573 writeb(0x00, dev_private->me_regbase + 0x0);
574 sleep(1);
575
576 /*
577 * Format of the firmware
578 * Build longs from the byte-wise coded header
579 * Byte 1-3: length of the array
580 * Byte 4-7: version
581 * Byte 8-11: date
582 * Byte 12-15: reserved
583 */
584 if (length < 16)
585 return -EINVAL;
586 file_length = (((unsigned int)me2600_firmware[0] & 0xff) << 24) +
587 (((unsigned int)me2600_firmware[1] & 0xff) << 16) +
588 (((unsigned int)me2600_firmware[2] & 0xff) << 8) +
589 ((unsigned int)me2600_firmware[3] & 0xff);
590
591 /*
592 * Loop for writing firmware byte by byte to xilinx
593 * Firmware data start at offfset 16
594 */
595 for (i = 0; i < file_length; i++)
596 writeb((me2600_firmware[16 + i] & 0xff),
597 dev_private->me_regbase + 0x0);
598
599 /* Write 5 dummy values to xilinx */
600 for (i = 0; i < 5; i++)
601 writeb(0x00, dev_private->me_regbase + 0x0);
602
603 /* Test if there was an error during download -> INTB was thrown */
604 value = readl(dev_private->plx_regbase + PLX_INTCSR);
605 if (value & 0x20) {
606 /* Disable interrupt */
607 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
608 printk(KERN_ERR "comedi%d: Xilinx download failed\n",
609 dev->minor);
610 return -EIO;
611 }
612
613 /* Wait until the Xilinx is ready for real work */
614 sleep(1);
615
616 /* Enable PLX-Interrupts */
617 writel(0x43, dev_private->plx_regbase + PLX_INTCSR);
618
619 return 0;
620 }
621
622 /* Reset device */
623 static int me_reset(struct comedi_device *dev)
624 {
625 /* Reset board */
626 writew(0x00, dev_private->me_regbase + ME_CONTROL_1);
627 writew(0x00, dev_private->me_regbase + ME_CONTROL_2);
628 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
629 writew(0x00, dev_private->me_regbase + ME_DAC_CONTROL);
630
631 /* Save values in the board context */
632 dev_private->dac_control = 0;
633 dev_private->control_1 = 0;
634 dev_private->control_2 = 0;
635
636 return 0;
637 }
638
639 /*
640 * Attach
641 *
642 * - Register PCI device
643 * - Declare device driver capability
644 */
645 static int me_attach(struct comedi_device *dev, struct comedi_devconfig *it)
646 {
647 struct pci_dev *pci_device;
648 struct comedi_subdevice *subdevice;
649 struct me_board *board;
650 resource_size_t plx_regbase_tmp;
651 unsigned long plx_regbase_size_tmp;
652 resource_size_t me_regbase_tmp;
653 unsigned long me_regbase_size_tmp;
654 resource_size_t swap_regbase_tmp;
655 unsigned long swap_regbase_size_tmp;
656 resource_size_t regbase_tmp;
657 int result, error, i;
658
659 /* Allocate private memory */
660 if (alloc_private(dev, sizeof(struct me_private_data)) < 0)
661 return -ENOMEM;
662
663 /* Probe the device to determine what device in the series it is. */
664 for (pci_device = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL);
665 pci_device != NULL;
666 pci_device = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pci_device)) {
667 if (pci_device->vendor == PCI_VENDOR_ID_MEILHAUS) {
668 for (i = 0; i < me_board_nbr; i++) {
669 if (me_boards[i].device_id ==
670 pci_device->device) {
671 /*
672 * was a particular bus/slot requested?
673 */
674 if ((it->options[0] != 0)
675 || (it->options[1] != 0)) {
676 /*
677 * are we on the wrong bus/slot?
678 */
679 if (pci_device->bus->number !=
680 it->options[0]
681 ||
682 PCI_SLOT(pci_device->devfn)
683 != it->options[1]) {
684 continue;
685 }
686 }
687
688 dev->board_ptr = me_boards + i;
689 board =
690 (struct me_board *)dev->board_ptr;
691 dev_private->pci_device = pci_device;
692 goto found;
693 }
694 }
695 }
696 }
697
698 printk(KERN_ERR
699 "comedi%d: no supported board found! (req. bus/slot : %d/%d)\n",
700 dev->minor, it->options[0], it->options[1]);
701 return -EIO;
702
703 found:
704 printk(KERN_INFO "comedi%d: found %s at PCI bus %d, slot %d\n",
705 dev->minor, me_boards[i].name,
706 pci_device->bus->number, PCI_SLOT(pci_device->devfn));
707
708 /* Enable PCI device and request PCI regions */
709 if (comedi_pci_enable(pci_device, ME_DRIVER_NAME) < 0) {
710 printk(KERN_ERR "comedi%d: Failed to enable PCI device and "
711 "request regions\n", dev->minor);
712 return -EIO;
713 }
714
715 /* Set data in device structure */
716 dev->board_name = board->name;
717
718 /* Read PLX register base address [PCI_BASE_ADDRESS #0]. */
719 plx_regbase_tmp = pci_resource_start(pci_device, 0);
720 plx_regbase_size_tmp = pci_resource_len(pci_device, 0);
721 dev_private->plx_regbase =
722 ioremap(plx_regbase_tmp, plx_regbase_size_tmp);
723 dev_private->plx_regbase_size = plx_regbase_size_tmp;
724 if (!dev_private->plx_regbase) {
725 printk("comedi%d: Failed to remap I/O memory\n", dev->minor);
726 return -ENOMEM;
727 }
728
729 /* Read Swap base address [PCI_BASE_ADDRESS #5]. */
730
731 swap_regbase_tmp = pci_resource_start(pci_device, 5);
732 swap_regbase_size_tmp = pci_resource_len(pci_device, 5);
733
734 if (!swap_regbase_tmp)
735 printk(KERN_ERR "comedi%d: Swap not present\n", dev->minor);
736
737 /*---------------------------------------------- Workaround start ---*/
738 if (plx_regbase_tmp & 0x0080) {
739 printk(KERN_ERR "comedi%d: PLX-Bug detected\n", dev->minor);
740
741 if (swap_regbase_tmp) {
742 regbase_tmp = plx_regbase_tmp;
743 plx_regbase_tmp = swap_regbase_tmp;
744 swap_regbase_tmp = regbase_tmp;
745
746 result = pci_write_config_dword(pci_device,
747 PCI_BASE_ADDRESS_0,
748 plx_regbase_tmp);
749 if (result != PCIBIOS_SUCCESSFUL)
750 return -EIO;
751
752 result = pci_write_config_dword(pci_device,
753 PCI_BASE_ADDRESS_5,
754 swap_regbase_tmp);
755 if (result != PCIBIOS_SUCCESSFUL)
756 return -EIO;
757 } else {
758 plx_regbase_tmp -= 0x80;
759 result = pci_write_config_dword(pci_device,
760 PCI_BASE_ADDRESS_0,
761 plx_regbase_tmp);
762 if (result != PCIBIOS_SUCCESSFUL)
763 return -EIO;
764 }
765 }
766 /*--------------------------------------------- Workaround end -----*/
767
768 /* Read Meilhaus register base address [PCI_BASE_ADDRESS #2]. */
769
770 me_regbase_tmp = pci_resource_start(pci_device, 2);
771 me_regbase_size_tmp = pci_resource_len(pci_device, 2);
772 dev_private->me_regbase_size = me_regbase_size_tmp;
773 dev_private->me_regbase = ioremap(me_regbase_tmp, me_regbase_size_tmp);
774 if (!dev_private->me_regbase) {
775 printk(KERN_ERR "comedi%d: Failed to remap I/O memory\n",
776 dev->minor);
777 return -ENOMEM;
778 }
779 /* Download firmware and reset card */
780 if (board->device_id == ME2600_DEVICE_ID) {
781 unsigned char *aux_data;
782 int aux_len;
783
784 aux_data = comedi_aux_data(it->options, 0);
785 aux_len = it->options[COMEDI_DEVCONF_AUX_DATA_LENGTH];
786
787 if (!aux_data || aux_len < 1) {
788 comedi_error(dev, "You must provide me2600 firmware "
789 "using the --init-data option of "
790 "comedi_config");
791 return -EINVAL;
792 }
793 me2600_xilinx_download(dev, aux_data, aux_len);
794 }
795
796 me_reset(dev);
797
798 /* device driver capabilities */
799 error = alloc_subdevices(dev, 3);
800 if (error < 0)
801 return error;
802
803 subdevice = dev->subdevices + 0;
804 subdevice->type = COMEDI_SUBD_AI;
805 subdevice->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_CMD_READ;
806 subdevice->n_chan = board->ai_channel_nbr;
807 subdevice->maxdata = board->ai_resolution_mask;
808 subdevice->len_chanlist = board->ai_channel_nbr;
809 subdevice->range_table = board->ai_range_list;
810 subdevice->cancel = me_ai_cancel;
811 subdevice->insn_read = me_ai_insn_read;
812 subdevice->do_cmdtest = me_ai_do_cmd_test;
813 subdevice->do_cmd = me_ai_do_cmd;
814
815 subdevice = dev->subdevices + 1;
816 subdevice->type = COMEDI_SUBD_AO;
817 subdevice->subdev_flags = SDF_WRITEABLE | SDF_COMMON;
818 subdevice->n_chan = board->ao_channel_nbr;
819 subdevice->maxdata = board->ao_resolution_mask;
820 subdevice->len_chanlist = board->ao_channel_nbr;
821 subdevice->range_table = board->ao_range_list;
822 subdevice->insn_read = me_ao_insn_read;
823 subdevice->insn_write = me_ao_insn_write;
824
825 subdevice = dev->subdevices + 2;
826 subdevice->type = COMEDI_SUBD_DIO;
827 subdevice->subdev_flags = SDF_READABLE | SDF_WRITEABLE;
828 subdevice->n_chan = board->dio_channel_nbr;
829 subdevice->maxdata = 1;
830 subdevice->len_chanlist = board->dio_channel_nbr;
831 subdevice->range_table = &range_digital;
832 subdevice->insn_bits = me_dio_insn_bits;
833 subdevice->insn_config = me_dio_insn_config;
834 subdevice->io_bits = 0;
835
836 printk(KERN_INFO "comedi%d: " ME_DRIVER_NAME " attached.\n",
837 dev->minor);
838 return 0;
839 }
840
841 /* Detach */
842 static int me_detach(struct comedi_device *dev)
843 {
844 if (dev_private) {
845 if (dev_private->me_regbase) {
846 me_reset(dev);
847 iounmap(dev_private->me_regbase);
848 }
849 if (dev_private->plx_regbase)
850 iounmap(dev_private->plx_regbase);
851 if (dev_private->pci_device) {
852 if (dev_private->plx_regbase_size)
853 comedi_pci_disable(dev_private->pci_device);
854
855 pci_dev_put(dev_private->pci_device);
856 }
857 }
858 return 0;
859 }
860
861 MODULE_AUTHOR("Comedi http://www.comedi.org");
862 MODULE_DESCRIPTION("Comedi low-level driver");
863 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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