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staging: comedi: remove inline alloc_private()
[deliverable/linux.git] / drivers / staging / comedi / drivers / me_daq.c
1 /*
2
3 comedi/drivers/me_daq.c
4
5 Hardware driver for Meilhaus data acquisition cards:
6
7 ME-2000i, ME-2600i, ME-3000vm1
8
9 Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 /*
27 Driver: me_daq
28 Description: Meilhaus PCI data acquisition cards
29 Author: Michael Hillmann <hillmann@syscongroup.de>
30 Devices: [Meilhaus] ME-2600i (me_daq), ME-2000i
31 Status: experimental
32
33 Supports:
34
35 Analog Output
36
37 Configuration options:
38
39 [0] - PCI bus number (optional)
40 [1] - PCI slot number (optional)
41
42 If bus/slot is not specified, the first available PCI
43 device will be used.
44 */
45
46 #include <linux/interrupt.h>
47 #include <linux/sched.h>
48 #include <linux/firmware.h>
49 #include "../comedidev.h"
50
51 #define ME2600_FIRMWARE "me2600_firmware.bin"
52
53 #define PCI_VENDOR_ID_MEILHAUS 0x1402
54 #define ME2000_DEVICE_ID 0x2000
55 #define ME2600_DEVICE_ID 0x2600
56
57 #define PLX_INTCSR 0x4C /* PLX interrupt status register */
58 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
59
60 #define ME_CONTROL_1 0x0000 /* - | W */
61 #define INTERRUPT_ENABLE (1<<15)
62 #define COUNTER_B_IRQ (1<<12)
63 #define COUNTER_A_IRQ (1<<11)
64 #define CHANLIST_READY_IRQ (1<<10)
65 #define EXT_IRQ (1<<9)
66 #define ADFIFO_HALFFULL_IRQ (1<<8)
67 #define SCAN_COUNT_ENABLE (1<<5)
68 #define SIMULTANEOUS_ENABLE (1<<4)
69 #define TRIGGER_FALLING_EDGE (1<<3)
70 #define CONTINUOUS_MODE (1<<2)
71 #define DISABLE_ADC (0<<0)
72 #define SOFTWARE_TRIGGERED_ADC (1<<0)
73 #define SCAN_TRIGGERED_ADC (2<<0)
74 #define EXT_TRIGGERED_ADC (3<<0)
75 #define ME_ADC_START 0x0000 /* R | - */
76 #define ME_CONTROL_2 0x0002 /* - | W */
77 #define ENABLE_ADFIFO (1<<10)
78 #define ENABLE_CHANLIST (1<<9)
79 #define ENABLE_PORT_B (1<<7)
80 #define ENABLE_PORT_A (1<<6)
81 #define ENABLE_COUNTER_B (1<<4)
82 #define ENABLE_COUNTER_A (1<<3)
83 #define ENABLE_DAC (1<<1)
84 #define BUFFERED_DAC (1<<0)
85 #define ME_DAC_UPDATE 0x0002 /* R | - */
86 #define ME_STATUS 0x0004 /* R | - */
87 #define COUNTER_B_IRQ_PENDING (1<<12)
88 #define COUNTER_A_IRQ_PENDING (1<<11)
89 #define CHANLIST_READY_IRQ_PENDING (1<<10)
90 #define EXT_IRQ_PENDING (1<<9)
91 #define ADFIFO_HALFFULL_IRQ_PENDING (1<<8)
92 #define ADFIFO_FULL (1<<4)
93 #define ADFIFO_HALFFULL (1<<3)
94 #define ADFIFO_EMPTY (1<<2)
95 #define CHANLIST_FULL (1<<1)
96 #define FST_ACTIVE (1<<0)
97 #define ME_RESET_INTERRUPT 0x0004 /* - | W */
98 #define ME_DIO_PORT_A 0x0006 /* R | W */
99 #define ME_DIO_PORT_B 0x0008 /* R | W */
100 #define ME_TIMER_DATA_0 0x000A /* - | W */
101 #define ME_TIMER_DATA_1 0x000C /* - | W */
102 #define ME_TIMER_DATA_2 0x000E /* - | W */
103 #define ME_CHANNEL_LIST 0x0010 /* - | W */
104 #define ADC_UNIPOLAR (1<<6)
105 #define ADC_GAIN_0 (0<<4)
106 #define ADC_GAIN_1 (1<<4)
107 #define ADC_GAIN_2 (2<<4)
108 #define ADC_GAIN_3 (3<<4)
109 #define ME_READ_AD_FIFO 0x0010 /* R | - */
110 #define ME_DAC_CONTROL 0x0012 /* - | W */
111 #define DAC_UNIPOLAR_D (0<<4)
112 #define DAC_BIPOLAR_D (1<<4)
113 #define DAC_UNIPOLAR_C (0<<5)
114 #define DAC_BIPOLAR_C (1<<5)
115 #define DAC_UNIPOLAR_B (0<<6)
116 #define DAC_BIPOLAR_B (1<<6)
117 #define DAC_UNIPOLAR_A (0<<7)
118 #define DAC_BIPOLAR_A (1<<7)
119 #define DAC_GAIN_0_D (0<<8)
120 #define DAC_GAIN_1_D (1<<8)
121 #define DAC_GAIN_0_C (0<<9)
122 #define DAC_GAIN_1_C (1<<9)
123 #define DAC_GAIN_0_B (0<<10)
124 #define DAC_GAIN_1_B (1<<10)
125 #define DAC_GAIN_0_A (0<<11)
126 #define DAC_GAIN_1_A (1<<11)
127 #define ME_DAC_CONTROL_UPDATE 0x0012 /* R | - */
128 #define ME_DAC_DATA_A 0x0014 /* - | W */
129 #define ME_DAC_DATA_B 0x0016 /* - | W */
130 #define ME_DAC_DATA_C 0x0018 /* - | W */
131 #define ME_DAC_DATA_D 0x001A /* - | W */
132 #define ME_COUNTER_ENDDATA_A 0x001C /* - | W */
133 #define ME_COUNTER_ENDDATA_B 0x001E /* - | W */
134 #define ME_COUNTER_STARTDATA_A 0x0020 /* - | W */
135 #define ME_COUNTER_VALUE_A 0x0020 /* R | - */
136 #define ME_COUNTER_STARTDATA_B 0x0022 /* - | W */
137 #define ME_COUNTER_VALUE_B 0x0022 /* R | - */
138
139 static const struct comedi_lrange me2000_ai_range = {
140 8,
141 {
142 BIP_RANGE(10),
143 BIP_RANGE(5),
144 BIP_RANGE(2.5),
145 BIP_RANGE(1.25),
146 UNI_RANGE(10),
147 UNI_RANGE(5),
148 UNI_RANGE(2.5),
149 UNI_RANGE(1.25)
150 }
151 };
152
153 static const struct comedi_lrange me2600_ai_range = {
154 8,
155 {
156 BIP_RANGE(10),
157 BIP_RANGE(5),
158 BIP_RANGE(2.5),
159 BIP_RANGE(1.25),
160 UNI_RANGE(10),
161 UNI_RANGE(5),
162 UNI_RANGE(2.5),
163 UNI_RANGE(1.25)
164 }
165 };
166
167 static const struct comedi_lrange me2600_ao_range = {
168 3,
169 {
170 BIP_RANGE(10),
171 BIP_RANGE(5),
172 UNI_RANGE(10)
173 }
174 };
175
176 /* Board specification structure */
177 struct me_board {
178 const char *name; /* driver name */
179 int device_id;
180 int ao_channel_nbr; /* DA config */
181 int ao_resolution;
182 int ao_resolution_mask;
183 const struct comedi_lrange *ao_range_list;
184 int ai_channel_nbr; /* AD config */
185 int ai_resolution;
186 int ai_resolution_mask;
187 const struct comedi_lrange *ai_range_list;
188 int dio_channel_nbr; /* DIO config */
189 };
190
191 static const struct me_board me_boards[] = {
192 {
193 .name = "me-2600i",
194 .device_id = ME2600_DEVICE_ID,
195 /* Analog Output */
196 .ao_channel_nbr = 4,
197 .ao_resolution = 12,
198 .ao_resolution_mask = 0x0fff,
199 .ao_range_list = &me2600_ao_range,
200 .ai_channel_nbr = 16,
201 /* Analog Input */
202 .ai_resolution = 12,
203 .ai_resolution_mask = 0x0fff,
204 .ai_range_list = &me2600_ai_range,
205 .dio_channel_nbr = 32,
206 },
207 {
208 .name = "me-2000i",
209 .device_id = ME2000_DEVICE_ID,
210 /* Analog Output */
211 .ao_channel_nbr = 0,
212 .ao_resolution = 0,
213 .ao_resolution_mask = 0,
214 .ao_range_list = NULL,
215 .ai_channel_nbr = 16,
216 /* Analog Input */
217 .ai_resolution = 12,
218 .ai_resolution_mask = 0x0fff,
219 .ai_range_list = &me2000_ai_range,
220 .dio_channel_nbr = 32,
221 }
222 };
223
224 /* Private data structure */
225 struct me_private_data {
226 void __iomem *plx_regbase; /* PLX configuration base address */
227 void __iomem *me_regbase; /* Base address of the Meilhaus card */
228 unsigned long plx_regbase_size; /* Size of PLX configuration space */
229 unsigned long me_regbase_size; /* Size of Meilhaus space */
230
231 unsigned short control_1; /* Mirror of CONTROL_1 register */
232 unsigned short control_2; /* Mirror of CONTROL_2 register */
233 unsigned short dac_control; /* Mirror of the DAC_CONTROL register */
234 int ao_readback[4]; /* Mirror of analog output data */
235 };
236
237 /*
238 * ------------------------------------------------------------------
239 *
240 * Helpful functions
241 *
242 * ------------------------------------------------------------------
243 */
244 static inline void sleep(unsigned sec)
245 {
246 current->state = TASK_INTERRUPTIBLE;
247 schedule_timeout(sec * HZ);
248 }
249
250 /*
251 * ------------------------------------------------------------------
252 *
253 * DIGITAL INPUT/OUTPUT SECTION
254 *
255 * ------------------------------------------------------------------
256 */
257 static int me_dio_insn_config(struct comedi_device *dev,
258 struct comedi_subdevice *s,
259 struct comedi_insn *insn, unsigned int *data)
260 {
261 struct me_private_data *dev_private = dev->private;
262 int bits;
263 int mask = 1 << CR_CHAN(insn->chanspec);
264
265 /* calculate port */
266 if (mask & 0x0000ffff) { /* Port A in use */
267 bits = 0x0000ffff;
268
269 /* Enable Port A */
270 dev_private->control_2 |= ENABLE_PORT_A;
271 writew(dev_private->control_2,
272 dev_private->me_regbase + ME_CONTROL_2);
273 } else { /* Port B in use */
274
275 bits = 0xffff0000;
276
277 /* Enable Port B */
278 dev_private->control_2 |= ENABLE_PORT_B;
279 writew(dev_private->control_2,
280 dev_private->me_regbase + ME_CONTROL_2);
281 }
282
283 if (data[0]) {
284 /* Config port as output */
285 s->io_bits |= bits;
286 } else {
287 /* Config port as input */
288 s->io_bits &= ~bits;
289 }
290
291 return 1;
292 }
293
294 /* Digital instant input/outputs */
295 static int me_dio_insn_bits(struct comedi_device *dev,
296 struct comedi_subdevice *s,
297 struct comedi_insn *insn, unsigned int *data)
298 {
299 struct me_private_data *dev_private = dev->private;
300 unsigned int mask = data[0];
301
302 s->state &= ~mask;
303 s->state |= (mask & data[1]);
304
305 mask &= s->io_bits;
306 if (mask & 0x0000ffff) { /* Port A */
307 writew((s->state & 0xffff),
308 dev_private->me_regbase + ME_DIO_PORT_A);
309 } else {
310 data[1] &= ~0x0000ffff;
311 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_A);
312 }
313
314 if (mask & 0xffff0000) { /* Port B */
315 writew(((s->state >> 16) & 0xffff),
316 dev_private->me_regbase + ME_DIO_PORT_B);
317 } else {
318 data[1] &= ~0xffff0000;
319 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_B) << 16;
320 }
321
322 return insn->n;
323 }
324
325 /*
326 * ------------------------------------------------------------------
327 *
328 * ANALOG INPUT SECTION
329 *
330 * ------------------------------------------------------------------
331 */
332
333 /* Analog instant input */
334 static int me_ai_insn_read(struct comedi_device *dev,
335 struct comedi_subdevice *s,
336 struct comedi_insn *insn, unsigned int *data)
337 {
338 struct me_private_data *dev_private = dev->private;
339 unsigned short value;
340 int chan = CR_CHAN((&insn->chanspec)[0]);
341 int rang = CR_RANGE((&insn->chanspec)[0]);
342 int aref = CR_AREF((&insn->chanspec)[0]);
343 int i;
344
345 /* stop any running conversion */
346 dev_private->control_1 &= 0xFFFC;
347 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
348
349 /* clear chanlist and ad fifo */
350 dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
351 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
352
353 /* reset any pending interrupt */
354 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
355
356 /* enable the chanlist and ADC fifo */
357 dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
358 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
359
360 /* write to channel list fifo */
361 /* b3:b0 are the channel number */
362 value = chan & 0x0f;
363 /* b5:b4 are the channel gain */
364 value |= (rang & 0x03) << 4;
365 /* b6 channel polarity */
366 value |= (rang & 0x04) << 4;
367 /* b7 single or differential */
368 value |= ((aref & AREF_DIFF) ? 0x80 : 0);
369 writew(value & 0xff, dev_private->me_regbase + ME_CHANNEL_LIST);
370
371 /* set ADC mode to software trigger */
372 dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
373 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
374
375 /* start conversion by reading from ADC_START */
376 readw(dev_private->me_regbase + ME_ADC_START);
377
378 /* wait for ADC fifo not empty flag */
379 for (i = 100000; i > 0; i--)
380 if (!(readw(dev_private->me_regbase + ME_STATUS) & 0x0004))
381 break;
382
383 /* get value from ADC fifo */
384 if (i) {
385 data[0] =
386 (readw(dev_private->me_regbase +
387 ME_READ_AD_FIFO) ^ 0x800) & 0x0FFF;
388 } else {
389 dev_err(dev->class_dev, "Cannot get single value\n");
390 return -EIO;
391 }
392
393 /* stop any running conversion */
394 dev_private->control_1 &= 0xFFFC;
395 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
396
397 return 1;
398 }
399
400 /*
401 * ------------------------------------------------------------------
402 *
403 * HARDWARE TRIGGERED ANALOG INPUT SECTION
404 *
405 * ------------------------------------------------------------------
406 */
407
408 /* Cancel analog input autoscan */
409 static int me_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
410 {
411 struct me_private_data *dev_private = dev->private;
412
413 /* disable interrupts */
414
415 /* stop any running conversion */
416 dev_private->control_1 &= 0xFFFC;
417 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
418
419 return 0;
420 }
421
422 /* Test analog input command */
423 static int me_ai_do_cmd_test(struct comedi_device *dev,
424 struct comedi_subdevice *s, struct comedi_cmd *cmd)
425 {
426 return 0;
427 }
428
429 /* Analog input command */
430 static int me_ai_do_cmd(struct comedi_device *dev,
431 struct comedi_subdevice *s)
432 {
433 return 0;
434 }
435
436 /*
437 * ------------------------------------------------------------------
438 *
439 * ANALOG OUTPUT SECTION
440 *
441 * ------------------------------------------------------------------
442 */
443
444 /* Analog instant output */
445 static int me_ao_insn_write(struct comedi_device *dev,
446 struct comedi_subdevice *s,
447 struct comedi_insn *insn, unsigned int *data)
448 {
449 struct me_private_data *dev_private = dev->private;
450 int chan;
451 int rang;
452 int i;
453
454 /* Enable all DAC */
455 dev_private->control_2 |= ENABLE_DAC;
456 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
457
458 /* and set DAC to "buffered" mode */
459 dev_private->control_2 |= BUFFERED_DAC;
460 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
461
462 /* Set dac-control register */
463 for (i = 0; i < insn->n; i++) {
464 chan = CR_CHAN((&insn->chanspec)[i]);
465 rang = CR_RANGE((&insn->chanspec)[i]);
466
467 /* clear bits for this channel */
468 dev_private->dac_control &= ~(0x0880 >> chan);
469 if (rang == 0)
470 dev_private->dac_control |=
471 ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
472 else if (rang == 1)
473 dev_private->dac_control |=
474 ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
475 }
476 writew(dev_private->dac_control,
477 dev_private->me_regbase + ME_DAC_CONTROL);
478
479 /* Update dac-control register */
480 readw(dev_private->me_regbase + ME_DAC_CONTROL_UPDATE);
481
482 /* Set data register */
483 for (i = 0; i < insn->n; i++) {
484 chan = CR_CHAN((&insn->chanspec)[i]);
485 writew((data[0] & s->maxdata),
486 dev_private->me_regbase + ME_DAC_DATA_A + (chan << 1));
487 dev_private->ao_readback[chan] = (data[0] & s->maxdata);
488 }
489
490 /* Update dac with data registers */
491 readw(dev_private->me_regbase + ME_DAC_UPDATE);
492
493 return i;
494 }
495
496 /* Analog output readback */
497 static int me_ao_insn_read(struct comedi_device *dev,
498 struct comedi_subdevice *s, struct comedi_insn *insn,
499 unsigned int *data)
500 {
501 struct me_private_data *dev_private = dev->private;
502 int i;
503
504 for (i = 0; i < insn->n; i++) {
505 data[i] =
506 dev_private->ao_readback[CR_CHAN((&insn->chanspec)[i])];
507 }
508
509 return 1;
510 }
511
512 /*
513 * ------------------------------------------------------------------
514 *
515 * INITIALISATION SECTION
516 *
517 * ------------------------------------------------------------------
518 */
519
520 /* Xilinx firmware download for card: ME-2600i */
521 static int me2600_xilinx_download(struct comedi_device *dev,
522 const u8 *data, size_t size)
523 {
524 struct me_private_data *dev_private = dev->private;
525 unsigned int value;
526 unsigned int file_length;
527 unsigned int i;
528
529 /* disable irq's on PLX */
530 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
531
532 /* First, make a dummy read to reset xilinx */
533 value = readw(dev_private->me_regbase + XILINX_DOWNLOAD_RESET);
534
535 /* Wait until reset is over */
536 sleep(1);
537
538 /* Write a dummy value to Xilinx */
539 writeb(0x00, dev_private->me_regbase + 0x0);
540 sleep(1);
541
542 /*
543 * Format of the firmware
544 * Build longs from the byte-wise coded header
545 * Byte 1-3: length of the array
546 * Byte 4-7: version
547 * Byte 8-11: date
548 * Byte 12-15: reserved
549 */
550 if (size < 16)
551 return -EINVAL;
552
553 file_length = (((unsigned int)data[0] & 0xff) << 24) +
554 (((unsigned int)data[1] & 0xff) << 16) +
555 (((unsigned int)data[2] & 0xff) << 8) +
556 ((unsigned int)data[3] & 0xff);
557
558 /*
559 * Loop for writing firmware byte by byte to xilinx
560 * Firmware data start at offfset 16
561 */
562 for (i = 0; i < file_length; i++)
563 writeb((data[16 + i] & 0xff),
564 dev_private->me_regbase + 0x0);
565
566 /* Write 5 dummy values to xilinx */
567 for (i = 0; i < 5; i++)
568 writeb(0x00, dev_private->me_regbase + 0x0);
569
570 /* Test if there was an error during download -> INTB was thrown */
571 value = readl(dev_private->plx_regbase + PLX_INTCSR);
572 if (value & 0x20) {
573 /* Disable interrupt */
574 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
575 dev_err(dev->class_dev, "Xilinx download failed\n");
576 return -EIO;
577 }
578
579 /* Wait until the Xilinx is ready for real work */
580 sleep(1);
581
582 /* Enable PLX-Interrupts */
583 writel(0x43, dev_private->plx_regbase + PLX_INTCSR);
584
585 return 0;
586 }
587
588 static int me2600_upload_firmware(struct comedi_device *dev)
589 {
590 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
591 const struct firmware *fw;
592 int ret;
593
594 ret = request_firmware(&fw, ME2600_FIRMWARE, &pcidev->dev);
595 if (ret)
596 return ret;
597
598 ret = me2600_xilinx_download(dev, fw->data, fw->size);
599 release_firmware(fw);
600
601 return ret;
602 }
603
604 /* Reset device */
605 static int me_reset(struct comedi_device *dev)
606 {
607 struct me_private_data *dev_private = dev->private;
608
609 /* Reset board */
610 writew(0x00, dev_private->me_regbase + ME_CONTROL_1);
611 writew(0x00, dev_private->me_regbase + ME_CONTROL_2);
612 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
613 writew(0x00, dev_private->me_regbase + ME_DAC_CONTROL);
614
615 /* Save values in the board context */
616 dev_private->dac_control = 0;
617 dev_private->control_1 = 0;
618 dev_private->control_2 = 0;
619
620 return 0;
621 }
622
623 static const void *me_find_boardinfo(struct comedi_device *dev,
624 struct pci_dev *pcidev)
625 {
626 const struct me_board *board;
627 int i;
628
629 for (i = 0; i < ARRAY_SIZE(me_boards); i++) {
630 board = &me_boards[i];
631 if (board->device_id == pcidev->device)
632 return board;
633 }
634 return NULL;
635 }
636
637 static int me_attach_pci(struct comedi_device *dev, struct pci_dev *pcidev)
638 {
639 const struct me_board *board;
640 struct me_private_data *dev_private;
641 struct comedi_subdevice *s;
642 resource_size_t plx_regbase_tmp;
643 unsigned long plx_regbase_size_tmp;
644 resource_size_t me_regbase_tmp;
645 unsigned long me_regbase_size_tmp;
646 resource_size_t swap_regbase_tmp;
647 unsigned long swap_regbase_size_tmp;
648 resource_size_t regbase_tmp;
649 int result, error;
650
651 comedi_set_hw_dev(dev, &pcidev->dev);
652
653 board = me_find_boardinfo(dev, pcidev);
654 if (!board)
655 return -ENODEV;
656 dev->board_ptr = board;
657 dev->board_name = board->name;
658
659 dev_private = kzalloc(sizeof(*dev_private), GFP_KERNEL);
660 if (!dev_private)
661 return -ENOMEM;
662 dev->private = dev_private;
663
664 /* Enable PCI device and request PCI regions */
665 if (comedi_pci_enable(pcidev, dev->board_name) < 0) {
666 dev_err(dev->class_dev,
667 "Failed to enable PCI device and request regions\n");
668 return -EIO;
669 }
670
671 /* Read PLX register base address [PCI_BASE_ADDRESS #0]. */
672 plx_regbase_tmp = pci_resource_start(pcidev, 0);
673 plx_regbase_size_tmp = pci_resource_len(pcidev, 0);
674 dev_private->plx_regbase =
675 ioremap(plx_regbase_tmp, plx_regbase_size_tmp);
676 dev_private->plx_regbase_size = plx_regbase_size_tmp;
677 if (!dev_private->plx_regbase) {
678 dev_err(dev->class_dev, "Failed to remap I/O memory\n");
679 return -ENOMEM;
680 }
681
682 /* Read Swap base address [PCI_BASE_ADDRESS #5]. */
683
684 swap_regbase_tmp = pci_resource_start(pcidev, 5);
685 swap_regbase_size_tmp = pci_resource_len(pcidev, 5);
686
687 if (!swap_regbase_tmp)
688 dev_err(dev->class_dev, "Swap not present\n");
689
690 /*---------------------------------------------- Workaround start ---*/
691 if (plx_regbase_tmp & 0x0080) {
692 dev_err(dev->class_dev, "PLX-Bug detected\n");
693
694 if (swap_regbase_tmp) {
695 regbase_tmp = plx_regbase_tmp;
696 plx_regbase_tmp = swap_regbase_tmp;
697 swap_regbase_tmp = regbase_tmp;
698
699 result = pci_write_config_dword(pcidev,
700 PCI_BASE_ADDRESS_0,
701 plx_regbase_tmp);
702 if (result != PCIBIOS_SUCCESSFUL)
703 return -EIO;
704
705 result = pci_write_config_dword(pcidev,
706 PCI_BASE_ADDRESS_5,
707 swap_regbase_tmp);
708 if (result != PCIBIOS_SUCCESSFUL)
709 return -EIO;
710 } else {
711 plx_regbase_tmp -= 0x80;
712 result = pci_write_config_dword(pcidev,
713 PCI_BASE_ADDRESS_0,
714 plx_regbase_tmp);
715 if (result != PCIBIOS_SUCCESSFUL)
716 return -EIO;
717 }
718 }
719 /*--------------------------------------------- Workaround end -----*/
720
721 /* Read Meilhaus register base address [PCI_BASE_ADDRESS #2]. */
722
723 me_regbase_tmp = pci_resource_start(pcidev, 2);
724 me_regbase_size_tmp = pci_resource_len(pcidev, 2);
725 dev_private->me_regbase_size = me_regbase_size_tmp;
726 dev_private->me_regbase = ioremap(me_regbase_tmp, me_regbase_size_tmp);
727 if (!dev_private->me_regbase) {
728 dev_err(dev->class_dev, "Failed to remap I/O memory\n");
729 return -ENOMEM;
730 }
731
732 /* Download firmware and reset card */
733 if (board->device_id == ME2600_DEVICE_ID) {
734 result = me2600_upload_firmware(dev);
735 if (result < 0)
736 return result;
737 }
738 me_reset(dev);
739
740 error = comedi_alloc_subdevices(dev, 3);
741 if (error)
742 return error;
743
744 s = &dev->subdevices[0];
745 s->type = COMEDI_SUBD_AI;
746 s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_CMD_READ;
747 s->n_chan = board->ai_channel_nbr;
748 s->maxdata = board->ai_resolution_mask;
749 s->len_chanlist = board->ai_channel_nbr;
750 s->range_table = board->ai_range_list;
751 s->cancel = me_ai_cancel;
752 s->insn_read = me_ai_insn_read;
753 s->do_cmdtest = me_ai_do_cmd_test;
754 s->do_cmd = me_ai_do_cmd;
755
756 s = &dev->subdevices[1];
757 s->type = COMEDI_SUBD_AO;
758 s->subdev_flags = SDF_WRITEABLE | SDF_COMMON;
759 s->n_chan = board->ao_channel_nbr;
760 s->maxdata = board->ao_resolution_mask;
761 s->len_chanlist = board->ao_channel_nbr;
762 s->range_table = board->ao_range_list;
763 s->insn_read = me_ao_insn_read;
764 s->insn_write = me_ao_insn_write;
765
766 s = &dev->subdevices[2];
767 s->type = COMEDI_SUBD_DIO;
768 s->subdev_flags = SDF_READABLE | SDF_WRITEABLE;
769 s->n_chan = board->dio_channel_nbr;
770 s->maxdata = 1;
771 s->len_chanlist = board->dio_channel_nbr;
772 s->range_table = &range_digital;
773 s->insn_bits = me_dio_insn_bits;
774 s->insn_config = me_dio_insn_config;
775 s->io_bits = 0;
776
777 dev_info(dev->class_dev, "%s: %s attached\n",
778 dev->driver->driver_name, dev->board_name);
779
780 return 0;
781 }
782
783 static void me_detach(struct comedi_device *dev)
784 {
785 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
786 struct me_private_data *dev_private = dev->private;
787
788 if (dev_private) {
789 if (dev_private->me_regbase) {
790 me_reset(dev);
791 iounmap(dev_private->me_regbase);
792 }
793 if (dev_private->plx_regbase)
794 iounmap(dev_private->plx_regbase);
795 }
796 if (pcidev) {
797 if (dev_private->plx_regbase_size)
798 comedi_pci_disable(pcidev);
799 pci_dev_put(pcidev);
800 }
801 }
802
803 static struct comedi_driver me_daq_driver = {
804 .driver_name = "me_daq",
805 .module = THIS_MODULE,
806 .attach_pci = me_attach_pci,
807 .detach = me_detach,
808 };
809
810 static int __devinit me_daq_pci_probe(struct pci_dev *dev,
811 const struct pci_device_id *ent)
812 {
813 return comedi_pci_auto_config(dev, &me_daq_driver);
814 }
815
816 static void __devexit me_daq_pci_remove(struct pci_dev *dev)
817 {
818 comedi_pci_auto_unconfig(dev);
819 }
820
821 static DEFINE_PCI_DEVICE_TABLE(me_daq_pci_table) = {
822 { PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, ME2600_DEVICE_ID) },
823 { PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, ME2000_DEVICE_ID) },
824 { 0 }
825 };
826 MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
827
828 static struct pci_driver me_daq_pci_driver = {
829 .name = "me_daq",
830 .id_table = me_daq_pci_table,
831 .probe = me_daq_pci_probe,
832 .remove = __devexit_p(me_daq_pci_remove),
833 };
834 module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
835
836 MODULE_AUTHOR("Comedi http://www.comedi.org");
837 MODULE_DESCRIPTION("Comedi low-level driver");
838 MODULE_LICENSE("GPL");
839 MODULE_FIRMWARE(ME2600_FIRMWARE);
Linux kernel - Deliverables
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