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Merge branch 'for-v3.7' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping
[deliverable/linux.git] / drivers / staging / comedi / drivers / me_daq.c
1 /*
2
3 comedi/drivers/me_daq.c
4
5 Hardware driver for Meilhaus data acquisition cards:
6
7 ME-2000i, ME-2600i, ME-3000vm1
8
9 Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 /*
27 Driver: me_daq
28 Description: Meilhaus PCI data acquisition cards
29 Author: Michael Hillmann <hillmann@syscongroup.de>
30 Devices: [Meilhaus] ME-2600i (me_daq), ME-2000i
31 Status: experimental
32
33 Supports:
34
35 Analog Output
36
37 Configuration options:
38
39 [0] - PCI bus number (optional)
40 [1] - PCI slot number (optional)
41
42 If bus/slot is not specified, the first available PCI
43 device will be used.
44 */
45
46 #include <linux/interrupt.h>
47 #include <linux/sched.h>
48 #include <linux/firmware.h>
49 #include "../comedidev.h"
50
51 #define ME2600_FIRMWARE "me2600_firmware.bin"
52
53 #define PCI_VENDOR_ID_MEILHAUS 0x1402
54 #define ME2000_DEVICE_ID 0x2000
55 #define ME2600_DEVICE_ID 0x2600
56
57 #define PLX_INTCSR 0x4C /* PLX interrupt status register */
58 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
59
60 #define ME_CONTROL_1 0x0000 /* - | W */
61 #define INTERRUPT_ENABLE (1<<15)
62 #define COUNTER_B_IRQ (1<<12)
63 #define COUNTER_A_IRQ (1<<11)
64 #define CHANLIST_READY_IRQ (1<<10)
65 #define EXT_IRQ (1<<9)
66 #define ADFIFO_HALFFULL_IRQ (1<<8)
67 #define SCAN_COUNT_ENABLE (1<<5)
68 #define SIMULTANEOUS_ENABLE (1<<4)
69 #define TRIGGER_FALLING_EDGE (1<<3)
70 #define CONTINUOUS_MODE (1<<2)
71 #define DISABLE_ADC (0<<0)
72 #define SOFTWARE_TRIGGERED_ADC (1<<0)
73 #define SCAN_TRIGGERED_ADC (2<<0)
74 #define EXT_TRIGGERED_ADC (3<<0)
75 #define ME_ADC_START 0x0000 /* R | - */
76 #define ME_CONTROL_2 0x0002 /* - | W */
77 #define ENABLE_ADFIFO (1<<10)
78 #define ENABLE_CHANLIST (1<<9)
79 #define ENABLE_PORT_B (1<<7)
80 #define ENABLE_PORT_A (1<<6)
81 #define ENABLE_COUNTER_B (1<<4)
82 #define ENABLE_COUNTER_A (1<<3)
83 #define ENABLE_DAC (1<<1)
84 #define BUFFERED_DAC (1<<0)
85 #define ME_DAC_UPDATE 0x0002 /* R | - */
86 #define ME_STATUS 0x0004 /* R | - */
87 #define COUNTER_B_IRQ_PENDING (1<<12)
88 #define COUNTER_A_IRQ_PENDING (1<<11)
89 #define CHANLIST_READY_IRQ_PENDING (1<<10)
90 #define EXT_IRQ_PENDING (1<<9)
91 #define ADFIFO_HALFFULL_IRQ_PENDING (1<<8)
92 #define ADFIFO_FULL (1<<4)
93 #define ADFIFO_HALFFULL (1<<3)
94 #define ADFIFO_EMPTY (1<<2)
95 #define CHANLIST_FULL (1<<1)
96 #define FST_ACTIVE (1<<0)
97 #define ME_RESET_INTERRUPT 0x0004 /* - | W */
98 #define ME_DIO_PORT_A 0x0006 /* R | W */
99 #define ME_DIO_PORT_B 0x0008 /* R | W */
100 #define ME_TIMER_DATA_0 0x000A /* - | W */
101 #define ME_TIMER_DATA_1 0x000C /* - | W */
102 #define ME_TIMER_DATA_2 0x000E /* - | W */
103 #define ME_CHANNEL_LIST 0x0010 /* - | W */
104 #define ADC_UNIPOLAR (1<<6)
105 #define ADC_GAIN_0 (0<<4)
106 #define ADC_GAIN_1 (1<<4)
107 #define ADC_GAIN_2 (2<<4)
108 #define ADC_GAIN_3 (3<<4)
109 #define ME_READ_AD_FIFO 0x0010 /* R | - */
110 #define ME_DAC_CONTROL 0x0012 /* - | W */
111 #define DAC_UNIPOLAR_D (0<<4)
112 #define DAC_BIPOLAR_D (1<<4)
113 #define DAC_UNIPOLAR_C (0<<5)
114 #define DAC_BIPOLAR_C (1<<5)
115 #define DAC_UNIPOLAR_B (0<<6)
116 #define DAC_BIPOLAR_B (1<<6)
117 #define DAC_UNIPOLAR_A (0<<7)
118 #define DAC_BIPOLAR_A (1<<7)
119 #define DAC_GAIN_0_D (0<<8)
120 #define DAC_GAIN_1_D (1<<8)
121 #define DAC_GAIN_0_C (0<<9)
122 #define DAC_GAIN_1_C (1<<9)
123 #define DAC_GAIN_0_B (0<<10)
124 #define DAC_GAIN_1_B (1<<10)
125 #define DAC_GAIN_0_A (0<<11)
126 #define DAC_GAIN_1_A (1<<11)
127 #define ME_DAC_CONTROL_UPDATE 0x0012 /* R | - */
128 #define ME_DAC_DATA_A 0x0014 /* - | W */
129 #define ME_DAC_DATA_B 0x0016 /* - | W */
130 #define ME_DAC_DATA_C 0x0018 /* - | W */
131 #define ME_DAC_DATA_D 0x001A /* - | W */
132 #define ME_COUNTER_ENDDATA_A 0x001C /* - | W */
133 #define ME_COUNTER_ENDDATA_B 0x001E /* - | W */
134 #define ME_COUNTER_STARTDATA_A 0x0020 /* - | W */
135 #define ME_COUNTER_VALUE_A 0x0020 /* R | - */
136 #define ME_COUNTER_STARTDATA_B 0x0022 /* - | W */
137 #define ME_COUNTER_VALUE_B 0x0022 /* R | - */
138
139 static const struct comedi_lrange me2000_ai_range = {
140 8,
141 {
142 BIP_RANGE(10),
143 BIP_RANGE(5),
144 BIP_RANGE(2.5),
145 BIP_RANGE(1.25),
146 UNI_RANGE(10),
147 UNI_RANGE(5),
148 UNI_RANGE(2.5),
149 UNI_RANGE(1.25)
150 }
151 };
152
153 static const struct comedi_lrange me2600_ai_range = {
154 8,
155 {
156 BIP_RANGE(10),
157 BIP_RANGE(5),
158 BIP_RANGE(2.5),
159 BIP_RANGE(1.25),
160 UNI_RANGE(10),
161 UNI_RANGE(5),
162 UNI_RANGE(2.5),
163 UNI_RANGE(1.25)
164 }
165 };
166
167 static const struct comedi_lrange me2600_ao_range = {
168 3,
169 {
170 BIP_RANGE(10),
171 BIP_RANGE(5),
172 UNI_RANGE(10)
173 }
174 };
175
176 /* Board specification structure */
177 struct me_board {
178 const char *name; /* driver name */
179 int device_id;
180 int ao_channel_nbr; /* DA config */
181 int ao_resolution;
182 int ao_resolution_mask;
183 const struct comedi_lrange *ao_range_list;
184 int ai_channel_nbr; /* AD config */
185 int ai_resolution;
186 int ai_resolution_mask;
187 const struct comedi_lrange *ai_range_list;
188 int dio_channel_nbr; /* DIO config */
189 };
190
191 static const struct me_board me_boards[] = {
192 {
193 .name = "me-2600i",
194 .device_id = ME2600_DEVICE_ID,
195 /* Analog Output */
196 .ao_channel_nbr = 4,
197 .ao_resolution = 12,
198 .ao_resolution_mask = 0x0fff,
199 .ao_range_list = &me2600_ao_range,
200 .ai_channel_nbr = 16,
201 /* Analog Input */
202 .ai_resolution = 12,
203 .ai_resolution_mask = 0x0fff,
204 .ai_range_list = &me2600_ai_range,
205 .dio_channel_nbr = 32,
206 },
207 {
208 .name = "me-2000i",
209 .device_id = ME2000_DEVICE_ID,
210 /* Analog Output */
211 .ao_channel_nbr = 0,
212 .ao_resolution = 0,
213 .ao_resolution_mask = 0,
214 .ao_range_list = NULL,
215 .ai_channel_nbr = 16,
216 /* Analog Input */
217 .ai_resolution = 12,
218 .ai_resolution_mask = 0x0fff,
219 .ai_range_list = &me2000_ai_range,
220 .dio_channel_nbr = 32,
221 }
222 };
223
224 /* Private data structure */
225 struct me_private_data {
226 void __iomem *plx_regbase; /* PLX configuration base address */
227 void __iomem *me_regbase; /* Base address of the Meilhaus card */
228 unsigned long plx_regbase_size; /* Size of PLX configuration space */
229 unsigned long me_regbase_size; /* Size of Meilhaus space */
230
231 unsigned short control_1; /* Mirror of CONTROL_1 register */
232 unsigned short control_2; /* Mirror of CONTROL_2 register */
233 unsigned short dac_control; /* Mirror of the DAC_CONTROL register */
234 int ao_readback[4]; /* Mirror of analog output data */
235 };
236
237 #define dev_private ((struct me_private_data *)dev->private)
238
239 /*
240 * ------------------------------------------------------------------
241 *
242 * Helpful functions
243 *
244 * ------------------------------------------------------------------
245 */
246 static inline void sleep(unsigned sec)
247 {
248 current->state = TASK_INTERRUPTIBLE;
249 schedule_timeout(sec * HZ);
250 }
251
252 /*
253 * ------------------------------------------------------------------
254 *
255 * DIGITAL INPUT/OUTPUT SECTION
256 *
257 * ------------------------------------------------------------------
258 */
259 static int me_dio_insn_config(struct comedi_device *dev,
260 struct comedi_subdevice *s,
261 struct comedi_insn *insn, unsigned int *data)
262 {
263 int bits;
264 int mask = 1 << CR_CHAN(insn->chanspec);
265
266 /* calculate port */
267 if (mask & 0x0000ffff) { /* Port A in use */
268 bits = 0x0000ffff;
269
270 /* Enable Port A */
271 dev_private->control_2 |= ENABLE_PORT_A;
272 writew(dev_private->control_2,
273 dev_private->me_regbase + ME_CONTROL_2);
274 } else { /* Port B in use */
275
276 bits = 0xffff0000;
277
278 /* Enable Port B */
279 dev_private->control_2 |= ENABLE_PORT_B;
280 writew(dev_private->control_2,
281 dev_private->me_regbase + ME_CONTROL_2);
282 }
283
284 if (data[0]) {
285 /* Config port as output */
286 s->io_bits |= bits;
287 } else {
288 /* Config port as input */
289 s->io_bits &= ~bits;
290 }
291
292 return 1;
293 }
294
295 /* Digital instant input/outputs */
296 static int me_dio_insn_bits(struct comedi_device *dev,
297 struct comedi_subdevice *s,
298 struct comedi_insn *insn, unsigned int *data)
299 {
300 unsigned int mask = data[0];
301 s->state &= ~mask;
302 s->state |= (mask & data[1]);
303
304 mask &= s->io_bits;
305 if (mask & 0x0000ffff) { /* Port A */
306 writew((s->state & 0xffff),
307 dev_private->me_regbase + ME_DIO_PORT_A);
308 } else {
309 data[1] &= ~0x0000ffff;
310 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_A);
311 }
312
313 if (mask & 0xffff0000) { /* Port B */
314 writew(((s->state >> 16) & 0xffff),
315 dev_private->me_regbase + ME_DIO_PORT_B);
316 } else {
317 data[1] &= ~0xffff0000;
318 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_B) << 16;
319 }
320
321 return insn->n;
322 }
323
324 /*
325 * ------------------------------------------------------------------
326 *
327 * ANALOG INPUT SECTION
328 *
329 * ------------------------------------------------------------------
330 */
331
332 /* Analog instant input */
333 static int me_ai_insn_read(struct comedi_device *dev,
334 struct comedi_subdevice *s,
335 struct comedi_insn *insn, unsigned int *data)
336 {
337 unsigned short value;
338 int chan = CR_CHAN((&insn->chanspec)[0]);
339 int rang = CR_RANGE((&insn->chanspec)[0]);
340 int aref = CR_AREF((&insn->chanspec)[0]);
341 int i;
342
343 /* stop any running conversion */
344 dev_private->control_1 &= 0xFFFC;
345 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
346
347 /* clear chanlist and ad fifo */
348 dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
349 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
350
351 /* reset any pending interrupt */
352 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
353
354 /* enable the chanlist and ADC fifo */
355 dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
356 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
357
358 /* write to channel list fifo */
359 /* b3:b0 are the channel number */
360 value = chan & 0x0f;
361 /* b5:b4 are the channel gain */
362 value |= (rang & 0x03) << 4;
363 /* b6 channel polarity */
364 value |= (rang & 0x04) << 4;
365 /* b7 single or differential */
366 value |= ((aref & AREF_DIFF) ? 0x80 : 0);
367 writew(value & 0xff, dev_private->me_regbase + ME_CHANNEL_LIST);
368
369 /* set ADC mode to software trigger */
370 dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
371 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
372
373 /* start conversion by reading from ADC_START */
374 readw(dev_private->me_regbase + ME_ADC_START);
375
376 /* wait for ADC fifo not empty flag */
377 for (i = 100000; i > 0; i--)
378 if (!(readw(dev_private->me_regbase + ME_STATUS) & 0x0004))
379 break;
380
381 /* get value from ADC fifo */
382 if (i) {
383 data[0] =
384 (readw(dev_private->me_regbase +
385 ME_READ_AD_FIFO) ^ 0x800) & 0x0FFF;
386 } else {
387 printk(KERN_ERR "comedi%d: Cannot get single value\n",
388 dev->minor);
389 return -EIO;
390 }
391
392 /* stop any running conversion */
393 dev_private->control_1 &= 0xFFFC;
394 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
395
396 return 1;
397 }
398
399 /*
400 * ------------------------------------------------------------------
401 *
402 * HARDWARE TRIGGERED ANALOG INPUT SECTION
403 *
404 * ------------------------------------------------------------------
405 */
406
407 /* Cancel analog input autoscan */
408 static int me_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
409 {
410 /* disable interrupts */
411
412 /* stop any running conversion */
413 dev_private->control_1 &= 0xFFFC;
414 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
415
416 return 0;
417 }
418
419 /* Test analog input command */
420 static int me_ai_do_cmd_test(struct comedi_device *dev,
421 struct comedi_subdevice *s, struct comedi_cmd *cmd)
422 {
423 return 0;
424 }
425
426 /* Analog input command */
427 static int me_ai_do_cmd(struct comedi_device *dev,
428 struct comedi_subdevice *s)
429 {
430 return 0;
431 }
432
433 /*
434 * ------------------------------------------------------------------
435 *
436 * ANALOG OUTPUT SECTION
437 *
438 * ------------------------------------------------------------------
439 */
440
441 /* Analog instant output */
442 static int me_ao_insn_write(struct comedi_device *dev,
443 struct comedi_subdevice *s,
444 struct comedi_insn *insn, unsigned int *data)
445 {
446 int chan;
447 int rang;
448 int i;
449
450 /* Enable all DAC */
451 dev_private->control_2 |= ENABLE_DAC;
452 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
453
454 /* and set DAC to "buffered" mode */
455 dev_private->control_2 |= BUFFERED_DAC;
456 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
457
458 /* Set dac-control register */
459 for (i = 0; i < insn->n; i++) {
460 chan = CR_CHAN((&insn->chanspec)[i]);
461 rang = CR_RANGE((&insn->chanspec)[i]);
462
463 /* clear bits for this channel */
464 dev_private->dac_control &= ~(0x0880 >> chan);
465 if (rang == 0)
466 dev_private->dac_control |=
467 ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
468 else if (rang == 1)
469 dev_private->dac_control |=
470 ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
471 }
472 writew(dev_private->dac_control,
473 dev_private->me_regbase + ME_DAC_CONTROL);
474
475 /* Update dac-control register */
476 readw(dev_private->me_regbase + ME_DAC_CONTROL_UPDATE);
477
478 /* Set data register */
479 for (i = 0; i < insn->n; i++) {
480 chan = CR_CHAN((&insn->chanspec)[i]);
481 writew((data[0] & s->maxdata),
482 dev_private->me_regbase + ME_DAC_DATA_A + (chan << 1));
483 dev_private->ao_readback[chan] = (data[0] & s->maxdata);
484 }
485
486 /* Update dac with data registers */
487 readw(dev_private->me_regbase + ME_DAC_UPDATE);
488
489 return i;
490 }
491
492 /* Analog output readback */
493 static int me_ao_insn_read(struct comedi_device *dev,
494 struct comedi_subdevice *s, struct comedi_insn *insn,
495 unsigned int *data)
496 {
497 int i;
498
499 for (i = 0; i < insn->n; i++) {
500 data[i] =
501 dev_private->ao_readback[CR_CHAN((&insn->chanspec)[i])];
502 }
503
504 return 1;
505 }
506
507 /*
508 * ------------------------------------------------------------------
509 *
510 * INITIALISATION SECTION
511 *
512 * ------------------------------------------------------------------
513 */
514
515 /* Xilinx firmware download for card: ME-2600i */
516 static int me2600_xilinx_download(struct comedi_device *dev,
517 const u8 *data, size_t size)
518 {
519 unsigned int value;
520 unsigned int file_length;
521 unsigned int i;
522
523 /* disable irq's on PLX */
524 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
525
526 /* First, make a dummy read to reset xilinx */
527 value = readw(dev_private->me_regbase + XILINX_DOWNLOAD_RESET);
528
529 /* Wait until reset is over */
530 sleep(1);
531
532 /* Write a dummy value to Xilinx */
533 writeb(0x00, dev_private->me_regbase + 0x0);
534 sleep(1);
535
536 /*
537 * Format of the firmware
538 * Build longs from the byte-wise coded header
539 * Byte 1-3: length of the array
540 * Byte 4-7: version
541 * Byte 8-11: date
542 * Byte 12-15: reserved
543 */
544 if (size < 16)
545 return -EINVAL;
546
547 file_length = (((unsigned int)data[0] & 0xff) << 24) +
548 (((unsigned int)data[1] & 0xff) << 16) +
549 (((unsigned int)data[2] & 0xff) << 8) +
550 ((unsigned int)data[3] & 0xff);
551
552 /*
553 * Loop for writing firmware byte by byte to xilinx
554 * Firmware data start at offfset 16
555 */
556 for (i = 0; i < file_length; i++)
557 writeb((data[16 + i] & 0xff),
558 dev_private->me_regbase + 0x0);
559
560 /* Write 5 dummy values to xilinx */
561 for (i = 0; i < 5; i++)
562 writeb(0x00, dev_private->me_regbase + 0x0);
563
564 /* Test if there was an error during download -> INTB was thrown */
565 value = readl(dev_private->plx_regbase + PLX_INTCSR);
566 if (value & 0x20) {
567 /* Disable interrupt */
568 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
569 printk(KERN_ERR "comedi%d: Xilinx download failed\n",
570 dev->minor);
571 return -EIO;
572 }
573
574 /* Wait until the Xilinx is ready for real work */
575 sleep(1);
576
577 /* Enable PLX-Interrupts */
578 writel(0x43, dev_private->plx_regbase + PLX_INTCSR);
579
580 return 0;
581 }
582
583 static int me2600_upload_firmware(struct comedi_device *dev)
584 {
585 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
586 const struct firmware *fw;
587 int ret;
588
589 ret = request_firmware(&fw, ME2600_FIRMWARE, &pcidev->dev);
590 if (ret)
591 return ret;
592
593 ret = me2600_xilinx_download(dev, fw->data, fw->size);
594 release_firmware(fw);
595
596 return ret;
597 }
598
599 /* Reset device */
600 static int me_reset(struct comedi_device *dev)
601 {
602 /* Reset board */
603 writew(0x00, dev_private->me_regbase + ME_CONTROL_1);
604 writew(0x00, dev_private->me_regbase + ME_CONTROL_2);
605 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
606 writew(0x00, dev_private->me_regbase + ME_DAC_CONTROL);
607
608 /* Save values in the board context */
609 dev_private->dac_control = 0;
610 dev_private->control_1 = 0;
611 dev_private->control_2 = 0;
612
613 return 0;
614 }
615
616 static const void *me_find_boardinfo(struct comedi_device *dev,
617 struct pci_dev *pcidev)
618 {
619 const struct me_board *board;
620 int i;
621
622 for (i = 0; i < ARRAY_SIZE(me_boards); i++) {
623 board = &me_boards[i];
624 if (board->device_id == pcidev->device)
625 return board;
626 }
627 return NULL;
628 }
629
630 static int me_attach_pci(struct comedi_device *dev, struct pci_dev *pcidev)
631 {
632 const struct me_board *board;
633 struct comedi_subdevice *s;
634 resource_size_t plx_regbase_tmp;
635 unsigned long plx_regbase_size_tmp;
636 resource_size_t me_regbase_tmp;
637 unsigned long me_regbase_size_tmp;
638 resource_size_t swap_regbase_tmp;
639 unsigned long swap_regbase_size_tmp;
640 resource_size_t regbase_tmp;
641 int result, error;
642
643 comedi_set_hw_dev(dev, &pcidev->dev);
644
645 board = me_find_boardinfo(dev, pcidev);
646 if (!board)
647 return -ENODEV;
648 dev->board_ptr = board;
649 dev->board_name = board->name;
650
651 /* Allocate private memory */
652 if (alloc_private(dev, sizeof(struct me_private_data)) < 0)
653 return -ENOMEM;
654
655 /* Enable PCI device and request PCI regions */
656 if (comedi_pci_enable(pcidev, dev->board_name) < 0) {
657 printk(KERN_ERR "comedi%d: Failed to enable PCI device and "
658 "request regions\n", dev->minor);
659 return -EIO;
660 }
661
662 /* Read PLX register base address [PCI_BASE_ADDRESS #0]. */
663 plx_regbase_tmp = pci_resource_start(pcidev, 0);
664 plx_regbase_size_tmp = pci_resource_len(pcidev, 0);
665 dev_private->plx_regbase =
666 ioremap(plx_regbase_tmp, plx_regbase_size_tmp);
667 dev_private->plx_regbase_size = plx_regbase_size_tmp;
668 if (!dev_private->plx_regbase) {
669 printk("comedi%d: Failed to remap I/O memory\n", dev->minor);
670 return -ENOMEM;
671 }
672
673 /* Read Swap base address [PCI_BASE_ADDRESS #5]. */
674
675 swap_regbase_tmp = pci_resource_start(pcidev, 5);
676 swap_regbase_size_tmp = pci_resource_len(pcidev, 5);
677
678 if (!swap_regbase_tmp)
679 printk(KERN_ERR "comedi%d: Swap not present\n", dev->minor);
680
681 /*---------------------------------------------- Workaround start ---*/
682 if (plx_regbase_tmp & 0x0080) {
683 printk(KERN_ERR "comedi%d: PLX-Bug detected\n", dev->minor);
684
685 if (swap_regbase_tmp) {
686 regbase_tmp = plx_regbase_tmp;
687 plx_regbase_tmp = swap_regbase_tmp;
688 swap_regbase_tmp = regbase_tmp;
689
690 result = pci_write_config_dword(pcidev,
691 PCI_BASE_ADDRESS_0,
692 plx_regbase_tmp);
693 if (result != PCIBIOS_SUCCESSFUL)
694 return -EIO;
695
696 result = pci_write_config_dword(pcidev,
697 PCI_BASE_ADDRESS_5,
698 swap_regbase_tmp);
699 if (result != PCIBIOS_SUCCESSFUL)
700 return -EIO;
701 } else {
702 plx_regbase_tmp -= 0x80;
703 result = pci_write_config_dword(pcidev,
704 PCI_BASE_ADDRESS_0,
705 plx_regbase_tmp);
706 if (result != PCIBIOS_SUCCESSFUL)
707 return -EIO;
708 }
709 }
710 /*--------------------------------------------- Workaround end -----*/
711
712 /* Read Meilhaus register base address [PCI_BASE_ADDRESS #2]. */
713
714 me_regbase_tmp = pci_resource_start(pcidev, 2);
715 me_regbase_size_tmp = pci_resource_len(pcidev, 2);
716 dev_private->me_regbase_size = me_regbase_size_tmp;
717 dev_private->me_regbase = ioremap(me_regbase_tmp, me_regbase_size_tmp);
718 if (!dev_private->me_regbase) {
719 printk(KERN_ERR "comedi%d: Failed to remap I/O memory\n",
720 dev->minor);
721 return -ENOMEM;
722 }
723
724 /* Download firmware and reset card */
725 if (board->device_id == ME2600_DEVICE_ID) {
726 result = me2600_upload_firmware(dev);
727 if (result < 0)
728 return result;
729 }
730 me_reset(dev);
731
732 error = comedi_alloc_subdevices(dev, 3);
733 if (error)
734 return error;
735
736 s = &dev->subdevices[0];
737 s->type = COMEDI_SUBD_AI;
738 s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_CMD_READ;
739 s->n_chan = board->ai_channel_nbr;
740 s->maxdata = board->ai_resolution_mask;
741 s->len_chanlist = board->ai_channel_nbr;
742 s->range_table = board->ai_range_list;
743 s->cancel = me_ai_cancel;
744 s->insn_read = me_ai_insn_read;
745 s->do_cmdtest = me_ai_do_cmd_test;
746 s->do_cmd = me_ai_do_cmd;
747
748 s = &dev->subdevices[1];
749 s->type = COMEDI_SUBD_AO;
750 s->subdev_flags = SDF_WRITEABLE | SDF_COMMON;
751 s->n_chan = board->ao_channel_nbr;
752 s->maxdata = board->ao_resolution_mask;
753 s->len_chanlist = board->ao_channel_nbr;
754 s->range_table = board->ao_range_list;
755 s->insn_read = me_ao_insn_read;
756 s->insn_write = me_ao_insn_write;
757
758 s = &dev->subdevices[2];
759 s->type = COMEDI_SUBD_DIO;
760 s->subdev_flags = SDF_READABLE | SDF_WRITEABLE;
761 s->n_chan = board->dio_channel_nbr;
762 s->maxdata = 1;
763 s->len_chanlist = board->dio_channel_nbr;
764 s->range_table = &range_digital;
765 s->insn_bits = me_dio_insn_bits;
766 s->insn_config = me_dio_insn_config;
767 s->io_bits = 0;
768
769 dev_info(dev->class_dev, "%s: %s attached\n",
770 dev->driver->driver_name, dev->board_name);
771
772 return 0;
773 }
774
775 static void me_detach(struct comedi_device *dev)
776 {
777 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
778
779 if (dev_private) {
780 if (dev_private->me_regbase) {
781 me_reset(dev);
782 iounmap(dev_private->me_regbase);
783 }
784 if (dev_private->plx_regbase)
785 iounmap(dev_private->plx_regbase);
786 }
787 if (pcidev) {
788 if (dev_private->plx_regbase_size)
789 comedi_pci_disable(pcidev);
790 pci_dev_put(pcidev);
791 }
792 }
793
794 static struct comedi_driver me_daq_driver = {
795 .driver_name = "me_daq",
796 .module = THIS_MODULE,
797 .attach_pci = me_attach_pci,
798 .detach = me_detach,
799 };
800
801 static int __devinit me_daq_pci_probe(struct pci_dev *dev,
802 const struct pci_device_id *ent)
803 {
804 return comedi_pci_auto_config(dev, &me_daq_driver);
805 }
806
807 static void __devexit me_daq_pci_remove(struct pci_dev *dev)
808 {
809 comedi_pci_auto_unconfig(dev);
810 }
811
812 static DEFINE_PCI_DEVICE_TABLE(me_daq_pci_table) = {
813 { PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, ME2600_DEVICE_ID) },
814 { PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, ME2000_DEVICE_ID) },
815 { 0 }
816 };
817 MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
818
819 static struct pci_driver me_daq_pci_driver = {
820 .name = "me_daq",
821 .id_table = me_daq_pci_table,
822 .probe = me_daq_pci_probe,
823 .remove = __devexit_p(me_daq_pci_remove),
824 };
825 module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
826
827 MODULE_AUTHOR("Comedi http://www.comedi.org");
828 MODULE_DESCRIPTION("Comedi low-level driver");
829 MODULE_LICENSE("GPL");
830 MODULE_FIRMWARE(ME2600_FIRMWARE);
Linux kernel - Deliverables
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