3 Hardware driver for NI Mite PCI interface chip
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 The PCI-MIO E series driver was originally written by
26 Tomasz Motylewski <...>, and ported to comedi by ds.
28 References for specifications:
30 321747b.pdf Register Level Programmer Manual (obsolete)
31 321747c.pdf Register Level Programmer Manual (new)
32 DAQ-STC reference manual
34 Other possibly relevant info:
36 320517c.pdf User manual (obsolete)
37 320517f.pdf User manual (new)
39 320906c.pdf maximum signal ratings
41 321791a.pdf discontinuation of at-mio-16e-10 rev. c
42 321808a.pdf about at-mio-16e-10 rev P
43 321837a.pdf discontinuation of at-mio-16de-10 rev d
44 321838a.pdf about at-mio-16de-10 rev N
50 /* #define USE_KMALLOC */
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
54 #include <linux/pci.h>
56 #include "../comedidev.h"
58 #include "comedi_fc.h"
61 #define PCI_MITE_SIZE 4096
62 #define PCI_DAQ_SIZE 4096
63 #define PCI_DAQ_SIZE_660X 8192
65 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
67 struct mite_struct
*mite_alloc(struct pci_dev
*pcidev
)
69 struct mite_struct
*mite
;
72 mite
= kzalloc(sizeof(*mite
), GFP_KERNEL
);
74 spin_lock_init(&mite
->lock
);
75 mite
->pcidev
= pcidev
;
76 for (i
= 0; i
< MAX_MITE_DMA_CHANNELS
; ++i
) {
77 mite
->channels
[i
].mite
= mite
;
78 mite
->channels
[i
].channel
= i
;
79 mite
->channels
[i
].done
= 1;
84 EXPORT_SYMBOL(mite_alloc
);
86 static void dump_chip_signature(u32 csigr_bits
)
88 pr_info("version = %i, type = %i, mite mode = %i, interface mode = %i\n",
89 mite_csigr_version(csigr_bits
), mite_csigr_type(csigr_bits
),
90 mite_csigr_mmode(csigr_bits
), mite_csigr_imode(csigr_bits
));
91 pr_info("num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
92 mite_csigr_dmac(csigr_bits
), mite_csigr_wpdep(csigr_bits
),
93 mite_csigr_wins(csigr_bits
), mite_csigr_iowins(csigr_bits
));
96 static unsigned mite_fifo_size(struct mite_struct
*mite
, unsigned channel
)
98 unsigned fcr_bits
= readl(mite
->mite_io_addr
+ MITE_FCR(channel
));
99 unsigned empty_count
= (fcr_bits
>> 16) & 0xff;
100 unsigned full_count
= fcr_bits
& 0xff;
101 return empty_count
+ full_count
;
104 int mite_setup2(struct mite_struct
*mite
, unsigned use_iodwbsr_1
)
106 unsigned long length
;
107 resource_size_t addr
;
110 unsigned unknown_dma_burst_bits
;
112 pci_set_master(mite
->pcidev
);
114 addr
= pci_resource_start(mite
->pcidev
, 0);
115 mite
->mite_phys_addr
= addr
;
116 mite
->mite_io_addr
= ioremap(addr
, PCI_MITE_SIZE
);
117 if (!mite
->mite_io_addr
) {
118 dev_err(&mite
->pcidev
->dev
,
119 "Failed to remap mite io memory address\n");
123 addr
= pci_resource_start(mite
->pcidev
, 1);
124 mite
->daq_phys_addr
= addr
;
125 length
= pci_resource_len(mite
->pcidev
, 1);
127 * In case of a 660x board, DAQ size is 8k instead of 4k
128 * (see as shown by lspci output)
130 mite
->daq_io_addr
= ioremap(mite
->daq_phys_addr
, length
);
131 if (!mite
->daq_io_addr
) {
132 dev_err(&mite
->pcidev
->dev
,
133 "Failed to remap daq io memory address\n");
138 writel(0, mite
->mite_io_addr
+ MITE_IODWBSR
);
139 dev_info(&mite
->pcidev
->dev
,
140 "using I/O Window Base Size register 1\n");
141 writel(mite
->daq_phys_addr
| WENAB
|
142 MITE_IODWBSR_1_WSIZE_bits(length
),
143 mite
->mite_io_addr
+ MITE_IODWBSR_1
);
144 writel(0, mite
->mite_io_addr
+ MITE_IODWCR_1
);
146 writel(mite
->daq_phys_addr
| WENAB
,
147 mite
->mite_io_addr
+ MITE_IODWBSR
);
150 * make sure dma bursts work. I got this from running a bus analyzer
151 * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
152 * of 0x61f and bursts worked. 6281 powered up with register value of
153 * 0x1f and bursts didn't work. The NI windows driver reads the
154 * register, then does a bitwise-or of 0x600 with it and writes it back.
156 unknown_dma_burst_bits
=
157 readl(mite
->mite_io_addr
+ MITE_UNKNOWN_DMA_BURST_REG
);
158 unknown_dma_burst_bits
|= UNKNOWN_DMA_BURST_ENABLE_BITS
;
159 writel(unknown_dma_burst_bits
,
160 mite
->mite_io_addr
+ MITE_UNKNOWN_DMA_BURST_REG
);
162 csigr_bits
= readl(mite
->mite_io_addr
+ MITE_CSIGR
);
163 mite
->num_channels
= mite_csigr_dmac(csigr_bits
);
164 if (mite
->num_channels
> MAX_MITE_DMA_CHANNELS
) {
165 dev_warn(&mite
->pcidev
->dev
,
166 "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
167 mite
->num_channels
, MAX_MITE_DMA_CHANNELS
);
168 mite
->num_channels
= MAX_MITE_DMA_CHANNELS
;
170 dump_chip_signature(csigr_bits
);
171 for (i
= 0; i
< mite
->num_channels
; i
++) {
172 writel(CHOR_DMARESET
, mite
->mite_io_addr
+ MITE_CHOR(i
));
173 /* disable interrupts */
174 writel(CHCR_CLR_DMA_IE
| CHCR_CLR_LINKP_IE
| CHCR_CLR_SAR_IE
|
175 CHCR_CLR_DONE_IE
| CHCR_CLR_MRDY_IE
| CHCR_CLR_DRDY_IE
|
176 CHCR_CLR_LC_IE
| CHCR_CLR_CONT_RB_IE
,
177 mite
->mite_io_addr
+ MITE_CHCR(i
));
179 mite
->fifo_size
= mite_fifo_size(mite
, 0);
180 dev_info(&mite
->pcidev
->dev
, "fifo size is %i.\n", mite
->fifo_size
);
183 EXPORT_SYMBOL(mite_setup2
);
185 int mite_setup(struct mite_struct
*mite
)
187 return mite_setup2(mite
, 0);
189 EXPORT_SYMBOL(mite_setup
);
191 void mite_unsetup(struct mite_struct
*mite
)
193 /* unsigned long offset, start, length; */
198 if (mite
->mite_io_addr
) {
199 iounmap(mite
->mite_io_addr
);
200 mite
->mite_io_addr
= NULL
;
202 if (mite
->daq_io_addr
) {
203 iounmap(mite
->daq_io_addr
);
204 mite
->daq_io_addr
= NULL
;
206 if (mite
->mite_phys_addr
)
207 mite
->mite_phys_addr
= 0;
209 EXPORT_SYMBOL(mite_unsetup
);
211 struct mite_dma_descriptor_ring
*mite_alloc_ring(struct mite_struct
*mite
)
213 struct mite_dma_descriptor_ring
*ring
=
214 kmalloc(sizeof(struct mite_dma_descriptor_ring
), GFP_KERNEL
);
218 ring
->hw_dev
= get_device(&mite
->pcidev
->dev
);
219 if (ring
->hw_dev
== NULL
) {
224 ring
->descriptors
= NULL
;
225 ring
->descriptors_dma_addr
= 0;
228 EXPORT_SYMBOL(mite_alloc_ring
);
230 void mite_free_ring(struct mite_dma_descriptor_ring
*ring
)
233 if (ring
->descriptors
) {
234 dma_free_coherent(ring
->hw_dev
,
236 sizeof(struct mite_dma_descriptor
),
238 ring
->descriptors_dma_addr
);
240 put_device(ring
->hw_dev
);
244 EXPORT_SYMBOL(mite_free_ring
);
246 struct mite_channel
*mite_request_channel_in_range(struct mite_struct
*mite
,
248 mite_dma_descriptor_ring
249 *ring
, unsigned min_channel
,
250 unsigned max_channel
)
254 struct mite_channel
*channel
= NULL
;
256 /* spin lock so mite_release_channel can be called safely
259 spin_lock_irqsave(&mite
->lock
, flags
);
260 for (i
= min_channel
; i
<= max_channel
; ++i
) {
261 if (mite
->channel_allocated
[i
] == 0) {
262 mite
->channel_allocated
[i
] = 1;
263 channel
= &mite
->channels
[i
];
264 channel
->ring
= ring
;
268 spin_unlock_irqrestore(&mite
->lock
, flags
);
271 EXPORT_SYMBOL(mite_request_channel_in_range
);
273 void mite_release_channel(struct mite_channel
*mite_chan
)
275 struct mite_struct
*mite
= mite_chan
->mite
;
278 /* spin lock to prevent races with mite_request_channel */
279 spin_lock_irqsave(&mite
->lock
, flags
);
280 if (mite
->channel_allocated
[mite_chan
->channel
]) {
281 mite_dma_disarm(mite_chan
);
282 mite_dma_reset(mite_chan
);
284 * disable all channel's interrupts (do it after disarm/reset so
285 * MITE_CHCR reg isn't changed while dma is still active!)
287 writel(CHCR_CLR_DMA_IE
| CHCR_CLR_LINKP_IE
|
288 CHCR_CLR_SAR_IE
| CHCR_CLR_DONE_IE
|
289 CHCR_CLR_MRDY_IE
| CHCR_CLR_DRDY_IE
|
290 CHCR_CLR_LC_IE
| CHCR_CLR_CONT_RB_IE
,
291 mite
->mite_io_addr
+ MITE_CHCR(mite_chan
->channel
));
292 mite
->channel_allocated
[mite_chan
->channel
] = 0;
293 mite_chan
->ring
= NULL
;
296 spin_unlock_irqrestore(&mite
->lock
, flags
);
298 EXPORT_SYMBOL(mite_release_channel
);
300 void mite_dma_arm(struct mite_channel
*mite_chan
)
302 struct mite_struct
*mite
= mite_chan
->mite
;
306 MDPRINTK("mite_dma_arm ch%i\n", mite_chan
->channel
);
308 * memory barrier is intended to insure any twiddling with the buffer
309 * is done before writing to the mite to arm dma transfer
314 spin_lock_irqsave(&mite
->lock
, flags
);
316 writel(chor
, mite
->mite_io_addr
+ MITE_CHOR(mite_chan
->channel
));
318 spin_unlock_irqrestore(&mite
->lock
, flags
);
319 /* mite_dma_tcr(mite, channel); */
321 EXPORT_SYMBOL(mite_dma_arm
);
323 /**************************************/
325 int mite_buf_change(struct mite_dma_descriptor_ring
*ring
,
326 struct comedi_async
*async
)
328 unsigned int n_links
;
331 if (ring
->descriptors
) {
332 dma_free_coherent(ring
->hw_dev
,
334 sizeof(struct mite_dma_descriptor
),
336 ring
->descriptors_dma_addr
);
338 ring
->descriptors
= NULL
;
339 ring
->descriptors_dma_addr
= 0;
342 if (async
->prealloc_bufsz
== 0)
345 n_links
= async
->prealloc_bufsz
>> PAGE_SHIFT
;
347 MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring
->hw_dev
, n_links
);
350 dma_alloc_coherent(ring
->hw_dev
,
351 n_links
* sizeof(struct mite_dma_descriptor
),
352 &ring
->descriptors_dma_addr
, GFP_KERNEL
);
353 if (!ring
->descriptors
) {
354 dev_err(async
->subdevice
->device
->class_dev
,
355 "mite: ring buffer allocation failed\n");
358 ring
->n_links
= n_links
;
360 for (i
= 0; i
< n_links
; i
++) {
361 ring
->descriptors
[i
].count
= cpu_to_le32(PAGE_SIZE
);
362 ring
->descriptors
[i
].addr
=
363 cpu_to_le32(async
->buf_page_list
[i
].dma_addr
);
364 ring
->descriptors
[i
].next
=
365 cpu_to_le32(ring
->descriptors_dma_addr
+ (i
+
367 sizeof(struct mite_dma_descriptor
));
369 ring
->descriptors
[n_links
- 1].next
=
370 cpu_to_le32(ring
->descriptors_dma_addr
);
372 * barrier is meant to insure that all the writes to the dma descriptors
373 * have completed before the dma controller is commanded to read them
378 EXPORT_SYMBOL(mite_buf_change
);
380 void mite_prep_dma(struct mite_channel
*mite_chan
,
381 unsigned int num_device_bits
, unsigned int num_memory_bits
)
383 unsigned int chor
, chcr
, mcr
, dcr
, lkcr
;
384 struct mite_struct
*mite
= mite_chan
->mite
;
386 MDPRINTK("mite_prep_dma ch%i\n", mite_chan
->channel
);
388 /* reset DMA and FIFO */
389 chor
= CHOR_DMARESET
| CHOR_FRESET
;
390 writel(chor
, mite
->mite_io_addr
+ MITE_CHOR(mite_chan
->channel
));
392 /* short link chaining mode */
393 chcr
= CHCR_SET_DMA_IE
| CHCR_LINKSHORT
| CHCR_SET_DONE_IE
|
396 * Link Complete Interrupt: interrupt every time a link
397 * in MITE_RING is completed. This can generate a lot of
398 * extra interrupts, but right now we update the values
399 * of buf_int_ptr and buf_int_count at each interrupt. A
400 * better method is to poll the MITE before each user
401 * "read()" to calculate the number of bytes available.
403 chcr
|= CHCR_SET_LC_IE
;
404 if (num_memory_bits
== 32 && num_device_bits
== 16) {
406 * Doing a combined 32 and 16 bit byteswap gets the 16 bit
407 * samples into the fifo in the right order. Tested doing 32 bit
408 * memory to 16 bit device transfers to the analog out of a
409 * pxi-6281, which has mite version = 1, type = 4. This also
410 * works for dma reads from the counters on e-series boards.
412 chcr
|= CHCR_BYTE_SWAP_DEVICE
| CHCR_BYTE_SWAP_MEMORY
;
414 if (mite_chan
->dir
== COMEDI_INPUT
)
415 chcr
|= CHCR_DEV_TO_MEM
;
417 writel(chcr
, mite
->mite_io_addr
+ MITE_CHCR(mite_chan
->channel
));
420 mcr
= CR_RL(64) | CR_ASEQUP
;
421 switch (num_memory_bits
) {
432 pr_warn("bug! invalid mem bit width for dma transfer\n");
435 writel(mcr
, mite
->mite_io_addr
+ MITE_MCR(mite_chan
->channel
));
438 dcr
= CR_RL(64) | CR_ASEQUP
;
439 dcr
|= CR_PORTIO
| CR_AMDEVICE
| CR_REQSDRQ(mite_chan
->channel
);
440 switch (num_device_bits
) {
451 pr_warn("bug! invalid dev bit width for dma transfer\n");
454 writel(dcr
, mite
->mite_io_addr
+ MITE_DCR(mite_chan
->channel
));
457 writel(0, mite
->mite_io_addr
+ MITE_DAR(mite_chan
->channel
));
459 /* the link is 32bits */
460 lkcr
= CR_RL(64) | CR_ASEQUP
| CR_PSIZE32
;
461 writel(lkcr
, mite
->mite_io_addr
+ MITE_LKCR(mite_chan
->channel
));
463 /* starting address for link chaining */
464 writel(mite_chan
->ring
->descriptors_dma_addr
,
465 mite
->mite_io_addr
+ MITE_LKAR(mite_chan
->channel
));
467 MDPRINTK("exit mite_prep_dma\n");
469 EXPORT_SYMBOL(mite_prep_dma
);
471 static u32
mite_device_bytes_transferred(struct mite_channel
*mite_chan
)
473 struct mite_struct
*mite
= mite_chan
->mite
;
474 return readl(mite
->mite_io_addr
+ MITE_DAR(mite_chan
->channel
));
477 u32
mite_bytes_in_transit(struct mite_channel
*mite_chan
)
479 struct mite_struct
*mite
= mite_chan
->mite
;
480 return readl(mite
->mite_io_addr
+
481 MITE_FCR(mite_chan
->channel
)) & 0x000000FF;
483 EXPORT_SYMBOL(mite_bytes_in_transit
);
485 /* returns lower bound for number of bytes transferred from device to memory */
486 u32
mite_bytes_written_to_memory_lb(struct mite_channel
*mite_chan
)
488 u32 device_byte_count
;
490 device_byte_count
= mite_device_bytes_transferred(mite_chan
);
491 return device_byte_count
- mite_bytes_in_transit(mite_chan
);
493 EXPORT_SYMBOL(mite_bytes_written_to_memory_lb
);
495 /* returns upper bound for number of bytes transferred from device to memory */
496 u32
mite_bytes_written_to_memory_ub(struct mite_channel
*mite_chan
)
498 u32 in_transit_count
;
500 in_transit_count
= mite_bytes_in_transit(mite_chan
);
501 return mite_device_bytes_transferred(mite_chan
) - in_transit_count
;
503 EXPORT_SYMBOL(mite_bytes_written_to_memory_ub
);
505 /* returns lower bound for number of bytes read from memory to device */
506 u32
mite_bytes_read_from_memory_lb(struct mite_channel
*mite_chan
)
508 u32 device_byte_count
;
510 device_byte_count
= mite_device_bytes_transferred(mite_chan
);
511 return device_byte_count
+ mite_bytes_in_transit(mite_chan
);
513 EXPORT_SYMBOL(mite_bytes_read_from_memory_lb
);
515 /* returns upper bound for number of bytes read from memory to device */
516 u32
mite_bytes_read_from_memory_ub(struct mite_channel
*mite_chan
)
518 u32 in_transit_count
;
520 in_transit_count
= mite_bytes_in_transit(mite_chan
);
521 return mite_device_bytes_transferred(mite_chan
) + in_transit_count
;
523 EXPORT_SYMBOL(mite_bytes_read_from_memory_ub
);
525 unsigned mite_dma_tcr(struct mite_channel
*mite_chan
)
527 struct mite_struct
*mite
= mite_chan
->mite
;
531 lkar
= readl(mite
->mite_io_addr
+ MITE_LKAR(mite_chan
->channel
));
532 tcr
= readl(mite
->mite_io_addr
+ MITE_TCR(mite_chan
->channel
));
533 MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan
->channel
,
538 EXPORT_SYMBOL(mite_dma_tcr
);
540 void mite_dma_disarm(struct mite_channel
*mite_chan
)
542 struct mite_struct
*mite
= mite_chan
->mite
;
547 writel(chor
, mite
->mite_io_addr
+ MITE_CHOR(mite_chan
->channel
));
549 EXPORT_SYMBOL(mite_dma_disarm
);
551 int mite_sync_input_dma(struct mite_channel
*mite_chan
,
552 struct comedi_async
*async
)
555 unsigned int nbytes
, old_alloc_count
;
556 const unsigned bytes_per_scan
= cfc_bytes_per_scan(async
->subdevice
);
558 old_alloc_count
= async
->buf_write_alloc_count
;
559 /* write alloc as much as we can */
560 comedi_buf_write_alloc(async
, async
->prealloc_bufsz
);
562 nbytes
= mite_bytes_written_to_memory_lb(mite_chan
);
563 if ((int)(mite_bytes_written_to_memory_ub(mite_chan
) -
564 old_alloc_count
) > 0) {
565 dev_warn(async
->subdevice
->device
->class_dev
,
566 "mite: DMA overwrite of free area\n");
567 async
->events
|= COMEDI_CB_OVERFLOW
;
571 count
= nbytes
- async
->buf_write_count
;
572 /* it's possible count will be negative due to
573 * conservative value returned by mite_bytes_written_to_memory_lb */
577 comedi_buf_write_free(async
, count
);
579 async
->scan_progress
+= count
;
580 if (async
->scan_progress
>= bytes_per_scan
) {
581 async
->scan_progress
%= bytes_per_scan
;
582 async
->events
|= COMEDI_CB_EOS
;
584 async
->events
|= COMEDI_CB_BLOCK
;
587 EXPORT_SYMBOL(mite_sync_input_dma
);
589 int mite_sync_output_dma(struct mite_channel
*mite_chan
,
590 struct comedi_async
*async
)
593 u32 nbytes_ub
, nbytes_lb
;
594 unsigned int old_alloc_count
;
596 async
->cmd
.stop_arg
* cfc_bytes_per_scan(async
->subdevice
);
598 old_alloc_count
= async
->buf_read_alloc_count
;
599 /* read alloc as much as we can */
600 comedi_buf_read_alloc(async
, async
->prealloc_bufsz
);
601 nbytes_lb
= mite_bytes_read_from_memory_lb(mite_chan
);
602 if (async
->cmd
.stop_src
== TRIG_COUNT
&&
603 (int)(nbytes_lb
- stop_count
) > 0)
604 nbytes_lb
= stop_count
;
605 nbytes_ub
= mite_bytes_read_from_memory_ub(mite_chan
);
606 if (async
->cmd
.stop_src
== TRIG_COUNT
&&
607 (int)(nbytes_ub
- stop_count
) > 0)
608 nbytes_ub
= stop_count
;
609 if ((int)(nbytes_ub
- old_alloc_count
) > 0) {
610 dev_warn(async
->subdevice
->device
->class_dev
,
611 "mite: DMA underrun\n");
612 async
->events
|= COMEDI_CB_OVERFLOW
;
615 count
= nbytes_lb
- async
->buf_read_count
;
620 comedi_buf_read_free(async
, count
);
621 async
->events
|= COMEDI_CB_BLOCK
;
625 EXPORT_SYMBOL(mite_sync_output_dma
);
627 unsigned mite_get_status(struct mite_channel
*mite_chan
)
629 struct mite_struct
*mite
= mite_chan
->mite
;
633 spin_lock_irqsave(&mite
->lock
, flags
);
634 status
= readl(mite
->mite_io_addr
+ MITE_CHSR(mite_chan
->channel
));
635 if (status
& CHSR_DONE
) {
638 mite
->mite_io_addr
+ MITE_CHOR(mite_chan
->channel
));
641 spin_unlock_irqrestore(&mite
->lock
, flags
);
644 EXPORT_SYMBOL(mite_get_status
);
646 int mite_done(struct mite_channel
*mite_chan
)
648 struct mite_struct
*mite
= mite_chan
->mite
;
652 mite_get_status(mite_chan
);
653 spin_lock_irqsave(&mite
->lock
, flags
);
654 done
= mite_chan
->done
;
655 spin_unlock_irqrestore(&mite
->lock
, flags
);
658 EXPORT_SYMBOL(mite_done
);
662 /* names of bits in mite registers */
664 static const char *const mite_CHOR_strings
[] = {
665 "start", "cont", "stop", "abort",
666 "freset", "clrlc", "clrrb", "clrdone",
667 "clr_lpause", "set_lpause", "clr_send_tc",
668 "set_send_tc", "12", "13", "14",
669 "15", "16", "17", "18",
670 "19", "20", "21", "22",
671 "23", "24", "25", "26",
672 "27", "28", "29", "30",
676 static const char *const mite_CHCR_strings
[] = {
677 "continue", "ringbuff", "2", "3",
679 "8", "9", "10", "11",
680 "12", "13", "bursten", "fifodis",
681 "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
682 "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
683 "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
684 "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
687 static const char *const mite_MCR_strings
[] = {
688 "amdevice", "1", "2", "3",
689 "4", "5", "portio", "portvxi",
690 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
691 "12", "13", "blocken", "berhand",
692 "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
693 "rd512", "rl1", "rl2", "rl8",
694 "24", "25", "26", "27",
695 "28", "29", "30", "stopen",
698 static const char *const mite_DCR_strings
[] = {
699 "amdevice", "1", "2", "3",
700 "4", "5", "portio", "portvxi",
701 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
702 "aseqxp8", "13", "blocken", "berhand",
703 "reqsintlim", "reqs1", "reqs2", "rd32",
704 "rd512", "rl1", "rl2", "rl8",
705 "23", "24", "25", "27",
706 "28", "wsdevc", "wsdevs", "rwdevpack",
709 static const char *const mite_LKCR_strings
[] = {
710 "amdevice", "1", "2", "3",
711 "4", "5", "portio", "portvxi",
712 "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
713 "12", "13", "14", "berhand",
714 "16", "17", "18", "rd32",
715 "rd512", "rl1", "rl2", "rl8",
716 "24", "25", "26", "27",
717 "28", "29", "30", "chngend",
720 static const char *const mite_CHSR_strings
[] = {
721 "d.err0", "d.err1", "m.err0", "m.err1",
722 "l.err0", "l.err1", "drq0", "drq1",
723 "end", "xferr", "operr0", "operr1",
724 "stops", "habort", "sabort", "error",
725 "16", "conts_rb", "18", "linkc",
726 "20", "drdy", "22", "mrdy",
727 "24", "done", "26", "sars",
728 "28", "lpauses", "30", "int",
731 static void mite_decode(const char *const *bit_str
, unsigned int bits
)
735 for (i
= 31; i
>= 0; i
--) {
737 pr_debug(" %s\n", bit_str
[i
]);
741 void mite_dump_regs(struct mite_channel
*mite_chan
)
743 void __iomem
*mite_io_addr
= mite_chan
->mite
->mite_io_addr
;
746 int channel
= mite_chan
->channel
;
748 pr_debug("mite_dump_regs ch%i\n", channel
);
749 pr_debug("mite address is =%p\n", mite_io_addr
);
751 offset
= MITE_CHOR(channel
);
752 value
= readl(mite_io_addr
+ offset
);
753 pr_debug("mite status[CHOR] at 0x%08x =0x%08x\n", offset
, value
);
754 mite_decode(mite_CHOR_strings
, value
);
755 offset
= MITE_CHCR(channel
);
756 value
= readl(mite_io_addr
+ offset
);
757 pr_debug("mite status[CHCR] at 0x%08x =0x%08x\n", offset
, value
);
758 mite_decode(mite_CHCR_strings
, value
);
759 offset
= MITE_TCR(channel
);
760 value
= readl(mite_io_addr
+ offset
);
761 pr_debug("mite status[TCR] at 0x%08x =0x%08x\n", offset
, value
);
762 offset
= MITE_MCR(channel
);
763 value
= readl(mite_io_addr
+ offset
);
764 pr_debug("mite status[MCR] at 0x%08x =0x%08x\n", offset
, value
);
765 mite_decode(mite_MCR_strings
, value
);
766 offset
= MITE_MAR(channel
);
767 value
= readl(mite_io_addr
+ offset
);
768 pr_debug("mite status[MAR] at 0x%08x =0x%08x\n", offset
, value
);
769 offset
= MITE_DCR(channel
);
770 value
= readl(mite_io_addr
+ offset
);
771 pr_debug("mite status[DCR] at 0x%08x =0x%08x\n", offset
, value
);
772 mite_decode(mite_DCR_strings
, value
);
773 offset
= MITE_DAR(channel
);
774 value
= readl(mite_io_addr
+ offset
);
775 pr_debug("mite status[DAR] at 0x%08x =0x%08x\n", offset
, value
);
776 offset
= MITE_LKCR(channel
);
777 value
= readl(mite_io_addr
+ offset
);
778 pr_debug("mite status[LKCR] at 0x%08x =0x%08x\n", offset
, value
);
779 mite_decode(mite_LKCR_strings
, value
);
780 offset
= MITE_LKAR(channel
);
781 value
= readl(mite_io_addr
+ offset
);
782 pr_debug("mite status[LKAR] at 0x%08x =0x%08x\n", offset
, value
);
783 offset
= MITE_CHSR(channel
);
784 value
= readl(mite_io_addr
+ offset
);
785 pr_debug("mite status[CHSR] at 0x%08x =0x%08x\n", offset
, value
);
786 mite_decode(mite_CHSR_strings
, value
);
787 offset
= MITE_FCR(channel
);
788 value
= readl(mite_io_addr
+ offset
);
789 pr_debug("mite status[FCR] at 0x%08x =0x%08x\n", offset
, value
);
791 EXPORT_SYMBOL(mite_dump_regs
);
794 static int __init
mite_module_init(void)
799 static void __exit
mite_module_exit(void)
803 module_init(mite_module_init
);
804 module_exit(mite_module_exit
);
806 MODULE_AUTHOR("Comedi http://www.comedi.org");
807 MODULE_DESCRIPTION("Comedi low-level driver");
808 MODULE_LICENSE("GPL");