drivers/staging/comedi/drivers/mite.h

   1 /*
   2  * module/mite.h
   3  * Hardware driver for NI Mite PCI interface chip
   4  *
   5  * COMEDI - Linux Control and Measurement Device Interface
   6  * Copyright (C) 1999 David A. Schleef <ds@schleef.org>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #ifndef _MITE_H_
  20 #define _MITE_H_
  21
  22 #include <linux/io.h>
  23 #include <linux/log2.h>
  24 #include <linux/spinlock.h>
  25
  26 #define MAX_MITE_DMA_CHANNELS 8
  27
  28 struct comedi_device;
  29 struct comedi_subdevice;
  30 struct device;
  31 struct pci_dev;
  32
  33 struct mite_dma_descriptor {
  34         __le32 count;
  35         __le32 addr;
  36         __le32 next;
  37         u32 dar;
  38 };
  39
  40 struct mite_dma_descriptor_ring {
  41         struct device *hw_dev;
  42         unsigned int n_links;
  43         struct mite_dma_descriptor *descriptors;
  44         dma_addr_t descriptors_dma_addr;
  45 };
  46
  47 struct mite_channel {
  48         struct mite_struct *mite;
  49         unsigned channel;
  50         int dir;
  51         int done;
  52         struct mite_dma_descriptor_ring *ring;
  53 };
  54
  55 struct mite_struct {
  56         struct pci_dev *pcidev;
  57         resource_size_t mite_phys_addr;
  58         void __iomem *mite_io_addr;
  59         resource_size_t daq_phys_addr;
  60         struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
  61         short channel_allocated[MAX_MITE_DMA_CHANNELS];
  62         int num_channels;
  63         unsigned fifo_size;
  64         spinlock_t lock;
  65 };
  66
  67 struct mite_struct *mite_alloc(struct pci_dev *pcidev);
  68
  69 int mite_setup2(struct comedi_device *, struct mite_struct *, bool use_win1);
  70
  71 static inline int mite_setup(struct comedi_device *dev,
  72                              struct mite_struct *mite)
  73 {
  74         return mite_setup2(dev, mite, false);
  75 }
  76
  77 void mite_detach(struct mite_struct *mite);
  78 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite);
  79 void mite_free_ring(struct mite_dma_descriptor_ring *ring);
  80 struct mite_channel *
  81 mite_request_channel_in_range(struct mite_struct *mite,
  82                               struct mite_dma_descriptor_ring *ring,
  83                               unsigned min_channel, unsigned max_channel);
  84 static inline struct mite_channel *
  85 mite_request_channel(struct mite_struct *mite,
  86                      struct mite_dma_descriptor_ring *ring)
  87 {
  88         return mite_request_channel_in_range(mite, ring, 0,
  89                                              mite->num_channels - 1);
  90 }
  91
  92 void mite_release_channel(struct mite_channel *mite_chan);
  93
  94 unsigned mite_dma_tcr(struct mite_channel *mite_chan);
  95 void mite_dma_arm(struct mite_channel *mite_chan);
  96 void mite_dma_disarm(struct mite_channel *mite_chan);
  97 int mite_sync_input_dma(struct mite_channel *mite_chan,
  98                         struct comedi_subdevice *s);
  99 int mite_sync_output_dma(struct mite_channel *mite_chan,
 100                          struct comedi_subdevice *s);
 101 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
 102 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
 103 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
 104 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
 105 u32 mite_bytes_in_transit(struct mite_channel *mite_chan);
 106 unsigned mite_get_status(struct mite_channel *mite_chan);
 107 int mite_done(struct mite_channel *mite_chan);
 108
 109 void mite_prep_dma(struct mite_channel *mite_chan,
 110                    unsigned int num_device_bits, unsigned int num_memory_bits);
 111 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
 112                     struct comedi_subdevice *s);
 113
 114 enum mite_registers {
 115         /*
 116          * The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
 117          * written and read back.  The bits 0x1f always read as 1.
 118          * The rest always read as zero.
 119          */
 120         MITE_UNKNOWN_DMA_BURST_REG = 0x28,
 121         MITE_IODWBSR = 0xc0,    /* IO Device Window Base Size Register */
 122         MITE_IODWBSR_1 = 0xc4,  /* IO Device Window Base Size Register 1 */
 123         MITE_IODWCR_1 = 0xf4,
 124         MITE_PCI_CONFIG_OFFSET = 0x300,
 125         MITE_CSIGR = 0x460      /* chip signature */
 126 };
 127
 128 #define MITE_CHAN(x)    (0x500 + 0x100 * (x))
 129 #define MITE_CHOR(x)    (0x00 + MITE_CHAN(x))   /* channel operation */
 130 #define MITE_CHCR(x)    (0x04 + MITE_CHAN(x))   /* channel control */
 131 #define MITE_TCR(x)     (0x08 + MITE_CHAN(x))   /* transfer count */
 132 #define MITE_MCR(x)     (0x0c + MITE_CHAN(x))   /* memory configuration */
 133 #define MITE_MAR(x)     (0x10 + MITE_CHAN(x))   /* memory address */
 134 #define MITE_DCR(x)     (0x14 + MITE_CHAN(x))   /* device configuration */
 135 #define MITE_DAR(x)     (0x18 + MITE_CHAN(x))   /* device address */
 136 #define MITE_LKCR(x)    (0x1c + MITE_CHAN(x))   /* link configuration */
 137 #define MITE_LKAR(x)    (0x20 + MITE_CHAN(x))   /* link address */
 138 #define MITE_LLKAR(x)   (0x24 + MITE_CHAN(x))   /* see tnt5002 manual */
 139 #define MITE_BAR(x)     (0x28 + MITE_CHAN(x))   /* base address */
 140 #define MITE_BCR(x)     (0x2c + MITE_CHAN(x))   /* base count */
 141 #define MITE_SAR(x)     (0x30 + MITE_CHAN(x))   /* ? address */
 142 #define MITE_WSCR(x)    (0x34 + MITE_CHAN(x))   /* ? */
 143 #define MITE_WSER(x)    (0x38 + MITE_CHAN(x))   /* ? */
 144 #define MITE_CHSR(x)    (0x3c + MITE_CHAN(x))   /* channel status */
 145 #define MITE_FCR(x)     (0x40 + MITE_CHAN(x))   /* fifo count */
 146
 147 enum MITE_IODWBSR_bits {
 148         WENAB = 0x80,           /* window enable */
 149 };
 150
 151 static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
 152 {
 153         unsigned order = 0;
 154
 155         BUG_ON(size == 0);
 156         order = ilog2(size);
 157         BUG_ON(order < 1);
 158         return (order - 1) & 0x1f;
 159 }
 160
 161 enum MITE_UNKNOWN_DMA_BURST_bits {
 162         UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
 163 };
 164
 165 static inline int mite_csigr_version(u32 csigr_bits)
 166 {
 167         return csigr_bits & 0xf;
 168 };
 169
 170 static inline int mite_csigr_type(u32 csigr_bits)
 171 {                               /* original mite = 0, minimite = 1 */
 172         return (csigr_bits >> 4) & 0xf;
 173 };
 174
 175 static inline int mite_csigr_mmode(u32 csigr_bits)
 176 {                               /* mite mode, minimite = 1 */
 177         return (csigr_bits >> 8) & 0x3;
 178 };
 179
 180 static inline int mite_csigr_imode(u32 csigr_bits)
 181 {                               /* cpu port interface mode, pci = 0x3 */
 182         return (csigr_bits >> 12) & 0x3;
 183 };
 184
 185 static inline int mite_csigr_dmac(u32 csigr_bits)
 186 {                               /* number of dma channels */
 187         return (csigr_bits >> 16) & 0xf;
 188 };
 189
 190 static inline int mite_csigr_wpdep(u32 csigr_bits)
 191 {                               /* write post fifo depth */
 192         unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
 193
 194         return (wpdep_bits) ? (1 << (wpdep_bits - 1)) : 0;
 195 }
 196
 197 static inline int mite_csigr_wins(u32 csigr_bits)
 198 {
 199         return (csigr_bits >> 24) & 0x1f;
 200 };
 201
 202 static inline int mite_csigr_iowins(u32 csigr_bits)
 203 {                               /* number of io windows */
 204         return (csigr_bits >> 29) & 0x7;
 205 };
 206
 207 enum MITE_MCR_bits {
 208         MCRPON = 0,
 209 };
 210
 211 enum MITE_DCR_bits {
 212         DCR_NORMAL = (1 << 29),
 213         DCRPON = 0,
 214 };
 215
 216 enum MITE_CHOR_bits {
 217         CHOR_DMARESET = (1 << 31),
 218         CHOR_SET_SEND_TC = (1 << 11),
 219         CHOR_CLR_SEND_TC = (1 << 10),
 220         CHOR_SET_LPAUSE = (1 << 9),
 221         CHOR_CLR_LPAUSE = (1 << 8),
 222         CHOR_CLRDONE = (1 << 7),
 223         CHOR_CLRRB = (1 << 6),
 224         CHOR_CLRLC = (1 << 5),
 225         CHOR_FRESET = (1 << 4),
 226         CHOR_ABORT = (1 << 3),  /* stop without emptying fifo */
 227         CHOR_STOP = (1 << 2),   /* stop after emptying fifo */
 228         CHOR_CONT = (1 << 1),
 229         CHOR_START = (1 << 0),
 230         CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
 231 };
 232
 233 enum MITE_CHCR_bits {
 234         CHCR_SET_DMA_IE = (1 << 31),
 235         CHCR_CLR_DMA_IE = (1 << 30),
 236         CHCR_SET_LINKP_IE = (1 << 29),
 237         CHCR_CLR_LINKP_IE = (1 << 28),
 238         CHCR_SET_SAR_IE = (1 << 27),
 239         CHCR_CLR_SAR_IE = (1 << 26),
 240         CHCR_SET_DONE_IE = (1 << 25),
 241         CHCR_CLR_DONE_IE = (1 << 24),
 242         CHCR_SET_MRDY_IE = (1 << 23),
 243         CHCR_CLR_MRDY_IE = (1 << 22),
 244         CHCR_SET_DRDY_IE = (1 << 21),
 245         CHCR_CLR_DRDY_IE = (1 << 20),
 246         CHCR_SET_LC_IE = (1 << 19),
 247         CHCR_CLR_LC_IE = (1 << 18),
 248         CHCR_SET_CONT_RB_IE = (1 << 17),
 249         CHCR_CLR_CONT_RB_IE = (1 << 16),
 250         CHCR_FIFODIS = (1 << 15),
 251         CHCR_FIFO_ON = 0,
 252         CHCR_BURSTEN = (1 << 14),
 253         CHCR_NO_BURSTEN = 0,
 254         CHCR_BYTE_SWAP_DEVICE = (1 << 6),
 255         CHCR_BYTE_SWAP_MEMORY = (1 << 4),
 256         CHCR_DIR = (1 << 3),
 257         CHCR_DEV_TO_MEM = CHCR_DIR,
 258         CHCR_MEM_TO_DEV = 0,
 259         CHCR_NORMAL = (0 << 0),
 260         CHCR_CONTINUE = (1 << 0),
 261         CHCR_RINGBUFF = (2 << 0),
 262         CHCR_LINKSHORT = (4 << 0),
 263         CHCR_LINKLONG = (5 << 0),
 264         CHCRPON =
 265             (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
 266              CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 267              CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
 268 };
 269
 270 enum ConfigRegister_bits {
 271         CR_REQS_MASK = 0x7 << 16,
 272         CR_ASEQDONT = 0x0 << 10,
 273         CR_ASEQUP = 0x1 << 10,
 274         CR_ASEQDOWN = 0x2 << 10,
 275         CR_ASEQ_MASK = 0x3 << 10,
 276         CR_PSIZE8 = (1 << 8),
 277         CR_PSIZE16 = (2 << 8),
 278         CR_PSIZE32 = (3 << 8),
 279         CR_PORTCPU = (0 << 6),
 280         CR_PORTIO = (1 << 6),
 281         CR_PORTVXI = (2 << 6),
 282         CR_PORTMXI = (3 << 6),
 283         CR_AMDEVICE = (1 << 0),
 284 };
 285
 286 static inline int CR_REQS(int source)
 287 {
 288         return (source & 0x7) << 16;
 289 };
 290
 291 static inline int CR_REQSDRQ(unsigned drq_line)
 292 {
 293         /* This also works on m-series when using channels (drq_line) 4 or 5. */
 294         return CR_REQS((drq_line & 0x3) | 0x4);
 295 }
 296
 297 static inline int CR_RL(unsigned int retry_limit)
 298 {
 299         int value = 0;
 300
 301         if (retry_limit)
 302                 value = 1 + ilog2(retry_limit);
 303         if (value > 0x7)
 304                 value = 0x7;
 305         return (value & 0x7) << 21;
 306 }
 307
 308 enum CHSR_bits {
 309         CHSR_INT = (1 << 31),
 310         CHSR_LPAUSES = (1 << 29),
 311         CHSR_SARS = (1 << 27),
 312         CHSR_DONE = (1 << 25),
 313         CHSR_MRDY = (1 << 23),
 314         CHSR_DRDY = (1 << 21),
 315         CHSR_LINKC = (1 << 19),
 316         CHSR_CONTS_RB = (1 << 17),
 317         CHSR_ERROR = (1 << 15),
 318         CHSR_SABORT = (1 << 14),
 319         CHSR_HABORT = (1 << 13),
 320         CHSR_STOPS = (1 << 12),
 321         CHSR_OPERR_mask = (3 << 10),
 322         CHSR_OPERR_NOERROR = (0 << 10),
 323         CHSR_OPERR_FIFOERROR = (1 << 10),
 324         CHSR_OPERR_LINKERROR = (1 << 10),       /* ??? */
 325         CHSR_XFERR = (1 << 9),
 326         CHSR_END = (1 << 8),
 327         CHSR_DRQ1 = (1 << 7),
 328         CHSR_DRQ0 = (1 << 6),
 329         CHSR_LxERR_mask = (3 << 4),
 330         CHSR_LBERR = (1 << 4),
 331         CHSR_LRERR = (2 << 4),
 332         CHSR_LOERR = (3 << 4),
 333         CHSR_MxERR_mask = (3 << 2),
 334         CHSR_MBERR = (1 << 2),
 335         CHSR_MRERR = (2 << 2),
 336         CHSR_MOERR = (3 << 2),
 337         CHSR_DxERR_mask = (3 << 0),
 338         CHSR_DBERR = (1 << 0),
 339         CHSR_DRERR = (2 << 0),
 340         CHSR_DOERR = (3 << 0),
 341 };
 342
 343 static inline void mite_dma_reset(struct mite_channel *mite_chan)
 344 {
 345         writel(CHOR_DMARESET | CHOR_FRESET,
 346                mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 347 };
 348
 349 #endif