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staging: comedi: remove FSF address from boilerplate text
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_65xx.c
1 /*
2 comedi/drivers/ni_6514.c
3 driver for National Instruments PCI-6514
4
5 Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
6 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20 */
21 /*
22 Driver: ni_65xx
23 Description: National Instruments 65xx static dio boards
24 Author: Jon Grierson <jd@renko.co.uk>,
25 Frank Mori Hess <fmhess@users.sourceforge.net>
26 Status: testing
27 Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510,
28 PCI-6511, PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514,
29 PXI-6514, PCI-6515, PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519,
30 PCI-6520, PCI-6521, PXI-6521, PCI-6528, PXI-6528
31 Updated: Wed Oct 18 08:59:11 EDT 2006
32
33 Based on the PCI-6527 driver by ds.
34 The interrupt subdevice (subdevice 3) is probably broken for all boards
35 except maybe the 6514.
36
37 */
38
39 /*
40 Manuals (available from ftp://ftp.natinst.com/support/manuals)
41
42 370106b.pdf 6514 Register Level Programmer Manual
43
44 */
45
46 #define DEBUG 1
47 #define DEBUG_FLAGS
48
49 #include <linux/pci.h>
50 #include <linux/interrupt.h>
51 #include <linux/slab.h>
52
53 #include "../comedidev.h"
54
55 #include "comedi_fc.h"
56 #include "mite.h"
57
58 #define NI6514_DIO_SIZE 4096
59 #define NI6514_MITE_SIZE 4096
60
61 #define NI_65XX_MAX_NUM_PORTS 12
62 static const unsigned ni_65xx_channels_per_port = 8;
63 static const unsigned ni_65xx_port_offset = 0x10;
64
65 static inline unsigned Port_Data(unsigned port)
66 {
67 return 0x40 + port * ni_65xx_port_offset;
68 }
69
70 static inline unsigned Port_Select(unsigned port)
71 {
72 return 0x41 + port * ni_65xx_port_offset;
73 }
74
75 static inline unsigned Rising_Edge_Detection_Enable(unsigned port)
76 {
77 return 0x42 + port * ni_65xx_port_offset;
78 }
79
80 static inline unsigned Falling_Edge_Detection_Enable(unsigned port)
81 {
82 return 0x43 + port * ni_65xx_port_offset;
83 }
84
85 static inline unsigned Filter_Enable(unsigned port)
86 {
87 return 0x44 + port * ni_65xx_port_offset;
88 }
89
90 #define ID_Register 0x00
91
92 #define Clear_Register 0x01
93 #define ClrEdge 0x08
94 #define ClrOverflow 0x04
95
96 #define Filter_Interval 0x08
97
98 #define Change_Status 0x02
99 #define MasterInterruptStatus 0x04
100 #define Overflow 0x02
101 #define EdgeStatus 0x01
102
103 #define Master_Interrupt_Control 0x03
104 #define FallingEdgeIntEnable 0x10
105 #define RisingEdgeIntEnable 0x08
106 #define MasterInterruptEnable 0x04
107 #define OverflowIntEnable 0x02
108 #define EdgeIntEnable 0x01
109
110 enum ni_65xx_boardid {
111 BOARD_PCI6509,
112 BOARD_PXI6509,
113 BOARD_PCI6510,
114 BOARD_PCI6511,
115 BOARD_PXI6511,
116 BOARD_PCI6512,
117 BOARD_PXI6512,
118 BOARD_PCI6513,
119 BOARD_PXI6513,
120 BOARD_PCI6514,
121 BOARD_PXI6514,
122 BOARD_PCI6515,
123 BOARD_PXI6515,
124 BOARD_PCI6516,
125 BOARD_PCI6517,
126 BOARD_PCI6518,
127 BOARD_PCI6519,
128 BOARD_PCI6520,
129 BOARD_PCI6521,
130 BOARD_PXI6521,
131 BOARD_PCI6528,
132 BOARD_PXI6528,
133 };
134
135 struct ni_65xx_board {
136 const char *name;
137 unsigned num_dio_ports;
138 unsigned num_di_ports;
139 unsigned num_do_ports;
140 unsigned invert_outputs:1;
141 };
142
143 static const struct ni_65xx_board ni_65xx_boards[] = {
144 [BOARD_PCI6509] = {
145 .name = "pci-6509",
146 .num_dio_ports = 12,
147 },
148 [BOARD_PXI6509] = {
149 .name = "pxi-6509",
150 .num_dio_ports = 12,
151 },
152 [BOARD_PCI6510] = {
153 .name = "pci-6510",
154 .num_di_ports = 4,
155 },
156 [BOARD_PCI6511] = {
157 .name = "pci-6511",
158 .num_di_ports = 8,
159 },
160 [BOARD_PXI6511] = {
161 .name = "pxi-6511",
162 .num_di_ports = 8,
163 },
164 [BOARD_PCI6512] = {
165 .name = "pci-6512",
166 .num_do_ports = 8,
167 },
168 [BOARD_PXI6512] = {
169 .name = "pxi-6512",
170 .num_do_ports = 8,
171 },
172 [BOARD_PCI6513] = {
173 .name = "pci-6513",
174 .num_do_ports = 8,
175 .invert_outputs = 1,
176 },
177 [BOARD_PXI6513] = {
178 .name = "pxi-6513",
179 .num_do_ports = 8,
180 .invert_outputs = 1,
181 },
182 [BOARD_PCI6514] = {
183 .name = "pci-6514",
184 .num_di_ports = 4,
185 .num_do_ports = 4,
186 .invert_outputs = 1,
187 },
188 [BOARD_PXI6514] = {
189 .name = "pxi-6514",
190 .num_di_ports = 4,
191 .num_do_ports = 4,
192 .invert_outputs = 1,
193 },
194 [BOARD_PCI6515] = {
195 .name = "pci-6515",
196 .num_di_ports = 4,
197 .num_do_ports = 4,
198 .invert_outputs = 1,
199 },
200 [BOARD_PXI6515] = {
201 .name = "pxi-6515",
202 .num_di_ports = 4,
203 .num_do_ports = 4,
204 .invert_outputs = 1,
205 },
206 [BOARD_PCI6516] = {
207 .name = "pci-6516",
208 .num_do_ports = 4,
209 .invert_outputs = 1,
210 },
211 [BOARD_PCI6517] = {
212 .name = "pci-6517",
213 .num_do_ports = 4,
214 .invert_outputs = 1,
215 },
216 [BOARD_PCI6518] = {
217 .name = "pci-6518",
218 .num_di_ports = 2,
219 .num_do_ports = 2,
220 .invert_outputs = 1,
221 },
222 [BOARD_PCI6519] = {
223 .name = "pci-6519",
224 .num_di_ports = 2,
225 .num_do_ports = 2,
226 .invert_outputs = 1,
227 },
228 [BOARD_PCI6520] = {
229 .name = "pci-6520",
230 .num_di_ports = 1,
231 .num_do_ports = 1,
232 },
233 [BOARD_PCI6521] = {
234 .name = "pci-6521",
235 .num_di_ports = 1,
236 .num_do_ports = 1,
237 },
238 [BOARD_PXI6521] = {
239 .name = "pxi-6521",
240 .num_di_ports = 1,
241 .num_do_ports = 1,
242 },
243 [BOARD_PCI6528] = {
244 .name = "pci-6528",
245 .num_di_ports = 3,
246 .num_do_ports = 3,
247 },
248 [BOARD_PXI6528] = {
249 .name = "pxi-6528",
250 .num_di_ports = 3,
251 .num_do_ports = 3,
252 },
253 };
254
255 static inline unsigned ni_65xx_port_by_channel(unsigned channel)
256 {
257 return channel / ni_65xx_channels_per_port;
258 }
259
260 static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
261 *board)
262 {
263 return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
264 }
265
266 struct ni_65xx_private {
267 struct mite_struct *mite;
268 unsigned int filter_interval;
269 unsigned short filter_enable[NI_65XX_MAX_NUM_PORTS];
270 unsigned short output_bits[NI_65XX_MAX_NUM_PORTS];
271 unsigned short dio_direction[NI_65XX_MAX_NUM_PORTS];
272 };
273
274 struct ni_65xx_subdevice_private {
275 unsigned base_port;
276 };
277
278 static inline struct ni_65xx_subdevice_private *sprivate(struct comedi_subdevice
279 *subdev)
280 {
281 return subdev->private;
282 }
283
284 static struct ni_65xx_subdevice_private *ni_65xx_alloc_subdevice_private(void)
285 {
286 struct ni_65xx_subdevice_private *subdev_private =
287 kzalloc(sizeof(struct ni_65xx_subdevice_private), GFP_KERNEL);
288 if (subdev_private == NULL)
289 return NULL;
290 return subdev_private;
291 }
292
293 static int ni_65xx_config_filter(struct comedi_device *dev,
294 struct comedi_subdevice *s,
295 struct comedi_insn *insn, unsigned int *data)
296 {
297 struct ni_65xx_private *devpriv = dev->private;
298 const unsigned chan = CR_CHAN(insn->chanspec);
299 const unsigned port =
300 sprivate(s)->base_port + ni_65xx_port_by_channel(chan);
301
302 if (data[0] != INSN_CONFIG_FILTER)
303 return -EINVAL;
304 if (data[1]) {
305 static const unsigned filter_resolution_ns = 200;
306 static const unsigned max_filter_interval = 0xfffff;
307 unsigned interval =
308 (data[1] +
309 (filter_resolution_ns / 2)) / filter_resolution_ns;
310 if (interval > max_filter_interval)
311 interval = max_filter_interval;
312 data[1] = interval * filter_resolution_ns;
313
314 if (interval != devpriv->filter_interval) {
315 writeb(interval,
316 devpriv->mite->daq_io_addr +
317 Filter_Interval);
318 devpriv->filter_interval = interval;
319 }
320
321 devpriv->filter_enable[port] |=
322 1 << (chan % ni_65xx_channels_per_port);
323 } else {
324 devpriv->filter_enable[port] &=
325 ~(1 << (chan % ni_65xx_channels_per_port));
326 }
327
328 writeb(devpriv->filter_enable[port],
329 devpriv->mite->daq_io_addr + Filter_Enable(port));
330
331 return 2;
332 }
333
334 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
335 struct comedi_subdevice *s,
336 struct comedi_insn *insn, unsigned int *data)
337 {
338 struct ni_65xx_private *devpriv = dev->private;
339 unsigned port;
340
341 if (insn->n < 1)
342 return -EINVAL;
343 port = sprivate(s)->base_port +
344 ni_65xx_port_by_channel(CR_CHAN(insn->chanspec));
345 switch (data[0]) {
346 case INSN_CONFIG_FILTER:
347 return ni_65xx_config_filter(dev, s, insn, data);
348 break;
349 case INSN_CONFIG_DIO_OUTPUT:
350 if (s->type != COMEDI_SUBD_DIO)
351 return -EINVAL;
352 devpriv->dio_direction[port] = COMEDI_OUTPUT;
353 writeb(0, devpriv->mite->daq_io_addr + Port_Select(port));
354 return 1;
355 break;
356 case INSN_CONFIG_DIO_INPUT:
357 if (s->type != COMEDI_SUBD_DIO)
358 return -EINVAL;
359 devpriv->dio_direction[port] = COMEDI_INPUT;
360 writeb(1, devpriv->mite->daq_io_addr + Port_Select(port));
361 return 1;
362 break;
363 case INSN_CONFIG_DIO_QUERY:
364 if (s->type != COMEDI_SUBD_DIO)
365 return -EINVAL;
366 data[1] = devpriv->dio_direction[port];
367 return insn->n;
368 break;
369 default:
370 break;
371 }
372 return -EINVAL;
373 }
374
375 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
376 struct comedi_subdevice *s,
377 struct comedi_insn *insn, unsigned int *data)
378 {
379 const struct ni_65xx_board *board = comedi_board(dev);
380 struct ni_65xx_private *devpriv = dev->private;
381 unsigned base_bitfield_channel;
382 const unsigned max_ports_per_bitfield = 5;
383 unsigned read_bits = 0;
384 unsigned j;
385
386 base_bitfield_channel = CR_CHAN(insn->chanspec);
387 for (j = 0; j < max_ports_per_bitfield; ++j) {
388 const unsigned port_offset =
389 ni_65xx_port_by_channel(base_bitfield_channel) + j;
390 const unsigned port =
391 sprivate(s)->base_port + port_offset;
392 unsigned base_port_channel;
393 unsigned port_mask, port_data, port_read_bits;
394 int bitshift;
395 if (port >= ni_65xx_total_num_ports(board))
396 break;
397 base_port_channel = port_offset * ni_65xx_channels_per_port;
398 port_mask = data[0];
399 port_data = data[1];
400 bitshift = base_port_channel - base_bitfield_channel;
401 if (bitshift >= 32 || bitshift <= -32)
402 break;
403 if (bitshift > 0) {
404 port_mask >>= bitshift;
405 port_data >>= bitshift;
406 } else {
407 port_mask <<= -bitshift;
408 port_data <<= -bitshift;
409 }
410 port_mask &= 0xff;
411 port_data &= 0xff;
412 if (port_mask) {
413 unsigned bits;
414 devpriv->output_bits[port] &= ~port_mask;
415 devpriv->output_bits[port] |=
416 port_data & port_mask;
417 bits = devpriv->output_bits[port];
418 if (board->invert_outputs)
419 bits = ~bits;
420 writeb(bits,
421 devpriv->mite->daq_io_addr +
422 Port_Data(port));
423 }
424 port_read_bits =
425 readb(devpriv->mite->daq_io_addr + Port_Data(port));
426 if (s->type == COMEDI_SUBD_DO && board->invert_outputs) {
427 /* Outputs inverted, so invert value read back from
428 * DO subdevice. (Does not apply to boards with DIO
429 * subdevice.) */
430 port_read_bits ^= 0xFF;
431 }
432 if (bitshift > 0)
433 port_read_bits <<= bitshift;
434 else
435 port_read_bits >>= -bitshift;
436
437 read_bits |= port_read_bits;
438 }
439 data[1] = read_bits;
440 return insn->n;
441 }
442
443 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
444 {
445 struct comedi_device *dev = d;
446 struct ni_65xx_private *devpriv = dev->private;
447 struct comedi_subdevice *s = &dev->subdevices[2];
448 unsigned int status;
449
450 status = readb(devpriv->mite->daq_io_addr + Change_Status);
451 if ((status & MasterInterruptStatus) == 0)
452 return IRQ_NONE;
453 if ((status & EdgeStatus) == 0)
454 return IRQ_NONE;
455
456 writeb(ClrEdge | ClrOverflow,
457 devpriv->mite->daq_io_addr + Clear_Register);
458
459 comedi_buf_put(s->async, 0);
460 s->async->events |= COMEDI_CB_EOS;
461 comedi_event(dev, s);
462 return IRQ_HANDLED;
463 }
464
465 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
466 struct comedi_subdevice *s,
467 struct comedi_cmd *cmd)
468 {
469 int err = 0;
470
471 /* Step 1 : check if triggers are trivially valid */
472
473 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
474 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
475 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
476 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
477 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
478
479 if (err)
480 return 1;
481
482 /* Step 2a : make sure trigger sources are unique */
483 /* Step 2b : and mutually compatible */
484
485 if (err)
486 return 2;
487
488 /* Step 3: check if arguments are trivially valid */
489
490 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
491 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
492 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
493 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
494 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
495
496 if (err)
497 return 3;
498
499 /* step 4: fix up any arguments */
500
501 if (err)
502 return 4;
503
504 return 0;
505 }
506
507 static int ni_65xx_intr_cmd(struct comedi_device *dev,
508 struct comedi_subdevice *s)
509 {
510 struct ni_65xx_private *devpriv = dev->private;
511 /* struct comedi_cmd *cmd = &s->async->cmd; */
512
513 writeb(ClrEdge | ClrOverflow,
514 devpriv->mite->daq_io_addr + Clear_Register);
515 writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
516 MasterInterruptEnable | EdgeIntEnable,
517 devpriv->mite->daq_io_addr + Master_Interrupt_Control);
518
519 return 0;
520 }
521
522 static int ni_65xx_intr_cancel(struct comedi_device *dev,
523 struct comedi_subdevice *s)
524 {
525 struct ni_65xx_private *devpriv = dev->private;
526
527 writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
528
529 return 0;
530 }
531
532 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
533 struct comedi_subdevice *s,
534 struct comedi_insn *insn, unsigned int *data)
535 {
536 data[1] = 0;
537 return insn->n;
538 }
539
540 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
541 struct comedi_subdevice *s,
542 struct comedi_insn *insn,
543 unsigned int *data)
544 {
545 struct ni_65xx_private *devpriv = dev->private;
546
547 if (insn->n < 1)
548 return -EINVAL;
549 if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
550 return -EINVAL;
551
552 writeb(data[1],
553 devpriv->mite->daq_io_addr +
554 Rising_Edge_Detection_Enable(0));
555 writeb(data[1] >> 8,
556 devpriv->mite->daq_io_addr +
557 Rising_Edge_Detection_Enable(0x10));
558 writeb(data[1] >> 16,
559 devpriv->mite->daq_io_addr +
560 Rising_Edge_Detection_Enable(0x20));
561 writeb(data[1] >> 24,
562 devpriv->mite->daq_io_addr +
563 Rising_Edge_Detection_Enable(0x30));
564
565 writeb(data[2],
566 devpriv->mite->daq_io_addr +
567 Falling_Edge_Detection_Enable(0));
568 writeb(data[2] >> 8,
569 devpriv->mite->daq_io_addr +
570 Falling_Edge_Detection_Enable(0x10));
571 writeb(data[2] >> 16,
572 devpriv->mite->daq_io_addr +
573 Falling_Edge_Detection_Enable(0x20));
574 writeb(data[2] >> 24,
575 devpriv->mite->daq_io_addr +
576 Falling_Edge_Detection_Enable(0x30));
577
578 return 2;
579 }
580
581 static int ni_65xx_auto_attach(struct comedi_device *dev,
582 unsigned long context)
583 {
584 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
585 const struct ni_65xx_board *board = NULL;
586 struct ni_65xx_private *devpriv;
587 struct comedi_subdevice *s;
588 unsigned i;
589 int ret;
590
591 if (context < ARRAY_SIZE(ni_65xx_boards))
592 board = &ni_65xx_boards[context];
593 if (!board)
594 return -ENODEV;
595 dev->board_ptr = board;
596 dev->board_name = board->name;
597
598 ret = comedi_pci_enable(dev);
599 if (ret)
600 return ret;
601
602 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
603 if (!devpriv)
604 return -ENOMEM;
605 dev->private = devpriv;
606
607 devpriv->mite = mite_alloc(pcidev);
608 if (!devpriv->mite)
609 return -ENOMEM;
610
611 ret = mite_setup(devpriv->mite);
612 if (ret < 0) {
613 dev_warn(dev->class_dev, "error setting up mite\n");
614 return ret;
615 }
616
617 dev->irq = mite_irq(devpriv->mite);
618 dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
619 readb(devpriv->mite->daq_io_addr + ID_Register));
620
621 ret = comedi_alloc_subdevices(dev, 4);
622 if (ret)
623 return ret;
624
625 s = &dev->subdevices[0];
626 if (board->num_di_ports) {
627 s->type = COMEDI_SUBD_DI;
628 s->subdev_flags = SDF_READABLE;
629 s->n_chan =
630 board->num_di_ports * ni_65xx_channels_per_port;
631 s->range_table = &range_digital;
632 s->maxdata = 1;
633 s->insn_config = ni_65xx_dio_insn_config;
634 s->insn_bits = ni_65xx_dio_insn_bits;
635 s->private = ni_65xx_alloc_subdevice_private();
636 if (s->private == NULL)
637 return -ENOMEM;
638 sprivate(s)->base_port = 0;
639 } else {
640 s->type = COMEDI_SUBD_UNUSED;
641 }
642
643 s = &dev->subdevices[1];
644 if (board->num_do_ports) {
645 s->type = COMEDI_SUBD_DO;
646 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
647 s->n_chan =
648 board->num_do_ports * ni_65xx_channels_per_port;
649 s->range_table = &range_digital;
650 s->maxdata = 1;
651 s->insn_bits = ni_65xx_dio_insn_bits;
652 s->private = ni_65xx_alloc_subdevice_private();
653 if (s->private == NULL)
654 return -ENOMEM;
655 sprivate(s)->base_port = board->num_di_ports;
656 } else {
657 s->type = COMEDI_SUBD_UNUSED;
658 }
659
660 s = &dev->subdevices[2];
661 if (board->num_dio_ports) {
662 s->type = COMEDI_SUBD_DIO;
663 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
664 s->n_chan =
665 board->num_dio_ports * ni_65xx_channels_per_port;
666 s->range_table = &range_digital;
667 s->maxdata = 1;
668 s->insn_config = ni_65xx_dio_insn_config;
669 s->insn_bits = ni_65xx_dio_insn_bits;
670 s->private = ni_65xx_alloc_subdevice_private();
671 if (s->private == NULL)
672 return -ENOMEM;
673 sprivate(s)->base_port = 0;
674 for (i = 0; i < board->num_dio_ports; ++i) {
675 /* configure all ports for input */
676 writeb(0x1,
677 devpriv->mite->daq_io_addr +
678 Port_Select(i));
679 }
680 } else {
681 s->type = COMEDI_SUBD_UNUSED;
682 }
683
684 s = &dev->subdevices[3];
685 dev->read_subdev = s;
686 s->type = COMEDI_SUBD_DI;
687 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
688 s->n_chan = 1;
689 s->range_table = &range_unknown;
690 s->maxdata = 1;
691 s->do_cmdtest = ni_65xx_intr_cmdtest;
692 s->do_cmd = ni_65xx_intr_cmd;
693 s->cancel = ni_65xx_intr_cancel;
694 s->insn_bits = ni_65xx_intr_insn_bits;
695 s->insn_config = ni_65xx_intr_insn_config;
696
697 for (i = 0; i < ni_65xx_total_num_ports(board); ++i) {
698 writeb(0x00,
699 devpriv->mite->daq_io_addr + Filter_Enable(i));
700 if (board->invert_outputs)
701 writeb(0x01,
702 devpriv->mite->daq_io_addr + Port_Data(i));
703 else
704 writeb(0x00,
705 devpriv->mite->daq_io_addr + Port_Data(i));
706 }
707 writeb(ClrEdge | ClrOverflow,
708 devpriv->mite->daq_io_addr + Clear_Register);
709 writeb(0x00,
710 devpriv->mite->daq_io_addr + Master_Interrupt_Control);
711
712 /* Set filter interval to 0 (32bit reg) */
713 writeb(0x00000000, devpriv->mite->daq_io_addr + Filter_Interval);
714
715 ret = request_irq(dev->irq, ni_65xx_interrupt, IRQF_SHARED,
716 "ni_65xx", dev);
717 if (ret < 0) {
718 dev->irq = 0;
719 dev_warn(dev->class_dev, "irq not available\n");
720 }
721
722 return 0;
723 }
724
725 static void ni_65xx_detach(struct comedi_device *dev)
726 {
727 struct ni_65xx_private *devpriv = dev->private;
728 int i;
729
730 if (devpriv && devpriv->mite && devpriv->mite->daq_io_addr) {
731 writeb(0x00,
732 devpriv->mite->daq_io_addr +
733 Master_Interrupt_Control);
734 }
735 if (dev->irq)
736 free_irq(dev->irq, dev);
737 for (i = 0; i < dev->n_subdevices; ++i)
738 comedi_spriv_free(dev, i);
739 if (devpriv) {
740 if (devpriv->mite) {
741 mite_unsetup(devpriv->mite);
742 mite_free(devpriv->mite);
743 }
744 }
745 comedi_pci_disable(dev);
746 }
747
748 static struct comedi_driver ni_65xx_driver = {
749 .driver_name = "ni_65xx",
750 .module = THIS_MODULE,
751 .auto_attach = ni_65xx_auto_attach,
752 .detach = ni_65xx_detach,
753 };
754
755 static int ni_65xx_pci_probe(struct pci_dev *dev,
756 const struct pci_device_id *id)
757 {
758 return comedi_pci_auto_config(dev, &ni_65xx_driver, id->driver_data);
759 }
760
761 static DEFINE_PCI_DEVICE_TABLE(ni_65xx_pci_table) = {
762 { PCI_VDEVICE(NI, 0x1710), BOARD_PXI6509 },
763 { PCI_VDEVICE(NI, 0x7085), BOARD_PCI6509 },
764 { PCI_VDEVICE(NI, 0x7086), BOARD_PXI6528 },
765 { PCI_VDEVICE(NI, 0x7087), BOARD_PCI6515 },
766 { PCI_VDEVICE(NI, 0x7088), BOARD_PCI6514 },
767 { PCI_VDEVICE(NI, 0x70a9), BOARD_PCI6528 },
768 { PCI_VDEVICE(NI, 0x70c3), BOARD_PCI6511 },
769 { PCI_VDEVICE(NI, 0x70c8), BOARD_PCI6513 },
770 { PCI_VDEVICE(NI, 0x70c9), BOARD_PXI6515 },
771 { PCI_VDEVICE(NI, 0x70cc), BOARD_PCI6512 },
772 { PCI_VDEVICE(NI, 0x70cd), BOARD_PXI6514 },
773 { PCI_VDEVICE(NI, 0x70d1), BOARD_PXI6513 },
774 { PCI_VDEVICE(NI, 0x70d2), BOARD_PXI6512 },
775 { PCI_VDEVICE(NI, 0x70d3), BOARD_PXI6511 },
776 { PCI_VDEVICE(NI, 0x7124), BOARD_PCI6510 },
777 { PCI_VDEVICE(NI, 0x7125), BOARD_PCI6516 },
778 { PCI_VDEVICE(NI, 0x7126), BOARD_PCI6517 },
779 { PCI_VDEVICE(NI, 0x7127), BOARD_PCI6518 },
780 { PCI_VDEVICE(NI, 0x7128), BOARD_PCI6519 },
781 { PCI_VDEVICE(NI, 0x718b), BOARD_PCI6521 },
782 { PCI_VDEVICE(NI, 0x718c), BOARD_PXI6521 },
783 { PCI_VDEVICE(NI, 0x71c5), BOARD_PCI6520 },
784 { 0 }
785 };
786 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
787
788 static struct pci_driver ni_65xx_pci_driver = {
789 .name = "ni_65xx",
790 .id_table = ni_65xx_pci_table,
791 .probe = ni_65xx_pci_probe,
792 .remove = comedi_pci_auto_unconfig,
793 };
794 module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
795
796 MODULE_AUTHOR("Comedi http://www.comedi.org");
797 MODULE_DESCRIPTION("Comedi low-level driver");
798 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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