2 comedi/drivers/ni_6514.c
3 driver for National Instruments PCI-6514
5 Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
6 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
23 Description: National Instruments 65xx static dio boards
24 Author: Jon Grierson <jd@renko.co.uk>,
25 Frank Mori Hess <fmhess@users.sourceforge.net>
27 Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510,
28 PCI-6511, PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514,
29 PXI-6514, PCI-6515, PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519,
30 PCI-6520, PCI-6521, PXI-6521, PCI-6528, PXI-6528
31 Updated: Wed Oct 18 08:59:11 EDT 2006
33 Based on the PCI-6527 driver by ds.
34 The interrupt subdevice (subdevice 3) is probably broken for all boards
35 except maybe the 6514.
40 Manuals (available from ftp://ftp.natinst.com/support/manuals)
42 370106b.pdf 6514 Register Level Programmer Manual
49 #include <linux/module.h>
50 #include <linux/pci.h>
51 #include <linux/interrupt.h>
53 #include "../comedidev.h"
55 #include "comedi_fc.h"
58 #define NI6514_DIO_SIZE 4096
59 #define NI6514_MITE_SIZE 4096
61 #define NI_65XX_MAX_NUM_PORTS 12
62 static const unsigned ni_65xx_channels_per_port
= 8;
63 static const unsigned ni_65xx_port_offset
= 0x10;
65 static inline unsigned Port_Data(unsigned port
)
67 return 0x40 + port
* ni_65xx_port_offset
;
70 static inline unsigned Port_Select(unsigned port
)
72 return 0x41 + port
* ni_65xx_port_offset
;
75 static inline unsigned Rising_Edge_Detection_Enable(unsigned port
)
77 return 0x42 + port
* ni_65xx_port_offset
;
80 static inline unsigned Falling_Edge_Detection_Enable(unsigned port
)
82 return 0x43 + port
* ni_65xx_port_offset
;
85 static inline unsigned Filter_Enable(unsigned port
)
87 return 0x44 + port
* ni_65xx_port_offset
;
90 #define ID_Register 0x00
92 #define Clear_Register 0x01
94 #define ClrOverflow 0x04
96 #define Filter_Interval 0x08
98 #define Change_Status 0x02
99 #define MasterInterruptStatus 0x04
100 #define Overflow 0x02
101 #define EdgeStatus 0x01
103 #define Master_Interrupt_Control 0x03
104 #define FallingEdgeIntEnable 0x10
105 #define RisingEdgeIntEnable 0x08
106 #define MasterInterruptEnable 0x04
107 #define OverflowIntEnable 0x02
108 #define EdgeIntEnable 0x01
110 enum ni_65xx_boardid
{
135 struct ni_65xx_board
{
137 unsigned num_dio_ports
;
138 unsigned num_di_ports
;
139 unsigned num_do_ports
;
140 unsigned invert_outputs
:1;
143 static const struct ni_65xx_board ni_65xx_boards
[] = {
255 static inline unsigned ni_65xx_port_by_channel(unsigned channel
)
257 return channel
/ ni_65xx_channels_per_port
;
260 static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
263 return board
->num_dio_ports
+ board
->num_di_ports
+ board
->num_do_ports
;
266 struct ni_65xx_private
{
267 struct mite_struct
*mite
;
268 unsigned int filter_interval
;
269 unsigned short filter_enable
[NI_65XX_MAX_NUM_PORTS
];
270 unsigned short output_bits
[NI_65XX_MAX_NUM_PORTS
];
271 unsigned short dio_direction
[NI_65XX_MAX_NUM_PORTS
];
274 struct ni_65xx_subdevice_private
{
278 static inline struct ni_65xx_subdevice_private
*sprivate(struct comedi_subdevice
281 return subdev
->private;
284 static int ni_65xx_config_filter(struct comedi_device
*dev
,
285 struct comedi_subdevice
*s
,
286 struct comedi_insn
*insn
, unsigned int *data
)
288 struct ni_65xx_private
*devpriv
= dev
->private;
289 const unsigned chan
= CR_CHAN(insn
->chanspec
);
290 const unsigned port
=
291 sprivate(s
)->base_port
+ ni_65xx_port_by_channel(chan
);
293 if (data
[0] != INSN_CONFIG_FILTER
)
296 static const unsigned filter_resolution_ns
= 200;
297 static const unsigned max_filter_interval
= 0xfffff;
300 (filter_resolution_ns
/ 2)) / filter_resolution_ns
;
301 if (interval
> max_filter_interval
)
302 interval
= max_filter_interval
;
303 data
[1] = interval
* filter_resolution_ns
;
305 if (interval
!= devpriv
->filter_interval
) {
307 devpriv
->mite
->daq_io_addr
+
309 devpriv
->filter_interval
= interval
;
312 devpriv
->filter_enable
[port
] |=
313 1 << (chan
% ni_65xx_channels_per_port
);
315 devpriv
->filter_enable
[port
] &=
316 ~(1 << (chan
% ni_65xx_channels_per_port
));
319 writeb(devpriv
->filter_enable
[port
],
320 devpriv
->mite
->daq_io_addr
+ Filter_Enable(port
));
325 static int ni_65xx_dio_insn_config(struct comedi_device
*dev
,
326 struct comedi_subdevice
*s
,
327 struct comedi_insn
*insn
, unsigned int *data
)
329 struct ni_65xx_private
*devpriv
= dev
->private;
334 port
= sprivate(s
)->base_port
+
335 ni_65xx_port_by_channel(CR_CHAN(insn
->chanspec
));
337 case INSN_CONFIG_FILTER
:
338 return ni_65xx_config_filter(dev
, s
, insn
, data
);
340 case INSN_CONFIG_DIO_OUTPUT
:
341 if (s
->type
!= COMEDI_SUBD_DIO
)
343 devpriv
->dio_direction
[port
] = COMEDI_OUTPUT
;
344 writeb(0, devpriv
->mite
->daq_io_addr
+ Port_Select(port
));
347 case INSN_CONFIG_DIO_INPUT
:
348 if (s
->type
!= COMEDI_SUBD_DIO
)
350 devpriv
->dio_direction
[port
] = COMEDI_INPUT
;
351 writeb(1, devpriv
->mite
->daq_io_addr
+ Port_Select(port
));
354 case INSN_CONFIG_DIO_QUERY
:
355 if (s
->type
!= COMEDI_SUBD_DIO
)
357 data
[1] = devpriv
->dio_direction
[port
];
366 static int ni_65xx_dio_insn_bits(struct comedi_device
*dev
,
367 struct comedi_subdevice
*s
,
368 struct comedi_insn
*insn
, unsigned int *data
)
370 const struct ni_65xx_board
*board
= comedi_board(dev
);
371 struct ni_65xx_private
*devpriv
= dev
->private;
372 int base_bitfield_channel
;
373 unsigned read_bits
= 0;
374 int last_port_offset
= ni_65xx_port_by_channel(s
->n_chan
- 1);
377 base_bitfield_channel
= CR_CHAN(insn
->chanspec
);
378 for (port_offset
= ni_65xx_port_by_channel(base_bitfield_channel
);
379 port_offset
<= last_port_offset
; port_offset
++) {
380 unsigned port
= sprivate(s
)->base_port
+ port_offset
;
381 int base_port_channel
= port_offset
* ni_65xx_channels_per_port
;
382 unsigned port_mask
, port_data
, port_read_bits
;
383 int bitshift
= base_port_channel
- base_bitfield_channel
;
390 port_mask
>>= bitshift
;
391 port_data
>>= bitshift
;
393 port_mask
<<= -bitshift
;
394 port_data
<<= -bitshift
;
400 devpriv
->output_bits
[port
] &= ~port_mask
;
401 devpriv
->output_bits
[port
] |=
402 port_data
& port_mask
;
403 bits
= devpriv
->output_bits
[port
];
404 if (board
->invert_outputs
)
407 devpriv
->mite
->daq_io_addr
+
411 readb(devpriv
->mite
->daq_io_addr
+ Port_Data(port
));
412 if (s
->type
== COMEDI_SUBD_DO
&& board
->invert_outputs
) {
413 /* Outputs inverted, so invert value read back from
414 * DO subdevice. (Does not apply to boards with DIO
416 port_read_bits
^= 0xFF;
419 port_read_bits
<<= bitshift
;
421 port_read_bits
>>= -bitshift
;
423 read_bits
|= port_read_bits
;
429 static irqreturn_t
ni_65xx_interrupt(int irq
, void *d
)
431 struct comedi_device
*dev
= d
;
432 struct ni_65xx_private
*devpriv
= dev
->private;
433 struct comedi_subdevice
*s
= &dev
->subdevices
[2];
436 status
= readb(devpriv
->mite
->daq_io_addr
+ Change_Status
);
437 if ((status
& MasterInterruptStatus
) == 0)
439 if ((status
& EdgeStatus
) == 0)
442 writeb(ClrEdge
| ClrOverflow
,
443 devpriv
->mite
->daq_io_addr
+ Clear_Register
);
445 comedi_buf_put(s
->async
, 0);
446 s
->async
->events
|= COMEDI_CB_EOS
;
447 comedi_event(dev
, s
);
451 static int ni_65xx_intr_cmdtest(struct comedi_device
*dev
,
452 struct comedi_subdevice
*s
,
453 struct comedi_cmd
*cmd
)
457 /* Step 1 : check if triggers are trivially valid */
459 err
|= cfc_check_trigger_src(&cmd
->start_src
, TRIG_NOW
);
460 err
|= cfc_check_trigger_src(&cmd
->scan_begin_src
, TRIG_OTHER
);
461 err
|= cfc_check_trigger_src(&cmd
->convert_src
, TRIG_FOLLOW
);
462 err
|= cfc_check_trigger_src(&cmd
->scan_end_src
, TRIG_COUNT
);
463 err
|= cfc_check_trigger_src(&cmd
->stop_src
, TRIG_COUNT
);
468 /* Step 2a : make sure trigger sources are unique */
469 /* Step 2b : and mutually compatible */
474 /* Step 3: check if arguments are trivially valid */
476 err
|= cfc_check_trigger_arg_is(&cmd
->start_arg
, 0);
477 err
|= cfc_check_trigger_arg_is(&cmd
->scan_begin_arg
, 0);
478 err
|= cfc_check_trigger_arg_is(&cmd
->convert_arg
, 0);
479 err
|= cfc_check_trigger_arg_is(&cmd
->scan_end_arg
, 1);
480 err
|= cfc_check_trigger_arg_is(&cmd
->stop_arg
, 0);
485 /* step 4: fix up any arguments */
493 static int ni_65xx_intr_cmd(struct comedi_device
*dev
,
494 struct comedi_subdevice
*s
)
496 struct ni_65xx_private
*devpriv
= dev
->private;
497 /* struct comedi_cmd *cmd = &s->async->cmd; */
499 writeb(ClrEdge
| ClrOverflow
,
500 devpriv
->mite
->daq_io_addr
+ Clear_Register
);
501 writeb(FallingEdgeIntEnable
| RisingEdgeIntEnable
|
502 MasterInterruptEnable
| EdgeIntEnable
,
503 devpriv
->mite
->daq_io_addr
+ Master_Interrupt_Control
);
508 static int ni_65xx_intr_cancel(struct comedi_device
*dev
,
509 struct comedi_subdevice
*s
)
511 struct ni_65xx_private
*devpriv
= dev
->private;
513 writeb(0x00, devpriv
->mite
->daq_io_addr
+ Master_Interrupt_Control
);
518 static int ni_65xx_intr_insn_bits(struct comedi_device
*dev
,
519 struct comedi_subdevice
*s
,
520 struct comedi_insn
*insn
, unsigned int *data
)
526 static int ni_65xx_intr_insn_config(struct comedi_device
*dev
,
527 struct comedi_subdevice
*s
,
528 struct comedi_insn
*insn
,
531 struct ni_65xx_private
*devpriv
= dev
->private;
535 if (data
[0] != INSN_CONFIG_CHANGE_NOTIFY
)
539 devpriv
->mite
->daq_io_addr
+
540 Rising_Edge_Detection_Enable(0));
542 devpriv
->mite
->daq_io_addr
+
543 Rising_Edge_Detection_Enable(0x10));
544 writeb(data
[1] >> 16,
545 devpriv
->mite
->daq_io_addr
+
546 Rising_Edge_Detection_Enable(0x20));
547 writeb(data
[1] >> 24,
548 devpriv
->mite
->daq_io_addr
+
549 Rising_Edge_Detection_Enable(0x30));
552 devpriv
->mite
->daq_io_addr
+
553 Falling_Edge_Detection_Enable(0));
555 devpriv
->mite
->daq_io_addr
+
556 Falling_Edge_Detection_Enable(0x10));
557 writeb(data
[2] >> 16,
558 devpriv
->mite
->daq_io_addr
+
559 Falling_Edge_Detection_Enable(0x20));
560 writeb(data
[2] >> 24,
561 devpriv
->mite
->daq_io_addr
+
562 Falling_Edge_Detection_Enable(0x30));
567 static int ni_65xx_auto_attach(struct comedi_device
*dev
,
568 unsigned long context
)
570 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
571 const struct ni_65xx_board
*board
= NULL
;
572 struct ni_65xx_private
*devpriv
;
573 struct ni_65xx_subdevice_private
*spriv
;
574 struct comedi_subdevice
*s
;
578 if (context
< ARRAY_SIZE(ni_65xx_boards
))
579 board
= &ni_65xx_boards
[context
];
582 dev
->board_ptr
= board
;
583 dev
->board_name
= board
->name
;
585 ret
= comedi_pci_enable(dev
);
589 devpriv
= comedi_alloc_devpriv(dev
, sizeof(*devpriv
));
593 devpriv
->mite
= mite_alloc(pcidev
);
597 ret
= mite_setup(devpriv
->mite
);
599 dev_warn(dev
->class_dev
, "error setting up mite\n");
603 dev
->irq
= mite_irq(devpriv
->mite
);
604 dev_info(dev
->class_dev
, "board: %s, ID=0x%02x", dev
->board_name
,
605 readb(devpriv
->mite
->daq_io_addr
+ ID_Register
));
607 ret
= comedi_alloc_subdevices(dev
, 4);
611 s
= &dev
->subdevices
[0];
612 if (board
->num_di_ports
) {
613 s
->type
= COMEDI_SUBD_DI
;
614 s
->subdev_flags
= SDF_READABLE
;
616 board
->num_di_ports
* ni_65xx_channels_per_port
;
617 s
->range_table
= &range_digital
;
619 s
->insn_config
= ni_65xx_dio_insn_config
;
620 s
->insn_bits
= ni_65xx_dio_insn_bits
;
621 spriv
= comedi_alloc_spriv(s
, sizeof(*spriv
));
624 spriv
->base_port
= 0;
626 s
->type
= COMEDI_SUBD_UNUSED
;
629 s
= &dev
->subdevices
[1];
630 if (board
->num_do_ports
) {
631 s
->type
= COMEDI_SUBD_DO
;
632 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
;
634 board
->num_do_ports
* ni_65xx_channels_per_port
;
635 s
->range_table
= &range_digital
;
637 s
->insn_bits
= ni_65xx_dio_insn_bits
;
638 spriv
= comedi_alloc_spriv(s
, sizeof(*spriv
));
641 spriv
->base_port
= board
->num_di_ports
;
643 s
->type
= COMEDI_SUBD_UNUSED
;
646 s
= &dev
->subdevices
[2];
647 if (board
->num_dio_ports
) {
648 s
->type
= COMEDI_SUBD_DIO
;
649 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
;
651 board
->num_dio_ports
* ni_65xx_channels_per_port
;
652 s
->range_table
= &range_digital
;
654 s
->insn_config
= ni_65xx_dio_insn_config
;
655 s
->insn_bits
= ni_65xx_dio_insn_bits
;
656 spriv
= comedi_alloc_spriv(s
, sizeof(*spriv
));
659 spriv
->base_port
= 0;
660 for (i
= 0; i
< board
->num_dio_ports
; ++i
) {
661 /* configure all ports for input */
663 devpriv
->mite
->daq_io_addr
+
667 s
->type
= COMEDI_SUBD_UNUSED
;
670 s
= &dev
->subdevices
[3];
671 dev
->read_subdev
= s
;
672 s
->type
= COMEDI_SUBD_DI
;
673 s
->subdev_flags
= SDF_READABLE
| SDF_CMD_READ
;
675 s
->range_table
= &range_unknown
;
677 s
->do_cmdtest
= ni_65xx_intr_cmdtest
;
678 s
->do_cmd
= ni_65xx_intr_cmd
;
679 s
->cancel
= ni_65xx_intr_cancel
;
680 s
->insn_bits
= ni_65xx_intr_insn_bits
;
681 s
->insn_config
= ni_65xx_intr_insn_config
;
683 for (i
= 0; i
< ni_65xx_total_num_ports(board
); ++i
) {
685 devpriv
->mite
->daq_io_addr
+ Filter_Enable(i
));
686 if (board
->invert_outputs
)
688 devpriv
->mite
->daq_io_addr
+ Port_Data(i
));
691 devpriv
->mite
->daq_io_addr
+ Port_Data(i
));
693 writeb(ClrEdge
| ClrOverflow
,
694 devpriv
->mite
->daq_io_addr
+ Clear_Register
);
696 devpriv
->mite
->daq_io_addr
+ Master_Interrupt_Control
);
698 /* Set filter interval to 0 (32bit reg) */
699 writeb(0x00000000, devpriv
->mite
->daq_io_addr
+ Filter_Interval
);
701 ret
= request_irq(dev
->irq
, ni_65xx_interrupt
, IRQF_SHARED
,
705 dev_warn(dev
->class_dev
, "irq not available\n");
711 static void ni_65xx_detach(struct comedi_device
*dev
)
713 struct ni_65xx_private
*devpriv
= dev
->private;
715 if (devpriv
&& devpriv
->mite
&& devpriv
->mite
->daq_io_addr
) {
717 devpriv
->mite
->daq_io_addr
+
718 Master_Interrupt_Control
);
721 free_irq(dev
->irq
, dev
);
724 mite_unsetup(devpriv
->mite
);
725 mite_free(devpriv
->mite
);
728 comedi_pci_disable(dev
);
731 static struct comedi_driver ni_65xx_driver
= {
732 .driver_name
= "ni_65xx",
733 .module
= THIS_MODULE
,
734 .auto_attach
= ni_65xx_auto_attach
,
735 .detach
= ni_65xx_detach
,
738 static int ni_65xx_pci_probe(struct pci_dev
*dev
,
739 const struct pci_device_id
*id
)
741 return comedi_pci_auto_config(dev
, &ni_65xx_driver
, id
->driver_data
);
744 static DEFINE_PCI_DEVICE_TABLE(ni_65xx_pci_table
) = {
745 { PCI_VDEVICE(NI
, 0x1710), BOARD_PXI6509
},
746 { PCI_VDEVICE(NI
, 0x7085), BOARD_PCI6509
},
747 { PCI_VDEVICE(NI
, 0x7086), BOARD_PXI6528
},
748 { PCI_VDEVICE(NI
, 0x7087), BOARD_PCI6515
},
749 { PCI_VDEVICE(NI
, 0x7088), BOARD_PCI6514
},
750 { PCI_VDEVICE(NI
, 0x70a9), BOARD_PCI6528
},
751 { PCI_VDEVICE(NI
, 0x70c3), BOARD_PCI6511
},
752 { PCI_VDEVICE(NI
, 0x70c8), BOARD_PCI6513
},
753 { PCI_VDEVICE(NI
, 0x70c9), BOARD_PXI6515
},
754 { PCI_VDEVICE(NI
, 0x70cc), BOARD_PCI6512
},
755 { PCI_VDEVICE(NI
, 0x70cd), BOARD_PXI6514
},
756 { PCI_VDEVICE(NI
, 0x70d1), BOARD_PXI6513
},
757 { PCI_VDEVICE(NI
, 0x70d2), BOARD_PXI6512
},
758 { PCI_VDEVICE(NI
, 0x70d3), BOARD_PXI6511
},
759 { PCI_VDEVICE(NI
, 0x7124), BOARD_PCI6510
},
760 { PCI_VDEVICE(NI
, 0x7125), BOARD_PCI6516
},
761 { PCI_VDEVICE(NI
, 0x7126), BOARD_PCI6517
},
762 { PCI_VDEVICE(NI
, 0x7127), BOARD_PCI6518
},
763 { PCI_VDEVICE(NI
, 0x7128), BOARD_PCI6519
},
764 { PCI_VDEVICE(NI
, 0x718b), BOARD_PCI6521
},
765 { PCI_VDEVICE(NI
, 0x718c), BOARD_PXI6521
},
766 { PCI_VDEVICE(NI
, 0x71c5), BOARD_PCI6520
},
769 MODULE_DEVICE_TABLE(pci
, ni_65xx_pci_table
);
771 static struct pci_driver ni_65xx_pci_driver
= {
773 .id_table
= ni_65xx_pci_table
,
774 .probe
= ni_65xx_pci_probe
,
775 .remove
= comedi_pci_auto_unconfig
,
777 module_comedi_pci_driver(ni_65xx_driver
, ni_65xx_pci_driver
);
779 MODULE_AUTHOR("Comedi http://www.comedi.org");
780 MODULE_DESCRIPTION("Comedi low-level driver");
781 MODULE_LICENSE("GPL");