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Merge 3.9-rc5 into staging-next
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_labpc.c
1 /*
2 * comedi/drivers/ni_labpc.c
3 * Driver for National Instruments Lab-PC series boards and compatibles
4 * Copyright (C) 2001-2003 Frank Mori Hess <fmhess@users.sourceforge.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21 /*
22 * Driver: ni_labpc
23 * Description: National Instruments Lab-PC (& compatibles)
24 * Devices: (National Instruments) Lab-PC-1200 [lab-pc-1200]
25 * (National Instruments) Lab-PC-1200AI [lab-pc-1200ai]
26 * (National Instruments) Lab-PC+ [lab-pc+]
27 * (National Instruments) PCI-1200 [pci-1200]
28 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
29 * Status: works
30 *
31 * Configuration options - ISA boards:
32 * [0] - I/O port base address
33 * [1] - IRQ (optional, required for timed or externally triggered
34 * conversions)
35 * [2] - DMA channel (optional)
36 *
37 * Configuration options - PCI boards:
38 * not applicable, uses PCI auto config
39 *
40 * Tested with lab-pc-1200. For the older Lab-PC+, not all input
41 * ranges and analog references will work, the available ranges/arefs
42 * will depend on how you have configured the jumpers on your board
43 * (see your owner's manual).
44 *
45 * Kernel-level ISA plug-and-play support for the lab-pc-1200 boards
46 * has not yet been added to the driver, mainly due to the fact that
47 * I don't know the device id numbers. If you have one of these boards,
48 * please file a bug report at http://comedi.org/ so I can get the
49 * necessary information from you.
50 *
51 * The 1200 series boards have onboard calibration dacs for correcting
52 * analog input/output offsets and gains. The proper settings for these
53 * caldacs are stored on the board's eeprom. To read the caldac values
54 * from the eeprom and store them into a file that can be then be used
55 * by comedilib, use the comedi_calibrate program.
56 *
57 * The Lab-pc+ has quirky chanlist requirements when scanning multiple
58 * channels. Multiple channel scan sequence must start at highest channel,
59 * then decrement down to channel 0. The rest of the cards can scan down
60 * like lab-pc+ or scan up from channel zero. Chanlists consisting of all
61 * one channel are also legal, and allow you to pace conversions in bursts.
62 *
63 * NI manuals:
64 * 341309a (labpc-1200 register manual)
65 * 340914a (pci-1200)
66 * 320502b (lab-pc+)
67 */
68
69 #include <linux/pci.h>
70 #include <linux/interrupt.h>
71 #include <linux/slab.h>
72 #include <linux/io.h>
73 #include <linux/delay.h>
74
75 #include "../comedidev.h"
76
77 #include <asm/dma.h>
78
79 #include "8253.h"
80 #include "8255.h"
81 #include "mite.h"
82 #include "comedi_fc.h"
83 #include "ni_labpc.h"
84
85 /*
86 * Register map (all registers are 8-bit)
87 */
88 #define STAT1_REG 0x00 /* R: Status 1 reg */
89 #define STAT1_DAVAIL (1 << 0)
90 #define STAT1_OVERRUN (1 << 1)
91 #define STAT1_OVERFLOW (1 << 2)
92 #define STAT1_CNTINT (1 << 3)
93 #define STAT1_GATA0 (1 << 5)
94 #define STAT1_EXTGATA0 (1 << 6)
95 #define CMD1_REG 0x00 /* W: Command 1 reg */
96 #define CMD1_MA(x) (((x) & 0x7) << 0)
97 #define CMD1_TWOSCMP (1 << 3)
98 #define CMD1_GAIN_MASK (7 << 4)
99 #define CMD1_SCANEN (1 << 7)
100 #define CMD2_REG 0x01 /* W: Command 2 reg */
101 #define CMD2_PRETRIG (1 << 0)
102 #define CMD2_HWTRIG (1 << 1)
103 #define CMD2_SWTRIG (1 << 2)
104 #define CMD2_TBSEL (1 << 3)
105 #define CMD2_2SDAC0 (1 << 4)
106 #define CMD2_2SDAC1 (1 << 5)
107 #define CMD2_LDAC(x) (1 << (6 + (x)))
108 #define CMD3_REG 0x02 /* W: Command 3 reg */
109 #define CMD3_DMAEN (1 << 0)
110 #define CMD3_DIOINTEN (1 << 1)
111 #define CMD3_DMATCINTEN (1 << 2)
112 #define CMD3_CNTINTEN (1 << 3)
113 #define CMD3_ERRINTEN (1 << 4)
114 #define CMD3_FIFOINTEN (1 << 5)
115 #define ADC_START_CONVERT_REG 0x03 /* W: Start Convert reg */
116 #define DAC_LSB_REG(x) (0x04 + 2 * (x)) /* W: DAC0/1 LSB reg */
117 #define DAC_MSB_REG(x) (0x05 + 2 * (x)) /* W: DAC0/1 MSB reg */
118 #define ADC_FIFO_CLEAR_REG 0x08 /* W: A/D FIFO Clear reg */
119 #define ADC_FIFO_REG 0x0a /* R: A/D FIFO reg */
120 #define DMATC_CLEAR_REG 0x0a /* W: DMA Interrupt Clear reg */
121 #define TIMER_CLEAR_REG 0x0c /* W: Timer Interrupt Clear reg */
122 #define CMD6_REG 0x0e /* W: Command 6 reg */
123 #define CMD6_NRSE (1 << 0)
124 #define CMD6_ADCUNI (1 << 1)
125 #define CMD6_DACUNI(x) (1 << (2 + (x)))
126 #define CMD6_HFINTEN (1 << 5)
127 #define CMD6_DQINTEN (1 << 6)
128 #define CMD6_SCANUP (1 << 7)
129 #define CMD4_REG 0x0f /* W: Command 3 reg */
130 #define CMD4_INTSCAN (1 << 0)
131 #define CMD4_EOIRCV (1 << 1)
132 #define CMD4_ECLKDRV (1 << 2)
133 #define CMD4_SEDIFF (1 << 3)
134 #define CMD4_ECLKRCV (1 << 4)
135 #define DIO_BASE_REG 0x10 /* R/W: 8255 DIO base reg */
136 #define COUNTER_A_BASE_REG 0x14 /* R/W: 8253 Counter A base reg */
137 #define COUNTER_B_BASE_REG 0x18 /* R/W: 8253 Counter B base reg */
138 #define CMD5_REG 0x1c /* W: Command 5 reg */
139 #define CMD5_WRTPRT (1 << 2)
140 #define CMD5_DITHEREN (1 << 3)
141 #define CMD5_CALDACLD (1 << 4)
142 #define CMD5_SCLK (1 << 5)
143 #define CMD5_SDATA (1 << 6)
144 #define CMD5_EEPROMCS (1 << 7)
145 #define STAT2_REG 0x1d /* R: Status 2 reg */
146 #define STAT2_PROMOUT (1 << 0)
147 #define STAT2_OUTA1 (1 << 1)
148 #define STAT2_FIFONHF (1 << 2)
149 #define INTERVAL_COUNT_REG 0x1e /* W: Interval Counter Data reg */
150 #define INTERVAL_STROBE_REG 0x1f /* W: Interval Counter Strobe reg */
151
152 #define LABPC_SIZE 0x20 /* size of ISA io region */
153 #define LABPC_TIMER_BASE 500 /* 2 MHz master clock */
154 #define LABPC_ADC_TIMEOUT 1000
155
156 enum scan_mode {
157 MODE_SINGLE_CHAN,
158 MODE_SINGLE_CHAN_INTERVAL,
159 MODE_MULT_CHAN_UP,
160 MODE_MULT_CHAN_DOWN,
161 };
162
163 static const int labpc_plus_ai_gain_bits[] = {
164 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70,
165 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70,
166 };
167
168 static const struct comedi_lrange range_labpc_plus_ai = {
169 16, {
170 BIP_RANGE(5),
171 BIP_RANGE(4),
172 BIP_RANGE(2.5),
173 BIP_RANGE(1),
174 BIP_RANGE(0.5),
175 BIP_RANGE(0.25),
176 BIP_RANGE(0.1),
177 BIP_RANGE(0.05),
178 UNI_RANGE(10),
179 UNI_RANGE(8),
180 UNI_RANGE(5),
181 UNI_RANGE(2),
182 UNI_RANGE(1),
183 UNI_RANGE(0.5),
184 UNI_RANGE(0.2),
185 UNI_RANGE(0.1)
186 }
187 };
188
189 const int labpc_1200_ai_gain_bits[] = {
190 0x00, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70,
191 0x00, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70,
192 };
193 EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits);
194
195 const struct comedi_lrange range_labpc_1200_ai = {
196 14, {
197 BIP_RANGE(5),
198 BIP_RANGE(2.5),
199 BIP_RANGE(1),
200 BIP_RANGE(0.5),
201 BIP_RANGE(0.25),
202 BIP_RANGE(0.1),
203 BIP_RANGE(0.05),
204 UNI_RANGE(10),
205 UNI_RANGE(5),
206 UNI_RANGE(2),
207 UNI_RANGE(1),
208 UNI_RANGE(0.5),
209 UNI_RANGE(0.2),
210 UNI_RANGE(0.1)
211 }
212 };
213 EXPORT_SYMBOL_GPL(range_labpc_1200_ai);
214
215 static const struct comedi_lrange range_labpc_ao = {
216 2, {
217 BIP_RANGE(5),
218 UNI_RANGE(10)
219 }
220 };
221
222 /* functions that do inb/outb and readb/writeb so we can use
223 * function pointers to decide which to use */
224 static inline unsigned int labpc_inb(unsigned long address)
225 {
226 return inb(address);
227 }
228
229 static inline void labpc_outb(unsigned int byte, unsigned long address)
230 {
231 outb(byte, address);
232 }
233
234 static inline unsigned int labpc_readb(unsigned long address)
235 {
236 return readb((void __iomem *)address);
237 }
238
239 static inline void labpc_writeb(unsigned int byte, unsigned long address)
240 {
241 writeb(byte, (void __iomem *)address);
242 }
243
244 static const struct labpc_boardinfo labpc_boards[] = {
245 {
246 .name = "lab-pc-1200",
247 .ai_speed = 10000,
248 .bustype = isa_bustype,
249 .register_layout = labpc_1200_layout,
250 .has_ao = 1,
251 .ai_range_table = &range_labpc_1200_ai,
252 .ai_range_code = labpc_1200_ai_gain_bits,
253 .ai_scan_up = 1,
254 }, {
255 .name = "lab-pc-1200ai",
256 .ai_speed = 10000,
257 .bustype = isa_bustype,
258 .register_layout = labpc_1200_layout,
259 .ai_range_table = &range_labpc_1200_ai,
260 .ai_range_code = labpc_1200_ai_gain_bits,
261 .ai_scan_up = 1,
262 }, {
263 .name = "lab-pc+",
264 .ai_speed = 12000,
265 .bustype = isa_bustype,
266 .register_layout = labpc_plus_layout,
267 .has_ao = 1,
268 .ai_range_table = &range_labpc_plus_ai,
269 .ai_range_code = labpc_plus_ai_gain_bits,
270 },
271 #ifdef CONFIG_COMEDI_PCI_DRIVERS
272 {
273 .name = "pci-1200",
274 .device_id = 0x161,
275 .ai_speed = 10000,
276 .bustype = pci_bustype,
277 .register_layout = labpc_1200_layout,
278 .has_ao = 1,
279 .ai_range_table = &range_labpc_1200_ai,
280 .ai_range_code = labpc_1200_ai_gain_bits,
281 .ai_scan_up = 1,
282 .has_mmio = 1,
283 },
284 #endif
285 };
286
287 /* size in bytes of dma buffer */
288 static const int dma_buffer_size = 0xff00;
289 /* 2 bytes per sample */
290 static const int sample_size = 2;
291
292 static int labpc_counter_load(struct comedi_device *dev,
293 unsigned long base_address,
294 unsigned int counter_number,
295 unsigned int count, unsigned int mode)
296 {
297 const struct labpc_boardinfo *board = comedi_board(dev);
298
299 if (board->has_mmio)
300 return i8254_mm_load((void __iomem *)base_address, 0,
301 counter_number, count, mode);
302 else
303 return i8254_load(base_address, 0, counter_number, count, mode);
304 }
305
306 static int labpc_counter_set_mode(struct comedi_device *dev,
307 unsigned long base_address,
308 unsigned int counter_number,
309 unsigned int mode)
310 {
311 const struct labpc_boardinfo *board = comedi_board(dev);
312
313 if (board->has_mmio)
314 return i8254_mm_set_mode((void __iomem *)base_address, 0,
315 counter_number, mode);
316 else
317 return i8254_set_mode(base_address, 0, counter_number, mode);
318 }
319
320 static bool labpc_range_is_unipolar(struct comedi_subdevice *s,
321 unsigned int range)
322 {
323 return s->range_table->range[range].min >= 0;
324 }
325
326 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
327 {
328 struct labpc_private *devpriv = dev->private;
329 unsigned long flags;
330
331 spin_lock_irqsave(&dev->spinlock, flags);
332 devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG);
333 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG);
334 spin_unlock_irqrestore(&dev->spinlock, flags);
335
336 devpriv->cmd3 = 0;
337 devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG);
338
339 return 0;
340 }
341
342 static void labpc_ai_set_chan_and_gain(struct comedi_device *dev,
343 enum scan_mode mode,
344 unsigned int chan,
345 unsigned int range,
346 unsigned int aref)
347 {
348 const struct labpc_boardinfo *board = comedi_board(dev);
349 struct labpc_private *devpriv = dev->private;
350
351 /* munge channel bits for differential/scan disabled mode */
352 if ((mode == MODE_SINGLE_CHAN || mode == MODE_SINGLE_CHAN_INTERVAL) &&
353 aref == AREF_DIFF)
354 chan *= 2;
355 devpriv->cmd1 = CMD1_MA(chan);
356 devpriv->cmd1 |= board->ai_range_code[range];
357
358 devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG);
359 }
360
361 static void labpc_setup_cmd6_reg(struct comedi_device *dev,
362 struct comedi_subdevice *s,
363 enum scan_mode mode,
364 enum transfer_type xfer,
365 unsigned int range,
366 unsigned int aref,
367 bool ena_intr)
368 {
369 const struct labpc_boardinfo *board = comedi_board(dev);
370 struct labpc_private *devpriv = dev->private;
371
372 if (board->register_layout != labpc_1200_layout)
373 return;
374
375 /* reference inputs to ground or common? */
376 if (aref != AREF_GROUND)
377 devpriv->cmd6 |= CMD6_NRSE;
378 else
379 devpriv->cmd6 &= ~CMD6_NRSE;
380
381 /* bipolar or unipolar range? */
382 if (labpc_range_is_unipolar(s, range))
383 devpriv->cmd6 |= CMD6_ADCUNI;
384 else
385 devpriv->cmd6 &= ~CMD6_ADCUNI;
386
387 /* interrupt on fifo half full? */
388 if (xfer == fifo_half_full_transfer)
389 devpriv->cmd6 |= CMD6_HFINTEN;
390 else
391 devpriv->cmd6 &= ~CMD6_HFINTEN;
392
393 /* enable interrupt on counter a1 terminal count? */
394 if (ena_intr)
395 devpriv->cmd6 |= CMD6_DQINTEN;
396 else
397 devpriv->cmd6 &= ~CMD6_DQINTEN;
398
399 /* are we scanning up or down through channels? */
400 if (mode == MODE_MULT_CHAN_UP)
401 devpriv->cmd6 |= CMD6_SCANUP;
402 else
403 devpriv->cmd6 &= ~CMD6_SCANUP;
404
405 devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG);
406 }
407
408 static unsigned int labpc_read_adc_fifo(struct comedi_device *dev)
409 {
410 struct labpc_private *devpriv = dev->private;
411 unsigned int lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
412 unsigned int msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
413
414 return (msb << 8) | lsb;
415 }
416
417 static void labpc_clear_adc_fifo(struct comedi_device *dev)
418 {
419 struct labpc_private *devpriv = dev->private;
420
421 devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG);
422 labpc_read_adc_fifo(dev);
423 }
424
425 static int labpc_ai_wait_for_data(struct comedi_device *dev,
426 int timeout)
427 {
428 struct labpc_private *devpriv = dev->private;
429 int i;
430
431 for (i = 0; i < timeout; i++) {
432 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG);
433 if (devpriv->stat1 & STAT1_DAVAIL)
434 return 0;
435 udelay(1);
436 }
437 return -ETIME;
438 }
439
440 static int labpc_ai_insn_read(struct comedi_device *dev,
441 struct comedi_subdevice *s,
442 struct comedi_insn *insn,
443 unsigned int *data)
444 {
445 struct labpc_private *devpriv = dev->private;
446 unsigned int chan = CR_CHAN(insn->chanspec);
447 unsigned int range = CR_RANGE(insn->chanspec);
448 unsigned int aref = CR_AREF(insn->chanspec);
449 int ret;
450 int i;
451
452 /* disable timed conversions, interrupt generation and dma */
453 labpc_cancel(dev, s);
454
455 labpc_ai_set_chan_and_gain(dev, MODE_SINGLE_CHAN, chan, range, aref);
456
457 labpc_setup_cmd6_reg(dev, s, MODE_SINGLE_CHAN, fifo_not_empty_transfer,
458 range, aref, false);
459
460 /* setup cmd4 register */
461 devpriv->cmd4 = 0;
462 devpriv->cmd4 |= CMD4_ECLKRCV;
463 /* single-ended/differential */
464 if (aref == AREF_DIFF)
465 devpriv->cmd4 |= CMD4_SEDIFF;
466 devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG);
467
468 /* initialize pacer counter to prevent any problems */
469 ret = labpc_counter_set_mode(dev, dev->iobase + COUNTER_A_BASE_REG,
470 0, I8254_MODE2);
471 if (ret)
472 return ret;
473
474 labpc_clear_adc_fifo(dev);
475
476 for (i = 0; i < insn->n; i++) {
477 /* trigger conversion */
478 devpriv->write_byte(0x1, dev->iobase + ADC_START_CONVERT_REG);
479
480 ret = labpc_ai_wait_for_data(dev, LABPC_ADC_TIMEOUT);
481 if (ret)
482 return ret;
483
484 data[i] = labpc_read_adc_fifo(dev);
485 }
486
487 return insn->n;
488 }
489
490 #ifdef CONFIG_ISA_DMA_API
491 /* utility function that suggests a dma transfer size in bytes */
492 static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd)
493 {
494 unsigned int size;
495 unsigned int freq;
496
497 if (cmd->convert_src == TRIG_TIMER)
498 freq = 1000000000 / cmd->convert_arg;
499 /* return some default value */
500 else
501 freq = 0xffffffff;
502
503 /* make buffer fill in no more than 1/3 second */
504 size = (freq / 3) * sample_size;
505
506 /* set a minimum and maximum size allowed */
507 if (size > dma_buffer_size)
508 size = dma_buffer_size - dma_buffer_size % sample_size;
509 else if (size < sample_size)
510 size = sample_size;
511
512 return size;
513 }
514 #endif
515
516 static bool labpc_use_continuous_mode(const struct comedi_cmd *cmd,
517 enum scan_mode mode)
518 {
519 if (mode == MODE_SINGLE_CHAN || cmd->scan_begin_src == TRIG_FOLLOW)
520 return true;
521
522 return false;
523 }
524
525 static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd,
526 enum scan_mode mode)
527 {
528 if (cmd->convert_src != TRIG_TIMER)
529 return 0;
530
531 if (mode == MODE_SINGLE_CHAN && cmd->scan_begin_src == TRIG_TIMER)
532 return cmd->scan_begin_arg;
533
534 return cmd->convert_arg;
535 }
536
537 static void labpc_set_ai_convert_period(struct comedi_cmd *cmd,
538 enum scan_mode mode, unsigned int ns)
539 {
540 if (cmd->convert_src != TRIG_TIMER)
541 return;
542
543 if (mode == MODE_SINGLE_CHAN &&
544 cmd->scan_begin_src == TRIG_TIMER) {
545 cmd->scan_begin_arg = ns;
546 if (cmd->convert_arg > cmd->scan_begin_arg)
547 cmd->convert_arg = cmd->scan_begin_arg;
548 } else
549 cmd->convert_arg = ns;
550 }
551
552 static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd,
553 enum scan_mode mode)
554 {
555 if (cmd->scan_begin_src != TRIG_TIMER)
556 return 0;
557
558 if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER)
559 return 0;
560
561 return cmd->scan_begin_arg;
562 }
563
564 static void labpc_set_ai_scan_period(struct comedi_cmd *cmd,
565 enum scan_mode mode, unsigned int ns)
566 {
567 if (cmd->scan_begin_src != TRIG_TIMER)
568 return;
569
570 if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER)
571 return;
572
573 cmd->scan_begin_arg = ns;
574 }
575
576 /* figures out what counter values to use based on command */
577 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd,
578 enum scan_mode mode)
579 {
580 struct labpc_private *devpriv = dev->private;
581 /* max value for 16 bit counter in mode 2 */
582 const int max_counter_value = 0x10000;
583 /* min value for 16 bit counter in mode 2 */
584 const int min_counter_value = 2;
585 unsigned int base_period;
586 unsigned int scan_period;
587 unsigned int convert_period;
588
589 /*
590 * if both convert and scan triggers are TRIG_TIMER, then they
591 * both rely on counter b0
592 */
593 convert_period = labpc_ai_convert_period(cmd, mode);
594 scan_period = labpc_ai_scan_period(cmd, mode);
595 if (convert_period && scan_period) {
596 /*
597 * pick the lowest b0 divisor value we can (for maximum input
598 * clock speed on convert and scan counters)
599 */
600 devpriv->divisor_b0 = (scan_period - 1) /
601 (LABPC_TIMER_BASE * max_counter_value) + 1;
602 if (devpriv->divisor_b0 < min_counter_value)
603 devpriv->divisor_b0 = min_counter_value;
604 if (devpriv->divisor_b0 > max_counter_value)
605 devpriv->divisor_b0 = max_counter_value;
606
607 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
608
609 /* set a0 for conversion frequency and b1 for scan frequency */
610 switch (cmd->flags & TRIG_ROUND_MASK) {
611 default:
612 case TRIG_ROUND_NEAREST:
613 devpriv->divisor_a0 =
614 (convert_period + (base_period / 2)) / base_period;
615 devpriv->divisor_b1 =
616 (scan_period + (base_period / 2)) / base_period;
617 break;
618 case TRIG_ROUND_UP:
619 devpriv->divisor_a0 =
620 (convert_period + (base_period - 1)) / base_period;
621 devpriv->divisor_b1 =
622 (scan_period + (base_period - 1)) / base_period;
623 break;
624 case TRIG_ROUND_DOWN:
625 devpriv->divisor_a0 = convert_period / base_period;
626 devpriv->divisor_b1 = scan_period / base_period;
627 break;
628 }
629 /* make sure a0 and b1 values are acceptable */
630 if (devpriv->divisor_a0 < min_counter_value)
631 devpriv->divisor_a0 = min_counter_value;
632 if (devpriv->divisor_a0 > max_counter_value)
633 devpriv->divisor_a0 = max_counter_value;
634 if (devpriv->divisor_b1 < min_counter_value)
635 devpriv->divisor_b1 = min_counter_value;
636 if (devpriv->divisor_b1 > max_counter_value)
637 devpriv->divisor_b1 = max_counter_value;
638 /* write corrected timings to command */
639 labpc_set_ai_convert_period(cmd, mode,
640 base_period * devpriv->divisor_a0);
641 labpc_set_ai_scan_period(cmd, mode,
642 base_period * devpriv->divisor_b1);
643 /*
644 * if only one TRIG_TIMER is used, we can employ the generic
645 * cascaded timing functions
646 */
647 } else if (scan_period) {
648 /*
649 * calculate cascaded counter values
650 * that give desired scan timing
651 */
652 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
653 &(devpriv->divisor_b1),
654 &(devpriv->divisor_b0),
655 &scan_period,
656 cmd->flags & TRIG_ROUND_MASK);
657 labpc_set_ai_scan_period(cmd, mode, scan_period);
658 } else if (convert_period) {
659 /*
660 * calculate cascaded counter values
661 * that give desired conversion timing
662 */
663 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
664 &(devpriv->divisor_a0),
665 &(devpriv->divisor_b0),
666 &convert_period,
667 cmd->flags & TRIG_ROUND_MASK);
668 labpc_set_ai_convert_period(cmd, mode, convert_period);
669 }
670 }
671
672 static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd)
673 {
674 if (cmd->chanlist_len == 1)
675 return MODE_SINGLE_CHAN;
676
677 /* chanlist may be NULL during cmdtest. */
678 if (cmd->chanlist == NULL)
679 return MODE_MULT_CHAN_UP;
680
681 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
682 return MODE_SINGLE_CHAN_INTERVAL;
683
684 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
685 return MODE_MULT_CHAN_UP;
686
687 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
688 return MODE_MULT_CHAN_DOWN;
689
690 pr_err("ni_labpc: bug! cannot determine AI scan mode\n");
691 return 0;
692 }
693
694 static int labpc_ai_chanlist_invalid(const struct comedi_device *dev,
695 const struct comedi_cmd *cmd,
696 enum scan_mode mode)
697 {
698 int channel, range, aref, i;
699
700 if (cmd->chanlist == NULL)
701 return 0;
702
703 if (mode == MODE_SINGLE_CHAN)
704 return 0;
705
706 if (mode == MODE_SINGLE_CHAN_INTERVAL) {
707 if (cmd->chanlist_len > 0xff) {
708 comedi_error(dev,
709 "ni_labpc: chanlist too long for single channel interval mode\n");
710 return 1;
711 }
712 }
713
714 channel = CR_CHAN(cmd->chanlist[0]);
715 range = CR_RANGE(cmd->chanlist[0]);
716 aref = CR_AREF(cmd->chanlist[0]);
717
718 for (i = 0; i < cmd->chanlist_len; i++) {
719
720 switch (mode) {
721 case MODE_SINGLE_CHAN_INTERVAL:
722 if (CR_CHAN(cmd->chanlist[i]) != channel) {
723 comedi_error(dev,
724 "channel scanning order specified in chanlist is not supported by hardware.\n");
725 return 1;
726 }
727 break;
728 case MODE_MULT_CHAN_UP:
729 if (CR_CHAN(cmd->chanlist[i]) != i) {
730 comedi_error(dev,
731 "channel scanning order specified in chanlist is not supported by hardware.\n");
732 return 1;
733 }
734 break;
735 case MODE_MULT_CHAN_DOWN:
736 if (CR_CHAN(cmd->chanlist[i]) !=
737 cmd->chanlist_len - i - 1) {
738 comedi_error(dev,
739 "channel scanning order specified in chanlist is not supported by hardware.\n");
740 return 1;
741 }
742 break;
743 default:
744 dev_err(dev->class_dev,
745 "ni_labpc: bug! in chanlist check\n");
746 return 1;
747 break;
748 }
749
750 if (CR_RANGE(cmd->chanlist[i]) != range) {
751 comedi_error(dev,
752 "entries in chanlist must all have the same range\n");
753 return 1;
754 }
755
756 if (CR_AREF(cmd->chanlist[i]) != aref) {
757 comedi_error(dev,
758 "entries in chanlist must all have the same reference\n");
759 return 1;
760 }
761 }
762
763 return 0;
764 }
765
766 static int labpc_ai_cmdtest(struct comedi_device *dev,
767 struct comedi_subdevice *s, struct comedi_cmd *cmd)
768 {
769 const struct labpc_boardinfo *board = comedi_board(dev);
770 int err = 0;
771 int tmp, tmp2;
772 unsigned int stop_mask;
773 enum scan_mode mode;
774
775 /* Step 1 : check if triggers are trivially valid */
776
777 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
778 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
779 TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT);
780 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
781 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
782
783 stop_mask = TRIG_COUNT | TRIG_NONE;
784 if (board->register_layout == labpc_1200_layout)
785 stop_mask |= TRIG_EXT;
786 err |= cfc_check_trigger_src(&cmd->stop_src, stop_mask);
787
788 if (err)
789 return 1;
790
791 /* Step 2a : make sure trigger sources are unique */
792
793 err |= cfc_check_trigger_is_unique(cmd->start_src);
794 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
795 err |= cfc_check_trigger_is_unique(cmd->convert_src);
796 err |= cfc_check_trigger_is_unique(cmd->stop_src);
797
798 /* Step 2b : and mutually compatible */
799
800 /* can't have external stop and start triggers at once */
801 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
802 err++;
803
804 if (err)
805 return 2;
806
807 /* Step 3: check if arguments are trivially valid */
808
809 if (cmd->start_arg == TRIG_NOW)
810 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
811
812 if (!cmd->chanlist_len)
813 err |= -EINVAL;
814 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
815
816 if (cmd->convert_src == TRIG_TIMER)
817 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
818 board->ai_speed);
819
820 /* make sure scan timing is not too fast */
821 if (cmd->scan_begin_src == TRIG_TIMER) {
822 if (cmd->convert_src == TRIG_TIMER)
823 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
824 cmd->convert_arg * cmd->chanlist_len);
825 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
826 board->ai_speed * cmd->chanlist_len);
827 }
828
829 switch (cmd->stop_src) {
830 case TRIG_COUNT:
831 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
832 break;
833 case TRIG_NONE:
834 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
835 break;
836 /*
837 * TRIG_EXT doesn't care since it doesn't
838 * trigger off a numbered channel
839 */
840 default:
841 break;
842 }
843
844 if (err)
845 return 3;
846
847 /* step 4: fix up any arguments */
848
849 tmp = cmd->convert_arg;
850 tmp2 = cmd->scan_begin_arg;
851 mode = labpc_ai_scan_mode(cmd);
852 labpc_adc_timing(dev, cmd, mode);
853 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
854 err++;
855
856 if (err)
857 return 4;
858
859 if (labpc_ai_chanlist_invalid(dev, cmd, mode))
860 return 5;
861
862 return 0;
863 }
864
865 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
866 {
867 const struct labpc_boardinfo *board = comedi_board(dev);
868 struct labpc_private *devpriv = dev->private;
869 struct comedi_async *async = s->async;
870 struct comedi_cmd *cmd = &async->cmd;
871 enum scan_mode mode = labpc_ai_scan_mode(cmd);
872 unsigned int chanspec = (mode == MODE_MULT_CHAN_UP)
873 ? cmd->chanlist[cmd->chanlist_len - 1]
874 : cmd->chanlist[0];
875 unsigned int chan = CR_CHAN(chanspec);
876 unsigned int range = CR_RANGE(chanspec);
877 unsigned int aref = CR_AREF(chanspec);
878 enum transfer_type xfer;
879 unsigned long flags;
880 int ret;
881
882 /* make sure board is disabled before setting up acquisition */
883 labpc_cancel(dev, s);
884
885 /* initialize software conversion count */
886 if (cmd->stop_src == TRIG_COUNT)
887 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
888
889 /* setup hardware conversion counter */
890 if (cmd->stop_src == TRIG_EXT) {
891 /*
892 * load counter a1 with count of 3
893 * (pc+ manual says this is minimum allowed) using mode 0
894 */
895 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
896 1, 3, I8254_MODE0);
897 } else {
898 /* just put counter a1 in mode 0 to set its output low */
899 ret = labpc_counter_set_mode(dev,
900 dev->iobase + COUNTER_A_BASE_REG,
901 1, I8254_MODE0);
902 }
903 if (ret) {
904 comedi_error(dev, "error loading counter a1");
905 return ret;
906 }
907
908 #ifdef CONFIG_ISA_DMA_API
909 /* figure out what method we will use to transfer data */
910 if (devpriv->dma_chan && /* need a dma channel allocated */
911 /*
912 * dma unsafe at RT priority,
913 * and too much setup time for TRIG_WAKE_EOS for
914 */
915 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
916 /* only available on the isa boards */
917 board->bustype == isa_bustype) {
918 xfer = isa_dma_transfer;
919 /* pc-plus has no fifo-half full interrupt */
920 } else
921 #endif
922 if (board->register_layout == labpc_1200_layout &&
923 /* wake-end-of-scan should interrupt on fifo not empty */
924 (cmd->flags & TRIG_WAKE_EOS) == 0 &&
925 /* make sure we are taking more than just a few points */
926 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
927 xfer = fifo_half_full_transfer;
928 } else
929 xfer = fifo_not_empty_transfer;
930 devpriv->current_transfer = xfer;
931
932 labpc_ai_set_chan_and_gain(dev, mode, chan, range, aref);
933
934 labpc_setup_cmd6_reg(dev, s, mode, xfer, range, aref,
935 (cmd->stop_src == TRIG_EXT));
936
937 /* manual says to set scan enable bit on second pass */
938 if (mode == MODE_MULT_CHAN_UP || mode == MODE_MULT_CHAN_DOWN) {
939 devpriv->cmd1 |= CMD1_SCANEN;
940 /* need a brief delay before enabling scan, or scan
941 * list will get screwed when you switch
942 * between scan up to scan down mode - dunno why */
943 udelay(1);
944 devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG);
945 }
946
947 devpriv->write_byte(cmd->chanlist_len,
948 dev->iobase + INTERVAL_COUNT_REG);
949 /* load count */
950 devpriv->write_byte(0x1, dev->iobase + INTERVAL_STROBE_REG);
951
952 if (cmd->convert_src == TRIG_TIMER ||
953 cmd->scan_begin_src == TRIG_TIMER) {
954 /* set up pacing */
955 labpc_adc_timing(dev, cmd, mode);
956 /* load counter b0 in mode 3 */
957 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
958 0, devpriv->divisor_b0, I8254_MODE3);
959 if (ret < 0) {
960 comedi_error(dev, "error loading counter b0");
961 return -1;
962 }
963 }
964 /* set up conversion pacing */
965 if (labpc_ai_convert_period(cmd, mode)) {
966 /* load counter a0 in mode 2 */
967 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
968 0, devpriv->divisor_a0, I8254_MODE2);
969 } else {
970 /* initialize pacer counter to prevent any problems */
971 ret = labpc_counter_set_mode(dev,
972 dev->iobase + COUNTER_A_BASE_REG,
973 0, I8254_MODE2);
974 }
975 if (ret) {
976 comedi_error(dev, "error loading counter a0");
977 return ret;
978 }
979
980 /* set up scan pacing */
981 if (labpc_ai_scan_period(cmd, mode)) {
982 /* load counter b1 in mode 2 */
983 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
984 1, devpriv->divisor_b1, I8254_MODE2);
985 if (ret < 0) {
986 comedi_error(dev, "error loading counter b1");
987 return -1;
988 }
989 }
990
991 labpc_clear_adc_fifo(dev);
992
993 #ifdef CONFIG_ISA_DMA_API
994 /* set up dma transfer */
995 if (xfer == isa_dma_transfer) {
996 unsigned long irq_flags;
997
998 irq_flags = claim_dma_lock();
999 disable_dma(devpriv->dma_chan);
1000 /* clear flip-flop to make sure 2-byte registers for
1001 * count and address get set correctly */
1002 clear_dma_ff(devpriv->dma_chan);
1003 set_dma_addr(devpriv->dma_chan,
1004 virt_to_bus(devpriv->dma_buffer));
1005 /* set appropriate size of transfer */
1006 devpriv->dma_transfer_size = labpc_suggest_transfer_size(cmd);
1007 if (cmd->stop_src == TRIG_COUNT &&
1008 devpriv->count * sample_size < devpriv->dma_transfer_size) {
1009 devpriv->dma_transfer_size =
1010 devpriv->count * sample_size;
1011 }
1012 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1013 enable_dma(devpriv->dma_chan);
1014 release_dma_lock(irq_flags);
1015 /* enable board's dma */
1016 devpriv->cmd3 |= (CMD3_DMAEN | CMD3_DMATCINTEN);
1017 } else
1018 devpriv->cmd3 &= ~(CMD3_DMAEN | CMD3_DMATCINTEN);
1019 #endif
1020
1021 /* enable error interrupts */
1022 devpriv->cmd3 |= CMD3_ERRINTEN;
1023 /* enable fifo not empty interrupt? */
1024 if (xfer == fifo_not_empty_transfer)
1025 devpriv->cmd3 |= CMD3_FIFOINTEN;
1026 else
1027 devpriv->cmd3 &= ~CMD3_FIFOINTEN;
1028 devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG);
1029
1030 /* setup any external triggering/pacing (cmd4 register) */
1031 devpriv->cmd4 = 0;
1032 if (cmd->convert_src != TRIG_EXT)
1033 devpriv->cmd4 |= CMD4_ECLKRCV;
1034 /* XXX should discard first scan when using interval scanning
1035 * since manual says it is not synced with scan clock */
1036 if (!labpc_use_continuous_mode(cmd, mode)) {
1037 devpriv->cmd4 |= CMD4_INTSCAN;
1038 if (cmd->scan_begin_src == TRIG_EXT)
1039 devpriv->cmd4 |= CMD4_EOIRCV;
1040 }
1041 /* single-ended/differential */
1042 if (aref == AREF_DIFF)
1043 devpriv->cmd4 |= CMD4_SEDIFF;
1044 devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG);
1045
1046 /* startup acquisition */
1047
1048 spin_lock_irqsave(&dev->spinlock, flags);
1049
1050 /* use 2 cascaded counters for pacing */
1051 devpriv->cmd2 |= CMD2_TBSEL;
1052
1053 devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG);
1054 if (cmd->start_src == TRIG_EXT)
1055 devpriv->cmd2 |= CMD2_HWTRIG;
1056 else
1057 devpriv->cmd2 |= CMD2_SWTRIG;
1058 if (cmd->stop_src == TRIG_EXT)
1059 devpriv->cmd2 |= (CMD2_HWTRIG | CMD2_PRETRIG);
1060
1061 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG);
1062
1063 spin_unlock_irqrestore(&dev->spinlock, flags);
1064
1065 return 0;
1066 }
1067
1068 #ifdef CONFIG_ISA_DMA_API
1069 static void labpc_drain_dma(struct comedi_device *dev)
1070 {
1071 struct labpc_private *devpriv = dev->private;
1072 struct comedi_subdevice *s = dev->read_subdev;
1073 struct comedi_async *async = s->async;
1074 int status;
1075 unsigned long flags;
1076 unsigned int max_points, num_points, residue, leftover;
1077 int i;
1078
1079 status = devpriv->stat1;
1080
1081 flags = claim_dma_lock();
1082 disable_dma(devpriv->dma_chan);
1083 /* clear flip-flop to make sure 2-byte registers for
1084 * count and address get set correctly */
1085 clear_dma_ff(devpriv->dma_chan);
1086
1087 /* figure out how many points to read */
1088 max_points = devpriv->dma_transfer_size / sample_size;
1089 /* residue is the number of points left to be done on the dma
1090 * transfer. It should always be zero at this point unless
1091 * the stop_src is set to external triggering.
1092 */
1093 residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1094 num_points = max_points - residue;
1095 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1096 num_points = devpriv->count;
1097
1098 /* figure out how many points will be stored next time */
1099 leftover = 0;
1100 if (async->cmd.stop_src != TRIG_COUNT) {
1101 leftover = devpriv->dma_transfer_size / sample_size;
1102 } else if (devpriv->count > num_points) {
1103 leftover = devpriv->count - num_points;
1104 if (leftover > max_points)
1105 leftover = max_points;
1106 }
1107
1108 /* write data to comedi buffer */
1109 for (i = 0; i < num_points; i++)
1110 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
1111
1112 if (async->cmd.stop_src == TRIG_COUNT)
1113 devpriv->count -= num_points;
1114
1115 /* set address and count for next transfer */
1116 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1117 set_dma_count(devpriv->dma_chan, leftover * sample_size);
1118 release_dma_lock(flags);
1119
1120 async->events |= COMEDI_CB_BLOCK;
1121 }
1122
1123 static void handle_isa_dma(struct comedi_device *dev)
1124 {
1125 struct labpc_private *devpriv = dev->private;
1126
1127 labpc_drain_dma(dev);
1128
1129 enable_dma(devpriv->dma_chan);
1130
1131 /* clear dma tc interrupt */
1132 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1133 }
1134 #endif
1135
1136 /* read all available samples from ai fifo */
1137 static int labpc_drain_fifo(struct comedi_device *dev)
1138 {
1139 struct labpc_private *devpriv = dev->private;
1140 short data;
1141 struct comedi_async *async = dev->read_subdev->async;
1142 const int timeout = 10000;
1143 unsigned int i;
1144
1145 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG);
1146
1147 for (i = 0; (devpriv->stat1 & STAT1_DAVAIL) && i < timeout;
1148 i++) {
1149 /* quit if we have all the data we want */
1150 if (async->cmd.stop_src == TRIG_COUNT) {
1151 if (devpriv->count == 0)
1152 break;
1153 devpriv->count--;
1154 }
1155 data = labpc_read_adc_fifo(dev);
1156 cfc_write_to_buffer(dev->read_subdev, data);
1157 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG);
1158 }
1159 if (i == timeout) {
1160 comedi_error(dev, "ai timeout, fifo never empties");
1161 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1162 return -1;
1163 }
1164
1165 return 0;
1166 }
1167
1168 /* makes sure all data acquired by board is transferred to comedi (used
1169 * when acquisition is terminated by stop_src == TRIG_EXT). */
1170 static void labpc_drain_dregs(struct comedi_device *dev)
1171 {
1172 #ifdef CONFIG_ISA_DMA_API
1173 struct labpc_private *devpriv = dev->private;
1174
1175 if (devpriv->current_transfer == isa_dma_transfer)
1176 labpc_drain_dma(dev);
1177 #endif
1178
1179 labpc_drain_fifo(dev);
1180 }
1181
1182 /* interrupt service routine */
1183 static irqreturn_t labpc_interrupt(int irq, void *d)
1184 {
1185 struct comedi_device *dev = d;
1186 const struct labpc_boardinfo *board = comedi_board(dev);
1187 struct labpc_private *devpriv = dev->private;
1188 struct comedi_subdevice *s = dev->read_subdev;
1189 struct comedi_async *async;
1190 struct comedi_cmd *cmd;
1191
1192 if (!dev->attached) {
1193 comedi_error(dev, "premature interrupt");
1194 return IRQ_HANDLED;
1195 }
1196
1197 async = s->async;
1198 cmd = &async->cmd;
1199 async->events = 0;
1200
1201 /* read board status */
1202 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG);
1203 if (board->register_layout == labpc_1200_layout)
1204 devpriv->stat2 = devpriv->read_byte(dev->iobase + STAT2_REG);
1205
1206 if ((devpriv->stat1 & (STAT1_GATA0 | STAT1_CNTINT | STAT1_OVERFLOW |
1207 STAT1_OVERRUN | STAT1_DAVAIL)) == 0
1208 && (devpriv->stat2 & STAT2_OUTA1) == 0
1209 && (devpriv->stat2 & STAT2_FIFONHF)) {
1210 return IRQ_NONE;
1211 }
1212
1213 if (devpriv->stat1 & STAT1_OVERRUN) {
1214 /* clear error interrupt */
1215 devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG);
1216 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1217 comedi_event(dev, s);
1218 comedi_error(dev, "overrun");
1219 return IRQ_HANDLED;
1220 }
1221
1222 #ifdef CONFIG_ISA_DMA_API
1223 if (devpriv->current_transfer == isa_dma_transfer) {
1224 /*
1225 * if a dma terminal count of external stop trigger
1226 * has occurred
1227 */
1228 if (devpriv->stat1 & STAT1_GATA0 ||
1229 (board->register_layout == labpc_1200_layout
1230 && devpriv->stat2 & STAT2_OUTA1)) {
1231 handle_isa_dma(dev);
1232 }
1233 } else
1234 #endif
1235 labpc_drain_fifo(dev);
1236
1237 if (devpriv->stat1 & STAT1_CNTINT) {
1238 comedi_error(dev, "handled timer interrupt?");
1239 /* clear it */
1240 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1241 }
1242
1243 if (devpriv->stat1 & STAT1_OVERFLOW) {
1244 /* clear error interrupt */
1245 devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG);
1246 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1247 comedi_event(dev, s);
1248 comedi_error(dev, "overflow");
1249 return IRQ_HANDLED;
1250 }
1251 /* handle external stop trigger */
1252 if (cmd->stop_src == TRIG_EXT) {
1253 if (devpriv->stat2 & STAT2_OUTA1) {
1254 labpc_drain_dregs(dev);
1255 labpc_cancel(dev, s);
1256 async->events |= COMEDI_CB_EOA;
1257 }
1258 }
1259
1260 /* TRIG_COUNT end of acquisition */
1261 if (cmd->stop_src == TRIG_COUNT) {
1262 if (devpriv->count == 0) {
1263 labpc_cancel(dev, s);
1264 async->events |= COMEDI_CB_EOA;
1265 }
1266 }
1267
1268 comedi_event(dev, s);
1269 return IRQ_HANDLED;
1270 }
1271
1272 static int labpc_ao_insn_write(struct comedi_device *dev,
1273 struct comedi_subdevice *s,
1274 struct comedi_insn *insn,
1275 unsigned int *data)
1276 {
1277 const struct labpc_boardinfo *board = comedi_board(dev);
1278 struct labpc_private *devpriv = dev->private;
1279 int channel, range;
1280 unsigned long flags;
1281 int lsb, msb;
1282
1283 channel = CR_CHAN(insn->chanspec);
1284
1285 /* turn off pacing of analog output channel */
1286 /* note: hardware bug in daqcard-1200 means pacing cannot
1287 * be independently enabled/disabled for its the two channels */
1288 spin_lock_irqsave(&dev->spinlock, flags);
1289 devpriv->cmd2 &= ~CMD2_LDAC(channel);
1290 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG);
1291 spin_unlock_irqrestore(&dev->spinlock, flags);
1292
1293 /* set range */
1294 if (board->register_layout == labpc_1200_layout) {
1295 range = CR_RANGE(insn->chanspec);
1296 if (labpc_range_is_unipolar(s, range))
1297 devpriv->cmd6 |= CMD6_DACUNI(channel);
1298 else
1299 devpriv->cmd6 &= ~CMD6_DACUNI(channel);
1300 /* write to register */
1301 devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG);
1302 }
1303 /* send data */
1304 lsb = data[0] & 0xff;
1305 msb = (data[0] >> 8) & 0xff;
1306 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1307 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1308
1309 /* remember value for readback */
1310 devpriv->ao_value[channel] = data[0];
1311
1312 return 1;
1313 }
1314
1315 static int labpc_ao_insn_read(struct comedi_device *dev,
1316 struct comedi_subdevice *s,
1317 struct comedi_insn *insn,
1318 unsigned int *data)
1319 {
1320 struct labpc_private *devpriv = dev->private;
1321
1322 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1323
1324 return 1;
1325 }
1326
1327 static int labpc_8255_mmio(int dir, int port, int data, unsigned long iobase)
1328 {
1329 if (dir) {
1330 writeb(data, (void __iomem *)(iobase + port));
1331 return 0;
1332 } else {
1333 return readb((void __iomem *)(iobase + port));
1334 }
1335 }
1336
1337 /* lowlevel write to eeprom/dac */
1338 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
1339 unsigned int value_width)
1340 {
1341 struct labpc_private *devpriv = dev->private;
1342 int i;
1343
1344 for (i = 1; i <= value_width; i++) {
1345 /* clear serial clock */
1346 devpriv->cmd5 &= ~CMD5_SCLK;
1347 /* send bits most significant bit first */
1348 if (value & (1 << (value_width - i)))
1349 devpriv->cmd5 |= CMD5_SDATA;
1350 else
1351 devpriv->cmd5 &= ~CMD5_SDATA;
1352 udelay(1);
1353 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1354 /* set clock to load bit */
1355 devpriv->cmd5 |= CMD5_SCLK;
1356 udelay(1);
1357 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1358 }
1359 }
1360
1361 /* lowlevel read from eeprom */
1362 static unsigned int labpc_serial_in(struct comedi_device *dev)
1363 {
1364 struct labpc_private *devpriv = dev->private;
1365 unsigned int value = 0;
1366 int i;
1367 const int value_width = 8; /* number of bits wide values are */
1368
1369 for (i = 1; i <= value_width; i++) {
1370 /* set serial clock */
1371 devpriv->cmd5 |= CMD5_SCLK;
1372 udelay(1);
1373 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1374 /* clear clock bit */
1375 devpriv->cmd5 &= ~CMD5_SCLK;
1376 udelay(1);
1377 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1378 /* read bits most significant bit first */
1379 udelay(1);
1380 devpriv->stat2 = devpriv->read_byte(dev->iobase + STAT2_REG);
1381 if (devpriv->stat2 & STAT2_PROMOUT)
1382 value |= 1 << (value_width - i);
1383 }
1384
1385 return value;
1386 }
1387
1388 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
1389 unsigned int address)
1390 {
1391 struct labpc_private *devpriv = dev->private;
1392 unsigned int value;
1393 /* bits to tell eeprom to expect a read */
1394 const int read_instruction = 0x3;
1395 /* 8 bit write lengths to eeprom */
1396 const int write_length = 8;
1397
1398 /* enable read/write to eeprom */
1399 devpriv->cmd5 &= ~CMD5_EEPROMCS;
1400 udelay(1);
1401 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1402 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT);
1403 udelay(1);
1404 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1405
1406 /* send read instruction */
1407 labpc_serial_out(dev, read_instruction, write_length);
1408 /* send 8 bit address to read from */
1409 labpc_serial_out(dev, address, write_length);
1410 /* read result */
1411 value = labpc_serial_in(dev);
1412
1413 /* disable read/write to eeprom */
1414 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT);
1415 udelay(1);
1416 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1417
1418 return value;
1419 }
1420
1421 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev)
1422 {
1423 struct labpc_private *devpriv = dev->private;
1424 unsigned int value;
1425 const int read_status_instruction = 0x5;
1426 const int write_length = 8; /* 8 bit write lengths to eeprom */
1427
1428 /* enable read/write to eeprom */
1429 devpriv->cmd5 &= ~CMD5_EEPROMCS;
1430 udelay(1);
1431 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1432 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT);
1433 udelay(1);
1434 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1435
1436 /* send read status instruction */
1437 labpc_serial_out(dev, read_status_instruction, write_length);
1438 /* read result */
1439 value = labpc_serial_in(dev);
1440
1441 /* disable read/write to eeprom */
1442 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT);
1443 udelay(1);
1444 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1445
1446 return value;
1447 }
1448
1449 static int labpc_eeprom_write(struct comedi_device *dev,
1450 unsigned int address, unsigned int value)
1451 {
1452 struct labpc_private *devpriv = dev->private;
1453 const int write_enable_instruction = 0x6;
1454 const int write_instruction = 0x2;
1455 const int write_length = 8; /* 8 bit write lengths to eeprom */
1456 const int write_in_progress_bit = 0x1;
1457 const int timeout = 10000;
1458 int i;
1459
1460 /* make sure there isn't already a write in progress */
1461 for (i = 0; i < timeout; i++) {
1462 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
1463 0)
1464 break;
1465 }
1466 if (i == timeout) {
1467 comedi_error(dev, "eeprom write timed out");
1468 return -ETIME;
1469 }
1470 /* update software copy of eeprom */
1471 devpriv->eeprom_data[address] = value;
1472
1473 /* enable read/write to eeprom */
1474 devpriv->cmd5 &= ~CMD5_EEPROMCS;
1475 udelay(1);
1476 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1477 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT);
1478 udelay(1);
1479 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1480
1481 /* send write_enable instruction */
1482 labpc_serial_out(dev, write_enable_instruction, write_length);
1483 devpriv->cmd5 &= ~CMD5_EEPROMCS;
1484 udelay(1);
1485 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1486
1487 /* send write instruction */
1488 devpriv->cmd5 |= CMD5_EEPROMCS;
1489 udelay(1);
1490 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1491 labpc_serial_out(dev, write_instruction, write_length);
1492 /* send 8 bit address to write to */
1493 labpc_serial_out(dev, address, write_length);
1494 /* write value */
1495 labpc_serial_out(dev, value, write_length);
1496 devpriv->cmd5 &= ~CMD5_EEPROMCS;
1497 udelay(1);
1498 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1499
1500 /* disable read/write to eeprom */
1501 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT);
1502 udelay(1);
1503 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1504
1505 return 0;
1506 }
1507
1508 /* writes to 8 bit calibration dacs */
1509 static void write_caldac(struct comedi_device *dev, unsigned int channel,
1510 unsigned int value)
1511 {
1512 struct labpc_private *devpriv = dev->private;
1513
1514 if (value == devpriv->caldac[channel])
1515 return;
1516 devpriv->caldac[channel] = value;
1517
1518 /* clear caldac load bit and make sure we don't write to eeprom */
1519 devpriv->cmd5 &= ~(CMD5_CALDACLD | CMD5_EEPROMCS | CMD5_WRTPRT);
1520 udelay(1);
1521 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1522
1523 /* write 4 bit channel */
1524 labpc_serial_out(dev, channel, 4);
1525 /* write 8 bit caldac value */
1526 labpc_serial_out(dev, value, 8);
1527
1528 /* set and clear caldac bit to load caldac value */
1529 devpriv->cmd5 |= CMD5_CALDACLD;
1530 udelay(1);
1531 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1532 devpriv->cmd5 &= ~CMD5_CALDACLD;
1533 udelay(1);
1534 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1535 }
1536
1537 static int labpc_calib_insn_write(struct comedi_device *dev,
1538 struct comedi_subdevice *s,
1539 struct comedi_insn *insn,
1540 unsigned int *data)
1541 {
1542 unsigned int chan = CR_CHAN(insn->chanspec);
1543
1544 /*
1545 * Only write the last data value to the caldac. Preceding
1546 * data would be overwritten anyway.
1547 */
1548 if (insn->n > 0)
1549 write_caldac(dev, chan, data[insn->n - 1]);
1550
1551 return insn->n;
1552 }
1553
1554 static int labpc_calib_insn_read(struct comedi_device *dev,
1555 struct comedi_subdevice *s,
1556 struct comedi_insn *insn,
1557 unsigned int *data)
1558 {
1559 struct labpc_private *devpriv = dev->private;
1560 unsigned int chan = CR_CHAN(insn->chanspec);
1561 int i;
1562
1563 for (i = 0; i < insn->n; i++)
1564 data[i] = devpriv->caldac[chan];
1565
1566 return insn->n;
1567 }
1568
1569 static int labpc_eeprom_insn_write(struct comedi_device *dev,
1570 struct comedi_subdevice *s,
1571 struct comedi_insn *insn,
1572 unsigned int *data)
1573 {
1574 unsigned int chan = CR_CHAN(insn->chanspec);
1575 int ret;
1576
1577 /* only allow writes to user area of eeprom */
1578 if (chan < 16 || chan > 127)
1579 return -EINVAL;
1580
1581 /*
1582 * Only write the last data value to the eeprom. Preceding
1583 * data would be overwritten anyway.
1584 */
1585 if (insn->n > 0) {
1586 ret = labpc_eeprom_write(dev, chan, data[insn->n - 1]);
1587 if (ret)
1588 return ret;
1589 }
1590
1591 return insn->n;
1592 }
1593
1594 static int labpc_eeprom_insn_read(struct comedi_device *dev,
1595 struct comedi_subdevice *s,
1596 struct comedi_insn *insn,
1597 unsigned int *data)
1598 {
1599 struct labpc_private *devpriv = dev->private;
1600 unsigned int chan = CR_CHAN(insn->chanspec);
1601 int i;
1602
1603 for (i = 0; i < insn->n; i++)
1604 data[i] = devpriv->eeprom_data[chan];
1605
1606 return insn->n;
1607 }
1608
1609 int labpc_common_attach(struct comedi_device *dev, unsigned long iobase,
1610 unsigned int irq, unsigned int dma_chan)
1611 {
1612 const struct labpc_boardinfo *board = comedi_board(dev);
1613 struct labpc_private *devpriv = dev->private;
1614 struct comedi_subdevice *s;
1615 unsigned long isr_flags;
1616 int ret;
1617 int i;
1618
1619 dev->board_name = board->name;
1620
1621 if (iobase == 0)
1622 return -EINVAL;
1623 if (board->bustype == isa_bustype) {
1624 if (!request_region(iobase, LABPC_SIZE, dev->board_name))
1625 return -EIO;
1626 }
1627 dev->iobase = iobase;
1628
1629 if (board->has_mmio) {
1630 devpriv->read_byte = labpc_readb;
1631 devpriv->write_byte = labpc_writeb;
1632 } else {
1633 devpriv->read_byte = labpc_inb;
1634 devpriv->write_byte = labpc_outb;
1635 }
1636
1637 /* initialize board's command registers */
1638 devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG);
1639 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG);
1640 devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG);
1641 devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG);
1642 if (board->register_layout == labpc_1200_layout) {
1643 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1644 devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG);
1645 }
1646
1647 if (irq) {
1648 isr_flags = 0;
1649 if (board->bustype == pci_bustype ||
1650 board->bustype == pcmcia_bustype)
1651 isr_flags |= IRQF_SHARED;
1652 ret = request_irq(irq, labpc_interrupt, isr_flags,
1653 dev->board_name, dev);
1654 if (ret == 0)
1655 dev->irq = irq;
1656 }
1657
1658 #ifdef CONFIG_ISA_DMA_API
1659 if (dev->irq && (dma_chan == 1 || dma_chan == 3)) {
1660 devpriv->dma_buffer = kmalloc(dma_buffer_size,
1661 GFP_KERNEL | GFP_DMA);
1662 if (devpriv->dma_buffer) {
1663 ret = request_dma(dma_chan, dev->board_name);
1664 if (ret == 0) {
1665 unsigned long dma_flags;
1666
1667 devpriv->dma_chan = dma_chan;
1668 dma_flags = claim_dma_lock();
1669 disable_dma(devpriv->dma_chan);
1670 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
1671 release_dma_lock(dma_flags);
1672 } else {
1673 kfree(devpriv->dma_buffer);
1674 }
1675 }
1676 }
1677 #endif
1678
1679 ret = comedi_alloc_subdevices(dev, 5);
1680 if (ret)
1681 return ret;
1682
1683 /* analog input subdevice */
1684 s = &dev->subdevices[0];
1685 s->type = COMEDI_SUBD_AI;
1686 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF;
1687 s->n_chan = 8;
1688 s->len_chanlist = 8;
1689 s->maxdata = 0x0fff;
1690 s->range_table = board->ai_range_table;
1691 s->insn_read = labpc_ai_insn_read;
1692 if (dev->irq) {
1693 dev->read_subdev = s;
1694 s->subdev_flags |= SDF_CMD_READ;
1695 s->do_cmd = labpc_ai_cmd;
1696 s->do_cmdtest = labpc_ai_cmdtest;
1697 s->cancel = labpc_cancel;
1698 }
1699
1700 /* analog output */
1701 s = &dev->subdevices[1];
1702 if (board->has_ao) {
1703 s->type = COMEDI_SUBD_AO;
1704 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
1705 s->n_chan = NUM_AO_CHAN;
1706 s->maxdata = 0x0fff;
1707 s->range_table = &range_labpc_ao;
1708 s->insn_read = labpc_ao_insn_read;
1709 s->insn_write = labpc_ao_insn_write;
1710
1711 /* initialize analog outputs to a known value */
1712 for (i = 0; i < s->n_chan; i++) {
1713 short lsb, msb;
1714
1715 devpriv->ao_value[i] = s->maxdata / 2;
1716 lsb = devpriv->ao_value[i] & 0xff;
1717 msb = (devpriv->ao_value[i] >> 8) & 0xff;
1718 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
1719 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
1720 }
1721 } else {
1722 s->type = COMEDI_SUBD_UNUSED;
1723 }
1724
1725 /* 8255 dio */
1726 s = &dev->subdevices[2];
1727 ret = subdev_8255_init(dev, s,
1728 (board->has_mmio) ? labpc_8255_mmio : NULL,
1729 dev->iobase + DIO_BASE_REG);
1730 if (ret)
1731 return ret;
1732
1733 /* calibration subdevices for boards that have one */
1734 s = &dev->subdevices[3];
1735 if (board->register_layout == labpc_1200_layout) {
1736 s->type = COMEDI_SUBD_CALIB;
1737 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1738 s->n_chan = 16;
1739 s->maxdata = 0xff;
1740 s->insn_read = labpc_calib_insn_read;
1741 s->insn_write = labpc_calib_insn_write;
1742
1743 for (i = 0; i < s->n_chan; i++)
1744 write_caldac(dev, i, s->maxdata / 2);
1745 } else
1746 s->type = COMEDI_SUBD_UNUSED;
1747
1748 /* EEPROM */
1749 s = &dev->subdevices[4];
1750 if (board->register_layout == labpc_1200_layout) {
1751 s->type = COMEDI_SUBD_MEMORY;
1752 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1753 s->n_chan = EEPROM_SIZE;
1754 s->maxdata = 0xff;
1755 s->insn_read = labpc_eeprom_insn_read;
1756 s->insn_write = labpc_eeprom_insn_write;
1757
1758 for (i = 0; i < s->n_chan; i++)
1759 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
1760 } else
1761 s->type = COMEDI_SUBD_UNUSED;
1762
1763 return 0;
1764 }
1765 EXPORT_SYMBOL_GPL(labpc_common_attach);
1766
1767 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1768 {
1769 const struct labpc_boardinfo *board = comedi_board(dev);
1770 struct labpc_private *devpriv;
1771 unsigned long iobase = 0;
1772 unsigned int irq = 0;
1773 unsigned int dma_chan = 0;
1774
1775 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1776 if (!devpriv)
1777 return -ENOMEM;
1778 dev->private = devpriv;
1779
1780 /* get base address, irq etc. based on bustype */
1781 switch (board->bustype) {
1782 case isa_bustype:
1783 #ifdef CONFIG_ISA_DMA_API
1784 iobase = it->options[0];
1785 irq = it->options[1];
1786 dma_chan = it->options[2];
1787 #else
1788 dev_err(dev->class_dev,
1789 "ni_labpc driver has not been built with ISA DMA support.\n");
1790 return -EINVAL;
1791 #endif
1792 break;
1793 case pci_bustype:
1794 #ifdef CONFIG_COMEDI_PCI_DRIVERS
1795 dev_err(dev->class_dev,
1796 "manual configuration of PCI board '%s' is not supported\n",
1797 board->name);
1798 return -EINVAL;
1799 #else
1800 dev_err(dev->class_dev,
1801 "ni_labpc driver has not been built with PCI support.\n");
1802 return -EINVAL;
1803 #endif
1804 break;
1805 default:
1806 dev_err(dev->class_dev,
1807 "ni_labpc: bug! couldn't determine board type\n");
1808 return -EINVAL;
1809 break;
1810 }
1811
1812 return labpc_common_attach(dev, iobase, irq, dma_chan);
1813 }
1814
1815 static const struct labpc_boardinfo *
1816 labpc_pci_find_boardinfo(struct pci_dev *pcidev)
1817 {
1818 unsigned int device_id = pcidev->device;
1819 unsigned int n;
1820
1821 for (n = 0; n < ARRAY_SIZE(labpc_boards); n++) {
1822 const struct labpc_boardinfo *board = &labpc_boards[n];
1823 if (board->bustype == pci_bustype &&
1824 board->device_id == device_id)
1825 return board;
1826 }
1827 return NULL;
1828 }
1829
1830 static int labpc_auto_attach(struct comedi_device *dev,
1831 unsigned long context_unused)
1832 {
1833 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1834 struct labpc_private *devpriv;
1835 unsigned long iobase;
1836 unsigned int irq;
1837 int ret;
1838
1839 if (!IS_ENABLED(CONFIG_COMEDI_PCI_DRIVERS))
1840 return -ENODEV;
1841
1842 ret = comedi_pci_enable(dev);
1843 if (ret)
1844 return ret;
1845
1846 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1847 if (!devpriv)
1848 return -ENOMEM;
1849 dev->private = devpriv;
1850
1851 dev->board_ptr = labpc_pci_find_boardinfo(pcidev);
1852 if (!dev->board_ptr)
1853 return -ENODEV;
1854 devpriv->mite = mite_alloc(pcidev);
1855 if (!devpriv->mite)
1856 return -ENOMEM;
1857 ret = mite_setup(devpriv->mite);
1858 if (ret < 0)
1859 return ret;
1860 iobase = (unsigned long)devpriv->mite->daq_io_addr;
1861 irq = mite_irq(devpriv->mite);
1862 return labpc_common_attach(dev, iobase, irq, 0);
1863 }
1864
1865 void labpc_common_detach(struct comedi_device *dev)
1866 {
1867 const struct labpc_boardinfo *board = comedi_board(dev);
1868 struct labpc_private *devpriv = dev->private;
1869 struct comedi_subdevice *s;
1870
1871 if (!board)
1872 return;
1873 if (dev->subdevices) {
1874 s = &dev->subdevices[2];
1875 subdev_8255_cleanup(dev, s);
1876 }
1877 #ifdef CONFIG_ISA_DMA_API
1878 /* only free stuff if it has been allocated by _attach */
1879 kfree(devpriv->dma_buffer);
1880 if (devpriv->dma_chan)
1881 free_dma(devpriv->dma_chan);
1882 #endif
1883 if (dev->irq)
1884 free_irq(dev->irq, dev);
1885 if (board->bustype == isa_bustype && dev->iobase)
1886 release_region(dev->iobase, LABPC_SIZE);
1887 #ifdef CONFIG_COMEDI_PCI_DRIVERS
1888 if (devpriv->mite) {
1889 mite_unsetup(devpriv->mite);
1890 mite_free(devpriv->mite);
1891 }
1892 if (board->bustype == pci_bustype)
1893 comedi_pci_disable(dev);
1894 #endif
1895 }
1896 EXPORT_SYMBOL_GPL(labpc_common_detach);
1897
1898 static struct comedi_driver labpc_driver = {
1899 .driver_name = "ni_labpc",
1900 .module = THIS_MODULE,
1901 .attach = labpc_attach,
1902 .auto_attach = labpc_auto_attach,
1903 .detach = labpc_common_detach,
1904 .num_names = ARRAY_SIZE(labpc_boards),
1905 .board_name = &labpc_boards[0].name,
1906 .offset = sizeof(struct labpc_boardinfo),
1907 };
1908
1909 #ifdef CONFIG_COMEDI_PCI_DRIVERS
1910 static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = {
1911 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161) },
1912 { 0 }
1913 };
1914 MODULE_DEVICE_TABLE(pci, labpc_pci_table);
1915
1916 static int labpc_pci_probe(struct pci_dev *dev,
1917 const struct pci_device_id *id)
1918 {
1919 return comedi_pci_auto_config(dev, &labpc_driver, id->driver_data);
1920 }
1921
1922 static struct pci_driver labpc_pci_driver = {
1923 .name = "ni_labpc",
1924 .id_table = labpc_pci_table,
1925 .probe = labpc_pci_probe,
1926 .remove = comedi_pci_auto_unconfig,
1927 };
1928 module_comedi_pci_driver(labpc_driver, labpc_pci_driver);
1929 #else
1930 module_comedi_driver(labpc_driver);
1931 #endif
1932
1933
1934 MODULE_AUTHOR("Comedi http://www.comedi.org");
1935 MODULE_DESCRIPTION("Comedi low-level driver");
1936 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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