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[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_labpc.c
1 /*
2 comedi/drivers/ni_labpc.c
3 Driver for National Instruments Lab-PC series boards and compatibles
4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
20 ************************************************************************
21 */
22 /*
23 Driver: ni_labpc
24 Description: National Instruments Lab-PC (& compatibles)
25 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
26 Devices: [National Instruments] Lab-PC-1200 (labpc-1200),
27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc)
28 Status: works
29
30 Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges
31 and analog references will work, the available ranges/arefs will
32 depend on how you have configured the jumpers on your board
33 (see your owner's manual).
34
35 Kernel-level ISA plug-and-play support for the lab-pc-1200
36 boards has not
37 yet been added to the driver, mainly due to the fact that
38 I don't know the device id numbers. If you have one
39 of these boards,
40 please file a bug report at http://comedi.org/
41 so I can get the necessary information from you.
42
43 The 1200 series boards have onboard calibration dacs for correcting
44 analog input/output offsets and gains. The proper settings for these
45 caldacs are stored on the board's eeprom. To read the caldac values
46 from the eeprom and store them into a file that can be then be used by
47 comedilib, use the comedi_calibrate program.
48
49 Configuration options - ISA boards:
50 [0] - I/O port base address
51 [1] - IRQ (optional, required for timed or externally triggered conversions)
52 [2] - DMA channel (optional)
53
54 Configuration options - PCI boards:
55 [0] - bus (optional)
56 [1] - slot (optional)
57
58 The Lab-pc+ has quirky chanlist requirements
59 when scanning multiple channels. Multiple channel scan
60 sequence must start at highest channel, then decrement down to
61 channel 0. The rest of the cards can scan down like lab-pc+ or scan
62 up from channel zero. Chanlists consisting of all one channel
63 are also legal, and allow you to pace conversions in bursts.
64
65 */
66
67 /*
68
69 NI manuals:
70 341309a (labpc-1200 register manual)
71 340914a (pci-1200)
72 320502b (lab-pc+)
73
74 */
75
76 #include <linux/pci.h>
77 #include <linux/interrupt.h>
78 #include <linux/slab.h>
79 #include <linux/io.h>
80 #include <linux/delay.h>
81
82 #include "../comedidev.h"
83
84 #include <asm/dma.h>
85
86 #include "8253.h"
87 #include "8255.h"
88 #include "mite.h"
89 #include "comedi_fc.h"
90 #include "ni_labpc.h"
91
92 #define DRV_NAME "ni_labpc"
93
94 /* size of io region used by board */
95 #define LABPC_SIZE 32
96 /* 2 MHz master clock */
97 #define LABPC_TIMER_BASE 500
98
99 /* Registers for the lab-pc+ */
100
101 /* write-only registers */
102 #define COMMAND1_REG 0x0
103 #define ADC_GAIN_MASK (0x7 << 4)
104 #define ADC_CHAN_BITS(x) ((x) & 0x7)
105 /* enables multi channel scans */
106 #define ADC_SCAN_EN_BIT 0x80
107 #define COMMAND2_REG 0x1
108 /* enable pretriggering (used in conjunction with SWTRIG) */
109 #define PRETRIG_BIT 0x1
110 /* enable paced conversions on external trigger */
111 #define HWTRIG_BIT 0x2
112 /* enable paced conversions */
113 #define SWTRIG_BIT 0x4
114 /* use two cascaded counters for pacing */
115 #define CASCADE_BIT 0x8
116 #define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1))
117 #define COMMAND3_REG 0x2
118 /* enable dma transfers */
119 #define DMA_EN_BIT 0x1
120 /* enable interrupts for 8255 */
121 #define DIO_INTR_EN_BIT 0x2
122 /* enable dma terminal count interrupt */
123 #define DMATC_INTR_EN_BIT 0x4
124 /* enable timer interrupt */
125 #define TIMER_INTR_EN_BIT 0x8
126 /* enable error interrupt */
127 #define ERR_INTR_EN_BIT 0x10
128 /* enable fifo not empty interrupt */
129 #define ADC_FNE_INTR_EN_BIT 0x20
130 #define ADC_CONVERT_REG 0x3
131 #define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1))
132 #define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1))
133 #define ADC_CLEAR_REG 0x8
134 #define DMATC_CLEAR_REG 0xa
135 #define TIMER_CLEAR_REG 0xc
136 /* 1200 boards only */
137 #define COMMAND6_REG 0xe
138 /* select ground or common-mode reference */
139 #define ADC_COMMON_BIT 0x1
140 /* adc unipolar */
141 #define ADC_UNIP_BIT 0x2
142 /* dac unipolar */
143 #define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1))
144 /* enable fifo half full interrupt */
145 #define ADC_FHF_INTR_EN_BIT 0x20
146 /* enable interrupt on end of hardware count */
147 #define A1_INTR_EN_BIT 0x40
148 /* scan up from channel zero instead of down to zero */
149 #define ADC_SCAN_UP_BIT 0x80
150 #define COMMAND4_REG 0xf
151 /* enables 'interval' scanning */
152 #define INTERVAL_SCAN_EN_BIT 0x1
153 /* enables external signal on counter b1 output to trigger scan */
154 #define EXT_SCAN_EN_BIT 0x2
155 /* chooses direction (output or input) for EXTCONV* line */
156 #define EXT_CONVERT_OUT_BIT 0x4
157 /* chooses differential inputs for adc (in conjunction with board jumper) */
158 #define ADC_DIFF_BIT 0x8
159 #define EXT_CONVERT_DISABLE_BIT 0x10
160 /* 1200 boards only, calibration stuff */
161 #define COMMAND5_REG 0x1c
162 /* enable eeprom for write */
163 #define EEPROM_WRITE_UNPROTECT_BIT 0x4
164 /* enable dithering */
165 #define DITHER_EN_BIT 0x8
166 /* load calibration dac */
167 #define CALDAC_LOAD_BIT 0x10
168 /* serial clock - rising edge writes, falling edge reads */
169 #define SCLOCK_BIT 0x20
170 /* serial data bit for writing to eeprom or calibration dacs */
171 #define SDATA_BIT 0x40
172 /* enable eeprom for read/write */
173 #define EEPROM_EN_BIT 0x80
174 #define INTERVAL_COUNT_REG 0x1e
175 #define INTERVAL_LOAD_REG 0x1f
176 #define INTERVAL_LOAD_BITS 0x1
177
178 /* read-only registers */
179 #define STATUS1_REG 0x0
180 /* data is available in fifo */
181 #define DATA_AVAIL_BIT 0x1
182 /* overrun has occurred */
183 #define OVERRUN_BIT 0x2
184 /* fifo overflow */
185 #define OVERFLOW_BIT 0x4
186 /* timer interrupt has occurred */
187 #define TIMER_BIT 0x8
188 /* dma terminal count has occurred */
189 #define DMATC_BIT 0x10
190 /* external trigger has occurred */
191 #define EXT_TRIG_BIT 0x40
192 /* 1200 boards only */
193 #define STATUS2_REG 0x1d
194 /* programmable eeprom serial output */
195 #define EEPROM_OUT_BIT 0x1
196 /* counter A1 terminal count */
197 #define A1_TC_BIT 0x2
198 /* fifo not half full */
199 #define FNHF_BIT 0x4
200 #define ADC_FIFO_REG 0xa
201
202 #define DIO_BASE_REG 0x10
203 #define COUNTER_A_BASE_REG 0x14
204 #define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3)
205 /* check modes put conversion pacer output in harmless state (a0 mode 2) */
206 #define INIT_A0_BITS 0x14
207 /* put hardware conversion counter output in harmless state (a1 mode 0) */
208 #define INIT_A1_BITS 0x70
209 #define COUNTER_B_BASE_REG 0x18
210
211 enum scan_mode {
212 MODE_SINGLE_CHAN,
213 MODE_SINGLE_CHAN_INTERVAL,
214 MODE_MULT_CHAN_UP,
215 MODE_MULT_CHAN_DOWN,
216 };
217
218 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
219 static irqreturn_t labpc_interrupt(int irq, void *d);
220 static int labpc_drain_fifo(struct comedi_device *dev);
221 #ifdef CONFIG_ISA_DMA_API
222 static void labpc_drain_dma(struct comedi_device *dev);
223 static void handle_isa_dma(struct comedi_device *dev);
224 #endif
225 static void labpc_drain_dregs(struct comedi_device *dev);
226 static int labpc_ai_cmdtest(struct comedi_device *dev,
227 struct comedi_subdevice *s, struct comedi_cmd *cmd);
228 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
229 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
230 struct comedi_insn *insn, unsigned int *data);
231 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
232 struct comedi_insn *insn, unsigned int *data);
233 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
234 struct comedi_insn *insn, unsigned int *data);
235 static int labpc_calib_read_insn(struct comedi_device *dev,
236 struct comedi_subdevice *s,
237 struct comedi_insn *insn, unsigned int *data);
238 static int labpc_calib_write_insn(struct comedi_device *dev,
239 struct comedi_subdevice *s,
240 struct comedi_insn *insn, unsigned int *data);
241 static int labpc_eeprom_read_insn(struct comedi_device *dev,
242 struct comedi_subdevice *s,
243 struct comedi_insn *insn, unsigned int *data);
244 static int labpc_eeprom_write_insn(struct comedi_device *dev,
245 struct comedi_subdevice *s,
246 struct comedi_insn *insn,
247 unsigned int *data);
248 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd,
249 enum scan_mode scan_mode);
250 #ifdef CONFIG_ISA_DMA_API
251 static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd);
252 #endif
253 static int labpc_dio_mem_callback(int dir, int port, int data,
254 unsigned long arg);
255 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
256 unsigned int num_bits);
257 static unsigned int labpc_serial_in(struct comedi_device *dev);
258 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
259 unsigned int address);
260 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev);
261 static int labpc_eeprom_write(struct comedi_device *dev,
262 unsigned int address,
263 unsigned int value);
264 static void write_caldac(struct comedi_device *dev, unsigned int channel,
265 unsigned int value);
266
267 /* analog input ranges */
268 #define NUM_LABPC_PLUS_AI_RANGES 16
269 /* indicates unipolar ranges */
270 static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = {
271 0,
272 0,
273 0,
274 0,
275 0,
276 0,
277 0,
278 0,
279 1,
280 1,
281 1,
282 1,
283 1,
284 1,
285 1,
286 1,
287 };
288
289 /* map range index to gain bits */
290 static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = {
291 0x00,
292 0x10,
293 0x20,
294 0x30,
295 0x40,
296 0x50,
297 0x60,
298 0x70,
299 0x00,
300 0x10,
301 0x20,
302 0x30,
303 0x40,
304 0x50,
305 0x60,
306 0x70,
307 };
308
309 static const struct comedi_lrange range_labpc_plus_ai = {
310 NUM_LABPC_PLUS_AI_RANGES,
311 {
312 BIP_RANGE(5),
313 BIP_RANGE(4),
314 BIP_RANGE(2.5),
315 BIP_RANGE(1),
316 BIP_RANGE(0.5),
317 BIP_RANGE(0.25),
318 BIP_RANGE(0.1),
319 BIP_RANGE(0.05),
320 UNI_RANGE(10),
321 UNI_RANGE(8),
322 UNI_RANGE(5),
323 UNI_RANGE(2),
324 UNI_RANGE(1),
325 UNI_RANGE(0.5),
326 UNI_RANGE(0.2),
327 UNI_RANGE(0.1),
328 }
329 };
330
331 #define NUM_LABPC_1200_AI_RANGES 14
332 /* indicates unipolar ranges */
333 const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = {
334 0,
335 0,
336 0,
337 0,
338 0,
339 0,
340 0,
341 1,
342 1,
343 1,
344 1,
345 1,
346 1,
347 1,
348 };
349 EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar);
350
351 /* map range index to gain bits */
352 const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = {
353 0x00,
354 0x20,
355 0x30,
356 0x40,
357 0x50,
358 0x60,
359 0x70,
360 0x00,
361 0x20,
362 0x30,
363 0x40,
364 0x50,
365 0x60,
366 0x70,
367 };
368 EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits);
369
370 const struct comedi_lrange range_labpc_1200_ai = {
371 NUM_LABPC_1200_AI_RANGES,
372 {
373 BIP_RANGE(5),
374 BIP_RANGE(2.5),
375 BIP_RANGE(1),
376 BIP_RANGE(0.5),
377 BIP_RANGE(0.25),
378 BIP_RANGE(0.1),
379 BIP_RANGE(0.05),
380 UNI_RANGE(10),
381 UNI_RANGE(5),
382 UNI_RANGE(2),
383 UNI_RANGE(1),
384 UNI_RANGE(0.5),
385 UNI_RANGE(0.2),
386 UNI_RANGE(0.1),
387 }
388 };
389 EXPORT_SYMBOL_GPL(range_labpc_1200_ai);
390
391 /* analog output ranges */
392 #define AO_RANGE_IS_UNIPOLAR 0x1
393 static const struct comedi_lrange range_labpc_ao = {
394 2,
395 {
396 BIP_RANGE(5),
397 UNI_RANGE(10),
398 }
399 };
400
401 /* functions that do inb/outb and readb/writeb so we can use
402 * function pointers to decide which to use */
403 static inline unsigned int labpc_inb(unsigned long address)
404 {
405 return inb(address);
406 }
407
408 static inline void labpc_outb(unsigned int byte, unsigned long address)
409 {
410 outb(byte, address);
411 }
412
413 static inline unsigned int labpc_readb(unsigned long address)
414 {
415 return readb((void __iomem *)address);
416 }
417
418 static inline void labpc_writeb(unsigned int byte, unsigned long address)
419 {
420 writeb(byte, (void __iomem *)address);
421 }
422
423 static const struct labpc_board_struct labpc_boards[] = {
424 {
425 .name = "lab-pc-1200",
426 .ai_speed = 10000,
427 .bustype = isa_bustype,
428 .register_layout = labpc_1200_layout,
429 .has_ao = 1,
430 .ai_range_table = &range_labpc_1200_ai,
431 .ai_range_code = labpc_1200_ai_gain_bits,
432 .ai_range_is_unipolar = labpc_1200_is_unipolar,
433 .ai_scan_up = 1,
434 .memory_mapped_io = 0,
435 },
436 {
437 .name = "lab-pc-1200ai",
438 .ai_speed = 10000,
439 .bustype = isa_bustype,
440 .register_layout = labpc_1200_layout,
441 .has_ao = 0,
442 .ai_range_table = &range_labpc_1200_ai,
443 .ai_range_code = labpc_1200_ai_gain_bits,
444 .ai_range_is_unipolar = labpc_1200_is_unipolar,
445 .ai_scan_up = 1,
446 .memory_mapped_io = 0,
447 },
448 {
449 .name = "lab-pc+",
450 .ai_speed = 12000,
451 .bustype = isa_bustype,
452 .register_layout = labpc_plus_layout,
453 .has_ao = 1,
454 .ai_range_table = &range_labpc_plus_ai,
455 .ai_range_code = labpc_plus_ai_gain_bits,
456 .ai_range_is_unipolar = labpc_plus_is_unipolar,
457 .ai_scan_up = 0,
458 .memory_mapped_io = 0,
459 },
460 #ifdef CONFIG_COMEDI_PCI_DRIVERS
461 {
462 .name = "pci-1200",
463 .device_id = 0x161,
464 .ai_speed = 10000,
465 .bustype = pci_bustype,
466 .register_layout = labpc_1200_layout,
467 .has_ao = 1,
468 .ai_range_table = &range_labpc_1200_ai,
469 .ai_range_code = labpc_1200_ai_gain_bits,
470 .ai_range_is_unipolar = labpc_1200_is_unipolar,
471 .ai_scan_up = 1,
472 .memory_mapped_io = 1,
473 },
474 /* dummy entry so pci board works when comedi_config is passed driver name */
475 {
476 .name = DRV_NAME,
477 .bustype = pci_bustype,
478 },
479 #endif
480 };
481
482 /*
483 * Useful for shorthand access to the particular board structure
484 */
485 #define thisboard ((struct labpc_board_struct *)dev->board_ptr)
486
487 /* size in bytes of dma buffer */
488 static const int dma_buffer_size = 0xff00;
489 /* 2 bytes per sample */
490 static const int sample_size = 2;
491
492 static inline int labpc_counter_load(struct comedi_device *dev,
493 unsigned long base_address,
494 unsigned int counter_number,
495 unsigned int count, unsigned int mode)
496 {
497 if (thisboard->memory_mapped_io)
498 return i8254_mm_load((void __iomem *)base_address, 0,
499 counter_number, count, mode);
500 else
501 return i8254_load(base_address, 0, counter_number, count, mode);
502 }
503
504 int labpc_common_attach(struct comedi_device *dev, unsigned long iobase,
505 unsigned int irq, unsigned int dma_chan)
506 {
507 struct labpc_private *devpriv = dev->private;
508 struct comedi_subdevice *s;
509 int i;
510 unsigned long isr_flags;
511 #ifdef CONFIG_ISA_DMA_API
512 unsigned long dma_flags;
513 #endif
514 short lsb, msb;
515 int ret;
516
517 dev_info(dev->class_dev, "ni_labpc: %s\n", thisboard->name);
518 if (iobase == 0) {
519 dev_err(dev->class_dev, "io base address is zero!\n");
520 return -EINVAL;
521 }
522 /* request io regions for isa boards */
523 if (thisboard->bustype == isa_bustype) {
524 /* check if io addresses are available */
525 if (!request_region(iobase, LABPC_SIZE, DRV_NAME)) {
526 dev_err(dev->class_dev, "I/O port conflict\n");
527 return -EIO;
528 }
529 }
530 dev->iobase = iobase;
531
532 if (thisboard->memory_mapped_io) {
533 devpriv->read_byte = labpc_readb;
534 devpriv->write_byte = labpc_writeb;
535 } else {
536 devpriv->read_byte = labpc_inb;
537 devpriv->write_byte = labpc_outb;
538 }
539 /* initialize board's command registers */
540 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
541 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
542 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
543 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
544 if (thisboard->register_layout == labpc_1200_layout) {
545 devpriv->write_byte(devpriv->command5_bits,
546 dev->iobase + COMMAND5_REG);
547 devpriv->write_byte(devpriv->command6_bits,
548 dev->iobase + COMMAND6_REG);
549 }
550
551 /* grab our IRQ */
552 if (irq) {
553 isr_flags = 0;
554 if (thisboard->bustype == pci_bustype
555 || thisboard->bustype == pcmcia_bustype)
556 isr_flags |= IRQF_SHARED;
557 if (request_irq(irq, labpc_interrupt, isr_flags,
558 DRV_NAME, dev)) {
559 dev_err(dev->class_dev, "unable to allocate irq %u\n",
560 irq);
561 return -EINVAL;
562 }
563 }
564 dev->irq = irq;
565
566 #ifdef CONFIG_ISA_DMA_API
567 /* grab dma channel */
568 if (dma_chan > 3) {
569 dev_err(dev->class_dev, "invalid dma channel %u\n", dma_chan);
570 return -EINVAL;
571 } else if (dma_chan) {
572 /* allocate dma buffer */
573 devpriv->dma_buffer = kmalloc(dma_buffer_size,
574 GFP_KERNEL | GFP_DMA);
575 if (devpriv->dma_buffer == NULL)
576 return -ENOMEM;
577
578 if (request_dma(dma_chan, DRV_NAME)) {
579 dev_err(dev->class_dev,
580 "failed to allocate dma channel %u\n",
581 dma_chan);
582 return -EINVAL;
583 }
584 devpriv->dma_chan = dma_chan;
585 dma_flags = claim_dma_lock();
586 disable_dma(devpriv->dma_chan);
587 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
588 release_dma_lock(dma_flags);
589 }
590 #endif
591
592 dev->board_name = thisboard->name;
593
594 ret = comedi_alloc_subdevices(dev, 5);
595 if (ret)
596 return ret;
597
598 /* analog input subdevice */
599 s = &dev->subdevices[0];
600 dev->read_subdev = s;
601 s->type = COMEDI_SUBD_AI;
602 s->subdev_flags =
603 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
604 s->n_chan = 8;
605 s->len_chanlist = 8;
606 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
607 s->range_table = thisboard->ai_range_table;
608 s->do_cmd = labpc_ai_cmd;
609 s->do_cmdtest = labpc_ai_cmdtest;
610 s->insn_read = labpc_ai_rinsn;
611 s->cancel = labpc_cancel;
612
613 /* analog output */
614 s = &dev->subdevices[1];
615 if (thisboard->has_ao) {
616 /*
617 * Could provide command support, except it only has a
618 * one sample hardware buffer for analog output and no
619 * underrun flag.
620 */
621 s->type = COMEDI_SUBD_AO;
622 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
623 s->n_chan = NUM_AO_CHAN;
624 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
625 s->range_table = &range_labpc_ao;
626 s->insn_read = labpc_ao_rinsn;
627 s->insn_write = labpc_ao_winsn;
628 /* initialize analog outputs to a known value */
629 for (i = 0; i < s->n_chan; i++) {
630 devpriv->ao_value[i] = s->maxdata / 2;
631 lsb = devpriv->ao_value[i] & 0xff;
632 msb = (devpriv->ao_value[i] >> 8) & 0xff;
633 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
634 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
635 }
636 } else {
637 s->type = COMEDI_SUBD_UNUSED;
638 }
639
640 /* 8255 dio */
641 s = &dev->subdevices[2];
642 /* if board uses io memory we have to give a custom callback
643 * function to the 8255 driver */
644 if (thisboard->memory_mapped_io)
645 subdev_8255_init(dev, s, labpc_dio_mem_callback,
646 (unsigned long)(dev->iobase + DIO_BASE_REG));
647 else
648 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG);
649
650 /* calibration subdevices for boards that have one */
651 s = &dev->subdevices[3];
652 if (thisboard->register_layout == labpc_1200_layout) {
653 s->type = COMEDI_SUBD_CALIB;
654 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
655 s->n_chan = 16;
656 s->maxdata = 0xff;
657 s->insn_read = labpc_calib_read_insn;
658 s->insn_write = labpc_calib_write_insn;
659
660 for (i = 0; i < s->n_chan; i++)
661 write_caldac(dev, i, s->maxdata / 2);
662 } else
663 s->type = COMEDI_SUBD_UNUSED;
664
665 /* EEPROM */
666 s = &dev->subdevices[4];
667 if (thisboard->register_layout == labpc_1200_layout) {
668 s->type = COMEDI_SUBD_MEMORY;
669 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
670 s->n_chan = EEPROM_SIZE;
671 s->maxdata = 0xff;
672 s->insn_read = labpc_eeprom_read_insn;
673 s->insn_write = labpc_eeprom_write_insn;
674
675 for (i = 0; i < EEPROM_SIZE; i++)
676 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
677 } else
678 s->type = COMEDI_SUBD_UNUSED;
679
680 return 0;
681 }
682 EXPORT_SYMBOL_GPL(labpc_common_attach);
683
684 static const struct labpc_board_struct *
685 labpc_pci_find_boardinfo(struct pci_dev *pcidev)
686 {
687 unsigned int device_id = pcidev->device;
688 unsigned int n;
689
690 for (n = 0; n < ARRAY_SIZE(labpc_boards); n++) {
691 const struct labpc_board_struct *board = &labpc_boards[n];
692 if (board->bustype == pci_bustype &&
693 board->device_id == device_id)
694 return board;
695 }
696 return NULL;
697 }
698
699 static int labpc_auto_attach(struct comedi_device *dev,
700 unsigned long context_unused)
701 {
702 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
703 struct labpc_private *devpriv;
704 unsigned long iobase;
705 unsigned int irq;
706 int ret;
707
708 if (!IS_ENABLED(CONFIG_COMEDI_PCI_DRIVERS))
709 return -ENODEV;
710
711 ret = comedi_pci_enable(dev);
712 if (ret)
713 return ret;
714 dev->iobase = 1;
715
716 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
717 if (!devpriv)
718 return -ENOMEM;
719 dev->private = devpriv;
720
721 dev->board_ptr = labpc_pci_find_boardinfo(pcidev);
722 if (!dev->board_ptr)
723 return -ENODEV;
724 devpriv->mite = mite_alloc(pcidev);
725 if (!devpriv->mite)
726 return -ENOMEM;
727 ret = mite_setup(devpriv->mite);
728 if (ret < 0)
729 return ret;
730 iobase = (unsigned long)devpriv->mite->daq_io_addr;
731 irq = mite_irq(devpriv->mite);
732 return labpc_common_attach(dev, iobase, irq, 0);
733 }
734
735 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it)
736 {
737 struct labpc_private *devpriv;
738 unsigned long iobase = 0;
739 unsigned int irq = 0;
740 unsigned int dma_chan = 0;
741
742 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
743 if (!devpriv)
744 return -ENOMEM;
745 dev->private = devpriv;
746
747 /* get base address, irq etc. based on bustype */
748 switch (thisboard->bustype) {
749 case isa_bustype:
750 #ifdef CONFIG_ISA_DMA_API
751 iobase = it->options[0];
752 irq = it->options[1];
753 dma_chan = it->options[2];
754 #else
755 dev_err(dev->class_dev,
756 "ni_labpc driver has not been built with ISA DMA support.\n");
757 return -EINVAL;
758 #endif
759 break;
760 case pci_bustype:
761 #ifdef CONFIG_COMEDI_PCI_DRIVERS
762 dev_err(dev->class_dev,
763 "manual configuration of PCI board '%s' is not supported\n",
764 thisboard->name);
765 return -EINVAL;
766 #else
767 dev_err(dev->class_dev,
768 "ni_labpc driver has not been built with PCI support.\n");
769 return -EINVAL;
770 #endif
771 break;
772 default:
773 dev_err(dev->class_dev,
774 "ni_labpc: bug! couldn't determine board type\n");
775 return -EINVAL;
776 break;
777 }
778
779 return labpc_common_attach(dev, iobase, irq, dma_chan);
780 }
781
782 void labpc_common_detach(struct comedi_device *dev)
783 {
784 struct labpc_private *devpriv = dev->private;
785 struct comedi_subdevice *s;
786
787 if (!thisboard)
788 return;
789 if (dev->subdevices) {
790 s = &dev->subdevices[2];
791 subdev_8255_cleanup(dev, s);
792 }
793 #ifdef CONFIG_ISA_DMA_API
794 /* only free stuff if it has been allocated by _attach */
795 kfree(devpriv->dma_buffer);
796 if (devpriv->dma_chan)
797 free_dma(devpriv->dma_chan);
798 #endif
799 if (dev->irq)
800 free_irq(dev->irq, dev);
801 if (thisboard->bustype == isa_bustype && dev->iobase)
802 release_region(dev->iobase, LABPC_SIZE);
803 #ifdef CONFIG_COMEDI_PCI_DRIVERS
804 if (devpriv->mite) {
805 mite_unsetup(devpriv->mite);
806 mite_free(devpriv->mite);
807 }
808 comedi_pci_disable(dev);
809 #endif
810 };
811 EXPORT_SYMBOL_GPL(labpc_common_detach);
812
813 static void labpc_clear_adc_fifo(const struct comedi_device *dev)
814 {
815 struct labpc_private *devpriv = dev->private;
816
817 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
818 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
819 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
820 }
821
822 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
823 {
824 struct labpc_private *devpriv = dev->private;
825 unsigned long flags;
826
827 spin_lock_irqsave(&dev->spinlock, flags);
828 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
829 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
830 spin_unlock_irqrestore(&dev->spinlock, flags);
831
832 devpriv->command3_bits = 0;
833 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
834
835 return 0;
836 }
837
838 static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd)
839 {
840 if (cmd->chanlist_len == 1)
841 return MODE_SINGLE_CHAN;
842
843 /* chanlist may be NULL during cmdtest. */
844 if (cmd->chanlist == NULL)
845 return MODE_MULT_CHAN_UP;
846
847 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
848 return MODE_SINGLE_CHAN_INTERVAL;
849
850 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
851 return MODE_MULT_CHAN_UP;
852
853 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
854 return MODE_MULT_CHAN_DOWN;
855
856 pr_err("ni_labpc: bug! cannot determine AI scan mode\n");
857 return 0;
858 }
859
860 static int labpc_ai_chanlist_invalid(const struct comedi_device *dev,
861 const struct comedi_cmd *cmd,
862 enum scan_mode mode)
863 {
864 int channel, range, aref, i;
865
866 if (cmd->chanlist == NULL)
867 return 0;
868
869 if (mode == MODE_SINGLE_CHAN)
870 return 0;
871
872 if (mode == MODE_SINGLE_CHAN_INTERVAL) {
873 if (cmd->chanlist_len > 0xff) {
874 comedi_error(dev,
875 "ni_labpc: chanlist too long for single channel interval mode\n");
876 return 1;
877 }
878 }
879
880 channel = CR_CHAN(cmd->chanlist[0]);
881 range = CR_RANGE(cmd->chanlist[0]);
882 aref = CR_AREF(cmd->chanlist[0]);
883
884 for (i = 0; i < cmd->chanlist_len; i++) {
885
886 switch (mode) {
887 case MODE_SINGLE_CHAN_INTERVAL:
888 if (CR_CHAN(cmd->chanlist[i]) != channel) {
889 comedi_error(dev,
890 "channel scanning order specified in chanlist is not supported by hardware.\n");
891 return 1;
892 }
893 break;
894 case MODE_MULT_CHAN_UP:
895 if (CR_CHAN(cmd->chanlist[i]) != i) {
896 comedi_error(dev,
897 "channel scanning order specified in chanlist is not supported by hardware.\n");
898 return 1;
899 }
900 break;
901 case MODE_MULT_CHAN_DOWN:
902 if (CR_CHAN(cmd->chanlist[i]) !=
903 cmd->chanlist_len - i - 1) {
904 comedi_error(dev,
905 "channel scanning order specified in chanlist is not supported by hardware.\n");
906 return 1;
907 }
908 break;
909 default:
910 dev_err(dev->class_dev,
911 "ni_labpc: bug! in chanlist check\n");
912 return 1;
913 break;
914 }
915
916 if (CR_RANGE(cmd->chanlist[i]) != range) {
917 comedi_error(dev,
918 "entries in chanlist must all have the same range\n");
919 return 1;
920 }
921
922 if (CR_AREF(cmd->chanlist[i]) != aref) {
923 comedi_error(dev,
924 "entries in chanlist must all have the same reference\n");
925 return 1;
926 }
927 }
928
929 return 0;
930 }
931
932 static int labpc_use_continuous_mode(const struct comedi_cmd *cmd,
933 enum scan_mode mode)
934 {
935 if (mode == MODE_SINGLE_CHAN)
936 return 1;
937
938 if (cmd->scan_begin_src == TRIG_FOLLOW)
939 return 1;
940
941 return 0;
942 }
943
944 static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd,
945 enum scan_mode mode)
946 {
947 if (cmd->convert_src != TRIG_TIMER)
948 return 0;
949
950 if (mode == MODE_SINGLE_CHAN && cmd->scan_begin_src == TRIG_TIMER)
951 return cmd->scan_begin_arg;
952
953 return cmd->convert_arg;
954 }
955
956 static void labpc_set_ai_convert_period(struct comedi_cmd *cmd,
957 enum scan_mode mode, unsigned int ns)
958 {
959 if (cmd->convert_src != TRIG_TIMER)
960 return;
961
962 if (mode == MODE_SINGLE_CHAN &&
963 cmd->scan_begin_src == TRIG_TIMER) {
964 cmd->scan_begin_arg = ns;
965 if (cmd->convert_arg > cmd->scan_begin_arg)
966 cmd->convert_arg = cmd->scan_begin_arg;
967 } else
968 cmd->convert_arg = ns;
969 }
970
971 static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd,
972 enum scan_mode mode)
973 {
974 if (cmd->scan_begin_src != TRIG_TIMER)
975 return 0;
976
977 if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER)
978 return 0;
979
980 return cmd->scan_begin_arg;
981 }
982
983 static void labpc_set_ai_scan_period(struct comedi_cmd *cmd,
984 enum scan_mode mode, unsigned int ns)
985 {
986 if (cmd->scan_begin_src != TRIG_TIMER)
987 return;
988
989 if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER)
990 return;
991
992 cmd->scan_begin_arg = ns;
993 }
994
995 static int labpc_ai_cmdtest(struct comedi_device *dev,
996 struct comedi_subdevice *s, struct comedi_cmd *cmd)
997 {
998 int err = 0;
999 int tmp, tmp2;
1000 unsigned int stop_mask;
1001 enum scan_mode mode;
1002
1003 /* Step 1 : check if triggers are trivially valid */
1004
1005 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
1006 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
1007 TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT);
1008 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
1009 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1010
1011 stop_mask = TRIG_COUNT | TRIG_NONE;
1012 if (thisboard->register_layout == labpc_1200_layout)
1013 stop_mask |= TRIG_EXT;
1014 err |= cfc_check_trigger_src(&cmd->stop_src, stop_mask);
1015
1016 if (err)
1017 return 1;
1018
1019 /* Step 2a : make sure trigger sources are unique */
1020
1021 err |= cfc_check_trigger_is_unique(cmd->start_src);
1022 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
1023 err |= cfc_check_trigger_is_unique(cmd->convert_src);
1024 err |= cfc_check_trigger_is_unique(cmd->stop_src);
1025
1026 /* Step 2b : and mutually compatible */
1027
1028 /* can't have external stop and start triggers at once */
1029 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
1030 err++;
1031
1032 if (err)
1033 return 2;
1034
1035 /* Step 3: check if arguments are trivially valid */
1036
1037 if (cmd->start_arg == TRIG_NOW)
1038 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
1039
1040 if (!cmd->chanlist_len)
1041 err |= -EINVAL;
1042 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
1043
1044 if (cmd->convert_src == TRIG_TIMER)
1045 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
1046 thisboard->ai_speed);
1047
1048 /* make sure scan timing is not too fast */
1049 if (cmd->scan_begin_src == TRIG_TIMER) {
1050 if (cmd->convert_src == TRIG_TIMER)
1051 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
1052 cmd->convert_arg * cmd->chanlist_len);
1053 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
1054 thisboard->ai_speed * cmd->chanlist_len);
1055 }
1056
1057 switch (cmd->stop_src) {
1058 case TRIG_COUNT:
1059 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
1060 break;
1061 case TRIG_NONE:
1062 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
1063 break;
1064 /*
1065 * TRIG_EXT doesn't care since it doesn't
1066 * trigger off a numbered channel
1067 */
1068 default:
1069 break;
1070 }
1071
1072 if (err)
1073 return 3;
1074
1075 /* step 4: fix up any arguments */
1076
1077 tmp = cmd->convert_arg;
1078 tmp2 = cmd->scan_begin_arg;
1079 mode = labpc_ai_scan_mode(cmd);
1080 labpc_adc_timing(dev, cmd, mode);
1081 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
1082 err++;
1083
1084 if (err)
1085 return 4;
1086
1087 if (labpc_ai_chanlist_invalid(dev, cmd, mode))
1088 return 5;
1089
1090 return 0;
1091 }
1092
1093 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1094 {
1095 struct labpc_private *devpriv = dev->private;
1096 int channel, range, aref;
1097 #ifdef CONFIG_ISA_DMA_API
1098 unsigned long irq_flags;
1099 #endif
1100 int ret;
1101 struct comedi_async *async = s->async;
1102 struct comedi_cmd *cmd = &async->cmd;
1103 enum transfer_type xfer;
1104 enum scan_mode mode;
1105 unsigned long flags;
1106
1107 if (!dev->irq) {
1108 comedi_error(dev, "no irq assigned, cannot perform command");
1109 return -1;
1110 }
1111
1112 range = CR_RANGE(cmd->chanlist[0]);
1113 aref = CR_AREF(cmd->chanlist[0]);
1114
1115 /* make sure board is disabled before setting up acquisition */
1116 spin_lock_irqsave(&dev->spinlock, flags);
1117 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1118 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1119 spin_unlock_irqrestore(&dev->spinlock, flags);
1120
1121 devpriv->command3_bits = 0;
1122 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1123
1124 /* initialize software conversion count */
1125 if (cmd->stop_src == TRIG_COUNT)
1126 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
1127
1128 /* setup hardware conversion counter */
1129 if (cmd->stop_src == TRIG_EXT) {
1130 /*
1131 * load counter a1 with count of 3
1132 * (pc+ manual says this is minimum allowed) using mode 0
1133 */
1134 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1135 1, 3, 0);
1136 if (ret < 0) {
1137 comedi_error(dev, "error loading counter a1");
1138 return -1;
1139 }
1140 } else /*
1141 * otherwise, just put a1 in mode 0
1142 * with no count to set its output low
1143 */
1144 devpriv->write_byte(INIT_A1_BITS,
1145 dev->iobase + COUNTER_A_CONTROL_REG);
1146
1147 #ifdef CONFIG_ISA_DMA_API
1148 /* figure out what method we will use to transfer data */
1149 if (devpriv->dma_chan && /* need a dma channel allocated */
1150 /*
1151 * dma unsafe at RT priority,
1152 * and too much setup time for TRIG_WAKE_EOS for
1153 */
1154 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
1155 /* only available on the isa boards */
1156 thisboard->bustype == isa_bustype) {
1157 xfer = isa_dma_transfer;
1158 /* pc-plus has no fifo-half full interrupt */
1159 } else
1160 #endif
1161 if (thisboard->register_layout == labpc_1200_layout &&
1162 /* wake-end-of-scan should interrupt on fifo not empty */
1163 (cmd->flags & TRIG_WAKE_EOS) == 0 &&
1164 /* make sure we are taking more than just a few points */
1165 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
1166 xfer = fifo_half_full_transfer;
1167 } else
1168 xfer = fifo_not_empty_transfer;
1169 devpriv->current_transfer = xfer;
1170 mode = labpc_ai_scan_mode(cmd);
1171
1172 /* setup command6 register for 1200 boards */
1173 if (thisboard->register_layout == labpc_1200_layout) {
1174 /* reference inputs to ground or common? */
1175 if (aref != AREF_GROUND)
1176 devpriv->command6_bits |= ADC_COMMON_BIT;
1177 else
1178 devpriv->command6_bits &= ~ADC_COMMON_BIT;
1179 /* bipolar or unipolar range? */
1180 if (thisboard->ai_range_is_unipolar[range])
1181 devpriv->command6_bits |= ADC_UNIP_BIT;
1182 else
1183 devpriv->command6_bits &= ~ADC_UNIP_BIT;
1184 /* interrupt on fifo half full? */
1185 if (xfer == fifo_half_full_transfer)
1186 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT;
1187 else
1188 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1189 /* enable interrupt on counter a1 terminal count? */
1190 if (cmd->stop_src == TRIG_EXT)
1191 devpriv->command6_bits |= A1_INTR_EN_BIT;
1192 else
1193 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1194 /* are we scanning up or down through channels? */
1195 if (mode == MODE_MULT_CHAN_UP)
1196 devpriv->command6_bits |= ADC_SCAN_UP_BIT;
1197 else
1198 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT;
1199 /* write to register */
1200 devpriv->write_byte(devpriv->command6_bits,
1201 dev->iobase + COMMAND6_REG);
1202 }
1203
1204 /* setup channel list, etc (command1 register) */
1205 devpriv->command1_bits = 0;
1206 if (mode == MODE_MULT_CHAN_UP)
1207 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
1208 else
1209 channel = CR_CHAN(cmd->chanlist[0]);
1210 /* munge channel bits for differential / scan disabled mode */
1211 if ((mode == MODE_SINGLE_CHAN || mode == MODE_SINGLE_CHAN_INTERVAL) &&
1212 aref == AREF_DIFF)
1213 channel *= 2;
1214 devpriv->command1_bits |= ADC_CHAN_BITS(channel);
1215 devpriv->command1_bits |= thisboard->ai_range_code[range];
1216 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1217 /* manual says to set scan enable bit on second pass */
1218 if (mode == MODE_MULT_CHAN_UP || mode == MODE_MULT_CHAN_DOWN) {
1219 devpriv->command1_bits |= ADC_SCAN_EN_BIT;
1220 /* need a brief delay before enabling scan, or scan
1221 * list will get screwed when you switch
1222 * between scan up to scan down mode - dunno why */
1223 udelay(1);
1224 devpriv->write_byte(devpriv->command1_bits,
1225 dev->iobase + COMMAND1_REG);
1226 }
1227
1228 devpriv->write_byte(cmd->chanlist_len,
1229 dev->iobase + INTERVAL_COUNT_REG);
1230 /* load count */
1231 devpriv->write_byte(INTERVAL_LOAD_BITS,
1232 dev->iobase + INTERVAL_LOAD_REG);
1233
1234 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) {
1235 /* set up pacing */
1236 labpc_adc_timing(dev, cmd, mode);
1237 /* load counter b0 in mode 3 */
1238 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1239 0, devpriv->divisor_b0, 3);
1240 if (ret < 0) {
1241 comedi_error(dev, "error loading counter b0");
1242 return -1;
1243 }
1244 }
1245 /* set up conversion pacing */
1246 if (labpc_ai_convert_period(cmd, mode)) {
1247 /* load counter a0 in mode 2 */
1248 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1249 0, devpriv->divisor_a0, 2);
1250 if (ret < 0) {
1251 comedi_error(dev, "error loading counter a0");
1252 return -1;
1253 }
1254 } else
1255 devpriv->write_byte(INIT_A0_BITS,
1256 dev->iobase + COUNTER_A_CONTROL_REG);
1257
1258 /* set up scan pacing */
1259 if (labpc_ai_scan_period(cmd, mode)) {
1260 /* load counter b1 in mode 2 */
1261 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1262 1, devpriv->divisor_b1, 2);
1263 if (ret < 0) {
1264 comedi_error(dev, "error loading counter b1");
1265 return -1;
1266 }
1267 }
1268
1269 labpc_clear_adc_fifo(dev);
1270
1271 #ifdef CONFIG_ISA_DMA_API
1272 /* set up dma transfer */
1273 if (xfer == isa_dma_transfer) {
1274 irq_flags = claim_dma_lock();
1275 disable_dma(devpriv->dma_chan);
1276 /* clear flip-flop to make sure 2-byte registers for
1277 * count and address get set correctly */
1278 clear_dma_ff(devpriv->dma_chan);
1279 set_dma_addr(devpriv->dma_chan,
1280 virt_to_bus(devpriv->dma_buffer));
1281 /* set appropriate size of transfer */
1282 devpriv->dma_transfer_size = labpc_suggest_transfer_size(cmd);
1283 if (cmd->stop_src == TRIG_COUNT &&
1284 devpriv->count * sample_size < devpriv->dma_transfer_size) {
1285 devpriv->dma_transfer_size =
1286 devpriv->count * sample_size;
1287 }
1288 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1289 enable_dma(devpriv->dma_chan);
1290 release_dma_lock(irq_flags);
1291 /* enable board's dma */
1292 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT;
1293 } else
1294 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT;
1295 #endif
1296
1297 /* enable error interrupts */
1298 devpriv->command3_bits |= ERR_INTR_EN_BIT;
1299 /* enable fifo not empty interrupt? */
1300 if (xfer == fifo_not_empty_transfer)
1301 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT;
1302 else
1303 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT;
1304 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1305
1306 /* setup any external triggering/pacing (command4 register) */
1307 devpriv->command4_bits = 0;
1308 if (cmd->convert_src != TRIG_EXT)
1309 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1310 /* XXX should discard first scan when using interval scanning
1311 * since manual says it is not synced with scan clock */
1312 if (labpc_use_continuous_mode(cmd, mode) == 0) {
1313 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT;
1314 if (cmd->scan_begin_src == TRIG_EXT)
1315 devpriv->command4_bits |= EXT_SCAN_EN_BIT;
1316 }
1317 /* single-ended/differential */
1318 if (aref == AREF_DIFF)
1319 devpriv->command4_bits |= ADC_DIFF_BIT;
1320 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1321
1322 /* startup acquisition */
1323
1324 /* command2 reg */
1325 /* use 2 cascaded counters for pacing */
1326 spin_lock_irqsave(&dev->spinlock, flags);
1327 devpriv->command2_bits |= CASCADE_BIT;
1328 switch (cmd->start_src) {
1329 case TRIG_EXT:
1330 devpriv->command2_bits |= HWTRIG_BIT;
1331 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT;
1332 break;
1333 case TRIG_NOW:
1334 devpriv->command2_bits |= SWTRIG_BIT;
1335 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT;
1336 break;
1337 default:
1338 comedi_error(dev, "bug with start_src");
1339 spin_unlock_irqrestore(&dev->spinlock, flags);
1340 return -1;
1341 break;
1342 }
1343 switch (cmd->stop_src) {
1344 case TRIG_EXT:
1345 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT;
1346 break;
1347 case TRIG_COUNT:
1348 case TRIG_NONE:
1349 break;
1350 default:
1351 comedi_error(dev, "bug with stop_src");
1352 spin_unlock_irqrestore(&dev->spinlock, flags);
1353 return -1;
1354 }
1355 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1356 spin_unlock_irqrestore(&dev->spinlock, flags);
1357
1358 return 0;
1359 }
1360
1361 /* interrupt service routine */
1362 static irqreturn_t labpc_interrupt(int irq, void *d)
1363 {
1364 struct comedi_device *dev = d;
1365 struct labpc_private *devpriv = dev->private;
1366 struct comedi_subdevice *s = dev->read_subdev;
1367 struct comedi_async *async;
1368 struct comedi_cmd *cmd;
1369
1370 if (dev->attached == 0) {
1371 comedi_error(dev, "premature interrupt");
1372 return IRQ_HANDLED;
1373 }
1374
1375 async = s->async;
1376 cmd = &async->cmd;
1377 async->events = 0;
1378
1379 /* read board status */
1380 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1381 if (thisboard->register_layout == labpc_1200_layout)
1382 devpriv->status2_bits =
1383 devpriv->read_byte(dev->iobase + STATUS2_REG);
1384
1385 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT |
1386 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0
1387 && (devpriv->status2_bits & A1_TC_BIT) == 0
1388 && (devpriv->status2_bits & FNHF_BIT)) {
1389 return IRQ_NONE;
1390 }
1391
1392 if (devpriv->status1_bits & OVERRUN_BIT) {
1393 /* clear error interrupt */
1394 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1395 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1396 comedi_event(dev, s);
1397 comedi_error(dev, "overrun");
1398 return IRQ_HANDLED;
1399 }
1400
1401 #ifdef CONFIG_ISA_DMA_API
1402 if (devpriv->current_transfer == isa_dma_transfer) {
1403 /*
1404 * if a dma terminal count of external stop trigger
1405 * has occurred
1406 */
1407 if (devpriv->status1_bits & DMATC_BIT ||
1408 (thisboard->register_layout == labpc_1200_layout
1409 && devpriv->status2_bits & A1_TC_BIT)) {
1410 handle_isa_dma(dev);
1411 }
1412 } else
1413 #endif
1414 labpc_drain_fifo(dev);
1415
1416 if (devpriv->status1_bits & TIMER_BIT) {
1417 comedi_error(dev, "handled timer interrupt?");
1418 /* clear it */
1419 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1420 }
1421
1422 if (devpriv->status1_bits & OVERFLOW_BIT) {
1423 /* clear error interrupt */
1424 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1425 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1426 comedi_event(dev, s);
1427 comedi_error(dev, "overflow");
1428 return IRQ_HANDLED;
1429 }
1430 /* handle external stop trigger */
1431 if (cmd->stop_src == TRIG_EXT) {
1432 if (devpriv->status2_bits & A1_TC_BIT) {
1433 labpc_drain_dregs(dev);
1434 labpc_cancel(dev, s);
1435 async->events |= COMEDI_CB_EOA;
1436 }
1437 }
1438
1439 /* TRIG_COUNT end of acquisition */
1440 if (cmd->stop_src == TRIG_COUNT) {
1441 if (devpriv->count == 0) {
1442 labpc_cancel(dev, s);
1443 async->events |= COMEDI_CB_EOA;
1444 }
1445 }
1446
1447 comedi_event(dev, s);
1448 return IRQ_HANDLED;
1449 }
1450
1451 /* read all available samples from ai fifo */
1452 static int labpc_drain_fifo(struct comedi_device *dev)
1453 {
1454 struct labpc_private *devpriv = dev->private;
1455 unsigned int lsb, msb;
1456 short data;
1457 struct comedi_async *async = dev->read_subdev->async;
1458 const int timeout = 10000;
1459 unsigned int i;
1460
1461 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1462
1463 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout;
1464 i++) {
1465 /* quit if we have all the data we want */
1466 if (async->cmd.stop_src == TRIG_COUNT) {
1467 if (devpriv->count == 0)
1468 break;
1469 devpriv->count--;
1470 }
1471 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1472 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1473 data = (msb << 8) | lsb;
1474 cfc_write_to_buffer(dev->read_subdev, data);
1475 devpriv->status1_bits =
1476 devpriv->read_byte(dev->iobase + STATUS1_REG);
1477 }
1478 if (i == timeout) {
1479 comedi_error(dev, "ai timeout, fifo never empties");
1480 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1481 return -1;
1482 }
1483
1484 return 0;
1485 }
1486
1487 #ifdef CONFIG_ISA_DMA_API
1488 static void labpc_drain_dma(struct comedi_device *dev)
1489 {
1490 struct labpc_private *devpriv = dev->private;
1491 struct comedi_subdevice *s = dev->read_subdev;
1492 struct comedi_async *async = s->async;
1493 int status;
1494 unsigned long flags;
1495 unsigned int max_points, num_points, residue, leftover;
1496 int i;
1497
1498 status = devpriv->status1_bits;
1499
1500 flags = claim_dma_lock();
1501 disable_dma(devpriv->dma_chan);
1502 /* clear flip-flop to make sure 2-byte registers for
1503 * count and address get set correctly */
1504 clear_dma_ff(devpriv->dma_chan);
1505
1506 /* figure out how many points to read */
1507 max_points = devpriv->dma_transfer_size / sample_size;
1508 /* residue is the number of points left to be done on the dma
1509 * transfer. It should always be zero at this point unless
1510 * the stop_src is set to external triggering.
1511 */
1512 residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1513 num_points = max_points - residue;
1514 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1515 num_points = devpriv->count;
1516
1517 /* figure out how many points will be stored next time */
1518 leftover = 0;
1519 if (async->cmd.stop_src != TRIG_COUNT) {
1520 leftover = devpriv->dma_transfer_size / sample_size;
1521 } else if (devpriv->count > num_points) {
1522 leftover = devpriv->count - num_points;
1523 if (leftover > max_points)
1524 leftover = max_points;
1525 }
1526
1527 /* write data to comedi buffer */
1528 for (i = 0; i < num_points; i++)
1529 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
1530
1531 if (async->cmd.stop_src == TRIG_COUNT)
1532 devpriv->count -= num_points;
1533
1534 /* set address and count for next transfer */
1535 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1536 set_dma_count(devpriv->dma_chan, leftover * sample_size);
1537 release_dma_lock(flags);
1538
1539 async->events |= COMEDI_CB_BLOCK;
1540 }
1541
1542 static void handle_isa_dma(struct comedi_device *dev)
1543 {
1544 struct labpc_private *devpriv = dev->private;
1545
1546 labpc_drain_dma(dev);
1547
1548 enable_dma(devpriv->dma_chan);
1549
1550 /* clear dma tc interrupt */
1551 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1552 }
1553 #endif
1554
1555 /* makes sure all data acquired by board is transferred to comedi (used
1556 * when acquisition is terminated by stop_src == TRIG_EXT). */
1557 static void labpc_drain_dregs(struct comedi_device *dev)
1558 {
1559 #ifdef CONFIG_ISA_DMA_API
1560 struct labpc_private *devpriv = dev->private;
1561
1562 if (devpriv->current_transfer == isa_dma_transfer)
1563 labpc_drain_dma(dev);
1564 #endif
1565
1566 labpc_drain_fifo(dev);
1567 }
1568
1569 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1570 struct comedi_insn *insn, unsigned int *data)
1571 {
1572 struct labpc_private *devpriv = dev->private;
1573 int i, n;
1574 int chan, range;
1575 int lsb, msb;
1576 int timeout = 1000;
1577 unsigned long flags;
1578
1579 /* disable timed conversions */
1580 spin_lock_irqsave(&dev->spinlock, flags);
1581 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1582 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1583 spin_unlock_irqrestore(&dev->spinlock, flags);
1584
1585 /* disable interrupt generation and dma */
1586 devpriv->command3_bits = 0;
1587 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1588
1589 /* set gain and channel */
1590 devpriv->command1_bits = 0;
1591 chan = CR_CHAN(insn->chanspec);
1592 range = CR_RANGE(insn->chanspec);
1593 devpriv->command1_bits |= thisboard->ai_range_code[range];
1594 /* munge channel bits for differential/scan disabled mode */
1595 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1596 chan *= 2;
1597 devpriv->command1_bits |= ADC_CHAN_BITS(chan);
1598 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1599
1600 /* setup command6 register for 1200 boards */
1601 if (thisboard->register_layout == labpc_1200_layout) {
1602 /* reference inputs to ground or common? */
1603 if (CR_AREF(insn->chanspec) != AREF_GROUND)
1604 devpriv->command6_bits |= ADC_COMMON_BIT;
1605 else
1606 devpriv->command6_bits &= ~ADC_COMMON_BIT;
1607 /* bipolar or unipolar range? */
1608 if (thisboard->ai_range_is_unipolar[range])
1609 devpriv->command6_bits |= ADC_UNIP_BIT;
1610 else
1611 devpriv->command6_bits &= ~ADC_UNIP_BIT;
1612 /* don't interrupt on fifo half full */
1613 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1614 /* don't enable interrupt on counter a1 terminal count? */
1615 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1616 /* write to register */
1617 devpriv->write_byte(devpriv->command6_bits,
1618 dev->iobase + COMMAND6_REG);
1619 }
1620 /* setup command4 register */
1621 devpriv->command4_bits = 0;
1622 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1623 /* single-ended/differential */
1624 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1625 devpriv->command4_bits |= ADC_DIFF_BIT;
1626 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1627
1628 /*
1629 * initialize pacer counter output to make sure it doesn't
1630 * cause any problems
1631 */
1632 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG);
1633
1634 labpc_clear_adc_fifo(dev);
1635
1636 for (n = 0; n < insn->n; n++) {
1637 /* trigger conversion */
1638 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG);
1639
1640 for (i = 0; i < timeout; i++) {
1641 if (devpriv->read_byte(dev->iobase +
1642 STATUS1_REG) & DATA_AVAIL_BIT)
1643 break;
1644 udelay(1);
1645 }
1646 if (i == timeout) {
1647 comedi_error(dev, "timeout");
1648 return -ETIME;
1649 }
1650 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1651 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1652 data[n] = (msb << 8) | lsb;
1653 }
1654
1655 return n;
1656 }
1657
1658 /* analog output insn */
1659 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1660 struct comedi_insn *insn, unsigned int *data)
1661 {
1662 struct labpc_private *devpriv = dev->private;
1663 int channel, range;
1664 unsigned long flags;
1665 int lsb, msb;
1666
1667 channel = CR_CHAN(insn->chanspec);
1668
1669 /* turn off pacing of analog output channel */
1670 /* note: hardware bug in daqcard-1200 means pacing cannot
1671 * be independently enabled/disabled for its the two channels */
1672 spin_lock_irqsave(&dev->spinlock, flags);
1673 devpriv->command2_bits &= ~DAC_PACED_BIT(channel);
1674 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1675 spin_unlock_irqrestore(&dev->spinlock, flags);
1676
1677 /* set range */
1678 if (thisboard->register_layout == labpc_1200_layout) {
1679 range = CR_RANGE(insn->chanspec);
1680 if (range & AO_RANGE_IS_UNIPOLAR)
1681 devpriv->command6_bits |= DAC_UNIP_BIT(channel);
1682 else
1683 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel);
1684 /* write to register */
1685 devpriv->write_byte(devpriv->command6_bits,
1686 dev->iobase + COMMAND6_REG);
1687 }
1688 /* send data */
1689 lsb = data[0] & 0xff;
1690 msb = (data[0] >> 8) & 0xff;
1691 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1692 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1693
1694 /* remember value for readback */
1695 devpriv->ao_value[channel] = data[0];
1696
1697 return 1;
1698 }
1699
1700 /* analog output readback insn */
1701 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1702 struct comedi_insn *insn, unsigned int *data)
1703 {
1704 struct labpc_private *devpriv = dev->private;
1705
1706 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1707
1708 return 1;
1709 }
1710
1711 static int labpc_calib_read_insn(struct comedi_device *dev,
1712 struct comedi_subdevice *s,
1713 struct comedi_insn *insn, unsigned int *data)
1714 {
1715 struct labpc_private *devpriv = dev->private;
1716
1717 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)];
1718
1719 return 1;
1720 }
1721
1722 static int labpc_calib_write_insn(struct comedi_device *dev,
1723 struct comedi_subdevice *s,
1724 struct comedi_insn *insn, unsigned int *data)
1725 {
1726 int channel = CR_CHAN(insn->chanspec);
1727
1728 write_caldac(dev, channel, data[0]);
1729 return 1;
1730 }
1731
1732 static int labpc_eeprom_read_insn(struct comedi_device *dev,
1733 struct comedi_subdevice *s,
1734 struct comedi_insn *insn, unsigned int *data)
1735 {
1736 struct labpc_private *devpriv = dev->private;
1737
1738 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)];
1739
1740 return 1;
1741 }
1742
1743 static int labpc_eeprom_write_insn(struct comedi_device *dev,
1744 struct comedi_subdevice *s,
1745 struct comedi_insn *insn, unsigned int *data)
1746 {
1747 int channel = CR_CHAN(insn->chanspec);
1748 int ret;
1749
1750 /* only allow writes to user area of eeprom */
1751 if (channel < 16 || channel > 127) {
1752 dev_dbg(dev->class_dev,
1753 "eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)\n");
1754 return -EINVAL;
1755 }
1756
1757 ret = labpc_eeprom_write(dev, channel, data[0]);
1758 if (ret < 0)
1759 return ret;
1760
1761 return 1;
1762 }
1763
1764 #ifdef CONFIG_ISA_DMA_API
1765 /* utility function that suggests a dma transfer size in bytes */
1766 static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd)
1767 {
1768 unsigned int size;
1769 unsigned int freq;
1770
1771 if (cmd->convert_src == TRIG_TIMER)
1772 freq = 1000000000 / cmd->convert_arg;
1773 /* return some default value */
1774 else
1775 freq = 0xffffffff;
1776
1777 /* make buffer fill in no more than 1/3 second */
1778 size = (freq / 3) * sample_size;
1779
1780 /* set a minimum and maximum size allowed */
1781 if (size > dma_buffer_size)
1782 size = dma_buffer_size - dma_buffer_size % sample_size;
1783 else if (size < sample_size)
1784 size = sample_size;
1785
1786 return size;
1787 }
1788 #endif
1789
1790 /* figures out what counter values to use based on command */
1791 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd,
1792 enum scan_mode mode)
1793 {
1794 struct labpc_private *devpriv = dev->private;
1795 /* max value for 16 bit counter in mode 2 */
1796 const int max_counter_value = 0x10000;
1797 /* min value for 16 bit counter in mode 2 */
1798 const int min_counter_value = 2;
1799 unsigned int base_period;
1800 unsigned int scan_period;
1801 unsigned int convert_period;
1802
1803 /*
1804 * if both convert and scan triggers are TRIG_TIMER, then they
1805 * both rely on counter b0
1806 */
1807 convert_period = labpc_ai_convert_period(cmd, mode);
1808 scan_period = labpc_ai_scan_period(cmd, mode);
1809 if (convert_period && scan_period) {
1810 /*
1811 * pick the lowest b0 divisor value we can (for maximum input
1812 * clock speed on convert and scan counters)
1813 */
1814 devpriv->divisor_b0 = (scan_period - 1) /
1815 (LABPC_TIMER_BASE * max_counter_value) + 1;
1816 if (devpriv->divisor_b0 < min_counter_value)
1817 devpriv->divisor_b0 = min_counter_value;
1818 if (devpriv->divisor_b0 > max_counter_value)
1819 devpriv->divisor_b0 = max_counter_value;
1820
1821 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
1822
1823 /* set a0 for conversion frequency and b1 for scan frequency */
1824 switch (cmd->flags & TRIG_ROUND_MASK) {
1825 default:
1826 case TRIG_ROUND_NEAREST:
1827 devpriv->divisor_a0 =
1828 (convert_period + (base_period / 2)) / base_period;
1829 devpriv->divisor_b1 =
1830 (scan_period + (base_period / 2)) / base_period;
1831 break;
1832 case TRIG_ROUND_UP:
1833 devpriv->divisor_a0 =
1834 (convert_period + (base_period - 1)) / base_period;
1835 devpriv->divisor_b1 =
1836 (scan_period + (base_period - 1)) / base_period;
1837 break;
1838 case TRIG_ROUND_DOWN:
1839 devpriv->divisor_a0 = convert_period / base_period;
1840 devpriv->divisor_b1 = scan_period / base_period;
1841 break;
1842 }
1843 /* make sure a0 and b1 values are acceptable */
1844 if (devpriv->divisor_a0 < min_counter_value)
1845 devpriv->divisor_a0 = min_counter_value;
1846 if (devpriv->divisor_a0 > max_counter_value)
1847 devpriv->divisor_a0 = max_counter_value;
1848 if (devpriv->divisor_b1 < min_counter_value)
1849 devpriv->divisor_b1 = min_counter_value;
1850 if (devpriv->divisor_b1 > max_counter_value)
1851 devpriv->divisor_b1 = max_counter_value;
1852 /* write corrected timings to command */
1853 labpc_set_ai_convert_period(cmd, mode,
1854 base_period * devpriv->divisor_a0);
1855 labpc_set_ai_scan_period(cmd, mode,
1856 base_period * devpriv->divisor_b1);
1857 /*
1858 * if only one TRIG_TIMER is used, we can employ the generic
1859 * cascaded timing functions
1860 */
1861 } else if (scan_period) {
1862 /*
1863 * calculate cascaded counter values
1864 * that give desired scan timing
1865 */
1866 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1867 &(devpriv->divisor_b1),
1868 &(devpriv->divisor_b0),
1869 &scan_period,
1870 cmd->flags & TRIG_ROUND_MASK);
1871 labpc_set_ai_scan_period(cmd, mode, scan_period);
1872 } else if (convert_period) {
1873 /*
1874 * calculate cascaded counter values
1875 * that give desired conversion timing
1876 */
1877 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1878 &(devpriv->divisor_a0),
1879 &(devpriv->divisor_b0),
1880 &convert_period,
1881 cmd->flags & TRIG_ROUND_MASK);
1882 labpc_set_ai_convert_period(cmd, mode, convert_period);
1883 }
1884 }
1885
1886 static int labpc_dio_mem_callback(int dir, int port, int data,
1887 unsigned long iobase)
1888 {
1889 if (dir) {
1890 writeb(data, (void __iomem *)(iobase + port));
1891 return 0;
1892 } else {
1893 return readb((void __iomem *)(iobase + port));
1894 }
1895 }
1896
1897 /* lowlevel write to eeprom/dac */
1898 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
1899 unsigned int value_width)
1900 {
1901 struct labpc_private *devpriv = dev->private;
1902 int i;
1903
1904 for (i = 1; i <= value_width; i++) {
1905 /* clear serial clock */
1906 devpriv->command5_bits &= ~SCLOCK_BIT;
1907 /* send bits most significant bit first */
1908 if (value & (1 << (value_width - i)))
1909 devpriv->command5_bits |= SDATA_BIT;
1910 else
1911 devpriv->command5_bits &= ~SDATA_BIT;
1912 udelay(1);
1913 devpriv->write_byte(devpriv->command5_bits,
1914 dev->iobase + COMMAND5_REG);
1915 /* set clock to load bit */
1916 devpriv->command5_bits |= SCLOCK_BIT;
1917 udelay(1);
1918 devpriv->write_byte(devpriv->command5_bits,
1919 dev->iobase + COMMAND5_REG);
1920 }
1921 }
1922
1923 /* lowlevel read from eeprom */
1924 static unsigned int labpc_serial_in(struct comedi_device *dev)
1925 {
1926 struct labpc_private *devpriv = dev->private;
1927 unsigned int value = 0;
1928 int i;
1929 const int value_width = 8; /* number of bits wide values are */
1930
1931 for (i = 1; i <= value_width; i++) {
1932 /* set serial clock */
1933 devpriv->command5_bits |= SCLOCK_BIT;
1934 udelay(1);
1935 devpriv->write_byte(devpriv->command5_bits,
1936 dev->iobase + COMMAND5_REG);
1937 /* clear clock bit */
1938 devpriv->command5_bits &= ~SCLOCK_BIT;
1939 udelay(1);
1940 devpriv->write_byte(devpriv->command5_bits,
1941 dev->iobase + COMMAND5_REG);
1942 /* read bits most significant bit first */
1943 udelay(1);
1944 devpriv->status2_bits =
1945 devpriv->read_byte(dev->iobase + STATUS2_REG);
1946 if (devpriv->status2_bits & EEPROM_OUT_BIT)
1947 value |= 1 << (value_width - i);
1948 }
1949
1950 return value;
1951 }
1952
1953 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
1954 unsigned int address)
1955 {
1956 struct labpc_private *devpriv = dev->private;
1957 unsigned int value;
1958 /* bits to tell eeprom to expect a read */
1959 const int read_instruction = 0x3;
1960 /* 8 bit write lengths to eeprom */
1961 const int write_length = 8;
1962
1963 /* enable read/write to eeprom */
1964 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1965 udelay(1);
1966 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1967 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1968 udelay(1);
1969 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1970
1971 /* send read instruction */
1972 labpc_serial_out(dev, read_instruction, write_length);
1973 /* send 8 bit address to read from */
1974 labpc_serial_out(dev, address, write_length);
1975 /* read result */
1976 value = labpc_serial_in(dev);
1977
1978 /* disable read/write to eeprom */
1979 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1980 udelay(1);
1981 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1982
1983 return value;
1984 }
1985
1986 static int labpc_eeprom_write(struct comedi_device *dev,
1987 unsigned int address, unsigned int value)
1988 {
1989 struct labpc_private *devpriv = dev->private;
1990 const int write_enable_instruction = 0x6;
1991 const int write_instruction = 0x2;
1992 const int write_length = 8; /* 8 bit write lengths to eeprom */
1993 const int write_in_progress_bit = 0x1;
1994 const int timeout = 10000;
1995 int i;
1996
1997 /* make sure there isn't already a write in progress */
1998 for (i = 0; i < timeout; i++) {
1999 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
2000 0)
2001 break;
2002 }
2003 if (i == timeout) {
2004 comedi_error(dev, "eeprom write timed out");
2005 return -ETIME;
2006 }
2007 /* update software copy of eeprom */
2008 devpriv->eeprom_data[address] = value;
2009
2010 /* enable read/write to eeprom */
2011 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2012 udelay(1);
2013 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2014 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2015 udelay(1);
2016 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2017
2018 /* send write_enable instruction */
2019 labpc_serial_out(dev, write_enable_instruction, write_length);
2020 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2021 udelay(1);
2022 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2023
2024 /* send write instruction */
2025 devpriv->command5_bits |= EEPROM_EN_BIT;
2026 udelay(1);
2027 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2028 labpc_serial_out(dev, write_instruction, write_length);
2029 /* send 8 bit address to write to */
2030 labpc_serial_out(dev, address, write_length);
2031 /* write value */
2032 labpc_serial_out(dev, value, write_length);
2033 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2034 udelay(1);
2035 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2036
2037 /* disable read/write to eeprom */
2038 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2039 udelay(1);
2040 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2041
2042 return 0;
2043 }
2044
2045 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev)
2046 {
2047 struct labpc_private *devpriv = dev->private;
2048 unsigned int value;
2049 const int read_status_instruction = 0x5;
2050 const int write_length = 8; /* 8 bit write lengths to eeprom */
2051
2052 /* enable read/write to eeprom */
2053 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2054 udelay(1);
2055 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2056 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2057 udelay(1);
2058 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2059
2060 /* send read status instruction */
2061 labpc_serial_out(dev, read_status_instruction, write_length);
2062 /* read result */
2063 value = labpc_serial_in(dev);
2064
2065 /* disable read/write to eeprom */
2066 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2067 udelay(1);
2068 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2069
2070 return value;
2071 }
2072
2073 /* writes to 8 bit calibration dacs */
2074 static void write_caldac(struct comedi_device *dev, unsigned int channel,
2075 unsigned int value)
2076 {
2077 struct labpc_private *devpriv = dev->private;
2078
2079 if (value == devpriv->caldac[channel])
2080 return;
2081 devpriv->caldac[channel] = value;
2082
2083 /* clear caldac load bit and make sure we don't write to eeprom */
2084 devpriv->command5_bits &=
2085 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2086 udelay(1);
2087 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2088
2089 /* write 4 bit channel */
2090 labpc_serial_out(dev, channel, 4);
2091 /* write 8 bit caldac value */
2092 labpc_serial_out(dev, value, 8);
2093
2094 /* set and clear caldac bit to load caldac value */
2095 devpriv->command5_bits |= CALDAC_LOAD_BIT;
2096 udelay(1);
2097 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2098 devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
2099 udelay(1);
2100 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2101 }
2102
2103 static struct comedi_driver labpc_driver = {
2104 .driver_name = DRV_NAME,
2105 .module = THIS_MODULE,
2106 .attach = labpc_attach,
2107 .auto_attach = labpc_auto_attach,
2108 .detach = labpc_common_detach,
2109 .num_names = ARRAY_SIZE(labpc_boards),
2110 .board_name = &labpc_boards[0].name,
2111 .offset = sizeof(struct labpc_board_struct),
2112 };
2113
2114 #ifdef CONFIG_COMEDI_PCI_DRIVERS
2115 static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = {
2116 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161)},
2117 {0}
2118 };
2119 MODULE_DEVICE_TABLE(pci, labpc_pci_table);
2120
2121 static int labpc_pci_probe(struct pci_dev *dev,
2122 const struct pci_device_id *id)
2123 {
2124 return comedi_pci_auto_config(dev, &labpc_driver, id->driver_data);
2125 }
2126
2127 static struct pci_driver labpc_pci_driver = {
2128 .name = DRV_NAME,
2129 .id_table = labpc_pci_table,
2130 .probe = labpc_pci_probe,
2131 .remove = comedi_pci_auto_unconfig,
2132 };
2133 module_comedi_pci_driver(labpc_driver, labpc_pci_driver);
2134 #else
2135 module_comedi_driver(labpc_driver);
2136 #endif
2137
2138
2139 MODULE_AUTHOR("Comedi http://www.comedi.org");
2140 MODULE_DESCRIPTION("Comedi low-level driver");
2141 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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