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staging: comedi: ni_labpc: use module_comedi_pci_driver()
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_labpc.c
1 /*
2 comedi/drivers/ni_labpc.c
3 Driver for National Instruments Lab-PC series boards and compatibles
4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
20 ************************************************************************
21 */
22 /*
23 Driver: ni_labpc
24 Description: National Instruments Lab-PC (& compatibles)
25 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
26 Devices: [National Instruments] Lab-PC-1200 (labpc-1200),
27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc)
28 Status: works
29
30 Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges
31 and analog references will work, the available ranges/arefs will
32 depend on how you have configured the jumpers on your board
33 (see your owner's manual).
34
35 Kernel-level ISA plug-and-play support for the lab-pc-1200
36 boards has not
37 yet been added to the driver, mainly due to the fact that
38 I don't know the device id numbers. If you have one
39 of these boards,
40 please file a bug report at http://comedi.org/
41 so I can get the necessary information from you.
42
43 The 1200 series boards have onboard calibration dacs for correcting
44 analog input/output offsets and gains. The proper settings for these
45 caldacs are stored on the board's eeprom. To read the caldac values
46 from the eeprom and store them into a file that can be then be used by
47 comedilib, use the comedi_calibrate program.
48
49 Configuration options - ISA boards:
50 [0] - I/O port base address
51 [1] - IRQ (optional, required for timed or externally triggered conversions)
52 [2] - DMA channel (optional)
53
54 Configuration options - PCI boards:
55 [0] - bus (optional)
56 [1] - slot (optional)
57
58 The Lab-pc+ has quirky chanlist requirements
59 when scanning multiple channels. Multiple channel scan
60 sequence must start at highest channel, then decrement down to
61 channel 0. The rest of the cards can scan down like lab-pc+ or scan
62 up from channel zero. Chanlists consisting of all one channel
63 are also legal, and allow you to pace conversions in bursts.
64
65 */
66
67 /*
68
69 NI manuals:
70 341309a (labpc-1200 register manual)
71 340914a (pci-1200)
72 320502b (lab-pc+)
73
74 */
75
76 #include <linux/interrupt.h>
77 #include <linux/slab.h>
78 #include <linux/io.h>
79 #include "../comedidev.h"
80
81 #include <linux/delay.h>
82 #include <asm/dma.h>
83
84 #include "8253.h"
85 #include "8255.h"
86 #include "mite.h"
87 #include "comedi_fc.h"
88 #include "ni_labpc.h"
89
90 #define DRV_NAME "ni_labpc"
91
92 /* size of io region used by board */
93 #define LABPC_SIZE 32
94 /* 2 MHz master clock */
95 #define LABPC_TIMER_BASE 500
96
97 /* Registers for the lab-pc+ */
98
99 /* write-only registers */
100 #define COMMAND1_REG 0x0
101 #define ADC_GAIN_MASK (0x7 << 4)
102 #define ADC_CHAN_BITS(x) ((x) & 0x7)
103 /* enables multi channel scans */
104 #define ADC_SCAN_EN_BIT 0x80
105 #define COMMAND2_REG 0x1
106 /* enable pretriggering (used in conjunction with SWTRIG) */
107 #define PRETRIG_BIT 0x1
108 /* enable paced conversions on external trigger */
109 #define HWTRIG_BIT 0x2
110 /* enable paced conversions */
111 #define SWTRIG_BIT 0x4
112 /* use two cascaded counters for pacing */
113 #define CASCADE_BIT 0x8
114 #define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1))
115 #define COMMAND3_REG 0x2
116 /* enable dma transfers */
117 #define DMA_EN_BIT 0x1
118 /* enable interrupts for 8255 */
119 #define DIO_INTR_EN_BIT 0x2
120 /* enable dma terminal count interrupt */
121 #define DMATC_INTR_EN_BIT 0x4
122 /* enable timer interrupt */
123 #define TIMER_INTR_EN_BIT 0x8
124 /* enable error interrupt */
125 #define ERR_INTR_EN_BIT 0x10
126 /* enable fifo not empty interrupt */
127 #define ADC_FNE_INTR_EN_BIT 0x20
128 #define ADC_CONVERT_REG 0x3
129 #define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1))
130 #define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1))
131 #define ADC_CLEAR_REG 0x8
132 #define DMATC_CLEAR_REG 0xa
133 #define TIMER_CLEAR_REG 0xc
134 /* 1200 boards only */
135 #define COMMAND6_REG 0xe
136 /* select ground or common-mode reference */
137 #define ADC_COMMON_BIT 0x1
138 /* adc unipolar */
139 #define ADC_UNIP_BIT 0x2
140 /* dac unipolar */
141 #define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1))
142 /* enable fifo half full interrupt */
143 #define ADC_FHF_INTR_EN_BIT 0x20
144 /* enable interrupt on end of hardware count */
145 #define A1_INTR_EN_BIT 0x40
146 /* scan up from channel zero instead of down to zero */
147 #define ADC_SCAN_UP_BIT 0x80
148 #define COMMAND4_REG 0xf
149 /* enables 'interval' scanning */
150 #define INTERVAL_SCAN_EN_BIT 0x1
151 /* enables external signal on counter b1 output to trigger scan */
152 #define EXT_SCAN_EN_BIT 0x2
153 /* chooses direction (output or input) for EXTCONV* line */
154 #define EXT_CONVERT_OUT_BIT 0x4
155 /* chooses differential inputs for adc (in conjunction with board jumper) */
156 #define ADC_DIFF_BIT 0x8
157 #define EXT_CONVERT_DISABLE_BIT 0x10
158 /* 1200 boards only, calibration stuff */
159 #define COMMAND5_REG 0x1c
160 /* enable eeprom for write */
161 #define EEPROM_WRITE_UNPROTECT_BIT 0x4
162 /* enable dithering */
163 #define DITHER_EN_BIT 0x8
164 /* load calibration dac */
165 #define CALDAC_LOAD_BIT 0x10
166 /* serial clock - rising edge writes, falling edge reads */
167 #define SCLOCK_BIT 0x20
168 /* serial data bit for writing to eeprom or calibration dacs */
169 #define SDATA_BIT 0x40
170 /* enable eeprom for read/write */
171 #define EEPROM_EN_BIT 0x80
172 #define INTERVAL_COUNT_REG 0x1e
173 #define INTERVAL_LOAD_REG 0x1f
174 #define INTERVAL_LOAD_BITS 0x1
175
176 /* read-only registers */
177 #define STATUS1_REG 0x0
178 /* data is available in fifo */
179 #define DATA_AVAIL_BIT 0x1
180 /* overrun has occurred */
181 #define OVERRUN_BIT 0x2
182 /* fifo overflow */
183 #define OVERFLOW_BIT 0x4
184 /* timer interrupt has occurred */
185 #define TIMER_BIT 0x8
186 /* dma terminal count has occurred */
187 #define DMATC_BIT 0x10
188 /* external trigger has occurred */
189 #define EXT_TRIG_BIT 0x40
190 /* 1200 boards only */
191 #define STATUS2_REG 0x1d
192 /* programmable eeprom serial output */
193 #define EEPROM_OUT_BIT 0x1
194 /* counter A1 terminal count */
195 #define A1_TC_BIT 0x2
196 /* fifo not half full */
197 #define FNHF_BIT 0x4
198 #define ADC_FIFO_REG 0xa
199
200 #define DIO_BASE_REG 0x10
201 #define COUNTER_A_BASE_REG 0x14
202 #define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3)
203 /* check modes put conversion pacer output in harmless state (a0 mode 2) */
204 #define INIT_A0_BITS 0x14
205 /* put hardware conversion counter output in harmless state (a1 mode 0) */
206 #define INIT_A1_BITS 0x70
207 #define COUNTER_B_BASE_REG 0x18
208
209 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it);
210 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
211 static irqreturn_t labpc_interrupt(int irq, void *d);
212 static int labpc_drain_fifo(struct comedi_device *dev);
213 #ifdef CONFIG_ISA_DMA_API
214 static void labpc_drain_dma(struct comedi_device *dev);
215 static void handle_isa_dma(struct comedi_device *dev);
216 #endif
217 static void labpc_drain_dregs(struct comedi_device *dev);
218 static int labpc_ai_cmdtest(struct comedi_device *dev,
219 struct comedi_subdevice *s, struct comedi_cmd *cmd);
220 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
221 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
222 struct comedi_insn *insn, unsigned int *data);
223 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
224 struct comedi_insn *insn, unsigned int *data);
225 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
226 struct comedi_insn *insn, unsigned int *data);
227 static int labpc_calib_read_insn(struct comedi_device *dev,
228 struct comedi_subdevice *s,
229 struct comedi_insn *insn, unsigned int *data);
230 static int labpc_calib_write_insn(struct comedi_device *dev,
231 struct comedi_subdevice *s,
232 struct comedi_insn *insn, unsigned int *data);
233 static int labpc_eeprom_read_insn(struct comedi_device *dev,
234 struct comedi_subdevice *s,
235 struct comedi_insn *insn, unsigned int *data);
236 static int labpc_eeprom_write_insn(struct comedi_device *dev,
237 struct comedi_subdevice *s,
238 struct comedi_insn *insn,
239 unsigned int *data);
240 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd);
241 #ifdef CONFIG_ISA_DMA_API
242 static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd);
243 #endif
244 #ifdef CONFIG_COMEDI_PCI_DRIVERS
245 static int labpc_find_device(struct comedi_device *dev, int bus, int slot);
246 #endif
247 static int labpc_dio_mem_callback(int dir, int port, int data,
248 unsigned long arg);
249 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
250 unsigned int num_bits);
251 static unsigned int labpc_serial_in(struct comedi_device *dev);
252 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
253 unsigned int address);
254 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev);
255 static int labpc_eeprom_write(struct comedi_device *dev,
256 unsigned int address,
257 unsigned int value);
258 static void write_caldac(struct comedi_device *dev, unsigned int channel,
259 unsigned int value);
260
261 enum scan_mode {
262 MODE_SINGLE_CHAN,
263 MODE_SINGLE_CHAN_INTERVAL,
264 MODE_MULT_CHAN_UP,
265 MODE_MULT_CHAN_DOWN,
266 };
267
268 /* analog input ranges */
269 #define NUM_LABPC_PLUS_AI_RANGES 16
270 /* indicates unipolar ranges */
271 static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = {
272 0,
273 0,
274 0,
275 0,
276 0,
277 0,
278 0,
279 0,
280 1,
281 1,
282 1,
283 1,
284 1,
285 1,
286 1,
287 1,
288 };
289
290 /* map range index to gain bits */
291 static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = {
292 0x00,
293 0x10,
294 0x20,
295 0x30,
296 0x40,
297 0x50,
298 0x60,
299 0x70,
300 0x00,
301 0x10,
302 0x20,
303 0x30,
304 0x40,
305 0x50,
306 0x60,
307 0x70,
308 };
309
310 static const struct comedi_lrange range_labpc_plus_ai = {
311 NUM_LABPC_PLUS_AI_RANGES,
312 {
313 BIP_RANGE(5),
314 BIP_RANGE(4),
315 BIP_RANGE(2.5),
316 BIP_RANGE(1),
317 BIP_RANGE(0.5),
318 BIP_RANGE(0.25),
319 BIP_RANGE(0.1),
320 BIP_RANGE(0.05),
321 UNI_RANGE(10),
322 UNI_RANGE(8),
323 UNI_RANGE(5),
324 UNI_RANGE(2),
325 UNI_RANGE(1),
326 UNI_RANGE(0.5),
327 UNI_RANGE(0.2),
328 UNI_RANGE(0.1),
329 }
330 };
331
332 #define NUM_LABPC_1200_AI_RANGES 14
333 /* indicates unipolar ranges */
334 const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = {
335 0,
336 0,
337 0,
338 0,
339 0,
340 0,
341 0,
342 1,
343 1,
344 1,
345 1,
346 1,
347 1,
348 1,
349 };
350 EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar);
351
352 /* map range index to gain bits */
353 const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = {
354 0x00,
355 0x20,
356 0x30,
357 0x40,
358 0x50,
359 0x60,
360 0x70,
361 0x00,
362 0x20,
363 0x30,
364 0x40,
365 0x50,
366 0x60,
367 0x70,
368 };
369 EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits);
370
371 const struct comedi_lrange range_labpc_1200_ai = {
372 NUM_LABPC_1200_AI_RANGES,
373 {
374 BIP_RANGE(5),
375 BIP_RANGE(2.5),
376 BIP_RANGE(1),
377 BIP_RANGE(0.5),
378 BIP_RANGE(0.25),
379 BIP_RANGE(0.1),
380 BIP_RANGE(0.05),
381 UNI_RANGE(10),
382 UNI_RANGE(5),
383 UNI_RANGE(2),
384 UNI_RANGE(1),
385 UNI_RANGE(0.5),
386 UNI_RANGE(0.2),
387 UNI_RANGE(0.1),
388 }
389 };
390 EXPORT_SYMBOL_GPL(range_labpc_1200_ai);
391
392 /* analog output ranges */
393 #define AO_RANGE_IS_UNIPOLAR 0x1
394 static const struct comedi_lrange range_labpc_ao = {
395 2,
396 {
397 BIP_RANGE(5),
398 UNI_RANGE(10),
399 }
400 };
401
402 /* functions that do inb/outb and readb/writeb so we can use
403 * function pointers to decide which to use */
404 static inline unsigned int labpc_inb(unsigned long address)
405 {
406 return inb(address);
407 }
408
409 static inline void labpc_outb(unsigned int byte, unsigned long address)
410 {
411 outb(byte, address);
412 }
413
414 static inline unsigned int labpc_readb(unsigned long address)
415 {
416 return readb((void *)address);
417 }
418
419 static inline void labpc_writeb(unsigned int byte, unsigned long address)
420 {
421 writeb(byte, (void *)address);
422 }
423
424 static const struct labpc_board_struct labpc_boards[] = {
425 {
426 .name = "lab-pc-1200",
427 .ai_speed = 10000,
428 .bustype = isa_bustype,
429 .register_layout = labpc_1200_layout,
430 .has_ao = 1,
431 .ai_range_table = &range_labpc_1200_ai,
432 .ai_range_code = labpc_1200_ai_gain_bits,
433 .ai_range_is_unipolar = labpc_1200_is_unipolar,
434 .ai_scan_up = 1,
435 .memory_mapped_io = 0,
436 },
437 {
438 .name = "lab-pc-1200ai",
439 .ai_speed = 10000,
440 .bustype = isa_bustype,
441 .register_layout = labpc_1200_layout,
442 .has_ao = 0,
443 .ai_range_table = &range_labpc_1200_ai,
444 .ai_range_code = labpc_1200_ai_gain_bits,
445 .ai_range_is_unipolar = labpc_1200_is_unipolar,
446 .ai_scan_up = 1,
447 .memory_mapped_io = 0,
448 },
449 {
450 .name = "lab-pc+",
451 .ai_speed = 12000,
452 .bustype = isa_bustype,
453 .register_layout = labpc_plus_layout,
454 .has_ao = 1,
455 .ai_range_table = &range_labpc_plus_ai,
456 .ai_range_code = labpc_plus_ai_gain_bits,
457 .ai_range_is_unipolar = labpc_plus_is_unipolar,
458 .ai_scan_up = 0,
459 .memory_mapped_io = 0,
460 },
461 #ifdef CONFIG_COMEDI_PCI_DRIVERS
462 {
463 .name = "pci-1200",
464 .device_id = 0x161,
465 .ai_speed = 10000,
466 .bustype = pci_bustype,
467 .register_layout = labpc_1200_layout,
468 .has_ao = 1,
469 .ai_range_table = &range_labpc_1200_ai,
470 .ai_range_code = labpc_1200_ai_gain_bits,
471 .ai_range_is_unipolar = labpc_1200_is_unipolar,
472 .ai_scan_up = 1,
473 .memory_mapped_io = 1,
474 },
475 /* dummy entry so pci board works when comedi_config is passed driver name */
476 {
477 .name = DRV_NAME,
478 .bustype = pci_bustype,
479 },
480 #endif
481 };
482
483 /*
484 * Useful for shorthand access to the particular board structure
485 */
486 #define thisboard ((struct labpc_board_struct *)dev->board_ptr)
487
488 /* size in bytes of dma buffer */
489 static const int dma_buffer_size = 0xff00;
490 /* 2 bytes per sample */
491 static const int sample_size = 2;
492
493 #define devpriv ((struct labpc_private *)dev->private)
494
495 static struct comedi_driver labpc_driver = {
496 .driver_name = DRV_NAME,
497 .module = THIS_MODULE,
498 .attach = labpc_attach,
499 .detach = labpc_common_detach,
500 .num_names = ARRAY_SIZE(labpc_boards),
501 .board_name = &labpc_boards[0].name,
502 .offset = sizeof(struct labpc_board_struct),
503 };
504
505 #ifdef CONFIG_COMEDI_PCI_DRIVERS
506 static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = {
507 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161)},
508 {0}
509 };
510
511 MODULE_DEVICE_TABLE(pci, labpc_pci_table);
512 #endif /* CONFIG_COMEDI_PCI_DRIVERS */
513
514 static inline int labpc_counter_load(struct comedi_device *dev,
515 unsigned long base_address,
516 unsigned int counter_number,
517 unsigned int count, unsigned int mode)
518 {
519 if (thisboard->memory_mapped_io)
520 return i8254_mm_load((void *)base_address, 0, counter_number,
521 count, mode);
522 else
523 return i8254_load(base_address, 0, counter_number, count, mode);
524 }
525
526 int labpc_common_attach(struct comedi_device *dev, unsigned long iobase,
527 unsigned int irq, unsigned int dma_chan)
528 {
529 struct comedi_subdevice *s;
530 int i;
531 unsigned long isr_flags;
532 #ifdef CONFIG_ISA_DMA_API
533 unsigned long dma_flags;
534 #endif
535 short lsb, msb;
536 int ret;
537
538 dev_info(dev->class_dev, "ni_labpc: %s\n", thisboard->name);
539 if (iobase == 0) {
540 dev_err(dev->class_dev, "io base address is zero!\n");
541 return -EINVAL;
542 }
543 /* request io regions for isa boards */
544 if (thisboard->bustype == isa_bustype) {
545 /* check if io addresses are available */
546 if (!request_region(iobase, LABPC_SIZE,
547 labpc_driver.driver_name)) {
548 dev_err(dev->class_dev, "I/O port conflict\n");
549 return -EIO;
550 }
551 }
552 dev->iobase = iobase;
553
554 if (thisboard->memory_mapped_io) {
555 devpriv->read_byte = labpc_readb;
556 devpriv->write_byte = labpc_writeb;
557 } else {
558 devpriv->read_byte = labpc_inb;
559 devpriv->write_byte = labpc_outb;
560 }
561 /* initialize board's command registers */
562 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
563 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
564 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
565 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
566 if (thisboard->register_layout == labpc_1200_layout) {
567 devpriv->write_byte(devpriv->command5_bits,
568 dev->iobase + COMMAND5_REG);
569 devpriv->write_byte(devpriv->command6_bits,
570 dev->iobase + COMMAND6_REG);
571 }
572
573 /* grab our IRQ */
574 if (irq) {
575 isr_flags = 0;
576 if (thisboard->bustype == pci_bustype
577 || thisboard->bustype == pcmcia_bustype)
578 isr_flags |= IRQF_SHARED;
579 if (request_irq(irq, labpc_interrupt, isr_flags,
580 labpc_driver.driver_name, dev)) {
581 dev_err(dev->class_dev, "unable to allocate irq %u\n",
582 irq);
583 return -EINVAL;
584 }
585 }
586 dev->irq = irq;
587
588 #ifdef CONFIG_ISA_DMA_API
589 /* grab dma channel */
590 if (dma_chan > 3) {
591 dev_err(dev->class_dev, "invalid dma channel %u\n", dma_chan);
592 return -EINVAL;
593 } else if (dma_chan) {
594 /* allocate dma buffer */
595 devpriv->dma_buffer =
596 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA);
597 if (devpriv->dma_buffer == NULL) {
598 dev_err(dev->class_dev,
599 "failed to allocate dma buffer\n");
600 return -ENOMEM;
601 }
602 if (request_dma(dma_chan, labpc_driver.driver_name)) {
603 dev_err(dev->class_dev,
604 "failed to allocate dma channel %u\n",
605 dma_chan);
606 return -EINVAL;
607 }
608 devpriv->dma_chan = dma_chan;
609 dma_flags = claim_dma_lock();
610 disable_dma(devpriv->dma_chan);
611 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
612 release_dma_lock(dma_flags);
613 }
614 #endif
615
616 dev->board_name = thisboard->name;
617
618 ret = comedi_alloc_subdevices(dev, 5);
619 if (ret)
620 return ret;
621
622 /* analog input subdevice */
623 s = &dev->subdevices[0];
624 dev->read_subdev = s;
625 s->type = COMEDI_SUBD_AI;
626 s->subdev_flags =
627 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
628 s->n_chan = 8;
629 s->len_chanlist = 8;
630 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
631 s->range_table = thisboard->ai_range_table;
632 s->do_cmd = labpc_ai_cmd;
633 s->do_cmdtest = labpc_ai_cmdtest;
634 s->insn_read = labpc_ai_rinsn;
635 s->cancel = labpc_cancel;
636
637 /* analog output */
638 s = &dev->subdevices[1];
639 if (thisboard->has_ao) {
640 /*
641 * Could provide command support, except it only has a
642 * one sample hardware buffer for analog output and no
643 * underrun flag.
644 */
645 s->type = COMEDI_SUBD_AO;
646 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
647 s->n_chan = NUM_AO_CHAN;
648 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
649 s->range_table = &range_labpc_ao;
650 s->insn_read = labpc_ao_rinsn;
651 s->insn_write = labpc_ao_winsn;
652 /* initialize analog outputs to a known value */
653 for (i = 0; i < s->n_chan; i++) {
654 devpriv->ao_value[i] = s->maxdata / 2;
655 lsb = devpriv->ao_value[i] & 0xff;
656 msb = (devpriv->ao_value[i] >> 8) & 0xff;
657 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
658 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
659 }
660 } else {
661 s->type = COMEDI_SUBD_UNUSED;
662 }
663
664 /* 8255 dio */
665 s = &dev->subdevices[2];
666 /* if board uses io memory we have to give a custom callback
667 * function to the 8255 driver */
668 if (thisboard->memory_mapped_io)
669 subdev_8255_init(dev, s, labpc_dio_mem_callback,
670 (unsigned long)(dev->iobase + DIO_BASE_REG));
671 else
672 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG);
673
674 /* calibration subdevices for boards that have one */
675 s = &dev->subdevices[3];
676 if (thisboard->register_layout == labpc_1200_layout) {
677 s->type = COMEDI_SUBD_CALIB;
678 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
679 s->n_chan = 16;
680 s->maxdata = 0xff;
681 s->insn_read = labpc_calib_read_insn;
682 s->insn_write = labpc_calib_write_insn;
683
684 for (i = 0; i < s->n_chan; i++)
685 write_caldac(dev, i, s->maxdata / 2);
686 } else
687 s->type = COMEDI_SUBD_UNUSED;
688
689 /* EEPROM */
690 s = &dev->subdevices[4];
691 if (thisboard->register_layout == labpc_1200_layout) {
692 s->type = COMEDI_SUBD_MEMORY;
693 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
694 s->n_chan = EEPROM_SIZE;
695 s->maxdata = 0xff;
696 s->insn_read = labpc_eeprom_read_insn;
697 s->insn_write = labpc_eeprom_write_insn;
698
699 for (i = 0; i < EEPROM_SIZE; i++)
700 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
701 } else
702 s->type = COMEDI_SUBD_UNUSED;
703
704 return 0;
705 }
706 EXPORT_SYMBOL_GPL(labpc_common_attach);
707
708 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it)
709 {
710 unsigned long iobase = 0;
711 unsigned int irq = 0;
712 unsigned int dma_chan = 0;
713 #ifdef CONFIG_COMEDI_PCI_DRIVERS
714 int retval;
715 #endif
716
717 /* allocate and initialize dev->private */
718 if (alloc_private(dev, sizeof(struct labpc_private)) < 0)
719 return -ENOMEM;
720
721 /* get base address, irq etc. based on bustype */
722 switch (thisboard->bustype) {
723 case isa_bustype:
724 #ifdef CONFIG_ISA_DMA_API
725 iobase = it->options[0];
726 irq = it->options[1];
727 dma_chan = it->options[2];
728 #else
729 dev_err(dev->class_dev,
730 "ni_labpc driver has not been built with ISA DMA support.\n");
731 return -EINVAL;
732 #endif
733 break;
734 case pci_bustype:
735 #ifdef CONFIG_COMEDI_PCI_DRIVERS
736 retval = labpc_find_device(dev, it->options[0], it->options[1]);
737 if (retval < 0)
738 return retval;
739 retval = mite_setup(devpriv->mite);
740 if (retval < 0)
741 return retval;
742 iobase = (unsigned long)devpriv->mite->daq_io_addr;
743 irq = mite_irq(devpriv->mite);
744 #else
745 dev_err(dev->class_dev,
746 "ni_labpc driver has not been built with PCI support.\n");
747 return -EINVAL;
748 #endif
749 break;
750 default:
751 dev_err(dev->class_dev,
752 "ni_labpc: bug! couldn't determine board type\n");
753 return -EINVAL;
754 break;
755 }
756
757 return labpc_common_attach(dev, iobase, irq, dma_chan);
758 }
759
760 /* adapted from ni_pcimio for finding mite based boards (pc-1200) */
761 #ifdef CONFIG_COMEDI_PCI_DRIVERS
762 static int labpc_find_device(struct comedi_device *dev, int bus, int slot)
763 {
764 struct mite_struct *mite;
765 int i;
766 for (mite = mite_devices; mite; mite = mite->next) {
767 if (mite->used)
768 continue;
769 /* if bus/slot are specified then make sure we have the right bus/slot */
770 if (bus || slot) {
771 if (bus != mite->pcidev->bus->number
772 || slot != PCI_SLOT(mite->pcidev->devfn))
773 continue;
774 }
775 for (i = 0; i < labpc_driver.num_names; i++) {
776 if (labpc_boards[i].bustype != pci_bustype)
777 continue;
778 if (mite_device_id(mite) == labpc_boards[i].device_id) {
779 devpriv->mite = mite;
780 /* fixup board pointer, in case we were using the dummy "ni_labpc" entry */
781 dev->board_ptr = &labpc_boards[i];
782 return 0;
783 }
784 }
785 }
786 dev_err(dev->class_dev, "no device found\n");
787 mite_list_devices();
788 return -EIO;
789 }
790 #endif
791
792 void labpc_common_detach(struct comedi_device *dev)
793 {
794 struct comedi_subdevice *s;
795
796 if (dev->subdevices) {
797 s = &dev->subdevices[2];
798 subdev_8255_cleanup(dev, s);
799 }
800 #ifdef CONFIG_ISA_DMA_API
801 /* only free stuff if it has been allocated by _attach */
802 kfree(devpriv->dma_buffer);
803 if (devpriv->dma_chan)
804 free_dma(devpriv->dma_chan);
805 #endif
806 if (dev->irq)
807 free_irq(dev->irq, dev);
808 if (thisboard->bustype == isa_bustype && dev->iobase)
809 release_region(dev->iobase, LABPC_SIZE);
810 #ifdef CONFIG_COMEDI_PCI_DRIVERS
811 if (devpriv->mite)
812 mite_unsetup(devpriv->mite);
813 #endif
814 };
815 EXPORT_SYMBOL_GPL(labpc_common_detach);
816
817 static void labpc_clear_adc_fifo(const struct comedi_device *dev)
818 {
819 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
820 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
821 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
822 }
823
824 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
825 {
826 unsigned long flags;
827
828 spin_lock_irqsave(&dev->spinlock, flags);
829 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
830 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
831 spin_unlock_irqrestore(&dev->spinlock, flags);
832
833 devpriv->command3_bits = 0;
834 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
835
836 return 0;
837 }
838
839 static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd)
840 {
841 if (cmd->chanlist_len == 1)
842 return MODE_SINGLE_CHAN;
843
844 /* chanlist may be NULL during cmdtest. */
845 if (cmd->chanlist == NULL)
846 return MODE_MULT_CHAN_UP;
847
848 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
849 return MODE_SINGLE_CHAN_INTERVAL;
850
851 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
852 return MODE_MULT_CHAN_UP;
853
854 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
855 return MODE_MULT_CHAN_DOWN;
856
857 pr_err("ni_labpc: bug! cannot determine AI scan mode\n");
858 return 0;
859 }
860
861 static int labpc_ai_chanlist_invalid(const struct comedi_device *dev,
862 const struct comedi_cmd *cmd)
863 {
864 int mode, channel, range, aref, i;
865
866 if (cmd->chanlist == NULL)
867 return 0;
868
869 mode = labpc_ai_scan_mode(cmd);
870
871 if (mode == MODE_SINGLE_CHAN)
872 return 0;
873
874 if (mode == MODE_SINGLE_CHAN_INTERVAL) {
875 if (cmd->chanlist_len > 0xff) {
876 comedi_error(dev,
877 "ni_labpc: chanlist too long for single channel interval mode\n");
878 return 1;
879 }
880 }
881
882 channel = CR_CHAN(cmd->chanlist[0]);
883 range = CR_RANGE(cmd->chanlist[0]);
884 aref = CR_AREF(cmd->chanlist[0]);
885
886 for (i = 0; i < cmd->chanlist_len; i++) {
887
888 switch (mode) {
889 case MODE_SINGLE_CHAN_INTERVAL:
890 if (CR_CHAN(cmd->chanlist[i]) != channel) {
891 comedi_error(dev,
892 "channel scanning order specified in chanlist is not supported by hardware.\n");
893 return 1;
894 }
895 break;
896 case MODE_MULT_CHAN_UP:
897 if (CR_CHAN(cmd->chanlist[i]) != i) {
898 comedi_error(dev,
899 "channel scanning order specified in chanlist is not supported by hardware.\n");
900 return 1;
901 }
902 break;
903 case MODE_MULT_CHAN_DOWN:
904 if (CR_CHAN(cmd->chanlist[i]) !=
905 cmd->chanlist_len - i - 1) {
906 comedi_error(dev,
907 "channel scanning order specified in chanlist is not supported by hardware.\n");
908 return 1;
909 }
910 break;
911 default:
912 dev_err(dev->class_dev,
913 "ni_labpc: bug! in chanlist check\n");
914 return 1;
915 break;
916 }
917
918 if (CR_RANGE(cmd->chanlist[i]) != range) {
919 comedi_error(dev,
920 "entries in chanlist must all have the same range\n");
921 return 1;
922 }
923
924 if (CR_AREF(cmd->chanlist[i]) != aref) {
925 comedi_error(dev,
926 "entries in chanlist must all have the same reference\n");
927 return 1;
928 }
929 }
930
931 return 0;
932 }
933
934 static int labpc_use_continuous_mode(const struct comedi_cmd *cmd)
935 {
936 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN)
937 return 1;
938
939 if (cmd->scan_begin_src == TRIG_FOLLOW)
940 return 1;
941
942 return 0;
943 }
944
945 static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd)
946 {
947 if (cmd->convert_src != TRIG_TIMER)
948 return 0;
949
950 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
951 cmd->scan_begin_src == TRIG_TIMER)
952 return cmd->scan_begin_arg;
953
954 return cmd->convert_arg;
955 }
956
957 static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns)
958 {
959 if (cmd->convert_src != TRIG_TIMER)
960 return;
961
962 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
963 cmd->scan_begin_src == TRIG_TIMER) {
964 cmd->scan_begin_arg = ns;
965 if (cmd->convert_arg > cmd->scan_begin_arg)
966 cmd->convert_arg = cmd->scan_begin_arg;
967 } else
968 cmd->convert_arg = ns;
969 }
970
971 static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd)
972 {
973 if (cmd->scan_begin_src != TRIG_TIMER)
974 return 0;
975
976 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
977 cmd->convert_src == TRIG_TIMER)
978 return 0;
979
980 return cmd->scan_begin_arg;
981 }
982
983 static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns)
984 {
985 if (cmd->scan_begin_src != TRIG_TIMER)
986 return;
987
988 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
989 cmd->convert_src == TRIG_TIMER)
990 return;
991
992 cmd->scan_begin_arg = ns;
993 }
994
995 static int labpc_ai_cmdtest(struct comedi_device *dev,
996 struct comedi_subdevice *s, struct comedi_cmd *cmd)
997 {
998 int err = 0;
999 int tmp, tmp2;
1000 int stop_mask;
1001
1002 /* step 1: make sure trigger sources are trivially valid */
1003
1004 tmp = cmd->start_src;
1005 cmd->start_src &= TRIG_NOW | TRIG_EXT;
1006 if (!cmd->start_src || tmp != cmd->start_src)
1007 err++;
1008
1009 tmp = cmd->scan_begin_src;
1010 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT;
1011 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1012 err++;
1013
1014 tmp = cmd->convert_src;
1015 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
1016 if (!cmd->convert_src || tmp != cmd->convert_src)
1017 err++;
1018
1019 tmp = cmd->scan_end_src;
1020 cmd->scan_end_src &= TRIG_COUNT;
1021 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1022 err++;
1023
1024 tmp = cmd->stop_src;
1025 stop_mask = TRIG_COUNT | TRIG_NONE;
1026 if (thisboard->register_layout == labpc_1200_layout)
1027 stop_mask |= TRIG_EXT;
1028 cmd->stop_src &= stop_mask;
1029 if (!cmd->stop_src || tmp != cmd->stop_src)
1030 err++;
1031
1032 if (err)
1033 return 1;
1034
1035 /* step 2: make sure trigger sources are unique and mutually compatible */
1036
1037 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
1038 err++;
1039 if (cmd->scan_begin_src != TRIG_TIMER &&
1040 cmd->scan_begin_src != TRIG_FOLLOW &&
1041 cmd->scan_begin_src != TRIG_EXT)
1042 err++;
1043 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
1044 err++;
1045 if (cmd->stop_src != TRIG_COUNT &&
1046 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE)
1047 err++;
1048
1049 /* can't have external stop and start triggers at once */
1050 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
1051 err++;
1052
1053 if (err)
1054 return 2;
1055
1056 /* step 3: make sure arguments are trivially compatible */
1057
1058 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) {
1059 cmd->start_arg = 0;
1060 err++;
1061 }
1062
1063 if (!cmd->chanlist_len)
1064 err++;
1065
1066 if (cmd->scan_end_arg != cmd->chanlist_len) {
1067 cmd->scan_end_arg = cmd->chanlist_len;
1068 err++;
1069 }
1070
1071 if (cmd->convert_src == TRIG_TIMER) {
1072 if (cmd->convert_arg < thisboard->ai_speed) {
1073 cmd->convert_arg = thisboard->ai_speed;
1074 err++;
1075 }
1076 }
1077 /* make sure scan timing is not too fast */
1078 if (cmd->scan_begin_src == TRIG_TIMER) {
1079 if (cmd->convert_src == TRIG_TIMER &&
1080 cmd->scan_begin_arg <
1081 cmd->convert_arg * cmd->chanlist_len) {
1082 cmd->scan_begin_arg =
1083 cmd->convert_arg * cmd->chanlist_len;
1084 err++;
1085 }
1086 if (cmd->scan_begin_arg <
1087 thisboard->ai_speed * cmd->chanlist_len) {
1088 cmd->scan_begin_arg =
1089 thisboard->ai_speed * cmd->chanlist_len;
1090 err++;
1091 }
1092 }
1093 /* stop source */
1094 switch (cmd->stop_src) {
1095 case TRIG_COUNT:
1096 if (!cmd->stop_arg) {
1097 cmd->stop_arg = 1;
1098 err++;
1099 }
1100 break;
1101 case TRIG_NONE:
1102 if (cmd->stop_arg != 0) {
1103 cmd->stop_arg = 0;
1104 err++;
1105 }
1106 break;
1107 /*
1108 * TRIG_EXT doesn't care since it doesn't
1109 * trigger off a numbered channel
1110 */
1111 default:
1112 break;
1113 }
1114
1115 if (err)
1116 return 3;
1117
1118 /* step 4: fix up any arguments */
1119
1120 tmp = cmd->convert_arg;
1121 tmp2 = cmd->scan_begin_arg;
1122 labpc_adc_timing(dev, cmd);
1123 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
1124 err++;
1125
1126 if (err)
1127 return 4;
1128
1129 if (labpc_ai_chanlist_invalid(dev, cmd))
1130 return 5;
1131
1132 return 0;
1133 }
1134
1135 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1136 {
1137 int channel, range, aref;
1138 #ifdef CONFIG_ISA_DMA_API
1139 unsigned long irq_flags;
1140 #endif
1141 int ret;
1142 struct comedi_async *async = s->async;
1143 struct comedi_cmd *cmd = &async->cmd;
1144 enum transfer_type xfer;
1145 unsigned long flags;
1146
1147 if (!dev->irq) {
1148 comedi_error(dev, "no irq assigned, cannot perform command");
1149 return -1;
1150 }
1151
1152 range = CR_RANGE(cmd->chanlist[0]);
1153 aref = CR_AREF(cmd->chanlist[0]);
1154
1155 /* make sure board is disabled before setting up acquisition */
1156 spin_lock_irqsave(&dev->spinlock, flags);
1157 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1158 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1159 spin_unlock_irqrestore(&dev->spinlock, flags);
1160
1161 devpriv->command3_bits = 0;
1162 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1163
1164 /* initialize software conversion count */
1165 if (cmd->stop_src == TRIG_COUNT)
1166 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
1167
1168 /* setup hardware conversion counter */
1169 if (cmd->stop_src == TRIG_EXT) {
1170 /*
1171 * load counter a1 with count of 3
1172 * (pc+ manual says this is minimum allowed) using mode 0
1173 */
1174 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1175 1, 3, 0);
1176 if (ret < 0) {
1177 comedi_error(dev, "error loading counter a1");
1178 return -1;
1179 }
1180 } else /*
1181 * otherwise, just put a1 in mode 0
1182 * with no count to set its output low
1183 */
1184 devpriv->write_byte(INIT_A1_BITS,
1185 dev->iobase + COUNTER_A_CONTROL_REG);
1186
1187 #ifdef CONFIG_ISA_DMA_API
1188 /* figure out what method we will use to transfer data */
1189 if (devpriv->dma_chan && /* need a dma channel allocated */
1190 /*
1191 * dma unsafe at RT priority,
1192 * and too much setup time for TRIG_WAKE_EOS for
1193 */
1194 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
1195 /* only available on the isa boards */
1196 thisboard->bustype == isa_bustype) {
1197 xfer = isa_dma_transfer;
1198 /* pc-plus has no fifo-half full interrupt */
1199 } else
1200 #endif
1201 if (thisboard->register_layout == labpc_1200_layout &&
1202 /* wake-end-of-scan should interrupt on fifo not empty */
1203 (cmd->flags & TRIG_WAKE_EOS) == 0 &&
1204 /* make sure we are taking more than just a few points */
1205 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
1206 xfer = fifo_half_full_transfer;
1207 } else
1208 xfer = fifo_not_empty_transfer;
1209 devpriv->current_transfer = xfer;
1210
1211 /* setup command6 register for 1200 boards */
1212 if (thisboard->register_layout == labpc_1200_layout) {
1213 /* reference inputs to ground or common? */
1214 if (aref != AREF_GROUND)
1215 devpriv->command6_bits |= ADC_COMMON_BIT;
1216 else
1217 devpriv->command6_bits &= ~ADC_COMMON_BIT;
1218 /* bipolar or unipolar range? */
1219 if (thisboard->ai_range_is_unipolar[range])
1220 devpriv->command6_bits |= ADC_UNIP_BIT;
1221 else
1222 devpriv->command6_bits &= ~ADC_UNIP_BIT;
1223 /* interrupt on fifo half full? */
1224 if (xfer == fifo_half_full_transfer)
1225 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT;
1226 else
1227 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1228 /* enable interrupt on counter a1 terminal count? */
1229 if (cmd->stop_src == TRIG_EXT)
1230 devpriv->command6_bits |= A1_INTR_EN_BIT;
1231 else
1232 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1233 /* are we scanning up or down through channels? */
1234 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1235 devpriv->command6_bits |= ADC_SCAN_UP_BIT;
1236 else
1237 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT;
1238 /* write to register */
1239 devpriv->write_byte(devpriv->command6_bits,
1240 dev->iobase + COMMAND6_REG);
1241 }
1242
1243 /* setup channel list, etc (command1 register) */
1244 devpriv->command1_bits = 0;
1245 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1246 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
1247 else
1248 channel = CR_CHAN(cmd->chanlist[0]);
1249 /* munge channel bits for differential / scan disabled mode */
1250 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF)
1251 channel *= 2;
1252 devpriv->command1_bits |= ADC_CHAN_BITS(channel);
1253 devpriv->command1_bits |= thisboard->ai_range_code[range];
1254 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1255 /* manual says to set scan enable bit on second pass */
1256 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP ||
1257 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) {
1258 devpriv->command1_bits |= ADC_SCAN_EN_BIT;
1259 /* need a brief delay before enabling scan, or scan
1260 * list will get screwed when you switch
1261 * between scan up to scan down mode - dunno why */
1262 udelay(1);
1263 devpriv->write_byte(devpriv->command1_bits,
1264 dev->iobase + COMMAND1_REG);
1265 }
1266 /* setup any external triggering/pacing (command4 register) */
1267 devpriv->command4_bits = 0;
1268 if (cmd->convert_src != TRIG_EXT)
1269 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1270 /* XXX should discard first scan when using interval scanning
1271 * since manual says it is not synced with scan clock */
1272 if (labpc_use_continuous_mode(cmd) == 0) {
1273 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT;
1274 if (cmd->scan_begin_src == TRIG_EXT)
1275 devpriv->command4_bits |= EXT_SCAN_EN_BIT;
1276 }
1277 /* single-ended/differential */
1278 if (aref == AREF_DIFF)
1279 devpriv->command4_bits |= ADC_DIFF_BIT;
1280 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1281
1282 devpriv->write_byte(cmd->chanlist_len,
1283 dev->iobase + INTERVAL_COUNT_REG);
1284 /* load count */
1285 devpriv->write_byte(INTERVAL_LOAD_BITS,
1286 dev->iobase + INTERVAL_LOAD_REG);
1287
1288 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) {
1289 /* set up pacing */
1290 labpc_adc_timing(dev, cmd);
1291 /* load counter b0 in mode 3 */
1292 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1293 0, devpriv->divisor_b0, 3);
1294 if (ret < 0) {
1295 comedi_error(dev, "error loading counter b0");
1296 return -1;
1297 }
1298 }
1299 /* set up conversion pacing */
1300 if (labpc_ai_convert_period(cmd)) {
1301 /* load counter a0 in mode 2 */
1302 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1303 0, devpriv->divisor_a0, 2);
1304 if (ret < 0) {
1305 comedi_error(dev, "error loading counter a0");
1306 return -1;
1307 }
1308 } else
1309 devpriv->write_byte(INIT_A0_BITS,
1310 dev->iobase + COUNTER_A_CONTROL_REG);
1311
1312 /* set up scan pacing */
1313 if (labpc_ai_scan_period(cmd)) {
1314 /* load counter b1 in mode 2 */
1315 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1316 1, devpriv->divisor_b1, 2);
1317 if (ret < 0) {
1318 comedi_error(dev, "error loading counter b1");
1319 return -1;
1320 }
1321 }
1322
1323 labpc_clear_adc_fifo(dev);
1324
1325 #ifdef CONFIG_ISA_DMA_API
1326 /* set up dma transfer */
1327 if (xfer == isa_dma_transfer) {
1328 irq_flags = claim_dma_lock();
1329 disable_dma(devpriv->dma_chan);
1330 /* clear flip-flop to make sure 2-byte registers for
1331 * count and address get set correctly */
1332 clear_dma_ff(devpriv->dma_chan);
1333 set_dma_addr(devpriv->dma_chan,
1334 virt_to_bus(devpriv->dma_buffer));
1335 /* set appropriate size of transfer */
1336 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd);
1337 if (cmd->stop_src == TRIG_COUNT &&
1338 devpriv->count * sample_size < devpriv->dma_transfer_size) {
1339 devpriv->dma_transfer_size =
1340 devpriv->count * sample_size;
1341 }
1342 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1343 enable_dma(devpriv->dma_chan);
1344 release_dma_lock(irq_flags);
1345 /* enable board's dma */
1346 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT;
1347 } else
1348 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT;
1349 #endif
1350
1351 /* enable error interrupts */
1352 devpriv->command3_bits |= ERR_INTR_EN_BIT;
1353 /* enable fifo not empty interrupt? */
1354 if (xfer == fifo_not_empty_transfer)
1355 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT;
1356 else
1357 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT;
1358 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1359
1360 /* startup acquisition */
1361
1362 /* command2 reg */
1363 /* use 2 cascaded counters for pacing */
1364 spin_lock_irqsave(&dev->spinlock, flags);
1365 devpriv->command2_bits |= CASCADE_BIT;
1366 switch (cmd->start_src) {
1367 case TRIG_EXT:
1368 devpriv->command2_bits |= HWTRIG_BIT;
1369 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT;
1370 break;
1371 case TRIG_NOW:
1372 devpriv->command2_bits |= SWTRIG_BIT;
1373 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT;
1374 break;
1375 default:
1376 comedi_error(dev, "bug with start_src");
1377 spin_unlock_irqrestore(&dev->spinlock, flags);
1378 return -1;
1379 break;
1380 }
1381 switch (cmd->stop_src) {
1382 case TRIG_EXT:
1383 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT;
1384 break;
1385 case TRIG_COUNT:
1386 case TRIG_NONE:
1387 break;
1388 default:
1389 comedi_error(dev, "bug with stop_src");
1390 spin_unlock_irqrestore(&dev->spinlock, flags);
1391 return -1;
1392 }
1393 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1394 spin_unlock_irqrestore(&dev->spinlock, flags);
1395
1396 return 0;
1397 }
1398
1399 /* interrupt service routine */
1400 static irqreturn_t labpc_interrupt(int irq, void *d)
1401 {
1402 struct comedi_device *dev = d;
1403 struct comedi_subdevice *s = dev->read_subdev;
1404 struct comedi_async *async;
1405 struct comedi_cmd *cmd;
1406
1407 if (dev->attached == 0) {
1408 comedi_error(dev, "premature interrupt");
1409 return IRQ_HANDLED;
1410 }
1411
1412 async = s->async;
1413 cmd = &async->cmd;
1414 async->events = 0;
1415
1416 /* read board status */
1417 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1418 if (thisboard->register_layout == labpc_1200_layout)
1419 devpriv->status2_bits =
1420 devpriv->read_byte(dev->iobase + STATUS2_REG);
1421
1422 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT |
1423 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0
1424 && (devpriv->status2_bits & A1_TC_BIT) == 0
1425 && (devpriv->status2_bits & FNHF_BIT)) {
1426 return IRQ_NONE;
1427 }
1428
1429 if (devpriv->status1_bits & OVERRUN_BIT) {
1430 /* clear error interrupt */
1431 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1432 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1433 comedi_event(dev, s);
1434 comedi_error(dev, "overrun");
1435 return IRQ_HANDLED;
1436 }
1437
1438 #ifdef CONFIG_ISA_DMA_API
1439 if (devpriv->current_transfer == isa_dma_transfer) {
1440 /*
1441 * if a dma terminal count of external stop trigger
1442 * has occurred
1443 */
1444 if (devpriv->status1_bits & DMATC_BIT ||
1445 (thisboard->register_layout == labpc_1200_layout
1446 && devpriv->status2_bits & A1_TC_BIT)) {
1447 handle_isa_dma(dev);
1448 }
1449 } else
1450 #endif
1451 labpc_drain_fifo(dev);
1452
1453 if (devpriv->status1_bits & TIMER_BIT) {
1454 comedi_error(dev, "handled timer interrupt?");
1455 /* clear it */
1456 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1457 }
1458
1459 if (devpriv->status1_bits & OVERFLOW_BIT) {
1460 /* clear error interrupt */
1461 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1462 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1463 comedi_event(dev, s);
1464 comedi_error(dev, "overflow");
1465 return IRQ_HANDLED;
1466 }
1467 /* handle external stop trigger */
1468 if (cmd->stop_src == TRIG_EXT) {
1469 if (devpriv->status2_bits & A1_TC_BIT) {
1470 labpc_drain_dregs(dev);
1471 labpc_cancel(dev, s);
1472 async->events |= COMEDI_CB_EOA;
1473 }
1474 }
1475
1476 /* TRIG_COUNT end of acquisition */
1477 if (cmd->stop_src == TRIG_COUNT) {
1478 if (devpriv->count == 0) {
1479 labpc_cancel(dev, s);
1480 async->events |= COMEDI_CB_EOA;
1481 }
1482 }
1483
1484 comedi_event(dev, s);
1485 return IRQ_HANDLED;
1486 }
1487
1488 /* read all available samples from ai fifo */
1489 static int labpc_drain_fifo(struct comedi_device *dev)
1490 {
1491 unsigned int lsb, msb;
1492 short data;
1493 struct comedi_async *async = dev->read_subdev->async;
1494 const int timeout = 10000;
1495 unsigned int i;
1496
1497 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1498
1499 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout;
1500 i++) {
1501 /* quit if we have all the data we want */
1502 if (async->cmd.stop_src == TRIG_COUNT) {
1503 if (devpriv->count == 0)
1504 break;
1505 devpriv->count--;
1506 }
1507 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1508 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1509 data = (msb << 8) | lsb;
1510 cfc_write_to_buffer(dev->read_subdev, data);
1511 devpriv->status1_bits =
1512 devpriv->read_byte(dev->iobase + STATUS1_REG);
1513 }
1514 if (i == timeout) {
1515 comedi_error(dev, "ai timeout, fifo never empties");
1516 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1517 return -1;
1518 }
1519
1520 return 0;
1521 }
1522
1523 #ifdef CONFIG_ISA_DMA_API
1524 static void labpc_drain_dma(struct comedi_device *dev)
1525 {
1526 struct comedi_subdevice *s = dev->read_subdev;
1527 struct comedi_async *async = s->async;
1528 int status;
1529 unsigned long flags;
1530 unsigned int max_points, num_points, residue, leftover;
1531 int i;
1532
1533 status = devpriv->status1_bits;
1534
1535 flags = claim_dma_lock();
1536 disable_dma(devpriv->dma_chan);
1537 /* clear flip-flop to make sure 2-byte registers for
1538 * count and address get set correctly */
1539 clear_dma_ff(devpriv->dma_chan);
1540
1541 /* figure out how many points to read */
1542 max_points = devpriv->dma_transfer_size / sample_size;
1543 /* residue is the number of points left to be done on the dma
1544 * transfer. It should always be zero at this point unless
1545 * the stop_src is set to external triggering.
1546 */
1547 residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1548 num_points = max_points - residue;
1549 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1550 num_points = devpriv->count;
1551
1552 /* figure out how many points will be stored next time */
1553 leftover = 0;
1554 if (async->cmd.stop_src != TRIG_COUNT) {
1555 leftover = devpriv->dma_transfer_size / sample_size;
1556 } else if (devpriv->count > num_points) {
1557 leftover = devpriv->count - num_points;
1558 if (leftover > max_points)
1559 leftover = max_points;
1560 }
1561
1562 /* write data to comedi buffer */
1563 for (i = 0; i < num_points; i++)
1564 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
1565
1566 if (async->cmd.stop_src == TRIG_COUNT)
1567 devpriv->count -= num_points;
1568
1569 /* set address and count for next transfer */
1570 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1571 set_dma_count(devpriv->dma_chan, leftover * sample_size);
1572 release_dma_lock(flags);
1573
1574 async->events |= COMEDI_CB_BLOCK;
1575 }
1576
1577 static void handle_isa_dma(struct comedi_device *dev)
1578 {
1579 labpc_drain_dma(dev);
1580
1581 enable_dma(devpriv->dma_chan);
1582
1583 /* clear dma tc interrupt */
1584 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1585 }
1586 #endif
1587
1588 /* makes sure all data acquired by board is transferred to comedi (used
1589 * when acquisition is terminated by stop_src == TRIG_EXT). */
1590 static void labpc_drain_dregs(struct comedi_device *dev)
1591 {
1592 #ifdef CONFIG_ISA_DMA_API
1593 if (devpriv->current_transfer == isa_dma_transfer)
1594 labpc_drain_dma(dev);
1595 #endif
1596
1597 labpc_drain_fifo(dev);
1598 }
1599
1600 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1601 struct comedi_insn *insn, unsigned int *data)
1602 {
1603 int i, n;
1604 int chan, range;
1605 int lsb, msb;
1606 int timeout = 1000;
1607 unsigned long flags;
1608
1609 /* disable timed conversions */
1610 spin_lock_irqsave(&dev->spinlock, flags);
1611 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1612 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1613 spin_unlock_irqrestore(&dev->spinlock, flags);
1614
1615 /* disable interrupt generation and dma */
1616 devpriv->command3_bits = 0;
1617 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1618
1619 /* set gain and channel */
1620 devpriv->command1_bits = 0;
1621 chan = CR_CHAN(insn->chanspec);
1622 range = CR_RANGE(insn->chanspec);
1623 devpriv->command1_bits |= thisboard->ai_range_code[range];
1624 /* munge channel bits for differential/scan disabled mode */
1625 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1626 chan *= 2;
1627 devpriv->command1_bits |= ADC_CHAN_BITS(chan);
1628 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1629
1630 /* setup command6 register for 1200 boards */
1631 if (thisboard->register_layout == labpc_1200_layout) {
1632 /* reference inputs to ground or common? */
1633 if (CR_AREF(insn->chanspec) != AREF_GROUND)
1634 devpriv->command6_bits |= ADC_COMMON_BIT;
1635 else
1636 devpriv->command6_bits &= ~ADC_COMMON_BIT;
1637 /* bipolar or unipolar range? */
1638 if (thisboard->ai_range_is_unipolar[range])
1639 devpriv->command6_bits |= ADC_UNIP_BIT;
1640 else
1641 devpriv->command6_bits &= ~ADC_UNIP_BIT;
1642 /* don't interrupt on fifo half full */
1643 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1644 /* don't enable interrupt on counter a1 terminal count? */
1645 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1646 /* write to register */
1647 devpriv->write_byte(devpriv->command6_bits,
1648 dev->iobase + COMMAND6_REG);
1649 }
1650 /* setup command4 register */
1651 devpriv->command4_bits = 0;
1652 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1653 /* single-ended/differential */
1654 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1655 devpriv->command4_bits |= ADC_DIFF_BIT;
1656 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1657
1658 /*
1659 * initialize pacer counter output to make sure it doesn't
1660 * cause any problems
1661 */
1662 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG);
1663
1664 labpc_clear_adc_fifo(dev);
1665
1666 for (n = 0; n < insn->n; n++) {
1667 /* trigger conversion */
1668 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG);
1669
1670 for (i = 0; i < timeout; i++) {
1671 if (devpriv->read_byte(dev->iobase +
1672 STATUS1_REG) & DATA_AVAIL_BIT)
1673 break;
1674 udelay(1);
1675 }
1676 if (i == timeout) {
1677 comedi_error(dev, "timeout");
1678 return -ETIME;
1679 }
1680 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1681 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1682 data[n] = (msb << 8) | lsb;
1683 }
1684
1685 return n;
1686 }
1687
1688 /* analog output insn */
1689 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1690 struct comedi_insn *insn, unsigned int *data)
1691 {
1692 int channel, range;
1693 unsigned long flags;
1694 int lsb, msb;
1695
1696 channel = CR_CHAN(insn->chanspec);
1697
1698 /* turn off pacing of analog output channel */
1699 /* note: hardware bug in daqcard-1200 means pacing cannot
1700 * be independently enabled/disabled for its the two channels */
1701 spin_lock_irqsave(&dev->spinlock, flags);
1702 devpriv->command2_bits &= ~DAC_PACED_BIT(channel);
1703 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1704 spin_unlock_irqrestore(&dev->spinlock, flags);
1705
1706 /* set range */
1707 if (thisboard->register_layout == labpc_1200_layout) {
1708 range = CR_RANGE(insn->chanspec);
1709 if (range & AO_RANGE_IS_UNIPOLAR)
1710 devpriv->command6_bits |= DAC_UNIP_BIT(channel);
1711 else
1712 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel);
1713 /* write to register */
1714 devpriv->write_byte(devpriv->command6_bits,
1715 dev->iobase + COMMAND6_REG);
1716 }
1717 /* send data */
1718 lsb = data[0] & 0xff;
1719 msb = (data[0] >> 8) & 0xff;
1720 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1721 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1722
1723 /* remember value for readback */
1724 devpriv->ao_value[channel] = data[0];
1725
1726 return 1;
1727 }
1728
1729 /* analog output readback insn */
1730 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1731 struct comedi_insn *insn, unsigned int *data)
1732 {
1733 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1734
1735 return 1;
1736 }
1737
1738 static int labpc_calib_read_insn(struct comedi_device *dev,
1739 struct comedi_subdevice *s,
1740 struct comedi_insn *insn, unsigned int *data)
1741 {
1742 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)];
1743
1744 return 1;
1745 }
1746
1747 static int labpc_calib_write_insn(struct comedi_device *dev,
1748 struct comedi_subdevice *s,
1749 struct comedi_insn *insn, unsigned int *data)
1750 {
1751 int channel = CR_CHAN(insn->chanspec);
1752
1753 write_caldac(dev, channel, data[0]);
1754 return 1;
1755 }
1756
1757 static int labpc_eeprom_read_insn(struct comedi_device *dev,
1758 struct comedi_subdevice *s,
1759 struct comedi_insn *insn, unsigned int *data)
1760 {
1761 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)];
1762
1763 return 1;
1764 }
1765
1766 static int labpc_eeprom_write_insn(struct comedi_device *dev,
1767 struct comedi_subdevice *s,
1768 struct comedi_insn *insn, unsigned int *data)
1769 {
1770 int channel = CR_CHAN(insn->chanspec);
1771 int ret;
1772
1773 /* only allow writes to user area of eeprom */
1774 if (channel < 16 || channel > 127) {
1775 dev_dbg(dev->class_dev,
1776 "eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)\n");
1777 return -EINVAL;
1778 }
1779
1780 ret = labpc_eeprom_write(dev, channel, data[0]);
1781 if (ret < 0)
1782 return ret;
1783
1784 return 1;
1785 }
1786
1787 #ifdef CONFIG_ISA_DMA_API
1788 /* utility function that suggests a dma transfer size in bytes */
1789 static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd)
1790 {
1791 unsigned int size;
1792 unsigned int freq;
1793
1794 if (cmd.convert_src == TRIG_TIMER)
1795 freq = 1000000000 / cmd.convert_arg;
1796 /* return some default value */
1797 else
1798 freq = 0xffffffff;
1799
1800 /* make buffer fill in no more than 1/3 second */
1801 size = (freq / 3) * sample_size;
1802
1803 /* set a minimum and maximum size allowed */
1804 if (size > dma_buffer_size)
1805 size = dma_buffer_size - dma_buffer_size % sample_size;
1806 else if (size < sample_size)
1807 size = sample_size;
1808
1809 return size;
1810 }
1811 #endif
1812
1813 /* figures out what counter values to use based on command */
1814 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
1815 {
1816 /* max value for 16 bit counter in mode 2 */
1817 const int max_counter_value = 0x10000;
1818 /* min value for 16 bit counter in mode 2 */
1819 const int min_counter_value = 2;
1820 unsigned int base_period;
1821
1822 /*
1823 * if both convert and scan triggers are TRIG_TIMER, then they
1824 * both rely on counter b0
1825 */
1826 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) {
1827 /*
1828 * pick the lowest b0 divisor value we can (for maximum input
1829 * clock speed on convert and scan counters)
1830 */
1831 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) /
1832 (LABPC_TIMER_BASE * max_counter_value) + 1;
1833 if (devpriv->divisor_b0 < min_counter_value)
1834 devpriv->divisor_b0 = min_counter_value;
1835 if (devpriv->divisor_b0 > max_counter_value)
1836 devpriv->divisor_b0 = max_counter_value;
1837
1838 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
1839
1840 /* set a0 for conversion frequency and b1 for scan frequency */
1841 switch (cmd->flags & TRIG_ROUND_MASK) {
1842 default:
1843 case TRIG_ROUND_NEAREST:
1844 devpriv->divisor_a0 =
1845 (labpc_ai_convert_period(cmd) +
1846 (base_period / 2)) / base_period;
1847 devpriv->divisor_b1 =
1848 (labpc_ai_scan_period(cmd) +
1849 (base_period / 2)) / base_period;
1850 break;
1851 case TRIG_ROUND_UP:
1852 devpriv->divisor_a0 =
1853 (labpc_ai_convert_period(cmd) + (base_period -
1854 1)) / base_period;
1855 devpriv->divisor_b1 =
1856 (labpc_ai_scan_period(cmd) + (base_period -
1857 1)) / base_period;
1858 break;
1859 case TRIG_ROUND_DOWN:
1860 devpriv->divisor_a0 =
1861 labpc_ai_convert_period(cmd) / base_period;
1862 devpriv->divisor_b1 =
1863 labpc_ai_scan_period(cmd) / base_period;
1864 break;
1865 }
1866 /* make sure a0 and b1 values are acceptable */
1867 if (devpriv->divisor_a0 < min_counter_value)
1868 devpriv->divisor_a0 = min_counter_value;
1869 if (devpriv->divisor_a0 > max_counter_value)
1870 devpriv->divisor_a0 = max_counter_value;
1871 if (devpriv->divisor_b1 < min_counter_value)
1872 devpriv->divisor_b1 = min_counter_value;
1873 if (devpriv->divisor_b1 > max_counter_value)
1874 devpriv->divisor_b1 = max_counter_value;
1875 /* write corrected timings to command */
1876 labpc_set_ai_convert_period(cmd,
1877 base_period * devpriv->divisor_a0);
1878 labpc_set_ai_scan_period(cmd,
1879 base_period * devpriv->divisor_b1);
1880 /*
1881 * if only one TRIG_TIMER is used, we can employ the generic
1882 * cascaded timing functions
1883 */
1884 } else if (labpc_ai_scan_period(cmd)) {
1885 unsigned int scan_period;
1886
1887 scan_period = labpc_ai_scan_period(cmd);
1888 /*
1889 * calculate cascaded counter values
1890 * that give desired scan timing
1891 */
1892 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1893 &(devpriv->divisor_b1),
1894 &(devpriv->divisor_b0),
1895 &scan_period,
1896 cmd->flags & TRIG_ROUND_MASK);
1897 labpc_set_ai_scan_period(cmd, scan_period);
1898 } else if (labpc_ai_convert_period(cmd)) {
1899 unsigned int convert_period;
1900
1901 convert_period = labpc_ai_convert_period(cmd);
1902 /*
1903 * calculate cascaded counter values
1904 * that give desired conversion timing
1905 */
1906 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1907 &(devpriv->divisor_a0),
1908 &(devpriv->divisor_b0),
1909 &convert_period,
1910 cmd->flags & TRIG_ROUND_MASK);
1911 labpc_set_ai_convert_period(cmd, convert_period);
1912 }
1913 }
1914
1915 static int labpc_dio_mem_callback(int dir, int port, int data,
1916 unsigned long iobase)
1917 {
1918 if (dir) {
1919 writeb(data, (void *)(iobase + port));
1920 return 0;
1921 } else {
1922 return readb((void *)(iobase + port));
1923 }
1924 }
1925
1926 /* lowlevel write to eeprom/dac */
1927 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
1928 unsigned int value_width)
1929 {
1930 int i;
1931
1932 for (i = 1; i <= value_width; i++) {
1933 /* clear serial clock */
1934 devpriv->command5_bits &= ~SCLOCK_BIT;
1935 /* send bits most significant bit first */
1936 if (value & (1 << (value_width - i)))
1937 devpriv->command5_bits |= SDATA_BIT;
1938 else
1939 devpriv->command5_bits &= ~SDATA_BIT;
1940 udelay(1);
1941 devpriv->write_byte(devpriv->command5_bits,
1942 dev->iobase + COMMAND5_REG);
1943 /* set clock to load bit */
1944 devpriv->command5_bits |= SCLOCK_BIT;
1945 udelay(1);
1946 devpriv->write_byte(devpriv->command5_bits,
1947 dev->iobase + COMMAND5_REG);
1948 }
1949 }
1950
1951 /* lowlevel read from eeprom */
1952 static unsigned int labpc_serial_in(struct comedi_device *dev)
1953 {
1954 unsigned int value = 0;
1955 int i;
1956 const int value_width = 8; /* number of bits wide values are */
1957
1958 for (i = 1; i <= value_width; i++) {
1959 /* set serial clock */
1960 devpriv->command5_bits |= SCLOCK_BIT;
1961 udelay(1);
1962 devpriv->write_byte(devpriv->command5_bits,
1963 dev->iobase + COMMAND5_REG);
1964 /* clear clock bit */
1965 devpriv->command5_bits &= ~SCLOCK_BIT;
1966 udelay(1);
1967 devpriv->write_byte(devpriv->command5_bits,
1968 dev->iobase + COMMAND5_REG);
1969 /* read bits most significant bit first */
1970 udelay(1);
1971 devpriv->status2_bits =
1972 devpriv->read_byte(dev->iobase + STATUS2_REG);
1973 if (devpriv->status2_bits & EEPROM_OUT_BIT)
1974 value |= 1 << (value_width - i);
1975 }
1976
1977 return value;
1978 }
1979
1980 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
1981 unsigned int address)
1982 {
1983 unsigned int value;
1984 /* bits to tell eeprom to expect a read */
1985 const int read_instruction = 0x3;
1986 /* 8 bit write lengths to eeprom */
1987 const int write_length = 8;
1988
1989 /* enable read/write to eeprom */
1990 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1991 udelay(1);
1992 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1993 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1994 udelay(1);
1995 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1996
1997 /* send read instruction */
1998 labpc_serial_out(dev, read_instruction, write_length);
1999 /* send 8 bit address to read from */
2000 labpc_serial_out(dev, address, write_length);
2001 /* read result */
2002 value = labpc_serial_in(dev);
2003
2004 /* disable read/write to eeprom */
2005 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2006 udelay(1);
2007 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2008
2009 return value;
2010 }
2011
2012 static int labpc_eeprom_write(struct comedi_device *dev,
2013 unsigned int address, unsigned int value)
2014 {
2015 const int write_enable_instruction = 0x6;
2016 const int write_instruction = 0x2;
2017 const int write_length = 8; /* 8 bit write lengths to eeprom */
2018 const int write_in_progress_bit = 0x1;
2019 const int timeout = 10000;
2020 int i;
2021
2022 /* make sure there isn't already a write in progress */
2023 for (i = 0; i < timeout; i++) {
2024 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
2025 0)
2026 break;
2027 }
2028 if (i == timeout) {
2029 comedi_error(dev, "eeprom write timed out");
2030 return -ETIME;
2031 }
2032 /* update software copy of eeprom */
2033 devpriv->eeprom_data[address] = value;
2034
2035 /* enable read/write to eeprom */
2036 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2037 udelay(1);
2038 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2039 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2040 udelay(1);
2041 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2042
2043 /* send write_enable instruction */
2044 labpc_serial_out(dev, write_enable_instruction, write_length);
2045 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2046 udelay(1);
2047 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2048
2049 /* send write instruction */
2050 devpriv->command5_bits |= EEPROM_EN_BIT;
2051 udelay(1);
2052 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2053 labpc_serial_out(dev, write_instruction, write_length);
2054 /* send 8 bit address to write to */
2055 labpc_serial_out(dev, address, write_length);
2056 /* write value */
2057 labpc_serial_out(dev, value, write_length);
2058 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2059 udelay(1);
2060 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2061
2062 /* disable read/write to eeprom */
2063 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2064 udelay(1);
2065 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2066
2067 return 0;
2068 }
2069
2070 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev)
2071 {
2072 unsigned int value;
2073 const int read_status_instruction = 0x5;
2074 const int write_length = 8; /* 8 bit write lengths to eeprom */
2075
2076 /* enable read/write to eeprom */
2077 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2078 udelay(1);
2079 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2080 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2081 udelay(1);
2082 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2083
2084 /* send read status instruction */
2085 labpc_serial_out(dev, read_status_instruction, write_length);
2086 /* read result */
2087 value = labpc_serial_in(dev);
2088
2089 /* disable read/write to eeprom */
2090 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2091 udelay(1);
2092 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2093
2094 return value;
2095 }
2096
2097 /* writes to 8 bit calibration dacs */
2098 static void write_caldac(struct comedi_device *dev, unsigned int channel,
2099 unsigned int value)
2100 {
2101 if (value == devpriv->caldac[channel])
2102 return;
2103 devpriv->caldac[channel] = value;
2104
2105 /* clear caldac load bit and make sure we don't write to eeprom */
2106 devpriv->command5_bits &=
2107 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2108 udelay(1);
2109 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2110
2111 /* write 4 bit channel */
2112 labpc_serial_out(dev, channel, 4);
2113 /* write 8 bit caldac value */
2114 labpc_serial_out(dev, value, 8);
2115
2116 /* set and clear caldac bit to load caldac value */
2117 devpriv->command5_bits |= CALDAC_LOAD_BIT;
2118 udelay(1);
2119 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2120 devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
2121 udelay(1);
2122 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2123 }
2124
2125 #ifdef CONFIG_COMEDI_PCI_DRIVERS
2126 static int __devinit labpc_pci_probe(struct pci_dev *dev,
2127 const struct pci_device_id *ent)
2128 {
2129 return comedi_pci_auto_config(dev, &labpc_driver);
2130 }
2131
2132 static void __devexit labpc_pci_remove(struct pci_dev *dev)
2133 {
2134 comedi_pci_auto_unconfig(dev);
2135 }
2136
2137 static struct pci_driver labpc_pci_driver = {
2138 .name = DRV_NAME,
2139 .id_table = labpc_pci_table,
2140 .probe = labpc_pci_probe,
2141 .remove = __devexit_p(labpc_pci_remove)
2142 };
2143 module_comedi_pci_driver(labpc_driver, labpc_pci_driver);
2144 #else
2145 module_comedi_driver(labpc_driver);
2146 #endif
2147
2148
2149 MODULE_AUTHOR("Comedi http://www.comedi.org");
2150 MODULE_DESCRIPTION("Comedi low-level driver");
2151 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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