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staging: comedi: 8253: mmio address is a void __iomem *
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_labpc.c
1 /*
2 comedi/drivers/ni_labpc.c
3 Driver for National Instruments Lab-PC series boards and compatibles
4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
20 ************************************************************************
21 */
22 /*
23 Driver: ni_labpc
24 Description: National Instruments Lab-PC (& compatibles)
25 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
26 Devices: [National Instruments] Lab-PC-1200 (labpc-1200),
27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc)
28 Status: works
29
30 Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges
31 and analog references will work, the available ranges/arefs will
32 depend on how you have configured the jumpers on your board
33 (see your owner's manual).
34
35 Kernel-level ISA plug-and-play support for the lab-pc-1200
36 boards has not
37 yet been added to the driver, mainly due to the fact that
38 I don't know the device id numbers. If you have one
39 of these boards,
40 please file a bug report at http://comedi.org/
41 so I can get the necessary information from you.
42
43 The 1200 series boards have onboard calibration dacs for correcting
44 analog input/output offsets and gains. The proper settings for these
45 caldacs are stored on the board's eeprom. To read the caldac values
46 from the eeprom and store them into a file that can be then be used by
47 comedilib, use the comedi_calibrate program.
48
49 Configuration options - ISA boards:
50 [0] - I/O port base address
51 [1] - IRQ (optional, required for timed or externally triggered conversions)
52 [2] - DMA channel (optional)
53
54 Configuration options - PCI boards:
55 [0] - bus (optional)
56 [1] - slot (optional)
57
58 The Lab-pc+ has quirky chanlist requirements
59 when scanning multiple channels. Multiple channel scan
60 sequence must start at highest channel, then decrement down to
61 channel 0. The rest of the cards can scan down like lab-pc+ or scan
62 up from channel zero. Chanlists consisting of all one channel
63 are also legal, and allow you to pace conversions in bursts.
64
65 */
66
67 /*
68
69 NI manuals:
70 341309a (labpc-1200 register manual)
71 340914a (pci-1200)
72 320502b (lab-pc+)
73
74 */
75
76 #include <linux/interrupt.h>
77 #include <linux/slab.h>
78 #include <linux/io.h>
79 #include "../comedidev.h"
80
81 #include <linux/delay.h>
82 #include <asm/dma.h>
83
84 #include "8253.h"
85 #include "8255.h"
86 #include "mite.h"
87 #include "comedi_fc.h"
88 #include "ni_labpc.h"
89
90 #define DRV_NAME "ni_labpc"
91
92 /* size of io region used by board */
93 #define LABPC_SIZE 32
94 /* 2 MHz master clock */
95 #define LABPC_TIMER_BASE 500
96
97 /* Registers for the lab-pc+ */
98
99 /* write-only registers */
100 #define COMMAND1_REG 0x0
101 #define ADC_GAIN_MASK (0x7 << 4)
102 #define ADC_CHAN_BITS(x) ((x) & 0x7)
103 /* enables multi channel scans */
104 #define ADC_SCAN_EN_BIT 0x80
105 #define COMMAND2_REG 0x1
106 /* enable pretriggering (used in conjunction with SWTRIG) */
107 #define PRETRIG_BIT 0x1
108 /* enable paced conversions on external trigger */
109 #define HWTRIG_BIT 0x2
110 /* enable paced conversions */
111 #define SWTRIG_BIT 0x4
112 /* use two cascaded counters for pacing */
113 #define CASCADE_BIT 0x8
114 #define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1))
115 #define COMMAND3_REG 0x2
116 /* enable dma transfers */
117 #define DMA_EN_BIT 0x1
118 /* enable interrupts for 8255 */
119 #define DIO_INTR_EN_BIT 0x2
120 /* enable dma terminal count interrupt */
121 #define DMATC_INTR_EN_BIT 0x4
122 /* enable timer interrupt */
123 #define TIMER_INTR_EN_BIT 0x8
124 /* enable error interrupt */
125 #define ERR_INTR_EN_BIT 0x10
126 /* enable fifo not empty interrupt */
127 #define ADC_FNE_INTR_EN_BIT 0x20
128 #define ADC_CONVERT_REG 0x3
129 #define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1))
130 #define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1))
131 #define ADC_CLEAR_REG 0x8
132 #define DMATC_CLEAR_REG 0xa
133 #define TIMER_CLEAR_REG 0xc
134 /* 1200 boards only */
135 #define COMMAND6_REG 0xe
136 /* select ground or common-mode reference */
137 #define ADC_COMMON_BIT 0x1
138 /* adc unipolar */
139 #define ADC_UNIP_BIT 0x2
140 /* dac unipolar */
141 #define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1))
142 /* enable fifo half full interrupt */
143 #define ADC_FHF_INTR_EN_BIT 0x20
144 /* enable interrupt on end of hardware count */
145 #define A1_INTR_EN_BIT 0x40
146 /* scan up from channel zero instead of down to zero */
147 #define ADC_SCAN_UP_BIT 0x80
148 #define COMMAND4_REG 0xf
149 /* enables 'interval' scanning */
150 #define INTERVAL_SCAN_EN_BIT 0x1
151 /* enables external signal on counter b1 output to trigger scan */
152 #define EXT_SCAN_EN_BIT 0x2
153 /* chooses direction (output or input) for EXTCONV* line */
154 #define EXT_CONVERT_OUT_BIT 0x4
155 /* chooses differential inputs for adc (in conjunction with board jumper) */
156 #define ADC_DIFF_BIT 0x8
157 #define EXT_CONVERT_DISABLE_BIT 0x10
158 /* 1200 boards only, calibration stuff */
159 #define COMMAND5_REG 0x1c
160 /* enable eeprom for write */
161 #define EEPROM_WRITE_UNPROTECT_BIT 0x4
162 /* enable dithering */
163 #define DITHER_EN_BIT 0x8
164 /* load calibration dac */
165 #define CALDAC_LOAD_BIT 0x10
166 /* serial clock - rising edge writes, falling edge reads */
167 #define SCLOCK_BIT 0x20
168 /* serial data bit for writing to eeprom or calibration dacs */
169 #define SDATA_BIT 0x40
170 /* enable eeprom for read/write */
171 #define EEPROM_EN_BIT 0x80
172 #define INTERVAL_COUNT_REG 0x1e
173 #define INTERVAL_LOAD_REG 0x1f
174 #define INTERVAL_LOAD_BITS 0x1
175
176 /* read-only registers */
177 #define STATUS1_REG 0x0
178 /* data is available in fifo */
179 #define DATA_AVAIL_BIT 0x1
180 /* overrun has occurred */
181 #define OVERRUN_BIT 0x2
182 /* fifo overflow */
183 #define OVERFLOW_BIT 0x4
184 /* timer interrupt has occurred */
185 #define TIMER_BIT 0x8
186 /* dma terminal count has occurred */
187 #define DMATC_BIT 0x10
188 /* external trigger has occurred */
189 #define EXT_TRIG_BIT 0x40
190 /* 1200 boards only */
191 #define STATUS2_REG 0x1d
192 /* programmable eeprom serial output */
193 #define EEPROM_OUT_BIT 0x1
194 /* counter A1 terminal count */
195 #define A1_TC_BIT 0x2
196 /* fifo not half full */
197 #define FNHF_BIT 0x4
198 #define ADC_FIFO_REG 0xa
199
200 #define DIO_BASE_REG 0x10
201 #define COUNTER_A_BASE_REG 0x14
202 #define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3)
203 /* check modes put conversion pacer output in harmless state (a0 mode 2) */
204 #define INIT_A0_BITS 0x14
205 /* put hardware conversion counter output in harmless state (a1 mode 0) */
206 #define INIT_A1_BITS 0x70
207 #define COUNTER_B_BASE_REG 0x18
208
209 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
210 static irqreturn_t labpc_interrupt(int irq, void *d);
211 static int labpc_drain_fifo(struct comedi_device *dev);
212 #ifdef CONFIG_ISA_DMA_API
213 static void labpc_drain_dma(struct comedi_device *dev);
214 static void handle_isa_dma(struct comedi_device *dev);
215 #endif
216 static void labpc_drain_dregs(struct comedi_device *dev);
217 static int labpc_ai_cmdtest(struct comedi_device *dev,
218 struct comedi_subdevice *s, struct comedi_cmd *cmd);
219 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
220 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
221 struct comedi_insn *insn, unsigned int *data);
222 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
223 struct comedi_insn *insn, unsigned int *data);
224 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
225 struct comedi_insn *insn, unsigned int *data);
226 static int labpc_calib_read_insn(struct comedi_device *dev,
227 struct comedi_subdevice *s,
228 struct comedi_insn *insn, unsigned int *data);
229 static int labpc_calib_write_insn(struct comedi_device *dev,
230 struct comedi_subdevice *s,
231 struct comedi_insn *insn, unsigned int *data);
232 static int labpc_eeprom_read_insn(struct comedi_device *dev,
233 struct comedi_subdevice *s,
234 struct comedi_insn *insn, unsigned int *data);
235 static int labpc_eeprom_write_insn(struct comedi_device *dev,
236 struct comedi_subdevice *s,
237 struct comedi_insn *insn,
238 unsigned int *data);
239 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd);
240 #ifdef CONFIG_ISA_DMA_API
241 static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd);
242 #endif
243 static int labpc_dio_mem_callback(int dir, int port, int data,
244 unsigned long arg);
245 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
246 unsigned int num_bits);
247 static unsigned int labpc_serial_in(struct comedi_device *dev);
248 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
249 unsigned int address);
250 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev);
251 static int labpc_eeprom_write(struct comedi_device *dev,
252 unsigned int address,
253 unsigned int value);
254 static void write_caldac(struct comedi_device *dev, unsigned int channel,
255 unsigned int value);
256
257 enum scan_mode {
258 MODE_SINGLE_CHAN,
259 MODE_SINGLE_CHAN_INTERVAL,
260 MODE_MULT_CHAN_UP,
261 MODE_MULT_CHAN_DOWN,
262 };
263
264 /* analog input ranges */
265 #define NUM_LABPC_PLUS_AI_RANGES 16
266 /* indicates unipolar ranges */
267 static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = {
268 0,
269 0,
270 0,
271 0,
272 0,
273 0,
274 0,
275 0,
276 1,
277 1,
278 1,
279 1,
280 1,
281 1,
282 1,
283 1,
284 };
285
286 /* map range index to gain bits */
287 static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = {
288 0x00,
289 0x10,
290 0x20,
291 0x30,
292 0x40,
293 0x50,
294 0x60,
295 0x70,
296 0x00,
297 0x10,
298 0x20,
299 0x30,
300 0x40,
301 0x50,
302 0x60,
303 0x70,
304 };
305
306 static const struct comedi_lrange range_labpc_plus_ai = {
307 NUM_LABPC_PLUS_AI_RANGES,
308 {
309 BIP_RANGE(5),
310 BIP_RANGE(4),
311 BIP_RANGE(2.5),
312 BIP_RANGE(1),
313 BIP_RANGE(0.5),
314 BIP_RANGE(0.25),
315 BIP_RANGE(0.1),
316 BIP_RANGE(0.05),
317 UNI_RANGE(10),
318 UNI_RANGE(8),
319 UNI_RANGE(5),
320 UNI_RANGE(2),
321 UNI_RANGE(1),
322 UNI_RANGE(0.5),
323 UNI_RANGE(0.2),
324 UNI_RANGE(0.1),
325 }
326 };
327
328 #define NUM_LABPC_1200_AI_RANGES 14
329 /* indicates unipolar ranges */
330 const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = {
331 0,
332 0,
333 0,
334 0,
335 0,
336 0,
337 0,
338 1,
339 1,
340 1,
341 1,
342 1,
343 1,
344 1,
345 };
346 EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar);
347
348 /* map range index to gain bits */
349 const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = {
350 0x00,
351 0x20,
352 0x30,
353 0x40,
354 0x50,
355 0x60,
356 0x70,
357 0x00,
358 0x20,
359 0x30,
360 0x40,
361 0x50,
362 0x60,
363 0x70,
364 };
365 EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits);
366
367 const struct comedi_lrange range_labpc_1200_ai = {
368 NUM_LABPC_1200_AI_RANGES,
369 {
370 BIP_RANGE(5),
371 BIP_RANGE(2.5),
372 BIP_RANGE(1),
373 BIP_RANGE(0.5),
374 BIP_RANGE(0.25),
375 BIP_RANGE(0.1),
376 BIP_RANGE(0.05),
377 UNI_RANGE(10),
378 UNI_RANGE(5),
379 UNI_RANGE(2),
380 UNI_RANGE(1),
381 UNI_RANGE(0.5),
382 UNI_RANGE(0.2),
383 UNI_RANGE(0.1),
384 }
385 };
386 EXPORT_SYMBOL_GPL(range_labpc_1200_ai);
387
388 /* analog output ranges */
389 #define AO_RANGE_IS_UNIPOLAR 0x1
390 static const struct comedi_lrange range_labpc_ao = {
391 2,
392 {
393 BIP_RANGE(5),
394 UNI_RANGE(10),
395 }
396 };
397
398 /* functions that do inb/outb and readb/writeb so we can use
399 * function pointers to decide which to use */
400 static inline unsigned int labpc_inb(unsigned long address)
401 {
402 return inb(address);
403 }
404
405 static inline void labpc_outb(unsigned int byte, unsigned long address)
406 {
407 outb(byte, address);
408 }
409
410 static inline unsigned int labpc_readb(unsigned long address)
411 {
412 return readb((void __iomem *)address);
413 }
414
415 static inline void labpc_writeb(unsigned int byte, unsigned long address)
416 {
417 writeb(byte, (void __iomem *)address);
418 }
419
420 static const struct labpc_board_struct labpc_boards[] = {
421 {
422 .name = "lab-pc-1200",
423 .ai_speed = 10000,
424 .bustype = isa_bustype,
425 .register_layout = labpc_1200_layout,
426 .has_ao = 1,
427 .ai_range_table = &range_labpc_1200_ai,
428 .ai_range_code = labpc_1200_ai_gain_bits,
429 .ai_range_is_unipolar = labpc_1200_is_unipolar,
430 .ai_scan_up = 1,
431 .memory_mapped_io = 0,
432 },
433 {
434 .name = "lab-pc-1200ai",
435 .ai_speed = 10000,
436 .bustype = isa_bustype,
437 .register_layout = labpc_1200_layout,
438 .has_ao = 0,
439 .ai_range_table = &range_labpc_1200_ai,
440 .ai_range_code = labpc_1200_ai_gain_bits,
441 .ai_range_is_unipolar = labpc_1200_is_unipolar,
442 .ai_scan_up = 1,
443 .memory_mapped_io = 0,
444 },
445 {
446 .name = "lab-pc+",
447 .ai_speed = 12000,
448 .bustype = isa_bustype,
449 .register_layout = labpc_plus_layout,
450 .has_ao = 1,
451 .ai_range_table = &range_labpc_plus_ai,
452 .ai_range_code = labpc_plus_ai_gain_bits,
453 .ai_range_is_unipolar = labpc_plus_is_unipolar,
454 .ai_scan_up = 0,
455 .memory_mapped_io = 0,
456 },
457 #ifdef CONFIG_COMEDI_PCI_DRIVERS
458 {
459 .name = "pci-1200",
460 .device_id = 0x161,
461 .ai_speed = 10000,
462 .bustype = pci_bustype,
463 .register_layout = labpc_1200_layout,
464 .has_ao = 1,
465 .ai_range_table = &range_labpc_1200_ai,
466 .ai_range_code = labpc_1200_ai_gain_bits,
467 .ai_range_is_unipolar = labpc_1200_is_unipolar,
468 .ai_scan_up = 1,
469 .memory_mapped_io = 1,
470 },
471 /* dummy entry so pci board works when comedi_config is passed driver name */
472 {
473 .name = DRV_NAME,
474 .bustype = pci_bustype,
475 },
476 #endif
477 };
478
479 /*
480 * Useful for shorthand access to the particular board structure
481 */
482 #define thisboard ((struct labpc_board_struct *)dev->board_ptr)
483
484 /* size in bytes of dma buffer */
485 static const int dma_buffer_size = 0xff00;
486 /* 2 bytes per sample */
487 static const int sample_size = 2;
488
489 #define devpriv ((struct labpc_private *)dev->private)
490
491 static inline int labpc_counter_load(struct comedi_device *dev,
492 unsigned long base_address,
493 unsigned int counter_number,
494 unsigned int count, unsigned int mode)
495 {
496 if (thisboard->memory_mapped_io)
497 return i8254_mm_load((void __iomem *)base_address, 0,
498 counter_number, count, mode);
499 else
500 return i8254_load(base_address, 0, counter_number, count, mode);
501 }
502
503 int labpc_common_attach(struct comedi_device *dev, unsigned long iobase,
504 unsigned int irq, unsigned int dma_chan)
505 {
506 struct comedi_subdevice *s;
507 int i;
508 unsigned long isr_flags;
509 #ifdef CONFIG_ISA_DMA_API
510 unsigned long dma_flags;
511 #endif
512 short lsb, msb;
513 int ret;
514
515 dev_info(dev->class_dev, "ni_labpc: %s\n", thisboard->name);
516 if (iobase == 0) {
517 dev_err(dev->class_dev, "io base address is zero!\n");
518 return -EINVAL;
519 }
520 /* request io regions for isa boards */
521 if (thisboard->bustype == isa_bustype) {
522 /* check if io addresses are available */
523 if (!request_region(iobase, LABPC_SIZE, DRV_NAME)) {
524 dev_err(dev->class_dev, "I/O port conflict\n");
525 return -EIO;
526 }
527 }
528 dev->iobase = iobase;
529
530 if (thisboard->memory_mapped_io) {
531 devpriv->read_byte = labpc_readb;
532 devpriv->write_byte = labpc_writeb;
533 } else {
534 devpriv->read_byte = labpc_inb;
535 devpriv->write_byte = labpc_outb;
536 }
537 /* initialize board's command registers */
538 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
539 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
540 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
541 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
542 if (thisboard->register_layout == labpc_1200_layout) {
543 devpriv->write_byte(devpriv->command5_bits,
544 dev->iobase + COMMAND5_REG);
545 devpriv->write_byte(devpriv->command6_bits,
546 dev->iobase + COMMAND6_REG);
547 }
548
549 /* grab our IRQ */
550 if (irq) {
551 isr_flags = 0;
552 if (thisboard->bustype == pci_bustype
553 || thisboard->bustype == pcmcia_bustype)
554 isr_flags |= IRQF_SHARED;
555 if (request_irq(irq, labpc_interrupt, isr_flags,
556 DRV_NAME, dev)) {
557 dev_err(dev->class_dev, "unable to allocate irq %u\n",
558 irq);
559 return -EINVAL;
560 }
561 }
562 dev->irq = irq;
563
564 #ifdef CONFIG_ISA_DMA_API
565 /* grab dma channel */
566 if (dma_chan > 3) {
567 dev_err(dev->class_dev, "invalid dma channel %u\n", dma_chan);
568 return -EINVAL;
569 } else if (dma_chan) {
570 /* allocate dma buffer */
571 devpriv->dma_buffer =
572 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA);
573 if (devpriv->dma_buffer == NULL) {
574 dev_err(dev->class_dev,
575 "failed to allocate dma buffer\n");
576 return -ENOMEM;
577 }
578 if (request_dma(dma_chan, DRV_NAME)) {
579 dev_err(dev->class_dev,
580 "failed to allocate dma channel %u\n",
581 dma_chan);
582 return -EINVAL;
583 }
584 devpriv->dma_chan = dma_chan;
585 dma_flags = claim_dma_lock();
586 disable_dma(devpriv->dma_chan);
587 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
588 release_dma_lock(dma_flags);
589 }
590 #endif
591
592 dev->board_name = thisboard->name;
593
594 ret = comedi_alloc_subdevices(dev, 5);
595 if (ret)
596 return ret;
597
598 /* analog input subdevice */
599 s = &dev->subdevices[0];
600 dev->read_subdev = s;
601 s->type = COMEDI_SUBD_AI;
602 s->subdev_flags =
603 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
604 s->n_chan = 8;
605 s->len_chanlist = 8;
606 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
607 s->range_table = thisboard->ai_range_table;
608 s->do_cmd = labpc_ai_cmd;
609 s->do_cmdtest = labpc_ai_cmdtest;
610 s->insn_read = labpc_ai_rinsn;
611 s->cancel = labpc_cancel;
612
613 /* analog output */
614 s = &dev->subdevices[1];
615 if (thisboard->has_ao) {
616 /*
617 * Could provide command support, except it only has a
618 * one sample hardware buffer for analog output and no
619 * underrun flag.
620 */
621 s->type = COMEDI_SUBD_AO;
622 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
623 s->n_chan = NUM_AO_CHAN;
624 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
625 s->range_table = &range_labpc_ao;
626 s->insn_read = labpc_ao_rinsn;
627 s->insn_write = labpc_ao_winsn;
628 /* initialize analog outputs to a known value */
629 for (i = 0; i < s->n_chan; i++) {
630 devpriv->ao_value[i] = s->maxdata / 2;
631 lsb = devpriv->ao_value[i] & 0xff;
632 msb = (devpriv->ao_value[i] >> 8) & 0xff;
633 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
634 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
635 }
636 } else {
637 s->type = COMEDI_SUBD_UNUSED;
638 }
639
640 /* 8255 dio */
641 s = &dev->subdevices[2];
642 /* if board uses io memory we have to give a custom callback
643 * function to the 8255 driver */
644 if (thisboard->memory_mapped_io)
645 subdev_8255_init(dev, s, labpc_dio_mem_callback,
646 (unsigned long)(dev->iobase + DIO_BASE_REG));
647 else
648 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG);
649
650 /* calibration subdevices for boards that have one */
651 s = &dev->subdevices[3];
652 if (thisboard->register_layout == labpc_1200_layout) {
653 s->type = COMEDI_SUBD_CALIB;
654 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
655 s->n_chan = 16;
656 s->maxdata = 0xff;
657 s->insn_read = labpc_calib_read_insn;
658 s->insn_write = labpc_calib_write_insn;
659
660 for (i = 0; i < s->n_chan; i++)
661 write_caldac(dev, i, s->maxdata / 2);
662 } else
663 s->type = COMEDI_SUBD_UNUSED;
664
665 /* EEPROM */
666 s = &dev->subdevices[4];
667 if (thisboard->register_layout == labpc_1200_layout) {
668 s->type = COMEDI_SUBD_MEMORY;
669 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
670 s->n_chan = EEPROM_SIZE;
671 s->maxdata = 0xff;
672 s->insn_read = labpc_eeprom_read_insn;
673 s->insn_write = labpc_eeprom_write_insn;
674
675 for (i = 0; i < EEPROM_SIZE; i++)
676 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
677 } else
678 s->type = COMEDI_SUBD_UNUSED;
679
680 return 0;
681 }
682 EXPORT_SYMBOL_GPL(labpc_common_attach);
683
684 static const struct labpc_board_struct *
685 labpc_pci_find_boardinfo(struct pci_dev *pcidev)
686 {
687 unsigned int device_id = pcidev->device;
688 unsigned int n;
689
690 for (n = 0; n < ARRAY_SIZE(labpc_boards); n++) {
691 const struct labpc_board_struct *board = &labpc_boards[n];
692 if (board->bustype == pci_bustype &&
693 board->device_id == device_id)
694 return board;
695 }
696 return NULL;
697 }
698
699 static int __devinit labpc_attach_pci(struct comedi_device *dev,
700 struct pci_dev *pcidev)
701 {
702 unsigned long iobase;
703 unsigned int irq;
704 int ret;
705
706 if (!IS_ENABLED(CONFIG_COMEDI_PCI_DRIVERS))
707 return -ENODEV;
708 ret = alloc_private(dev, sizeof(struct labpc_private));
709 if (ret < 0)
710 return ret;
711 dev->board_ptr = labpc_pci_find_boardinfo(pcidev);
712 if (!dev->board_ptr)
713 return -ENODEV;
714 devpriv->mite = mite_alloc(pcidev);
715 if (!devpriv->mite)
716 return -ENOMEM;
717 ret = mite_setup(devpriv->mite);
718 if (ret < 0)
719 return ret;
720 iobase = (unsigned long)devpriv->mite->daq_io_addr;
721 irq = mite_irq(devpriv->mite);
722 return labpc_common_attach(dev, iobase, irq, 0);
723 }
724
725 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it)
726 {
727 unsigned long iobase = 0;
728 unsigned int irq = 0;
729 unsigned int dma_chan = 0;
730
731 /* allocate and initialize dev->private */
732 if (alloc_private(dev, sizeof(struct labpc_private)) < 0)
733 return -ENOMEM;
734
735 /* get base address, irq etc. based on bustype */
736 switch (thisboard->bustype) {
737 case isa_bustype:
738 #ifdef CONFIG_ISA_DMA_API
739 iobase = it->options[0];
740 irq = it->options[1];
741 dma_chan = it->options[2];
742 #else
743 dev_err(dev->class_dev,
744 "ni_labpc driver has not been built with ISA DMA support.\n");
745 return -EINVAL;
746 #endif
747 break;
748 case pci_bustype:
749 #ifdef CONFIG_COMEDI_PCI_DRIVERS
750 dev_err(dev->class_dev,
751 "manual configuration of PCI board '%s' is not supported\n",
752 thisboard->name);
753 return -EINVAL;
754 #else
755 dev_err(dev->class_dev,
756 "ni_labpc driver has not been built with PCI support.\n");
757 return -EINVAL;
758 #endif
759 break;
760 default:
761 dev_err(dev->class_dev,
762 "ni_labpc: bug! couldn't determine board type\n");
763 return -EINVAL;
764 break;
765 }
766
767 return labpc_common_attach(dev, iobase, irq, dma_chan);
768 }
769
770 void labpc_common_detach(struct comedi_device *dev)
771 {
772 struct comedi_subdevice *s;
773
774 if (dev->subdevices) {
775 s = &dev->subdevices[2];
776 subdev_8255_cleanup(dev, s);
777 }
778 #ifdef CONFIG_ISA_DMA_API
779 /* only free stuff if it has been allocated by _attach */
780 kfree(devpriv->dma_buffer);
781 if (devpriv->dma_chan)
782 free_dma(devpriv->dma_chan);
783 #endif
784 if (dev->irq)
785 free_irq(dev->irq, dev);
786 if (thisboard->bustype == isa_bustype && dev->iobase)
787 release_region(dev->iobase, LABPC_SIZE);
788 #ifdef CONFIG_COMEDI_PCI_DRIVERS
789 if (devpriv->mite) {
790 mite_unsetup(devpriv->mite);
791 mite_free(devpriv->mite);
792 }
793 #endif
794 };
795 EXPORT_SYMBOL_GPL(labpc_common_detach);
796
797 static void labpc_clear_adc_fifo(const struct comedi_device *dev)
798 {
799 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
800 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
801 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
802 }
803
804 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
805 {
806 unsigned long flags;
807
808 spin_lock_irqsave(&dev->spinlock, flags);
809 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
810 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
811 spin_unlock_irqrestore(&dev->spinlock, flags);
812
813 devpriv->command3_bits = 0;
814 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
815
816 return 0;
817 }
818
819 static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd)
820 {
821 if (cmd->chanlist_len == 1)
822 return MODE_SINGLE_CHAN;
823
824 /* chanlist may be NULL during cmdtest. */
825 if (cmd->chanlist == NULL)
826 return MODE_MULT_CHAN_UP;
827
828 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
829 return MODE_SINGLE_CHAN_INTERVAL;
830
831 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
832 return MODE_MULT_CHAN_UP;
833
834 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
835 return MODE_MULT_CHAN_DOWN;
836
837 pr_err("ni_labpc: bug! cannot determine AI scan mode\n");
838 return 0;
839 }
840
841 static int labpc_ai_chanlist_invalid(const struct comedi_device *dev,
842 const struct comedi_cmd *cmd)
843 {
844 int mode, channel, range, aref, i;
845
846 if (cmd->chanlist == NULL)
847 return 0;
848
849 mode = labpc_ai_scan_mode(cmd);
850
851 if (mode == MODE_SINGLE_CHAN)
852 return 0;
853
854 if (mode == MODE_SINGLE_CHAN_INTERVAL) {
855 if (cmd->chanlist_len > 0xff) {
856 comedi_error(dev,
857 "ni_labpc: chanlist too long for single channel interval mode\n");
858 return 1;
859 }
860 }
861
862 channel = CR_CHAN(cmd->chanlist[0]);
863 range = CR_RANGE(cmd->chanlist[0]);
864 aref = CR_AREF(cmd->chanlist[0]);
865
866 for (i = 0; i < cmd->chanlist_len; i++) {
867
868 switch (mode) {
869 case MODE_SINGLE_CHAN_INTERVAL:
870 if (CR_CHAN(cmd->chanlist[i]) != channel) {
871 comedi_error(dev,
872 "channel scanning order specified in chanlist is not supported by hardware.\n");
873 return 1;
874 }
875 break;
876 case MODE_MULT_CHAN_UP:
877 if (CR_CHAN(cmd->chanlist[i]) != i) {
878 comedi_error(dev,
879 "channel scanning order specified in chanlist is not supported by hardware.\n");
880 return 1;
881 }
882 break;
883 case MODE_MULT_CHAN_DOWN:
884 if (CR_CHAN(cmd->chanlist[i]) !=
885 cmd->chanlist_len - i - 1) {
886 comedi_error(dev,
887 "channel scanning order specified in chanlist is not supported by hardware.\n");
888 return 1;
889 }
890 break;
891 default:
892 dev_err(dev->class_dev,
893 "ni_labpc: bug! in chanlist check\n");
894 return 1;
895 break;
896 }
897
898 if (CR_RANGE(cmd->chanlist[i]) != range) {
899 comedi_error(dev,
900 "entries in chanlist must all have the same range\n");
901 return 1;
902 }
903
904 if (CR_AREF(cmd->chanlist[i]) != aref) {
905 comedi_error(dev,
906 "entries in chanlist must all have the same reference\n");
907 return 1;
908 }
909 }
910
911 return 0;
912 }
913
914 static int labpc_use_continuous_mode(const struct comedi_cmd *cmd)
915 {
916 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN)
917 return 1;
918
919 if (cmd->scan_begin_src == TRIG_FOLLOW)
920 return 1;
921
922 return 0;
923 }
924
925 static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd)
926 {
927 if (cmd->convert_src != TRIG_TIMER)
928 return 0;
929
930 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
931 cmd->scan_begin_src == TRIG_TIMER)
932 return cmd->scan_begin_arg;
933
934 return cmd->convert_arg;
935 }
936
937 static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns)
938 {
939 if (cmd->convert_src != TRIG_TIMER)
940 return;
941
942 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
943 cmd->scan_begin_src == TRIG_TIMER) {
944 cmd->scan_begin_arg = ns;
945 if (cmd->convert_arg > cmd->scan_begin_arg)
946 cmd->convert_arg = cmd->scan_begin_arg;
947 } else
948 cmd->convert_arg = ns;
949 }
950
951 static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd)
952 {
953 if (cmd->scan_begin_src != TRIG_TIMER)
954 return 0;
955
956 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
957 cmd->convert_src == TRIG_TIMER)
958 return 0;
959
960 return cmd->scan_begin_arg;
961 }
962
963 static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns)
964 {
965 if (cmd->scan_begin_src != TRIG_TIMER)
966 return;
967
968 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
969 cmd->convert_src == TRIG_TIMER)
970 return;
971
972 cmd->scan_begin_arg = ns;
973 }
974
975 static int labpc_ai_cmdtest(struct comedi_device *dev,
976 struct comedi_subdevice *s, struct comedi_cmd *cmd)
977 {
978 int err = 0;
979 int tmp, tmp2;
980 int stop_mask;
981
982 /* step 1: make sure trigger sources are trivially valid */
983
984 tmp = cmd->start_src;
985 cmd->start_src &= TRIG_NOW | TRIG_EXT;
986 if (!cmd->start_src || tmp != cmd->start_src)
987 err++;
988
989 tmp = cmd->scan_begin_src;
990 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT;
991 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
992 err++;
993
994 tmp = cmd->convert_src;
995 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
996 if (!cmd->convert_src || tmp != cmd->convert_src)
997 err++;
998
999 tmp = cmd->scan_end_src;
1000 cmd->scan_end_src &= TRIG_COUNT;
1001 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1002 err++;
1003
1004 tmp = cmd->stop_src;
1005 stop_mask = TRIG_COUNT | TRIG_NONE;
1006 if (thisboard->register_layout == labpc_1200_layout)
1007 stop_mask |= TRIG_EXT;
1008 cmd->stop_src &= stop_mask;
1009 if (!cmd->stop_src || tmp != cmd->stop_src)
1010 err++;
1011
1012 if (err)
1013 return 1;
1014
1015 /* step 2: make sure trigger sources are unique and mutually compatible */
1016
1017 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
1018 err++;
1019 if (cmd->scan_begin_src != TRIG_TIMER &&
1020 cmd->scan_begin_src != TRIG_FOLLOW &&
1021 cmd->scan_begin_src != TRIG_EXT)
1022 err++;
1023 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
1024 err++;
1025 if (cmd->stop_src != TRIG_COUNT &&
1026 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE)
1027 err++;
1028
1029 /* can't have external stop and start triggers at once */
1030 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
1031 err++;
1032
1033 if (err)
1034 return 2;
1035
1036 /* step 3: make sure arguments are trivially compatible */
1037
1038 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) {
1039 cmd->start_arg = 0;
1040 err++;
1041 }
1042
1043 if (!cmd->chanlist_len)
1044 err++;
1045
1046 if (cmd->scan_end_arg != cmd->chanlist_len) {
1047 cmd->scan_end_arg = cmd->chanlist_len;
1048 err++;
1049 }
1050
1051 if (cmd->convert_src == TRIG_TIMER) {
1052 if (cmd->convert_arg < thisboard->ai_speed) {
1053 cmd->convert_arg = thisboard->ai_speed;
1054 err++;
1055 }
1056 }
1057 /* make sure scan timing is not too fast */
1058 if (cmd->scan_begin_src == TRIG_TIMER) {
1059 if (cmd->convert_src == TRIG_TIMER &&
1060 cmd->scan_begin_arg <
1061 cmd->convert_arg * cmd->chanlist_len) {
1062 cmd->scan_begin_arg =
1063 cmd->convert_arg * cmd->chanlist_len;
1064 err++;
1065 }
1066 if (cmd->scan_begin_arg <
1067 thisboard->ai_speed * cmd->chanlist_len) {
1068 cmd->scan_begin_arg =
1069 thisboard->ai_speed * cmd->chanlist_len;
1070 err++;
1071 }
1072 }
1073 /* stop source */
1074 switch (cmd->stop_src) {
1075 case TRIG_COUNT:
1076 if (!cmd->stop_arg) {
1077 cmd->stop_arg = 1;
1078 err++;
1079 }
1080 break;
1081 case TRIG_NONE:
1082 if (cmd->stop_arg != 0) {
1083 cmd->stop_arg = 0;
1084 err++;
1085 }
1086 break;
1087 /*
1088 * TRIG_EXT doesn't care since it doesn't
1089 * trigger off a numbered channel
1090 */
1091 default:
1092 break;
1093 }
1094
1095 if (err)
1096 return 3;
1097
1098 /* step 4: fix up any arguments */
1099
1100 tmp = cmd->convert_arg;
1101 tmp2 = cmd->scan_begin_arg;
1102 labpc_adc_timing(dev, cmd);
1103 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
1104 err++;
1105
1106 if (err)
1107 return 4;
1108
1109 if (labpc_ai_chanlist_invalid(dev, cmd))
1110 return 5;
1111
1112 return 0;
1113 }
1114
1115 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1116 {
1117 int channel, range, aref;
1118 #ifdef CONFIG_ISA_DMA_API
1119 unsigned long irq_flags;
1120 #endif
1121 int ret;
1122 struct comedi_async *async = s->async;
1123 struct comedi_cmd *cmd = &async->cmd;
1124 enum transfer_type xfer;
1125 unsigned long flags;
1126
1127 if (!dev->irq) {
1128 comedi_error(dev, "no irq assigned, cannot perform command");
1129 return -1;
1130 }
1131
1132 range = CR_RANGE(cmd->chanlist[0]);
1133 aref = CR_AREF(cmd->chanlist[0]);
1134
1135 /* make sure board is disabled before setting up acquisition */
1136 spin_lock_irqsave(&dev->spinlock, flags);
1137 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1138 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1139 spin_unlock_irqrestore(&dev->spinlock, flags);
1140
1141 devpriv->command3_bits = 0;
1142 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1143
1144 /* initialize software conversion count */
1145 if (cmd->stop_src == TRIG_COUNT)
1146 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
1147
1148 /* setup hardware conversion counter */
1149 if (cmd->stop_src == TRIG_EXT) {
1150 /*
1151 * load counter a1 with count of 3
1152 * (pc+ manual says this is minimum allowed) using mode 0
1153 */
1154 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1155 1, 3, 0);
1156 if (ret < 0) {
1157 comedi_error(dev, "error loading counter a1");
1158 return -1;
1159 }
1160 } else /*
1161 * otherwise, just put a1 in mode 0
1162 * with no count to set its output low
1163 */
1164 devpriv->write_byte(INIT_A1_BITS,
1165 dev->iobase + COUNTER_A_CONTROL_REG);
1166
1167 #ifdef CONFIG_ISA_DMA_API
1168 /* figure out what method we will use to transfer data */
1169 if (devpriv->dma_chan && /* need a dma channel allocated */
1170 /*
1171 * dma unsafe at RT priority,
1172 * and too much setup time for TRIG_WAKE_EOS for
1173 */
1174 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
1175 /* only available on the isa boards */
1176 thisboard->bustype == isa_bustype) {
1177 xfer = isa_dma_transfer;
1178 /* pc-plus has no fifo-half full interrupt */
1179 } else
1180 #endif
1181 if (thisboard->register_layout == labpc_1200_layout &&
1182 /* wake-end-of-scan should interrupt on fifo not empty */
1183 (cmd->flags & TRIG_WAKE_EOS) == 0 &&
1184 /* make sure we are taking more than just a few points */
1185 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
1186 xfer = fifo_half_full_transfer;
1187 } else
1188 xfer = fifo_not_empty_transfer;
1189 devpriv->current_transfer = xfer;
1190
1191 /* setup command6 register for 1200 boards */
1192 if (thisboard->register_layout == labpc_1200_layout) {
1193 /* reference inputs to ground or common? */
1194 if (aref != AREF_GROUND)
1195 devpriv->command6_bits |= ADC_COMMON_BIT;
1196 else
1197 devpriv->command6_bits &= ~ADC_COMMON_BIT;
1198 /* bipolar or unipolar range? */
1199 if (thisboard->ai_range_is_unipolar[range])
1200 devpriv->command6_bits |= ADC_UNIP_BIT;
1201 else
1202 devpriv->command6_bits &= ~ADC_UNIP_BIT;
1203 /* interrupt on fifo half full? */
1204 if (xfer == fifo_half_full_transfer)
1205 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT;
1206 else
1207 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1208 /* enable interrupt on counter a1 terminal count? */
1209 if (cmd->stop_src == TRIG_EXT)
1210 devpriv->command6_bits |= A1_INTR_EN_BIT;
1211 else
1212 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1213 /* are we scanning up or down through channels? */
1214 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1215 devpriv->command6_bits |= ADC_SCAN_UP_BIT;
1216 else
1217 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT;
1218 /* write to register */
1219 devpriv->write_byte(devpriv->command6_bits,
1220 dev->iobase + COMMAND6_REG);
1221 }
1222
1223 /* setup channel list, etc (command1 register) */
1224 devpriv->command1_bits = 0;
1225 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1226 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
1227 else
1228 channel = CR_CHAN(cmd->chanlist[0]);
1229 /* munge channel bits for differential / scan disabled mode */
1230 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF)
1231 channel *= 2;
1232 devpriv->command1_bits |= ADC_CHAN_BITS(channel);
1233 devpriv->command1_bits |= thisboard->ai_range_code[range];
1234 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1235 /* manual says to set scan enable bit on second pass */
1236 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP ||
1237 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) {
1238 devpriv->command1_bits |= ADC_SCAN_EN_BIT;
1239 /* need a brief delay before enabling scan, or scan
1240 * list will get screwed when you switch
1241 * between scan up to scan down mode - dunno why */
1242 udelay(1);
1243 devpriv->write_byte(devpriv->command1_bits,
1244 dev->iobase + COMMAND1_REG);
1245 }
1246 /* setup any external triggering/pacing (command4 register) */
1247 devpriv->command4_bits = 0;
1248 if (cmd->convert_src != TRIG_EXT)
1249 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1250 /* XXX should discard first scan when using interval scanning
1251 * since manual says it is not synced with scan clock */
1252 if (labpc_use_continuous_mode(cmd) == 0) {
1253 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT;
1254 if (cmd->scan_begin_src == TRIG_EXT)
1255 devpriv->command4_bits |= EXT_SCAN_EN_BIT;
1256 }
1257 /* single-ended/differential */
1258 if (aref == AREF_DIFF)
1259 devpriv->command4_bits |= ADC_DIFF_BIT;
1260 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1261
1262 devpriv->write_byte(cmd->chanlist_len,
1263 dev->iobase + INTERVAL_COUNT_REG);
1264 /* load count */
1265 devpriv->write_byte(INTERVAL_LOAD_BITS,
1266 dev->iobase + INTERVAL_LOAD_REG);
1267
1268 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) {
1269 /* set up pacing */
1270 labpc_adc_timing(dev, cmd);
1271 /* load counter b0 in mode 3 */
1272 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1273 0, devpriv->divisor_b0, 3);
1274 if (ret < 0) {
1275 comedi_error(dev, "error loading counter b0");
1276 return -1;
1277 }
1278 }
1279 /* set up conversion pacing */
1280 if (labpc_ai_convert_period(cmd)) {
1281 /* load counter a0 in mode 2 */
1282 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1283 0, devpriv->divisor_a0, 2);
1284 if (ret < 0) {
1285 comedi_error(dev, "error loading counter a0");
1286 return -1;
1287 }
1288 } else
1289 devpriv->write_byte(INIT_A0_BITS,
1290 dev->iobase + COUNTER_A_CONTROL_REG);
1291
1292 /* set up scan pacing */
1293 if (labpc_ai_scan_period(cmd)) {
1294 /* load counter b1 in mode 2 */
1295 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1296 1, devpriv->divisor_b1, 2);
1297 if (ret < 0) {
1298 comedi_error(dev, "error loading counter b1");
1299 return -1;
1300 }
1301 }
1302
1303 labpc_clear_adc_fifo(dev);
1304
1305 #ifdef CONFIG_ISA_DMA_API
1306 /* set up dma transfer */
1307 if (xfer == isa_dma_transfer) {
1308 irq_flags = claim_dma_lock();
1309 disable_dma(devpriv->dma_chan);
1310 /* clear flip-flop to make sure 2-byte registers for
1311 * count and address get set correctly */
1312 clear_dma_ff(devpriv->dma_chan);
1313 set_dma_addr(devpriv->dma_chan,
1314 virt_to_bus(devpriv->dma_buffer));
1315 /* set appropriate size of transfer */
1316 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd);
1317 if (cmd->stop_src == TRIG_COUNT &&
1318 devpriv->count * sample_size < devpriv->dma_transfer_size) {
1319 devpriv->dma_transfer_size =
1320 devpriv->count * sample_size;
1321 }
1322 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1323 enable_dma(devpriv->dma_chan);
1324 release_dma_lock(irq_flags);
1325 /* enable board's dma */
1326 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT;
1327 } else
1328 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT;
1329 #endif
1330
1331 /* enable error interrupts */
1332 devpriv->command3_bits |= ERR_INTR_EN_BIT;
1333 /* enable fifo not empty interrupt? */
1334 if (xfer == fifo_not_empty_transfer)
1335 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT;
1336 else
1337 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT;
1338 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1339
1340 /* startup acquisition */
1341
1342 /* command2 reg */
1343 /* use 2 cascaded counters for pacing */
1344 spin_lock_irqsave(&dev->spinlock, flags);
1345 devpriv->command2_bits |= CASCADE_BIT;
1346 switch (cmd->start_src) {
1347 case TRIG_EXT:
1348 devpriv->command2_bits |= HWTRIG_BIT;
1349 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT;
1350 break;
1351 case TRIG_NOW:
1352 devpriv->command2_bits |= SWTRIG_BIT;
1353 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT;
1354 break;
1355 default:
1356 comedi_error(dev, "bug with start_src");
1357 spin_unlock_irqrestore(&dev->spinlock, flags);
1358 return -1;
1359 break;
1360 }
1361 switch (cmd->stop_src) {
1362 case TRIG_EXT:
1363 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT;
1364 break;
1365 case TRIG_COUNT:
1366 case TRIG_NONE:
1367 break;
1368 default:
1369 comedi_error(dev, "bug with stop_src");
1370 spin_unlock_irqrestore(&dev->spinlock, flags);
1371 return -1;
1372 }
1373 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1374 spin_unlock_irqrestore(&dev->spinlock, flags);
1375
1376 return 0;
1377 }
1378
1379 /* interrupt service routine */
1380 static irqreturn_t labpc_interrupt(int irq, void *d)
1381 {
1382 struct comedi_device *dev = d;
1383 struct comedi_subdevice *s = dev->read_subdev;
1384 struct comedi_async *async;
1385 struct comedi_cmd *cmd;
1386
1387 if (dev->attached == 0) {
1388 comedi_error(dev, "premature interrupt");
1389 return IRQ_HANDLED;
1390 }
1391
1392 async = s->async;
1393 cmd = &async->cmd;
1394 async->events = 0;
1395
1396 /* read board status */
1397 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1398 if (thisboard->register_layout == labpc_1200_layout)
1399 devpriv->status2_bits =
1400 devpriv->read_byte(dev->iobase + STATUS2_REG);
1401
1402 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT |
1403 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0
1404 && (devpriv->status2_bits & A1_TC_BIT) == 0
1405 && (devpriv->status2_bits & FNHF_BIT)) {
1406 return IRQ_NONE;
1407 }
1408
1409 if (devpriv->status1_bits & OVERRUN_BIT) {
1410 /* clear error interrupt */
1411 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1412 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1413 comedi_event(dev, s);
1414 comedi_error(dev, "overrun");
1415 return IRQ_HANDLED;
1416 }
1417
1418 #ifdef CONFIG_ISA_DMA_API
1419 if (devpriv->current_transfer == isa_dma_transfer) {
1420 /*
1421 * if a dma terminal count of external stop trigger
1422 * has occurred
1423 */
1424 if (devpriv->status1_bits & DMATC_BIT ||
1425 (thisboard->register_layout == labpc_1200_layout
1426 && devpriv->status2_bits & A1_TC_BIT)) {
1427 handle_isa_dma(dev);
1428 }
1429 } else
1430 #endif
1431 labpc_drain_fifo(dev);
1432
1433 if (devpriv->status1_bits & TIMER_BIT) {
1434 comedi_error(dev, "handled timer interrupt?");
1435 /* clear it */
1436 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1437 }
1438
1439 if (devpriv->status1_bits & OVERFLOW_BIT) {
1440 /* clear error interrupt */
1441 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1442 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1443 comedi_event(dev, s);
1444 comedi_error(dev, "overflow");
1445 return IRQ_HANDLED;
1446 }
1447 /* handle external stop trigger */
1448 if (cmd->stop_src == TRIG_EXT) {
1449 if (devpriv->status2_bits & A1_TC_BIT) {
1450 labpc_drain_dregs(dev);
1451 labpc_cancel(dev, s);
1452 async->events |= COMEDI_CB_EOA;
1453 }
1454 }
1455
1456 /* TRIG_COUNT end of acquisition */
1457 if (cmd->stop_src == TRIG_COUNT) {
1458 if (devpriv->count == 0) {
1459 labpc_cancel(dev, s);
1460 async->events |= COMEDI_CB_EOA;
1461 }
1462 }
1463
1464 comedi_event(dev, s);
1465 return IRQ_HANDLED;
1466 }
1467
1468 /* read all available samples from ai fifo */
1469 static int labpc_drain_fifo(struct comedi_device *dev)
1470 {
1471 unsigned int lsb, msb;
1472 short data;
1473 struct comedi_async *async = dev->read_subdev->async;
1474 const int timeout = 10000;
1475 unsigned int i;
1476
1477 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1478
1479 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout;
1480 i++) {
1481 /* quit if we have all the data we want */
1482 if (async->cmd.stop_src == TRIG_COUNT) {
1483 if (devpriv->count == 0)
1484 break;
1485 devpriv->count--;
1486 }
1487 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1488 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1489 data = (msb << 8) | lsb;
1490 cfc_write_to_buffer(dev->read_subdev, data);
1491 devpriv->status1_bits =
1492 devpriv->read_byte(dev->iobase + STATUS1_REG);
1493 }
1494 if (i == timeout) {
1495 comedi_error(dev, "ai timeout, fifo never empties");
1496 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1497 return -1;
1498 }
1499
1500 return 0;
1501 }
1502
1503 #ifdef CONFIG_ISA_DMA_API
1504 static void labpc_drain_dma(struct comedi_device *dev)
1505 {
1506 struct comedi_subdevice *s = dev->read_subdev;
1507 struct comedi_async *async = s->async;
1508 int status;
1509 unsigned long flags;
1510 unsigned int max_points, num_points, residue, leftover;
1511 int i;
1512
1513 status = devpriv->status1_bits;
1514
1515 flags = claim_dma_lock();
1516 disable_dma(devpriv->dma_chan);
1517 /* clear flip-flop to make sure 2-byte registers for
1518 * count and address get set correctly */
1519 clear_dma_ff(devpriv->dma_chan);
1520
1521 /* figure out how many points to read */
1522 max_points = devpriv->dma_transfer_size / sample_size;
1523 /* residue is the number of points left to be done on the dma
1524 * transfer. It should always be zero at this point unless
1525 * the stop_src is set to external triggering.
1526 */
1527 residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1528 num_points = max_points - residue;
1529 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1530 num_points = devpriv->count;
1531
1532 /* figure out how many points will be stored next time */
1533 leftover = 0;
1534 if (async->cmd.stop_src != TRIG_COUNT) {
1535 leftover = devpriv->dma_transfer_size / sample_size;
1536 } else if (devpriv->count > num_points) {
1537 leftover = devpriv->count - num_points;
1538 if (leftover > max_points)
1539 leftover = max_points;
1540 }
1541
1542 /* write data to comedi buffer */
1543 for (i = 0; i < num_points; i++)
1544 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
1545
1546 if (async->cmd.stop_src == TRIG_COUNT)
1547 devpriv->count -= num_points;
1548
1549 /* set address and count for next transfer */
1550 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1551 set_dma_count(devpriv->dma_chan, leftover * sample_size);
1552 release_dma_lock(flags);
1553
1554 async->events |= COMEDI_CB_BLOCK;
1555 }
1556
1557 static void handle_isa_dma(struct comedi_device *dev)
1558 {
1559 labpc_drain_dma(dev);
1560
1561 enable_dma(devpriv->dma_chan);
1562
1563 /* clear dma tc interrupt */
1564 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1565 }
1566 #endif
1567
1568 /* makes sure all data acquired by board is transferred to comedi (used
1569 * when acquisition is terminated by stop_src == TRIG_EXT). */
1570 static void labpc_drain_dregs(struct comedi_device *dev)
1571 {
1572 #ifdef CONFIG_ISA_DMA_API
1573 if (devpriv->current_transfer == isa_dma_transfer)
1574 labpc_drain_dma(dev);
1575 #endif
1576
1577 labpc_drain_fifo(dev);
1578 }
1579
1580 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1581 struct comedi_insn *insn, unsigned int *data)
1582 {
1583 int i, n;
1584 int chan, range;
1585 int lsb, msb;
1586 int timeout = 1000;
1587 unsigned long flags;
1588
1589 /* disable timed conversions */
1590 spin_lock_irqsave(&dev->spinlock, flags);
1591 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1592 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1593 spin_unlock_irqrestore(&dev->spinlock, flags);
1594
1595 /* disable interrupt generation and dma */
1596 devpriv->command3_bits = 0;
1597 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1598
1599 /* set gain and channel */
1600 devpriv->command1_bits = 0;
1601 chan = CR_CHAN(insn->chanspec);
1602 range = CR_RANGE(insn->chanspec);
1603 devpriv->command1_bits |= thisboard->ai_range_code[range];
1604 /* munge channel bits for differential/scan disabled mode */
1605 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1606 chan *= 2;
1607 devpriv->command1_bits |= ADC_CHAN_BITS(chan);
1608 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1609
1610 /* setup command6 register for 1200 boards */
1611 if (thisboard->register_layout == labpc_1200_layout) {
1612 /* reference inputs to ground or common? */
1613 if (CR_AREF(insn->chanspec) != AREF_GROUND)
1614 devpriv->command6_bits |= ADC_COMMON_BIT;
1615 else
1616 devpriv->command6_bits &= ~ADC_COMMON_BIT;
1617 /* bipolar or unipolar range? */
1618 if (thisboard->ai_range_is_unipolar[range])
1619 devpriv->command6_bits |= ADC_UNIP_BIT;
1620 else
1621 devpriv->command6_bits &= ~ADC_UNIP_BIT;
1622 /* don't interrupt on fifo half full */
1623 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1624 /* don't enable interrupt on counter a1 terminal count? */
1625 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1626 /* write to register */
1627 devpriv->write_byte(devpriv->command6_bits,
1628 dev->iobase + COMMAND6_REG);
1629 }
1630 /* setup command4 register */
1631 devpriv->command4_bits = 0;
1632 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1633 /* single-ended/differential */
1634 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1635 devpriv->command4_bits |= ADC_DIFF_BIT;
1636 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1637
1638 /*
1639 * initialize pacer counter output to make sure it doesn't
1640 * cause any problems
1641 */
1642 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG);
1643
1644 labpc_clear_adc_fifo(dev);
1645
1646 for (n = 0; n < insn->n; n++) {
1647 /* trigger conversion */
1648 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG);
1649
1650 for (i = 0; i < timeout; i++) {
1651 if (devpriv->read_byte(dev->iobase +
1652 STATUS1_REG) & DATA_AVAIL_BIT)
1653 break;
1654 udelay(1);
1655 }
1656 if (i == timeout) {
1657 comedi_error(dev, "timeout");
1658 return -ETIME;
1659 }
1660 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1661 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1662 data[n] = (msb << 8) | lsb;
1663 }
1664
1665 return n;
1666 }
1667
1668 /* analog output insn */
1669 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1670 struct comedi_insn *insn, unsigned int *data)
1671 {
1672 int channel, range;
1673 unsigned long flags;
1674 int lsb, msb;
1675
1676 channel = CR_CHAN(insn->chanspec);
1677
1678 /* turn off pacing of analog output channel */
1679 /* note: hardware bug in daqcard-1200 means pacing cannot
1680 * be independently enabled/disabled for its the two channels */
1681 spin_lock_irqsave(&dev->spinlock, flags);
1682 devpriv->command2_bits &= ~DAC_PACED_BIT(channel);
1683 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1684 spin_unlock_irqrestore(&dev->spinlock, flags);
1685
1686 /* set range */
1687 if (thisboard->register_layout == labpc_1200_layout) {
1688 range = CR_RANGE(insn->chanspec);
1689 if (range & AO_RANGE_IS_UNIPOLAR)
1690 devpriv->command6_bits |= DAC_UNIP_BIT(channel);
1691 else
1692 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel);
1693 /* write to register */
1694 devpriv->write_byte(devpriv->command6_bits,
1695 dev->iobase + COMMAND6_REG);
1696 }
1697 /* send data */
1698 lsb = data[0] & 0xff;
1699 msb = (data[0] >> 8) & 0xff;
1700 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1701 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1702
1703 /* remember value for readback */
1704 devpriv->ao_value[channel] = data[0];
1705
1706 return 1;
1707 }
1708
1709 /* analog output readback insn */
1710 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1711 struct comedi_insn *insn, unsigned int *data)
1712 {
1713 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1714
1715 return 1;
1716 }
1717
1718 static int labpc_calib_read_insn(struct comedi_device *dev,
1719 struct comedi_subdevice *s,
1720 struct comedi_insn *insn, unsigned int *data)
1721 {
1722 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)];
1723
1724 return 1;
1725 }
1726
1727 static int labpc_calib_write_insn(struct comedi_device *dev,
1728 struct comedi_subdevice *s,
1729 struct comedi_insn *insn, unsigned int *data)
1730 {
1731 int channel = CR_CHAN(insn->chanspec);
1732
1733 write_caldac(dev, channel, data[0]);
1734 return 1;
1735 }
1736
1737 static int labpc_eeprom_read_insn(struct comedi_device *dev,
1738 struct comedi_subdevice *s,
1739 struct comedi_insn *insn, unsigned int *data)
1740 {
1741 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)];
1742
1743 return 1;
1744 }
1745
1746 static int labpc_eeprom_write_insn(struct comedi_device *dev,
1747 struct comedi_subdevice *s,
1748 struct comedi_insn *insn, unsigned int *data)
1749 {
1750 int channel = CR_CHAN(insn->chanspec);
1751 int ret;
1752
1753 /* only allow writes to user area of eeprom */
1754 if (channel < 16 || channel > 127) {
1755 dev_dbg(dev->class_dev,
1756 "eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)\n");
1757 return -EINVAL;
1758 }
1759
1760 ret = labpc_eeprom_write(dev, channel, data[0]);
1761 if (ret < 0)
1762 return ret;
1763
1764 return 1;
1765 }
1766
1767 #ifdef CONFIG_ISA_DMA_API
1768 /* utility function that suggests a dma transfer size in bytes */
1769 static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd)
1770 {
1771 unsigned int size;
1772 unsigned int freq;
1773
1774 if (cmd.convert_src == TRIG_TIMER)
1775 freq = 1000000000 / cmd.convert_arg;
1776 /* return some default value */
1777 else
1778 freq = 0xffffffff;
1779
1780 /* make buffer fill in no more than 1/3 second */
1781 size = (freq / 3) * sample_size;
1782
1783 /* set a minimum and maximum size allowed */
1784 if (size > dma_buffer_size)
1785 size = dma_buffer_size - dma_buffer_size % sample_size;
1786 else if (size < sample_size)
1787 size = sample_size;
1788
1789 return size;
1790 }
1791 #endif
1792
1793 /* figures out what counter values to use based on command */
1794 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
1795 {
1796 /* max value for 16 bit counter in mode 2 */
1797 const int max_counter_value = 0x10000;
1798 /* min value for 16 bit counter in mode 2 */
1799 const int min_counter_value = 2;
1800 unsigned int base_period;
1801
1802 /*
1803 * if both convert and scan triggers are TRIG_TIMER, then they
1804 * both rely on counter b0
1805 */
1806 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) {
1807 /*
1808 * pick the lowest b0 divisor value we can (for maximum input
1809 * clock speed on convert and scan counters)
1810 */
1811 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) /
1812 (LABPC_TIMER_BASE * max_counter_value) + 1;
1813 if (devpriv->divisor_b0 < min_counter_value)
1814 devpriv->divisor_b0 = min_counter_value;
1815 if (devpriv->divisor_b0 > max_counter_value)
1816 devpriv->divisor_b0 = max_counter_value;
1817
1818 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
1819
1820 /* set a0 for conversion frequency and b1 for scan frequency */
1821 switch (cmd->flags & TRIG_ROUND_MASK) {
1822 default:
1823 case TRIG_ROUND_NEAREST:
1824 devpriv->divisor_a0 =
1825 (labpc_ai_convert_period(cmd) +
1826 (base_period / 2)) / base_period;
1827 devpriv->divisor_b1 =
1828 (labpc_ai_scan_period(cmd) +
1829 (base_period / 2)) / base_period;
1830 break;
1831 case TRIG_ROUND_UP:
1832 devpriv->divisor_a0 =
1833 (labpc_ai_convert_period(cmd) + (base_period -
1834 1)) / base_period;
1835 devpriv->divisor_b1 =
1836 (labpc_ai_scan_period(cmd) + (base_period -
1837 1)) / base_period;
1838 break;
1839 case TRIG_ROUND_DOWN:
1840 devpriv->divisor_a0 =
1841 labpc_ai_convert_period(cmd) / base_period;
1842 devpriv->divisor_b1 =
1843 labpc_ai_scan_period(cmd) / base_period;
1844 break;
1845 }
1846 /* make sure a0 and b1 values are acceptable */
1847 if (devpriv->divisor_a0 < min_counter_value)
1848 devpriv->divisor_a0 = min_counter_value;
1849 if (devpriv->divisor_a0 > max_counter_value)
1850 devpriv->divisor_a0 = max_counter_value;
1851 if (devpriv->divisor_b1 < min_counter_value)
1852 devpriv->divisor_b1 = min_counter_value;
1853 if (devpriv->divisor_b1 > max_counter_value)
1854 devpriv->divisor_b1 = max_counter_value;
1855 /* write corrected timings to command */
1856 labpc_set_ai_convert_period(cmd,
1857 base_period * devpriv->divisor_a0);
1858 labpc_set_ai_scan_period(cmd,
1859 base_period * devpriv->divisor_b1);
1860 /*
1861 * if only one TRIG_TIMER is used, we can employ the generic
1862 * cascaded timing functions
1863 */
1864 } else if (labpc_ai_scan_period(cmd)) {
1865 unsigned int scan_period;
1866
1867 scan_period = labpc_ai_scan_period(cmd);
1868 /*
1869 * calculate cascaded counter values
1870 * that give desired scan timing
1871 */
1872 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1873 &(devpriv->divisor_b1),
1874 &(devpriv->divisor_b0),
1875 &scan_period,
1876 cmd->flags & TRIG_ROUND_MASK);
1877 labpc_set_ai_scan_period(cmd, scan_period);
1878 } else if (labpc_ai_convert_period(cmd)) {
1879 unsigned int convert_period;
1880
1881 convert_period = labpc_ai_convert_period(cmd);
1882 /*
1883 * calculate cascaded counter values
1884 * that give desired conversion timing
1885 */
1886 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1887 &(devpriv->divisor_a0),
1888 &(devpriv->divisor_b0),
1889 &convert_period,
1890 cmd->flags & TRIG_ROUND_MASK);
1891 labpc_set_ai_convert_period(cmd, convert_period);
1892 }
1893 }
1894
1895 static int labpc_dio_mem_callback(int dir, int port, int data,
1896 unsigned long iobase)
1897 {
1898 if (dir) {
1899 writeb(data, (void __iomem *)(iobase + port));
1900 return 0;
1901 } else {
1902 return readb((void __iomem *)(iobase + port));
1903 }
1904 }
1905
1906 /* lowlevel write to eeprom/dac */
1907 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
1908 unsigned int value_width)
1909 {
1910 int i;
1911
1912 for (i = 1; i <= value_width; i++) {
1913 /* clear serial clock */
1914 devpriv->command5_bits &= ~SCLOCK_BIT;
1915 /* send bits most significant bit first */
1916 if (value & (1 << (value_width - i)))
1917 devpriv->command5_bits |= SDATA_BIT;
1918 else
1919 devpriv->command5_bits &= ~SDATA_BIT;
1920 udelay(1);
1921 devpriv->write_byte(devpriv->command5_bits,
1922 dev->iobase + COMMAND5_REG);
1923 /* set clock to load bit */
1924 devpriv->command5_bits |= SCLOCK_BIT;
1925 udelay(1);
1926 devpriv->write_byte(devpriv->command5_bits,
1927 dev->iobase + COMMAND5_REG);
1928 }
1929 }
1930
1931 /* lowlevel read from eeprom */
1932 static unsigned int labpc_serial_in(struct comedi_device *dev)
1933 {
1934 unsigned int value = 0;
1935 int i;
1936 const int value_width = 8; /* number of bits wide values are */
1937
1938 for (i = 1; i <= value_width; i++) {
1939 /* set serial clock */
1940 devpriv->command5_bits |= SCLOCK_BIT;
1941 udelay(1);
1942 devpriv->write_byte(devpriv->command5_bits,
1943 dev->iobase + COMMAND5_REG);
1944 /* clear clock bit */
1945 devpriv->command5_bits &= ~SCLOCK_BIT;
1946 udelay(1);
1947 devpriv->write_byte(devpriv->command5_bits,
1948 dev->iobase + COMMAND5_REG);
1949 /* read bits most significant bit first */
1950 udelay(1);
1951 devpriv->status2_bits =
1952 devpriv->read_byte(dev->iobase + STATUS2_REG);
1953 if (devpriv->status2_bits & EEPROM_OUT_BIT)
1954 value |= 1 << (value_width - i);
1955 }
1956
1957 return value;
1958 }
1959
1960 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
1961 unsigned int address)
1962 {
1963 unsigned int value;
1964 /* bits to tell eeprom to expect a read */
1965 const int read_instruction = 0x3;
1966 /* 8 bit write lengths to eeprom */
1967 const int write_length = 8;
1968
1969 /* enable read/write to eeprom */
1970 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1971 udelay(1);
1972 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1973 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1974 udelay(1);
1975 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1976
1977 /* send read instruction */
1978 labpc_serial_out(dev, read_instruction, write_length);
1979 /* send 8 bit address to read from */
1980 labpc_serial_out(dev, address, write_length);
1981 /* read result */
1982 value = labpc_serial_in(dev);
1983
1984 /* disable read/write to eeprom */
1985 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1986 udelay(1);
1987 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1988
1989 return value;
1990 }
1991
1992 static int labpc_eeprom_write(struct comedi_device *dev,
1993 unsigned int address, unsigned int value)
1994 {
1995 const int write_enable_instruction = 0x6;
1996 const int write_instruction = 0x2;
1997 const int write_length = 8; /* 8 bit write lengths to eeprom */
1998 const int write_in_progress_bit = 0x1;
1999 const int timeout = 10000;
2000 int i;
2001
2002 /* make sure there isn't already a write in progress */
2003 for (i = 0; i < timeout; i++) {
2004 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
2005 0)
2006 break;
2007 }
2008 if (i == timeout) {
2009 comedi_error(dev, "eeprom write timed out");
2010 return -ETIME;
2011 }
2012 /* update software copy of eeprom */
2013 devpriv->eeprom_data[address] = value;
2014
2015 /* enable read/write to eeprom */
2016 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2017 udelay(1);
2018 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2019 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2020 udelay(1);
2021 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2022
2023 /* send write_enable instruction */
2024 labpc_serial_out(dev, write_enable_instruction, write_length);
2025 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2026 udelay(1);
2027 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2028
2029 /* send write instruction */
2030 devpriv->command5_bits |= EEPROM_EN_BIT;
2031 udelay(1);
2032 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2033 labpc_serial_out(dev, write_instruction, write_length);
2034 /* send 8 bit address to write to */
2035 labpc_serial_out(dev, address, write_length);
2036 /* write value */
2037 labpc_serial_out(dev, value, write_length);
2038 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2039 udelay(1);
2040 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2041
2042 /* disable read/write to eeprom */
2043 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2044 udelay(1);
2045 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2046
2047 return 0;
2048 }
2049
2050 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev)
2051 {
2052 unsigned int value;
2053 const int read_status_instruction = 0x5;
2054 const int write_length = 8; /* 8 bit write lengths to eeprom */
2055
2056 /* enable read/write to eeprom */
2057 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2058 udelay(1);
2059 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2060 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2061 udelay(1);
2062 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2063
2064 /* send read status instruction */
2065 labpc_serial_out(dev, read_status_instruction, write_length);
2066 /* read result */
2067 value = labpc_serial_in(dev);
2068
2069 /* disable read/write to eeprom */
2070 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2071 udelay(1);
2072 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2073
2074 return value;
2075 }
2076
2077 /* writes to 8 bit calibration dacs */
2078 static void write_caldac(struct comedi_device *dev, unsigned int channel,
2079 unsigned int value)
2080 {
2081 if (value == devpriv->caldac[channel])
2082 return;
2083 devpriv->caldac[channel] = value;
2084
2085 /* clear caldac load bit and make sure we don't write to eeprom */
2086 devpriv->command5_bits &=
2087 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2088 udelay(1);
2089 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2090
2091 /* write 4 bit channel */
2092 labpc_serial_out(dev, channel, 4);
2093 /* write 8 bit caldac value */
2094 labpc_serial_out(dev, value, 8);
2095
2096 /* set and clear caldac bit to load caldac value */
2097 devpriv->command5_bits |= CALDAC_LOAD_BIT;
2098 udelay(1);
2099 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2100 devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
2101 udelay(1);
2102 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2103 }
2104
2105 static struct comedi_driver labpc_driver = {
2106 .driver_name = DRV_NAME,
2107 .module = THIS_MODULE,
2108 .attach = labpc_attach,
2109 .attach_pci = labpc_attach_pci,
2110 .detach = labpc_common_detach,
2111 .num_names = ARRAY_SIZE(labpc_boards),
2112 .board_name = &labpc_boards[0].name,
2113 .offset = sizeof(struct labpc_board_struct),
2114 };
2115
2116 #ifdef CONFIG_COMEDI_PCI_DRIVERS
2117 static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = {
2118 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161)},
2119 {0}
2120 };
2121 MODULE_DEVICE_TABLE(pci, labpc_pci_table);
2122
2123 static int __devinit labpc_pci_probe(struct pci_dev *dev,
2124 const struct pci_device_id *ent)
2125 {
2126 return comedi_pci_auto_config(dev, &labpc_driver);
2127 }
2128
2129 static void __devexit labpc_pci_remove(struct pci_dev *dev)
2130 {
2131 comedi_pci_auto_unconfig(dev);
2132 }
2133
2134 static struct pci_driver labpc_pci_driver = {
2135 .name = DRV_NAME,
2136 .id_table = labpc_pci_table,
2137 .probe = labpc_pci_probe,
2138 .remove = __devexit_p(labpc_pci_remove)
2139 };
2140 module_comedi_pci_driver(labpc_driver, labpc_pci_driver);
2141 #else
2142 module_comedi_driver(labpc_driver);
2143 #endif
2144
2145
2146 MODULE_AUTHOR("Comedi http://www.comedi.org");
2147 MODULE_DESCRIPTION("Comedi low-level driver");
2148 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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