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staging: comedi: remove inline alloc_private()
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_mio_common.c
1 /*
2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22
23 */
24
25 /*
26 This file is meant to be included by another file, e.g.,
27 ni_atmio.c or ni_pcimio.c.
28
29 Interrupt support originally added by Truxton Fulton
30 <trux@truxton.com>
31
32 References (from ftp://ftp.natinst.com/support/manuals):
33
34 340747b.pdf AT-MIO E series Register Level Programmer Manual
35 341079b.pdf PCI E Series RLPM
36 340934b.pdf DAQ-STC reference manual
37 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
38 release_ni611x.pdf
39 release_ni67xx.pdf
40 Other possibly relevant info:
41
42 320517c.pdf User manual (obsolete)
43 320517f.pdf User manual (new)
44 320889a.pdf delete
45 320906c.pdf maximum signal ratings
46 321066a.pdf about 16x
47 321791a.pdf discontinuation of at-mio-16e-10 rev. c
48 321808a.pdf about at-mio-16e-10 rev P
49 321837a.pdf discontinuation of at-mio-16de-10 rev d
50 321838a.pdf about at-mio-16de-10 rev N
51
52 ISSUES:
53
54 - the interrupt routine needs to be cleaned up
55
56 2006-02-07: S-Series PCI-6143: Support has been added but is not
57 fully tested as yet. Terry Barnaby, BEAM Ltd.
58 */
59
60 /* #define DEBUG_INTERRUPT */
61 /* #define DEBUG_STATUS_A */
62 /* #define DEBUG_STATUS_B */
63
64 #include <linux/interrupt.h>
65 #include <linux/sched.h>
66 #include "8255.h"
67 #include "mite.h"
68 #include "comedi_fc.h"
69
70 #ifndef MDPRINTK
71 #define MDPRINTK(format, args...)
72 #endif
73
74 /* A timeout count */
75 #define NI_TIMEOUT 1000
76 static const unsigned old_RTSI_clock_channel = 7;
77
78 /* Note: this table must match the ai_gain_* definitions */
79 static const short ni_gainlkup[][16] = {
80 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
81 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
82 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
83 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
84 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
85 [ai_gain_4] = {0, 1, 4, 7},
86 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
87 0x003, 0x004, 0x005, 0x006},
88 [ai_gain_622x] = {0, 1, 4, 5},
89 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
90 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
91 };
92
93 static const struct comedi_lrange range_ni_E_ai = { 16, {
94 RANGE(-10, 10),
95 RANGE(-5, 5),
96 RANGE(-2.5, 2.5),
97 RANGE(-1, 1),
98 RANGE(-0.5, 0.5),
99 RANGE(-0.25, 0.25),
100 RANGE(-0.1, 0.1),
101 RANGE(-0.05, 0.05),
102 RANGE(0, 20),
103 RANGE(0, 10),
104 RANGE(0, 5),
105 RANGE(0, 2),
106 RANGE(0, 1),
107 RANGE(0, 0.5),
108 RANGE(0, 0.2),
109 RANGE(0, 0.1),
110 }
111 };
112
113 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
114 RANGE(-10, 10),
115 RANGE(-5, 5),
116 RANGE(-1, 1),
117 RANGE(-0.1,
118 0.1),
119 RANGE(0, 10),
120 RANGE(0, 5),
121 RANGE(0, 1),
122 RANGE(0, 0.1),
123 }
124 };
125
126 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
127 RANGE(-10,
128 10),
129 RANGE(-5, 5),
130 RANGE(-2, 2),
131 RANGE(-1, 1),
132 RANGE(-0.5,
133 0.5),
134 RANGE(-0.2,
135 0.2),
136 RANGE(-0.1,
137 0.1),
138 RANGE(0, 10),
139 RANGE(0, 5),
140 RANGE(0, 2),
141 RANGE(0, 1),
142 RANGE(0,
143 0.5),
144 RANGE(0,
145 0.2),
146 RANGE(0,
147 0.1),
148 }
149 };
150
151 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
152 RANGE(-10, 10),
153 RANGE(-5, 5),
154 RANGE(-0.5,
155 0.5),
156 RANGE(-0.05,
157 0.05),
158 }
159 };
160
161 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
162 RANGE(-50, 50),
163 RANGE(-20, 20),
164 RANGE(-10, 10),
165 RANGE(-5, 5),
166 RANGE(-2, 2),
167 RANGE(-1, 1),
168 RANGE(-0.5, 0.5),
169 RANGE(-0.2, 0.2),
170 }
171 };
172
173 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
174 RANGE(-10, 10),
175 RANGE(-5, 5),
176 RANGE(-1, 1),
177 RANGE(-0.2, 0.2),
178 }
179 };
180
181 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
182 RANGE(-10, 10),
183 RANGE(-5, 5),
184 RANGE(-2, 2),
185 RANGE(-1, 1),
186 RANGE(-0.5, 0.5),
187 RANGE(-0.2, 0.2),
188 RANGE(-0.1, 0.1),
189 }
190 };
191
192 static const struct comedi_lrange range_ni_S_ai_6143 = { 1, {
193 RANGE(-5, +5),
194 }
195 };
196
197 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
198 RANGE(-10, 10),
199 RANGE(0, 10),
200 RANGE_ext(-1, 1),
201 RANGE_ext(0, 1),
202 }
203 };
204
205 static const struct comedi_lrange *const ni_range_lkup[] = {
206 [ai_gain_16] = &range_ni_E_ai,
207 [ai_gain_8] = &range_ni_E_ai_limited,
208 [ai_gain_14] = &range_ni_E_ai_limited14,
209 [ai_gain_4] = &range_ni_E_ai_bipolar4,
210 [ai_gain_611x] = &range_ni_E_ai_611x,
211 [ai_gain_622x] = &range_ni_M_ai_622x,
212 [ai_gain_628x] = &range_ni_M_ai_628x,
213 [ai_gain_6143] = &range_ni_S_ai_6143
214 };
215
216 static int ni_dio_insn_config(struct comedi_device *dev,
217 struct comedi_subdevice *s,
218 struct comedi_insn *insn, unsigned int *data);
219 static int ni_dio_insn_bits(struct comedi_device *dev,
220 struct comedi_subdevice *s,
221 struct comedi_insn *insn, unsigned int *data);
222 static int ni_cdio_cmdtest(struct comedi_device *dev,
223 struct comedi_subdevice *s, struct comedi_cmd *cmd);
224 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
225 static int ni_cdio_cancel(struct comedi_device *dev,
226 struct comedi_subdevice *s);
227 static void handle_cdio_interrupt(struct comedi_device *dev);
228 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
229 unsigned int trignum);
230
231 static int ni_serial_insn_config(struct comedi_device *dev,
232 struct comedi_subdevice *s,
233 struct comedi_insn *insn, unsigned int *data);
234 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
235 struct comedi_subdevice *s,
236 unsigned char data_out,
237 unsigned char *data_in);
238 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
239 struct comedi_subdevice *s,
240 unsigned char data_out,
241 unsigned char *data_in);
242
243 static int ni_calib_insn_read(struct comedi_device *dev,
244 struct comedi_subdevice *s,
245 struct comedi_insn *insn, unsigned int *data);
246 static int ni_calib_insn_write(struct comedi_device *dev,
247 struct comedi_subdevice *s,
248 struct comedi_insn *insn, unsigned int *data);
249
250 static int ni_eeprom_insn_read(struct comedi_device *dev,
251 struct comedi_subdevice *s,
252 struct comedi_insn *insn, unsigned int *data);
253 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
254 struct comedi_subdevice *s,
255 struct comedi_insn *insn,
256 unsigned int *data);
257
258 static int ni_pfi_insn_bits(struct comedi_device *dev,
259 struct comedi_subdevice *s,
260 struct comedi_insn *insn, unsigned int *data);
261 static int ni_pfi_insn_config(struct comedi_device *dev,
262 struct comedi_subdevice *s,
263 struct comedi_insn *insn, unsigned int *data);
264 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
265 unsigned chan);
266
267 static void ni_rtsi_init(struct comedi_device *dev);
268 static int ni_rtsi_insn_bits(struct comedi_device *dev,
269 struct comedi_subdevice *s,
270 struct comedi_insn *insn, unsigned int *data);
271 static int ni_rtsi_insn_config(struct comedi_device *dev,
272 struct comedi_subdevice *s,
273 struct comedi_insn *insn, unsigned int *data);
274
275 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
276 static int ni_read_eeprom(struct comedi_device *dev, int addr);
277
278 #ifdef DEBUG_STATUS_A
279 static void ni_mio_print_status_a(int status);
280 #else
281 #define ni_mio_print_status_a(a)
282 #endif
283 #ifdef DEBUG_STATUS_B
284 static void ni_mio_print_status_b(int status);
285 #else
286 #define ni_mio_print_status_b(a)
287 #endif
288
289 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
290 #ifndef PCIDMA
291 static void ni_handle_fifo_half_full(struct comedi_device *dev);
292 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
293 struct comedi_subdevice *s);
294 #endif
295 static void ni_handle_fifo_dregs(struct comedi_device *dev);
296 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
297 unsigned int trignum);
298 static void ni_load_channelgain_list(struct comedi_device *dev,
299 unsigned int n_chan, unsigned int *list);
300 static void shutdown_ai_command(struct comedi_device *dev);
301
302 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
303 unsigned int trignum);
304
305 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
306
307 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
308
309 static int ni_gpct_insn_write(struct comedi_device *dev,
310 struct comedi_subdevice *s,
311 struct comedi_insn *insn, unsigned int *data);
312 static int ni_gpct_insn_read(struct comedi_device *dev,
313 struct comedi_subdevice *s,
314 struct comedi_insn *insn, unsigned int *data);
315 static int ni_gpct_insn_config(struct comedi_device *dev,
316 struct comedi_subdevice *s,
317 struct comedi_insn *insn, unsigned int *data);
318 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
319 static int ni_gpct_cmdtest(struct comedi_device *dev,
320 struct comedi_subdevice *s, struct comedi_cmd *cmd);
321 static int ni_gpct_cancel(struct comedi_device *dev,
322 struct comedi_subdevice *s);
323 static void handle_gpct_interrupt(struct comedi_device *dev,
324 unsigned short counter_index);
325
326 static int init_cs5529(struct comedi_device *dev);
327 static int cs5529_do_conversion(struct comedi_device *dev,
328 unsigned short *data);
329 static int cs5529_ai_insn_read(struct comedi_device *dev,
330 struct comedi_subdevice *s,
331 struct comedi_insn *insn, unsigned int *data);
332 #ifdef NI_CS5529_DEBUG
333 static unsigned int cs5529_config_read(struct comedi_device *dev,
334 unsigned int reg_select_bits);
335 #endif
336 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
337 unsigned int reg_select_bits);
338
339 static int ni_m_series_pwm_config(struct comedi_device *dev,
340 struct comedi_subdevice *s,
341 struct comedi_insn *insn, unsigned int *data);
342 static int ni_6143_pwm_config(struct comedi_device *dev,
343 struct comedi_subdevice *s,
344 struct comedi_insn *insn, unsigned int *data);
345
346 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
347 unsigned period_ns);
348 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
349 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
350
351 enum aimodes {
352 AIMODE_NONE = 0,
353 AIMODE_HALF_FULL = 1,
354 AIMODE_SCAN = 2,
355 AIMODE_SAMPLE = 3,
356 };
357
358 enum ni_common_subdevices {
359 NI_AI_SUBDEV,
360 NI_AO_SUBDEV,
361 NI_DIO_SUBDEV,
362 NI_8255_DIO_SUBDEV,
363 NI_UNUSED_SUBDEV,
364 NI_CALIBRATION_SUBDEV,
365 NI_EEPROM_SUBDEV,
366 NI_PFI_DIO_SUBDEV,
367 NI_CS5529_CALIBRATION_SUBDEV,
368 NI_SERIAL_SUBDEV,
369 NI_RTSI_SUBDEV,
370 NI_GPCT0_SUBDEV,
371 NI_GPCT1_SUBDEV,
372 NI_FREQ_OUT_SUBDEV,
373 NI_NUM_SUBDEVICES
374 };
375 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
376 {
377 switch (counter_index) {
378 case 0:
379 return NI_GPCT0_SUBDEV;
380 break;
381 case 1:
382 return NI_GPCT1_SUBDEV;
383 break;
384 default:
385 break;
386 }
387 BUG();
388 return NI_GPCT0_SUBDEV;
389 }
390
391 enum timebase_nanoseconds {
392 TIMEBASE_1_NS = 50,
393 TIMEBASE_2_NS = 10000
394 };
395
396 #define SERIAL_DISABLED 0
397 #define SERIAL_600NS 600
398 #define SERIAL_1_2US 1200
399 #define SERIAL_10US 10000
400
401 static const int num_adc_stages_611x = 3;
402
403 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
404 unsigned ai_mite_status);
405 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
406 unsigned ao_mite_status);
407 static void get_last_sample_611x(struct comedi_device *dev);
408 static void get_last_sample_6143(struct comedi_device *dev);
409
410 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
411 unsigned bit_mask, unsigned bit_values)
412 {
413 struct ni_private *devpriv = dev->private;
414 unsigned long flags;
415
416 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
417 switch (reg) {
418 case Interrupt_A_Enable_Register:
419 devpriv->int_a_enable_reg &= ~bit_mask;
420 devpriv->int_a_enable_reg |= bit_values & bit_mask;
421 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
422 Interrupt_A_Enable_Register);
423 break;
424 case Interrupt_B_Enable_Register:
425 devpriv->int_b_enable_reg &= ~bit_mask;
426 devpriv->int_b_enable_reg |= bit_values & bit_mask;
427 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
428 Interrupt_B_Enable_Register);
429 break;
430 case IO_Bidirection_Pin_Register:
431 devpriv->io_bidirection_pin_reg &= ~bit_mask;
432 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
433 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
434 IO_Bidirection_Pin_Register);
435 break;
436 case AI_AO_Select:
437 devpriv->ai_ao_select_reg &= ~bit_mask;
438 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
439 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
440 break;
441 case G0_G1_Select:
442 devpriv->g0_g1_select_reg &= ~bit_mask;
443 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
444 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
445 break;
446 default:
447 printk("Warning %s() called with invalid register\n", __func__);
448 printk("reg is %d\n", reg);
449 break;
450 }
451 mmiowb();
452 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
453 }
454
455 #ifdef PCIDMA
456 static int ni_ai_drain_dma(struct comedi_device *dev);
457
458 /* DMA channel setup */
459
460 /* negative channel means no channel */
461 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
462 {
463 unsigned bitfield;
464
465 if (channel >= 0) {
466 bitfield =
467 (ni_stc_dma_channel_select_bitfield(channel) <<
468 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
469 } else {
470 bitfield = 0;
471 }
472 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
473 }
474
475 /* negative channel means no channel */
476 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
477 {
478 unsigned bitfield;
479
480 if (channel >= 0) {
481 bitfield =
482 (ni_stc_dma_channel_select_bitfield(channel) <<
483 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
484 } else {
485 bitfield = 0;
486 }
487 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
488 }
489
490 /* negative mite_channel means no channel */
491 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
492 unsigned gpct_index,
493 int mite_channel)
494 {
495 unsigned bitfield;
496
497 if (mite_channel >= 0) {
498 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
499 } else {
500 bitfield = 0;
501 }
502 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
503 bitfield);
504 }
505
506 /* negative mite_channel means no channel */
507 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
508 int mite_channel)
509 {
510 struct ni_private *devpriv = dev->private;
511 unsigned long flags;
512
513 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
514 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
515 if (mite_channel >= 0) {
516 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
517 under the assumption the cdio dma selection works just like ai/ao/gpct.
518 Definitely works for dma channels 0 and 1. */
519 devpriv->cdio_dma_select_reg |=
520 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
521 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
522 }
523 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
524 mmiowb();
525 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
526 }
527
528 static int ni_request_ai_mite_channel(struct comedi_device *dev)
529 {
530 struct ni_private *devpriv = dev->private;
531 unsigned long flags;
532
533 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
534 BUG_ON(devpriv->ai_mite_chan);
535 devpriv->ai_mite_chan =
536 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
537 if (devpriv->ai_mite_chan == NULL) {
538 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
539 comedi_error(dev,
540 "failed to reserve mite dma channel for analog input.");
541 return -EBUSY;
542 }
543 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
544 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
545 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
546 return 0;
547 }
548
549 static int ni_request_ao_mite_channel(struct comedi_device *dev)
550 {
551 struct ni_private *devpriv = dev->private;
552 unsigned long flags;
553
554 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
555 BUG_ON(devpriv->ao_mite_chan);
556 devpriv->ao_mite_chan =
557 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
558 if (devpriv->ao_mite_chan == NULL) {
559 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
560 comedi_error(dev,
561 "failed to reserve mite dma channel for analog outut.");
562 return -EBUSY;
563 }
564 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
565 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
566 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
567 return 0;
568 }
569
570 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
571 unsigned gpct_index,
572 enum comedi_io_direction direction)
573 {
574 struct ni_private *devpriv = dev->private;
575 unsigned long flags;
576 struct mite_channel *mite_chan;
577
578 BUG_ON(gpct_index >= NUM_GPCT);
579 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
580 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
581 mite_chan =
582 mite_request_channel(devpriv->mite,
583 devpriv->gpct_mite_ring[gpct_index]);
584 if (mite_chan == NULL) {
585 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
586 comedi_error(dev,
587 "failed to reserve mite dma channel for counter.");
588 return -EBUSY;
589 }
590 mite_chan->dir = direction;
591 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
592 mite_chan);
593 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
594 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
595 return 0;
596 }
597
598 #endif /* PCIDMA */
599
600 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
601 {
602 #ifdef PCIDMA
603 struct ni_private *devpriv = dev->private;
604 unsigned long flags;
605
606 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
607 BUG_ON(devpriv->cdo_mite_chan);
608 devpriv->cdo_mite_chan =
609 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
610 if (devpriv->cdo_mite_chan == NULL) {
611 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
612 comedi_error(dev,
613 "failed to reserve mite dma channel for correlated digital outut.");
614 return -EBUSY;
615 }
616 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
617 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
618 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
619 #endif /* PCIDMA */
620 return 0;
621 }
622
623 static void ni_release_ai_mite_channel(struct comedi_device *dev)
624 {
625 #ifdef PCIDMA
626 struct ni_private *devpriv = dev->private;
627 unsigned long flags;
628
629 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
630 if (devpriv->ai_mite_chan) {
631 ni_set_ai_dma_channel(dev, -1);
632 mite_release_channel(devpriv->ai_mite_chan);
633 devpriv->ai_mite_chan = NULL;
634 }
635 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
636 #endif /* PCIDMA */
637 }
638
639 static void ni_release_ao_mite_channel(struct comedi_device *dev)
640 {
641 #ifdef PCIDMA
642 struct ni_private *devpriv = dev->private;
643 unsigned long flags;
644
645 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
646 if (devpriv->ao_mite_chan) {
647 ni_set_ao_dma_channel(dev, -1);
648 mite_release_channel(devpriv->ao_mite_chan);
649 devpriv->ao_mite_chan = NULL;
650 }
651 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
652 #endif /* PCIDMA */
653 }
654
655 #ifdef PCIDMA
656 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
657 unsigned gpct_index)
658 {
659 struct ni_private *devpriv = dev->private;
660 unsigned long flags;
661
662 BUG_ON(gpct_index >= NUM_GPCT);
663 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
664 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
665 struct mite_channel *mite_chan =
666 devpriv->counter_dev->counters[gpct_index].mite_chan;
667
668 ni_set_gpct_dma_channel(dev, gpct_index, -1);
669 ni_tio_set_mite_channel(&devpriv->
670 counter_dev->counters[gpct_index],
671 NULL);
672 mite_release_channel(mite_chan);
673 }
674 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
675 }
676 #endif /* PCIDMA */
677
678 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
679 {
680 #ifdef PCIDMA
681 struct ni_private *devpriv = dev->private;
682 unsigned long flags;
683
684 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
685 if (devpriv->cdo_mite_chan) {
686 ni_set_cdo_dma_channel(dev, -1);
687 mite_release_channel(devpriv->cdo_mite_chan);
688 devpriv->cdo_mite_chan = NULL;
689 }
690 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
691 #endif /* PCIDMA */
692 }
693
694 /* e-series boards use the second irq signals to generate dma requests for their counters */
695 #ifdef PCIDMA
696 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
697 unsigned gpct_index, short enable)
698 {
699 struct ni_private *devpriv = dev->private;
700
701 if (boardtype.reg_type & ni_reg_m_series_mask)
702 return;
703 switch (gpct_index) {
704 case 0:
705 if (enable) {
706 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
707 Second_IRQ_A_Enable_Register);
708 } else {
709 devpriv->stc_writew(dev, 0,
710 Second_IRQ_A_Enable_Register);
711 }
712 break;
713 case 1:
714 if (enable) {
715 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
716 Second_IRQ_B_Enable_Register);
717 } else {
718 devpriv->stc_writew(dev, 0,
719 Second_IRQ_B_Enable_Register);
720 }
721 break;
722 default:
723 BUG();
724 break;
725 }
726 }
727 #endif /* PCIDMA */
728
729 static void ni_clear_ai_fifo(struct comedi_device *dev)
730 {
731 struct ni_private *devpriv = dev->private;
732
733 if (boardtype.reg_type == ni_reg_6143) {
734 /* Flush the 6143 data FIFO */
735 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */
736 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */
737 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */
738 } else {
739 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
740 if (boardtype.reg_type == ni_reg_625x) {
741 ni_writeb(0, M_Offset_Static_AI_Control(0));
742 ni_writeb(1, M_Offset_Static_AI_Control(0));
743 #if 0
744 /* the NI example code does 3 convert pulses for 625x boards,
745 but that appears to be wrong in practice. */
746 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
747 AI_Command_1_Register);
748 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
749 AI_Command_1_Register);
750 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
751 AI_Command_1_Register);
752 #endif
753 }
754 }
755 }
756
757 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
758 {
759 struct ni_private *devpriv = dev->private;
760
761 devpriv->stc_writew(dev, data >> 16, reg);
762 devpriv->stc_writew(dev, data & 0xffff, reg + 1);
763 }
764
765 static uint32_t win_in2(struct comedi_device *dev, int reg)
766 {
767 struct ni_private *devpriv = dev->private;
768 uint32_t bits;
769
770 bits = devpriv->stc_readw(dev, reg) << 16;
771 bits |= devpriv->stc_readw(dev, reg + 1);
772 return bits;
773 }
774
775 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
776 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
777 int addr)
778 {
779 struct ni_private *devpriv = dev->private;
780 unsigned long flags;
781
782 spin_lock_irqsave(&devpriv->window_lock, flags);
783 ni_writew(addr, AO_Window_Address_611x);
784 ni_writew(data, AO_Window_Data_611x);
785 spin_unlock_irqrestore(&devpriv->window_lock, flags);
786 }
787
788 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
789 int addr)
790 {
791 struct ni_private *devpriv = dev->private;
792 unsigned long flags;
793
794 spin_lock_irqsave(&devpriv->window_lock, flags);
795 ni_writew(addr, AO_Window_Address_611x);
796 ni_writel(data, AO_Window_Data_611x);
797 spin_unlock_irqrestore(&devpriv->window_lock, flags);
798 }
799
800 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
801 {
802 struct ni_private *devpriv = dev->private;
803 unsigned long flags;
804 unsigned short data;
805
806 spin_lock_irqsave(&devpriv->window_lock, flags);
807 ni_writew(addr, AO_Window_Address_611x);
808 data = ni_readw(AO_Window_Data_611x);
809 spin_unlock_irqrestore(&devpriv->window_lock, flags);
810 return data;
811 }
812
813 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
814 * share registers (such as Interrupt_A_Register) without interfering with
815 * each other.
816 *
817 * NOTE: the switch/case statements are optimized out for a constant argument
818 * so this is actually quite fast--- If you must wrap another function around this
819 * make it inline to avoid a large speed penalty.
820 *
821 * value should only be 1 or 0.
822 */
823 static inline void ni_set_bits(struct comedi_device *dev, int reg,
824 unsigned bits, unsigned value)
825 {
826 unsigned bit_values;
827
828 if (value)
829 bit_values = bits;
830 else
831 bit_values = 0;
832 ni_set_bitfield(dev, reg, bits, bit_values);
833 }
834
835 static irqreturn_t ni_E_interrupt(int irq, void *d)
836 {
837 struct comedi_device *dev = d;
838 struct ni_private *devpriv = dev->private;
839 unsigned short a_status;
840 unsigned short b_status;
841 unsigned int ai_mite_status = 0;
842 unsigned int ao_mite_status = 0;
843 unsigned long flags;
844 #ifdef PCIDMA
845 struct mite_struct *mite = devpriv->mite;
846 #endif
847
848 if (dev->attached == 0)
849 return IRQ_NONE;
850 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
851
852 /* lock to avoid race with comedi_poll */
853 spin_lock_irqsave(&dev->spinlock, flags);
854 a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
855 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
856 #ifdef PCIDMA
857 if (mite) {
858 unsigned long flags_too;
859
860 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
861 if (devpriv->ai_mite_chan) {
862 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
863 if (ai_mite_status & CHSR_LINKC)
864 writel(CHOR_CLRLC,
865 devpriv->mite->mite_io_addr +
866 MITE_CHOR(devpriv->
867 ai_mite_chan->channel));
868 }
869 if (devpriv->ao_mite_chan) {
870 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
871 if (ao_mite_status & CHSR_LINKC)
872 writel(CHOR_CLRLC,
873 mite->mite_io_addr +
874 MITE_CHOR(devpriv->
875 ao_mite_chan->channel));
876 }
877 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
878 }
879 #endif
880 ack_a_interrupt(dev, a_status);
881 ack_b_interrupt(dev, b_status);
882 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
883 handle_a_interrupt(dev, a_status, ai_mite_status);
884 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
885 handle_b_interrupt(dev, b_status, ao_mite_status);
886 handle_gpct_interrupt(dev, 0);
887 handle_gpct_interrupt(dev, 1);
888 handle_cdio_interrupt(dev);
889
890 spin_unlock_irqrestore(&dev->spinlock, flags);
891 return IRQ_HANDLED;
892 }
893
894 #ifdef PCIDMA
895 static void ni_sync_ai_dma(struct comedi_device *dev)
896 {
897 struct ni_private *devpriv = dev->private;
898 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
899 unsigned long flags;
900
901 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
902 if (devpriv->ai_mite_chan)
903 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
904 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
905 }
906
907 static void mite_handle_b_linkc(struct mite_struct *mite,
908 struct comedi_device *dev)
909 {
910 struct ni_private *devpriv = dev->private;
911 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
912 unsigned long flags;
913
914 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
915 if (devpriv->ao_mite_chan) {
916 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
917 }
918 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
919 }
920
921 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
922 {
923 struct ni_private *devpriv = dev->private;
924 static const int timeout = 10000;
925 int i;
926 for (i = 0; i < timeout; i++) {
927 unsigned short b_status;
928
929 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
930 if (b_status & AO_FIFO_Half_Full_St)
931 break;
932 /* if we poll too often, the pci bus activity seems
933 to slow the dma transfer down */
934 udelay(10);
935 }
936 if (i == timeout) {
937 comedi_error(dev, "timed out waiting for dma load");
938 return -EPIPE;
939 }
940 return 0;
941 }
942
943 #endif /* PCIDMA */
944 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
945 {
946 struct ni_private *devpriv = dev->private;
947
948 if (devpriv->aimode == AIMODE_SCAN) {
949 #ifdef PCIDMA
950 static const int timeout = 10;
951 int i;
952
953 for (i = 0; i < timeout; i++) {
954 ni_sync_ai_dma(dev);
955 if ((s->async->events & COMEDI_CB_EOS))
956 break;
957 udelay(1);
958 }
959 #else
960 ni_handle_fifo_dregs(dev);
961 s->async->events |= COMEDI_CB_EOS;
962 #endif
963 }
964 /* handle special case of single scan using AI_End_On_End_Of_Scan */
965 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
966 shutdown_ai_command(dev);
967 }
968 }
969
970 static void shutdown_ai_command(struct comedi_device *dev)
971 {
972 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
973
974 #ifdef PCIDMA
975 ni_ai_drain_dma(dev);
976 #endif
977 ni_handle_fifo_dregs(dev);
978 get_last_sample_611x(dev);
979 get_last_sample_6143(dev);
980
981 s->async->events |= COMEDI_CB_EOA;
982 }
983
984 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
985 {
986 if (s->
987 async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
988 COMEDI_CB_EOA)) {
989 switch (s - dev->subdevices) {
990 case NI_AI_SUBDEV:
991 ni_ai_reset(dev, s);
992 break;
993 case NI_AO_SUBDEV:
994 ni_ao_reset(dev, s);
995 break;
996 case NI_GPCT0_SUBDEV:
997 case NI_GPCT1_SUBDEV:
998 ni_gpct_cancel(dev, s);
999 break;
1000 case NI_DIO_SUBDEV:
1001 ni_cdio_cancel(dev, s);
1002 break;
1003 default:
1004 break;
1005 }
1006 }
1007 comedi_event(dev, s);
1008 }
1009
1010 static void handle_gpct_interrupt(struct comedi_device *dev,
1011 unsigned short counter_index)
1012 {
1013 #ifdef PCIDMA
1014 struct ni_private *devpriv = dev->private;
1015 struct comedi_subdevice *s;
1016
1017 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1018
1019 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1020 s);
1021 if (s->async->events)
1022 ni_event(dev, s);
1023 #endif
1024 }
1025
1026 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1027 {
1028 struct ni_private *devpriv = dev->private;
1029 unsigned short ack = 0;
1030
1031 if (a_status & AI_SC_TC_St) {
1032 ack |= AI_SC_TC_Interrupt_Ack;
1033 }
1034 if (a_status & AI_START1_St) {
1035 ack |= AI_START1_Interrupt_Ack;
1036 }
1037 if (a_status & AI_START_St) {
1038 ack |= AI_START_Interrupt_Ack;
1039 }
1040 if (a_status & AI_STOP_St) {
1041 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1042 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1043 }
1044 if (ack)
1045 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1046 }
1047
1048 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1049 unsigned ai_mite_status)
1050 {
1051 struct ni_private *devpriv = dev->private;
1052 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1053
1054 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1055 if (s->type == COMEDI_SUBD_UNUSED)
1056 return;
1057
1058 #ifdef DEBUG_INTERRUPT
1059 printk
1060 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1061 status, ai_mite_status);
1062 ni_mio_print_status_a(status);
1063 #endif
1064 #ifdef PCIDMA
1065 if (ai_mite_status & CHSR_LINKC) {
1066 ni_sync_ai_dma(dev);
1067 }
1068
1069 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1070 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1071 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1072 printk
1073 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1074 ai_mite_status);
1075 /* mite_print_chsr(ai_mite_status); */
1076 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1077 /* disable_irq(dev->irq); */
1078 }
1079 #endif
1080
1081 /* test for all uncommon interrupt events at the same time */
1082 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1083 AI_SC_TC_St | AI_START1_St)) {
1084 if (status == 0xffff) {
1085 printk
1086 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1087 /* we probably aren't even running a command now,
1088 * so it's a good idea to be careful. */
1089 if (comedi_get_subdevice_runflags(s) & SRF_RUNNING) {
1090 s->async->events |=
1091 COMEDI_CB_ERROR | COMEDI_CB_EOA;
1092 ni_event(dev, s);
1093 }
1094 return;
1095 }
1096 if (status & (AI_Overrun_St | AI_Overflow_St |
1097 AI_SC_TC_Error_St)) {
1098 printk("ni_mio_common: ai error a_status=%04x\n",
1099 status);
1100 ni_mio_print_status_a(status);
1101
1102 shutdown_ai_command(dev);
1103
1104 s->async->events |= COMEDI_CB_ERROR;
1105 if (status & (AI_Overrun_St | AI_Overflow_St))
1106 s->async->events |= COMEDI_CB_OVERFLOW;
1107
1108 ni_event(dev, s);
1109
1110 return;
1111 }
1112 if (status & AI_SC_TC_St) {
1113 #ifdef DEBUG_INTERRUPT
1114 printk("ni_mio_common: SC_TC interrupt\n");
1115 #endif
1116 if (!devpriv->ai_continuous) {
1117 shutdown_ai_command(dev);
1118 }
1119 }
1120 }
1121 #ifndef PCIDMA
1122 if (status & AI_FIFO_Half_Full_St) {
1123 int i;
1124 static const int timeout = 10;
1125 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1126 *fail to get the fifo less than half full, so loop to be sure.*/
1127 for (i = 0; i < timeout; ++i) {
1128 ni_handle_fifo_half_full(dev);
1129 if ((devpriv->stc_readw(dev,
1130 AI_Status_1_Register) &
1131 AI_FIFO_Half_Full_St) == 0)
1132 break;
1133 }
1134 }
1135 #endif /* !PCIDMA */
1136
1137 if ((status & AI_STOP_St)) {
1138 ni_handle_eos(dev, s);
1139 }
1140
1141 ni_event(dev, s);
1142
1143 #ifdef DEBUG_INTERRUPT
1144 status = devpriv->stc_readw(dev, AI_Status_1_Register);
1145 if (status & Interrupt_A_St) {
1146 printk
1147 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1148 status);
1149 }
1150 #endif
1151 }
1152
1153 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1154 {
1155 struct ni_private *devpriv = dev->private;
1156 unsigned short ack = 0;
1157
1158 if (b_status & AO_BC_TC_St) {
1159 ack |= AO_BC_TC_Interrupt_Ack;
1160 }
1161 if (b_status & AO_Overrun_St) {
1162 ack |= AO_Error_Interrupt_Ack;
1163 }
1164 if (b_status & AO_START_St) {
1165 ack |= AO_START_Interrupt_Ack;
1166 }
1167 if (b_status & AO_START1_St) {
1168 ack |= AO_START1_Interrupt_Ack;
1169 }
1170 if (b_status & AO_UC_TC_St) {
1171 ack |= AO_UC_TC_Interrupt_Ack;
1172 }
1173 if (b_status & AO_UI2_TC_St) {
1174 ack |= AO_UI2_TC_Interrupt_Ack;
1175 }
1176 if (b_status & AO_UPDATE_St) {
1177 ack |= AO_UPDATE_Interrupt_Ack;
1178 }
1179 if (ack)
1180 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1181 }
1182
1183 static void handle_b_interrupt(struct comedi_device *dev,
1184 unsigned short b_status, unsigned ao_mite_status)
1185 {
1186 struct ni_private *devpriv = dev->private;
1187 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1188 /* unsigned short ack=0; */
1189
1190 #ifdef DEBUG_INTERRUPT
1191 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1192 b_status, ao_mite_status);
1193 ni_mio_print_status_b(b_status);
1194 #endif
1195
1196 #ifdef PCIDMA
1197 /* Currently, mite.c requires us to handle LINKC */
1198 if (ao_mite_status & CHSR_LINKC) {
1199 mite_handle_b_linkc(devpriv->mite, dev);
1200 }
1201
1202 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1203 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1204 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1205 printk
1206 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1207 ao_mite_status);
1208 /* mite_print_chsr(ao_mite_status); */
1209 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1210 }
1211 #endif
1212
1213 if (b_status == 0xffff)
1214 return;
1215 if (b_status & AO_Overrun_St) {
1216 printk
1217 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1218 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1219 s->async->events |= COMEDI_CB_OVERFLOW;
1220 }
1221
1222 if (b_status & AO_BC_TC_St) {
1223 MDPRINTK
1224 ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1225 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1226 s->async->events |= COMEDI_CB_EOA;
1227 }
1228 #ifndef PCIDMA
1229 if (b_status & AO_FIFO_Request_St) {
1230 int ret;
1231
1232 ret = ni_ao_fifo_half_empty(dev, s);
1233 if (!ret) {
1234 printk("ni_mio_common: AO buffer underrun\n");
1235 ni_set_bits(dev, Interrupt_B_Enable_Register,
1236 AO_FIFO_Interrupt_Enable |
1237 AO_Error_Interrupt_Enable, 0);
1238 s->async->events |= COMEDI_CB_OVERFLOW;
1239 }
1240 }
1241 #endif
1242
1243 ni_event(dev, s);
1244 }
1245
1246 #ifdef DEBUG_STATUS_A
1247 static const char *const status_a_strings[] = {
1248 "passthru0", "fifo", "G0_gate", "G0_TC",
1249 "stop", "start", "sc_tc", "start1",
1250 "start2", "sc_tc_error", "overflow", "overrun",
1251 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1252 };
1253
1254 static void ni_mio_print_status_a(int status)
1255 {
1256 int i;
1257
1258 printk("A status:");
1259 for (i = 15; i >= 0; i--) {
1260 if (status & (1 << i)) {
1261 printk(" %s", status_a_strings[i]);
1262 }
1263 }
1264 printk("\n");
1265 }
1266 #endif
1267
1268 #ifdef DEBUG_STATUS_B
1269 static const char *const status_b_strings[] = {
1270 "passthru1", "fifo", "G1_gate", "G1_TC",
1271 "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1272 "start1", "overrun", "start", "bc_tc_error",
1273 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1274 };
1275
1276 static void ni_mio_print_status_b(int status)
1277 {
1278 int i;
1279
1280 printk("B status:");
1281 for (i = 15; i >= 0; i--) {
1282 if (status & (1 << i)) {
1283 printk(" %s", status_b_strings[i]);
1284 }
1285 }
1286 printk("\n");
1287 }
1288 #endif
1289
1290 #ifndef PCIDMA
1291
1292 static void ni_ao_fifo_load(struct comedi_device *dev,
1293 struct comedi_subdevice *s, int n)
1294 {
1295 struct comedi_async *async = s->async;
1296 struct comedi_cmd *cmd = &async->cmd;
1297 int chan;
1298 int i;
1299 short d;
1300 u32 packed_data;
1301 int range;
1302 int err = 1;
1303
1304 chan = async->cur_chan;
1305 for (i = 0; i < n; i++) {
1306 err &= comedi_buf_get(async, &d);
1307 if (err == 0)
1308 break;
1309
1310 range = CR_RANGE(cmd->chanlist[chan]);
1311
1312 if (boardtype.reg_type & ni_reg_6xxx_mask) {
1313 packed_data = d & 0xffff;
1314 /* 6711 only has 16 bit wide ao fifo */
1315 if (boardtype.reg_type != ni_reg_6711) {
1316 err &= comedi_buf_get(async, &d);
1317 if (err == 0)
1318 break;
1319 chan++;
1320 i++;
1321 packed_data |= (d << 16) & 0xffff0000;
1322 }
1323 ni_writel(packed_data, DAC_FIFO_Data_611x);
1324 } else {
1325 ni_writew(d, DAC_FIFO_Data);
1326 }
1327 chan++;
1328 chan %= cmd->chanlist_len;
1329 }
1330 async->cur_chan = chan;
1331 if (err == 0) {
1332 async->events |= COMEDI_CB_OVERFLOW;
1333 }
1334 }
1335
1336 /*
1337 * There's a small problem if the FIFO gets really low and we
1338 * don't have the data to fill it. Basically, if after we fill
1339 * the FIFO with all the data available, the FIFO is _still_
1340 * less than half full, we never clear the interrupt. If the
1341 * IRQ is in edge mode, we never get another interrupt, because
1342 * this one wasn't cleared. If in level mode, we get flooded
1343 * with interrupts that we can't fulfill, because nothing ever
1344 * gets put into the buffer.
1345 *
1346 * This kind of situation is recoverable, but it is easier to
1347 * just pretend we had a FIFO underrun, since there is a good
1348 * chance it will happen anyway. This is _not_ the case for
1349 * RT code, as RT code might purposely be running close to the
1350 * metal. Needs to be fixed eventually.
1351 */
1352 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1353 struct comedi_subdevice *s)
1354 {
1355 int n;
1356
1357 n = comedi_buf_read_n_available(s->async);
1358 if (n == 0) {
1359 s->async->events |= COMEDI_CB_OVERFLOW;
1360 return 0;
1361 }
1362
1363 n /= sizeof(short);
1364 if (n > boardtype.ao_fifo_depth / 2)
1365 n = boardtype.ao_fifo_depth / 2;
1366
1367 ni_ao_fifo_load(dev, s, n);
1368
1369 s->async->events |= COMEDI_CB_BLOCK;
1370
1371 return 1;
1372 }
1373
1374 static int ni_ao_prep_fifo(struct comedi_device *dev,
1375 struct comedi_subdevice *s)
1376 {
1377 struct ni_private *devpriv = dev->private;
1378 int n;
1379
1380 /* reset fifo */
1381 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1382 if (boardtype.reg_type & ni_reg_6xxx_mask)
1383 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1384
1385 /* load some data */
1386 n = comedi_buf_read_n_available(s->async);
1387 if (n == 0)
1388 return 0;
1389
1390 n /= sizeof(short);
1391 if (n > boardtype.ao_fifo_depth)
1392 n = boardtype.ao_fifo_depth;
1393
1394 ni_ao_fifo_load(dev, s, n);
1395
1396 return n;
1397 }
1398
1399 static void ni_ai_fifo_read(struct comedi_device *dev,
1400 struct comedi_subdevice *s, int n)
1401 {
1402 struct ni_private *devpriv = dev->private;
1403 struct comedi_async *async = s->async;
1404 int i;
1405
1406 if (boardtype.reg_type == ni_reg_611x) {
1407 short data[2];
1408 u32 dl;
1409
1410 for (i = 0; i < n / 2; i++) {
1411 dl = ni_readl(ADC_FIFO_Data_611x);
1412 /* This may get the hi/lo data in the wrong order */
1413 data[0] = (dl >> 16) & 0xffff;
1414 data[1] = dl & 0xffff;
1415 cfc_write_array_to_buffer(s, data, sizeof(data));
1416 }
1417 /* Check if there's a single sample stuck in the FIFO */
1418 if (n % 2) {
1419 dl = ni_readl(ADC_FIFO_Data_611x);
1420 data[0] = dl & 0xffff;
1421 cfc_write_to_buffer(s, data[0]);
1422 }
1423 } else if (boardtype.reg_type == ni_reg_6143) {
1424 short data[2];
1425 u32 dl;
1426
1427 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1428 for (i = 0; i < n / 2; i++) {
1429 dl = ni_readl(AIFIFO_Data_6143);
1430
1431 data[0] = (dl >> 16) & 0xffff;
1432 data[1] = dl & 0xffff;
1433 cfc_write_array_to_buffer(s, data, sizeof(data));
1434 }
1435 if (n % 2) {
1436 /* Assume there is a single sample stuck in the FIFO */
1437 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1438 dl = ni_readl(AIFIFO_Data_6143);
1439 data[0] = (dl >> 16) & 0xffff;
1440 cfc_write_to_buffer(s, data[0]);
1441 }
1442 } else {
1443 if (n > sizeof(devpriv->ai_fifo_buffer) /
1444 sizeof(devpriv->ai_fifo_buffer[0])) {
1445 comedi_error(dev, "bug! ai_fifo_buffer too small");
1446 async->events |= COMEDI_CB_ERROR;
1447 return;
1448 }
1449 for (i = 0; i < n; i++) {
1450 devpriv->ai_fifo_buffer[i] =
1451 ni_readw(ADC_FIFO_Data_Register);
1452 }
1453 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1454 n *
1455 sizeof(devpriv->ai_fifo_buffer[0]));
1456 }
1457 }
1458
1459 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1460 {
1461 int n;
1462 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1463
1464 n = boardtype.ai_fifo_depth / 2;
1465
1466 ni_ai_fifo_read(dev, s, n);
1467 }
1468 #endif
1469
1470 #ifdef PCIDMA
1471 static int ni_ai_drain_dma(struct comedi_device *dev)
1472 {
1473 struct ni_private *devpriv = dev->private;
1474 int i;
1475 static const int timeout = 10000;
1476 unsigned long flags;
1477 int retval = 0;
1478
1479 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1480 if (devpriv->ai_mite_chan) {
1481 for (i = 0; i < timeout; i++) {
1482 if ((devpriv->stc_readw(dev,
1483 AI_Status_1_Register) &
1484 AI_FIFO_Empty_St)
1485 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1486 0)
1487 break;
1488 udelay(5);
1489 }
1490 if (i == timeout) {
1491 printk("ni_mio_common: wait for dma drain timed out\n");
1492 printk
1493 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1494 mite_bytes_in_transit(devpriv->ai_mite_chan),
1495 devpriv->stc_readw(dev, AI_Status_1_Register));
1496 retval = -1;
1497 }
1498 }
1499 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1500
1501 ni_sync_ai_dma(dev);
1502
1503 return retval;
1504 }
1505 #endif
1506 /*
1507 Empties the AI fifo
1508 */
1509 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1510 {
1511 struct ni_private *devpriv = dev->private;
1512 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1513 short data[2];
1514 u32 dl;
1515 short fifo_empty;
1516 int i;
1517
1518 if (boardtype.reg_type == ni_reg_611x) {
1519 while ((devpriv->stc_readw(dev,
1520 AI_Status_1_Register) &
1521 AI_FIFO_Empty_St) == 0) {
1522 dl = ni_readl(ADC_FIFO_Data_611x);
1523
1524 /* This may get the hi/lo data in the wrong order */
1525 data[0] = (dl >> 16);
1526 data[1] = (dl & 0xffff);
1527 cfc_write_array_to_buffer(s, data, sizeof(data));
1528 }
1529 } else if (boardtype.reg_type == ni_reg_6143) {
1530 i = 0;
1531 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1532 dl = ni_readl(AIFIFO_Data_6143);
1533
1534 /* This may get the hi/lo data in the wrong order */
1535 data[0] = (dl >> 16);
1536 data[1] = (dl & 0xffff);
1537 cfc_write_array_to_buffer(s, data, sizeof(data));
1538 i += 2;
1539 }
1540 /* Check if stranded sample is present */
1541 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1542 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1543 dl = ni_readl(AIFIFO_Data_6143);
1544 data[0] = (dl >> 16) & 0xffff;
1545 cfc_write_to_buffer(s, data[0]);
1546 }
1547
1548 } else {
1549 fifo_empty =
1550 devpriv->stc_readw(dev,
1551 AI_Status_1_Register) & AI_FIFO_Empty_St;
1552 while (fifo_empty == 0) {
1553 for (i = 0;
1554 i <
1555 sizeof(devpriv->ai_fifo_buffer) /
1556 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1557 fifo_empty =
1558 devpriv->stc_readw(dev,
1559 AI_Status_1_Register) &
1560 AI_FIFO_Empty_St;
1561 if (fifo_empty)
1562 break;
1563 devpriv->ai_fifo_buffer[i] =
1564 ni_readw(ADC_FIFO_Data_Register);
1565 }
1566 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1567 i *
1568 sizeof(devpriv->
1569 ai_fifo_buffer[0]));
1570 }
1571 }
1572 }
1573
1574 static void get_last_sample_611x(struct comedi_device *dev)
1575 {
1576 struct ni_private *devpriv __maybe_unused = dev->private;
1577 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1578 short data;
1579 u32 dl;
1580
1581 if (boardtype.reg_type != ni_reg_611x)
1582 return;
1583
1584 /* Check if there's a single sample stuck in the FIFO */
1585 if (ni_readb(XXX_Status) & 0x80) {
1586 dl = ni_readl(ADC_FIFO_Data_611x);
1587 data = (dl & 0xffff);
1588 cfc_write_to_buffer(s, data);
1589 }
1590 }
1591
1592 static void get_last_sample_6143(struct comedi_device *dev)
1593 {
1594 struct ni_private *devpriv __maybe_unused = dev->private;
1595 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1596 short data;
1597 u32 dl;
1598
1599 if (boardtype.reg_type != ni_reg_6143)
1600 return;
1601
1602 /* Check if there's a single sample stuck in the FIFO */
1603 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1604 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1605 dl = ni_readl(AIFIFO_Data_6143);
1606
1607 /* This may get the hi/lo data in the wrong order */
1608 data = (dl >> 16) & 0xffff;
1609 cfc_write_to_buffer(s, data);
1610 }
1611 }
1612
1613 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1614 void *data, unsigned int num_bytes,
1615 unsigned int chan_index)
1616 {
1617 struct ni_private *devpriv = dev->private;
1618 struct comedi_async *async = s->async;
1619 unsigned int i;
1620 unsigned int length = num_bytes / bytes_per_sample(s);
1621 short *array = data;
1622 unsigned int *larray = data;
1623
1624 for (i = 0; i < length; i++) {
1625 #ifdef PCIDMA
1626 if (s->subdev_flags & SDF_LSAMPL)
1627 larray[i] = le32_to_cpu(larray[i]);
1628 else
1629 array[i] = le16_to_cpu(array[i]);
1630 #endif
1631 if (s->subdev_flags & SDF_LSAMPL)
1632 larray[i] += devpriv->ai_offset[chan_index];
1633 else
1634 array[i] += devpriv->ai_offset[chan_index];
1635 chan_index++;
1636 chan_index %= async->cmd.chanlist_len;
1637 }
1638 }
1639
1640 #ifdef PCIDMA
1641
1642 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1643 {
1644 struct ni_private *devpriv = dev->private;
1645 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1646 int retval;
1647 unsigned long flags;
1648
1649 retval = ni_request_ai_mite_channel(dev);
1650 if (retval)
1651 return retval;
1652 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1653
1654 /* write alloc the entire buffer */
1655 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1656
1657 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1658 if (devpriv->ai_mite_chan == NULL) {
1659 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1660 return -EIO;
1661 }
1662
1663 switch (boardtype.reg_type) {
1664 case ni_reg_611x:
1665 case ni_reg_6143:
1666 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1667 break;
1668 case ni_reg_628x:
1669 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1670 break;
1671 default:
1672 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1673 break;
1674 }
1675 /*start the MITE */
1676 mite_dma_arm(devpriv->ai_mite_chan);
1677 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1678
1679 return 0;
1680 }
1681
1682 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1683 {
1684 struct ni_private *devpriv = dev->private;
1685 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1686 int retval;
1687 unsigned long flags;
1688
1689 retval = ni_request_ao_mite_channel(dev);
1690 if (retval)
1691 return retval;
1692
1693 /* read alloc the entire buffer */
1694 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1695
1696 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1697 if (devpriv->ao_mite_chan) {
1698 if (boardtype.reg_type & (ni_reg_611x | ni_reg_6713)) {
1699 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1700 } else {
1701 /* doing 32 instead of 16 bit wide transfers from memory
1702 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1703 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1704 }
1705 mite_dma_arm(devpriv->ao_mite_chan);
1706 } else
1707 retval = -EIO;
1708 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1709
1710 return retval;
1711 }
1712
1713 #endif /* PCIDMA */
1714
1715 /*
1716 used for both cancel ioctl and board initialization
1717
1718 this is pretty harsh for a cancel, but it works...
1719 */
1720
1721 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1722 {
1723 struct ni_private *devpriv = dev->private;
1724
1725 ni_release_ai_mite_channel(dev);
1726 /* ai configuration */
1727 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1728 Joint_Reset_Register);
1729
1730 ni_set_bits(dev, Interrupt_A_Enable_Register,
1731 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1732 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1733 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1734 AI_FIFO_Interrupt_Enable, 0);
1735
1736 ni_clear_ai_fifo(dev);
1737
1738 if (boardtype.reg_type != ni_reg_6143)
1739 ni_writeb(0, Misc_Command);
1740
1741 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1742 devpriv->stc_writew(dev,
1743 AI_Start_Stop | AI_Mode_1_Reserved
1744 /*| AI_Trigger_Once */ ,
1745 AI_Mode_1_Register);
1746 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1747 /* generate FIFO interrupts on non-empty */
1748 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1749 if (boardtype.reg_type == ni_reg_611x) {
1750 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1751 AI_SOC_Polarity |
1752 AI_LOCALMUX_CLK_Pulse_Width,
1753 AI_Personal_Register);
1754 devpriv->stc_writew(dev,
1755 AI_SCAN_IN_PROG_Output_Select(3) |
1756 AI_EXTMUX_CLK_Output_Select(0) |
1757 AI_LOCALMUX_CLK_Output_Select(2) |
1758 AI_SC_TC_Output_Select(3) |
1759 AI_CONVERT_Output_Select
1760 (AI_CONVERT_Output_Enable_High),
1761 AI_Output_Control_Register);
1762 } else if (boardtype.reg_type == ni_reg_6143) {
1763 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1764 AI_SOC_Polarity |
1765 AI_LOCALMUX_CLK_Pulse_Width,
1766 AI_Personal_Register);
1767 devpriv->stc_writew(dev,
1768 AI_SCAN_IN_PROG_Output_Select(3) |
1769 AI_EXTMUX_CLK_Output_Select(0) |
1770 AI_LOCALMUX_CLK_Output_Select(2) |
1771 AI_SC_TC_Output_Select(3) |
1772 AI_CONVERT_Output_Select
1773 (AI_CONVERT_Output_Enable_Low),
1774 AI_Output_Control_Register);
1775 } else {
1776 unsigned ai_output_control_bits;
1777 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1778 AI_SOC_Polarity |
1779 AI_CONVERT_Pulse_Width |
1780 AI_LOCALMUX_CLK_Pulse_Width,
1781 AI_Personal_Register);
1782 ai_output_control_bits =
1783 AI_SCAN_IN_PROG_Output_Select(3) |
1784 AI_EXTMUX_CLK_Output_Select(0) |
1785 AI_LOCALMUX_CLK_Output_Select(2) |
1786 AI_SC_TC_Output_Select(3);
1787 if (boardtype.reg_type == ni_reg_622x)
1788 ai_output_control_bits |=
1789 AI_CONVERT_Output_Select
1790 (AI_CONVERT_Output_Enable_High);
1791 else
1792 ai_output_control_bits |=
1793 AI_CONVERT_Output_Select
1794 (AI_CONVERT_Output_Enable_Low);
1795 devpriv->stc_writew(dev, ai_output_control_bits,
1796 AI_Output_Control_Register);
1797 }
1798 /* the following registers should not be changed, because there
1799 * are no backup registers in devpriv. If you want to change
1800 * any of these, add a backup register and other appropriate code:
1801 * AI_Mode_1_Register
1802 * AI_Mode_3_Register
1803 * AI_Personal_Register
1804 * AI_Output_Control_Register
1805 */
1806 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1807
1808 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1809
1810 return 0;
1811 }
1812
1813 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1814 {
1815 unsigned long flags;
1816 int count;
1817
1818 /* lock to avoid race with interrupt handler */
1819 spin_lock_irqsave(&dev->spinlock, flags);
1820 #ifndef PCIDMA
1821 ni_handle_fifo_dregs(dev);
1822 #else
1823 ni_sync_ai_dma(dev);
1824 #endif
1825 count = s->async->buf_write_count - s->async->buf_read_count;
1826 spin_unlock_irqrestore(&dev->spinlock, flags);
1827
1828 return count;
1829 }
1830
1831 static int ni_ai_insn_read(struct comedi_device *dev,
1832 struct comedi_subdevice *s, struct comedi_insn *insn,
1833 unsigned int *data)
1834 {
1835 struct ni_private *devpriv = dev->private;
1836 int i, n;
1837 const unsigned int mask = (1 << boardtype.adbits) - 1;
1838 unsigned signbits;
1839 unsigned short d;
1840 unsigned long dl;
1841
1842 ni_load_channelgain_list(dev, 1, &insn->chanspec);
1843
1844 ni_clear_ai_fifo(dev);
1845
1846 signbits = devpriv->ai_offset[0];
1847 if (boardtype.reg_type == ni_reg_611x) {
1848 for (n = 0; n < num_adc_stages_611x; n++) {
1849 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1850 AI_Command_1_Register);
1851 udelay(1);
1852 }
1853 for (n = 0; n < insn->n; n++) {
1854 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1855 AI_Command_1_Register);
1856 /* The 611x has screwy 32-bit FIFOs. */
1857 d = 0;
1858 for (i = 0; i < NI_TIMEOUT; i++) {
1859 if (ni_readb(XXX_Status) & 0x80) {
1860 d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1861 & 0xffff;
1862 break;
1863 }
1864 if (!(devpriv->stc_readw(dev,
1865 AI_Status_1_Register) &
1866 AI_FIFO_Empty_St)) {
1867 d = ni_readl(ADC_FIFO_Data_611x) &
1868 0xffff;
1869 break;
1870 }
1871 }
1872 if (i == NI_TIMEOUT) {
1873 printk
1874 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1875 return -ETIME;
1876 }
1877 d += signbits;
1878 data[n] = d;
1879 }
1880 } else if (boardtype.reg_type == ni_reg_6143) {
1881 for (n = 0; n < insn->n; n++) {
1882 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1883 AI_Command_1_Register);
1884
1885 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1886 dl = 0;
1887 for (i = 0; i < NI_TIMEOUT; i++) {
1888 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1889 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1890 dl = ni_readl(AIFIFO_Data_6143);
1891 break;
1892 }
1893 }
1894 if (i == NI_TIMEOUT) {
1895 printk
1896 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1897 return -ETIME;
1898 }
1899 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1900 }
1901 } else {
1902 for (n = 0; n < insn->n; n++) {
1903 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1904 AI_Command_1_Register);
1905 for (i = 0; i < NI_TIMEOUT; i++) {
1906 if (!(devpriv->stc_readw(dev,
1907 AI_Status_1_Register) &
1908 AI_FIFO_Empty_St))
1909 break;
1910 }
1911 if (i == NI_TIMEOUT) {
1912 printk
1913 ("ni_mio_common: timeout in ni_ai_insn_read\n");
1914 return -ETIME;
1915 }
1916 if (boardtype.reg_type & ni_reg_m_series_mask) {
1917 data[n] =
1918 ni_readl(M_Offset_AI_FIFO_Data) & mask;
1919 } else {
1920 d = ni_readw(ADC_FIFO_Data_Register);
1921 d += signbits; /* subtle: needs to be short addition */
1922 data[n] = d;
1923 }
1924 }
1925 }
1926 return insn->n;
1927 }
1928
1929 static void ni_prime_channelgain_list(struct comedi_device *dev)
1930 {
1931 struct ni_private *devpriv = dev->private;
1932 int i;
1933
1934 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1935 for (i = 0; i < NI_TIMEOUT; ++i) {
1936 if (!(devpriv->stc_readw(dev,
1937 AI_Status_1_Register) &
1938 AI_FIFO_Empty_St)) {
1939 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1940 return;
1941 }
1942 udelay(1);
1943 }
1944 printk("ni_mio_common: timeout loading channel/gain list\n");
1945 }
1946
1947 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1948 unsigned int n_chan,
1949 unsigned int *list)
1950 {
1951 struct ni_private *devpriv = dev->private;
1952 unsigned int chan, range, aref;
1953 unsigned int i;
1954 unsigned offset;
1955 unsigned int dither;
1956 unsigned range_code;
1957
1958 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1959
1960 /* offset = 1 << (boardtype.adbits - 1); */
1961 if ((list[0] & CR_ALT_SOURCE)) {
1962 unsigned bypass_bits;
1963 chan = CR_CHAN(list[0]);
1964 range = CR_RANGE(list[0]);
1965 range_code = ni_gainlkup[boardtype.gainlkup][range];
1966 dither = ((list[0] & CR_ALT_FILTER) != 0);
1967 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1968 bypass_bits |= chan;
1969 bypass_bits |=
1970 (devpriv->ai_calib_source) &
1971 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1972 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1973 MSeries_AI_Bypass_Mode_Mux_Mask |
1974 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1975 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1976 if (dither)
1977 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1978 /* don't use 2's complement encoding */
1979 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1980 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1981 } else {
1982 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1983 }
1984 offset = 0;
1985 for (i = 0; i < n_chan; i++) {
1986 unsigned config_bits = 0;
1987 chan = CR_CHAN(list[i]);
1988 aref = CR_AREF(list[i]);
1989 range = CR_RANGE(list[i]);
1990 dither = ((list[i] & CR_ALT_FILTER) != 0);
1991
1992 range_code = ni_gainlkup[boardtype.gainlkup][range];
1993 devpriv->ai_offset[i] = offset;
1994 switch (aref) {
1995 case AREF_DIFF:
1996 config_bits |=
1997 MSeries_AI_Config_Channel_Type_Differential_Bits;
1998 break;
1999 case AREF_COMMON:
2000 config_bits |=
2001 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
2002 break;
2003 case AREF_GROUND:
2004 config_bits |=
2005 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
2006 break;
2007 case AREF_OTHER:
2008 break;
2009 }
2010 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
2011 config_bits |=
2012 MSeries_AI_Config_Bank_Bits(boardtype.reg_type, chan);
2013 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
2014 if (i == n_chan - 1)
2015 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
2016 if (dither)
2017 config_bits |= MSeries_AI_Config_Dither_Bit;
2018 /* don't use 2's complement encoding */
2019 config_bits |= MSeries_AI_Config_Polarity_Bit;
2020 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
2021 }
2022 ni_prime_channelgain_list(dev);
2023 }
2024
2025 /*
2026 * Notes on the 6110 and 6111:
2027 * These boards a slightly different than the rest of the series, since
2028 * they have multiple A/D converters.
2029 * From the driver side, the configuration memory is a
2030 * little different.
2031 * Configuration Memory Low:
2032 * bits 15-9: same
2033 * bit 8: unipolar/bipolar (should be 0 for bipolar)
2034 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
2035 * 1001 gain=0.1 (+/- 50)
2036 * 1010 0.2
2037 * 1011 0.1
2038 * 0001 1
2039 * 0010 2
2040 * 0011 5
2041 * 0100 10
2042 * 0101 20
2043 * 0110 50
2044 * Configuration Memory High:
2045 * bits 12-14: Channel Type
2046 * 001 for differential
2047 * 000 for calibration
2048 * bit 11: coupling (this is not currently handled)
2049 * 1 AC coupling
2050 * 0 DC coupling
2051 * bits 0-2: channel
2052 * valid channels are 0-3
2053 */
2054 static void ni_load_channelgain_list(struct comedi_device *dev,
2055 unsigned int n_chan, unsigned int *list)
2056 {
2057 struct ni_private *devpriv = dev->private;
2058 unsigned int chan, range, aref;
2059 unsigned int i;
2060 unsigned int hi, lo;
2061 unsigned offset;
2062 unsigned int dither;
2063
2064 if (boardtype.reg_type & ni_reg_m_series_mask) {
2065 ni_m_series_load_channelgain_list(dev, n_chan, list);
2066 return;
2067 }
2068 if (n_chan == 1 && (boardtype.reg_type != ni_reg_611x)
2069 && (boardtype.reg_type != ni_reg_6143)) {
2070 if (devpriv->changain_state
2071 && devpriv->changain_spec == list[0]) {
2072 /* ready to go. */
2073 return;
2074 }
2075 devpriv->changain_state = 1;
2076 devpriv->changain_spec = list[0];
2077 } else {
2078 devpriv->changain_state = 0;
2079 }
2080
2081 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2082
2083 /* Set up Calibration mode if required */
2084 if (boardtype.reg_type == ni_reg_6143) {
2085 if ((list[0] & CR_ALT_SOURCE)
2086 && !devpriv->ai_calib_source_enabled) {
2087 /* Strobe Relay enable bit */
2088 ni_writew(devpriv->ai_calib_source |
2089 Calibration_Channel_6143_RelayOn,
2090 Calibration_Channel_6143);
2091 ni_writew(devpriv->ai_calib_source,
2092 Calibration_Channel_6143);
2093 devpriv->ai_calib_source_enabled = 1;
2094 msleep_interruptible(100); /* Allow relays to change */
2095 } else if (!(list[0] & CR_ALT_SOURCE)
2096 && devpriv->ai_calib_source_enabled) {
2097 /* Strobe Relay disable bit */
2098 ni_writew(devpriv->ai_calib_source |
2099 Calibration_Channel_6143_RelayOff,
2100 Calibration_Channel_6143);
2101 ni_writew(devpriv->ai_calib_source,
2102 Calibration_Channel_6143);
2103 devpriv->ai_calib_source_enabled = 0;
2104 msleep_interruptible(100); /* Allow relays to change */
2105 }
2106 }
2107
2108 offset = 1 << (boardtype.adbits - 1);
2109 for (i = 0; i < n_chan; i++) {
2110 if ((boardtype.reg_type != ni_reg_6143)
2111 && (list[i] & CR_ALT_SOURCE)) {
2112 chan = devpriv->ai_calib_source;
2113 } else {
2114 chan = CR_CHAN(list[i]);
2115 }
2116 aref = CR_AREF(list[i]);
2117 range = CR_RANGE(list[i]);
2118 dither = ((list[i] & CR_ALT_FILTER) != 0);
2119
2120 /* fix the external/internal range differences */
2121 range = ni_gainlkup[boardtype.gainlkup][range];
2122 if (boardtype.reg_type == ni_reg_611x)
2123 devpriv->ai_offset[i] = offset;
2124 else
2125 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2126
2127 hi = 0;
2128 if ((list[i] & CR_ALT_SOURCE)) {
2129 if (boardtype.reg_type == ni_reg_611x)
2130 ni_writew(CR_CHAN(list[i]) & 0x0003,
2131 Calibration_Channel_Select_611x);
2132 } else {
2133 if (boardtype.reg_type == ni_reg_611x)
2134 aref = AREF_DIFF;
2135 else if (boardtype.reg_type == ni_reg_6143)
2136 aref = AREF_OTHER;
2137 switch (aref) {
2138 case AREF_DIFF:
2139 hi |= AI_DIFFERENTIAL;
2140 break;
2141 case AREF_COMMON:
2142 hi |= AI_COMMON;
2143 break;
2144 case AREF_GROUND:
2145 hi |= AI_GROUND;
2146 break;
2147 case AREF_OTHER:
2148 break;
2149 }
2150 }
2151 hi |= AI_CONFIG_CHANNEL(chan);
2152
2153 ni_writew(hi, Configuration_Memory_High);
2154
2155 if (boardtype.reg_type != ni_reg_6143) {
2156 lo = range;
2157 if (i == n_chan - 1)
2158 lo |= AI_LAST_CHANNEL;
2159 if (dither)
2160 lo |= AI_DITHER;
2161
2162 ni_writew(lo, Configuration_Memory_Low);
2163 }
2164 }
2165
2166 /* prime the channel/gain list */
2167 if ((boardtype.reg_type != ni_reg_611x)
2168 && (boardtype.reg_type != ni_reg_6143)) {
2169 ni_prime_channelgain_list(dev);
2170 }
2171 }
2172
2173 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2174 int round_mode)
2175 {
2176 struct ni_private *devpriv = dev->private;
2177 int divider;
2178
2179 switch (round_mode) {
2180 case TRIG_ROUND_NEAREST:
2181 default:
2182 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2183 break;
2184 case TRIG_ROUND_DOWN:
2185 divider = (nanosec) / devpriv->clock_ns;
2186 break;
2187 case TRIG_ROUND_UP:
2188 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2189 break;
2190 }
2191 return divider - 1;
2192 }
2193
2194 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2195 {
2196 struct ni_private *devpriv = dev->private;
2197
2198 return devpriv->clock_ns * (timer + 1);
2199 }
2200
2201 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2202 unsigned num_channels)
2203 {
2204 switch (boardtype.reg_type) {
2205 case ni_reg_611x:
2206 case ni_reg_6143:
2207 /* simultaneously-sampled inputs */
2208 return boardtype.ai_speed;
2209 break;
2210 default:
2211 /* multiplexed inputs */
2212 break;
2213 }
2214 return boardtype.ai_speed * num_channels;
2215 }
2216
2217 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2218 struct comedi_cmd *cmd)
2219 {
2220 struct ni_private *devpriv = dev->private;
2221 int err = 0;
2222 int tmp;
2223 unsigned int sources;
2224
2225 /* Step 1 : check if triggers are trivially valid */
2226
2227 if ((cmd->flags & CMDF_WRITE))
2228 cmd->flags &= ~CMDF_WRITE;
2229
2230 err |= cfc_check_trigger_src(&cmd->start_src,
2231 TRIG_NOW | TRIG_INT | TRIG_EXT);
2232 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2233 TRIG_TIMER | TRIG_EXT);
2234
2235 sources = TRIG_TIMER | TRIG_EXT;
2236 if (boardtype.reg_type == ni_reg_611x ||
2237 boardtype.reg_type == ni_reg_6143)
2238 sources |= TRIG_NOW;
2239 err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2240
2241 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2242 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2243
2244 if (err)
2245 return 1;
2246
2247 /* Step 2a : make sure trigger sources are unique */
2248
2249 err |= cfc_check_trigger_is_unique(cmd->start_src);
2250 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2251 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2252 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2253
2254 /* Step 2b : and mutually compatible */
2255
2256 if (err)
2257 return 2;
2258
2259 /* step 3: make sure arguments are trivially compatible */
2260
2261 if (cmd->start_src == TRIG_EXT) {
2262 /* external trigger */
2263 unsigned int tmp = CR_CHAN(cmd->start_arg);
2264
2265 if (tmp > 16)
2266 tmp = 16;
2267 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2268 if (cmd->start_arg != tmp) {
2269 cmd->start_arg = tmp;
2270 err++;
2271 }
2272 } else {
2273 if (cmd->start_arg != 0) {
2274 /* true for both TRIG_NOW and TRIG_INT */
2275 cmd->start_arg = 0;
2276 err++;
2277 }
2278 }
2279 if (cmd->scan_begin_src == TRIG_TIMER) {
2280 if (cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev,
2281 cmd->
2282 chanlist_len))
2283 {
2284 cmd->scan_begin_arg =
2285 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len);
2286 err++;
2287 }
2288 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) {
2289 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
2290 err++;
2291 }
2292 } else if (cmd->scan_begin_src == TRIG_EXT) {
2293 /* external trigger */
2294 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2295
2296 if (tmp > 16)
2297 tmp = 16;
2298 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2299 if (cmd->scan_begin_arg != tmp) {
2300 cmd->scan_begin_arg = tmp;
2301 err++;
2302 }
2303 } else { /* TRIG_OTHER */
2304 if (cmd->scan_begin_arg) {
2305 cmd->scan_begin_arg = 0;
2306 err++;
2307 }
2308 }
2309 if (cmd->convert_src == TRIG_TIMER) {
2310 if ((boardtype.reg_type == ni_reg_611x)
2311 || (boardtype.reg_type == ni_reg_6143)) {
2312 if (cmd->convert_arg != 0) {
2313 cmd->convert_arg = 0;
2314 err++;
2315 }
2316 } else {
2317 if (cmd->convert_arg < boardtype.ai_speed) {
2318 cmd->convert_arg = boardtype.ai_speed;
2319 err++;
2320 }
2321 if (cmd->convert_arg > devpriv->clock_ns * 0xffff) {
2322 cmd->convert_arg = devpriv->clock_ns * 0xffff;
2323 err++;
2324 }
2325 }
2326 } else if (cmd->convert_src == TRIG_EXT) {
2327 /* external trigger */
2328 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2329
2330 if (tmp > 16)
2331 tmp = 16;
2332 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2333 if (cmd->convert_arg != tmp) {
2334 cmd->convert_arg = tmp;
2335 err++;
2336 }
2337 } else if (cmd->convert_src == TRIG_NOW) {
2338 if (cmd->convert_arg != 0) {
2339 cmd->convert_arg = 0;
2340 err++;
2341 }
2342 }
2343
2344 if (cmd->scan_end_arg != cmd->chanlist_len) {
2345 cmd->scan_end_arg = cmd->chanlist_len;
2346 err++;
2347 }
2348 if (cmd->stop_src == TRIG_COUNT) {
2349 unsigned int max_count = 0x01000000;
2350
2351 if (boardtype.reg_type == ni_reg_611x)
2352 max_count -= num_adc_stages_611x;
2353 if (cmd->stop_arg > max_count) {
2354 cmd->stop_arg = max_count;
2355 err++;
2356 }
2357 if (cmd->stop_arg < 1) {
2358 cmd->stop_arg = 1;
2359 err++;
2360 }
2361 } else {
2362 /* TRIG_NONE */
2363 if (cmd->stop_arg != 0) {
2364 cmd->stop_arg = 0;
2365 err++;
2366 }
2367 }
2368
2369 if (err)
2370 return 3;
2371
2372 /* step 4: fix up any arguments */
2373
2374 if (cmd->scan_begin_src == TRIG_TIMER) {
2375 tmp = cmd->scan_begin_arg;
2376 cmd->scan_begin_arg =
2377 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2378 cmd->scan_begin_arg,
2379 cmd->
2380 flags &
2381 TRIG_ROUND_MASK));
2382 if (tmp != cmd->scan_begin_arg)
2383 err++;
2384 }
2385 if (cmd->convert_src == TRIG_TIMER) {
2386 if ((boardtype.reg_type != ni_reg_611x)
2387 && (boardtype.reg_type != ni_reg_6143)) {
2388 tmp = cmd->convert_arg;
2389 cmd->convert_arg =
2390 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2391 cmd->convert_arg,
2392 cmd->
2393 flags &
2394 TRIG_ROUND_MASK));
2395 if (tmp != cmd->convert_arg)
2396 err++;
2397 if (cmd->scan_begin_src == TRIG_TIMER &&
2398 cmd->scan_begin_arg <
2399 cmd->convert_arg * cmd->scan_end_arg) {
2400 cmd->scan_begin_arg =
2401 cmd->convert_arg * cmd->scan_end_arg;
2402 err++;
2403 }
2404 }
2405 }
2406
2407 if (err)
2408 return 4;
2409
2410 return 0;
2411 }
2412
2413 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2414 {
2415 struct ni_private *devpriv = dev->private;
2416 const struct comedi_cmd *cmd = &s->async->cmd;
2417 int timer;
2418 int mode1 = 0; /* mode1 is needed for both stop and convert */
2419 int mode2 = 0;
2420 int start_stop_select = 0;
2421 unsigned int stop_count;
2422 int interrupt_a_enable = 0;
2423
2424 MDPRINTK("ni_ai_cmd\n");
2425 if (dev->irq == 0) {
2426 comedi_error(dev, "cannot run command without an irq");
2427 return -EIO;
2428 }
2429 ni_clear_ai_fifo(dev);
2430
2431 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2432
2433 /* start configuration */
2434 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2435
2436 /* disable analog triggering for now, since it
2437 * interferes with the use of pfi0 */
2438 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2439 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2440 Analog_Trigger_Etc_Register);
2441
2442 switch (cmd->start_src) {
2443 case TRIG_INT:
2444 case TRIG_NOW:
2445 devpriv->stc_writew(dev, AI_START2_Select(0) |
2446 AI_START1_Sync | AI_START1_Edge |
2447 AI_START1_Select(0),
2448 AI_Trigger_Select_Register);
2449 break;
2450 case TRIG_EXT:
2451 {
2452 int chan = CR_CHAN(cmd->start_arg);
2453 unsigned int bits = AI_START2_Select(0) |
2454 AI_START1_Sync | AI_START1_Select(chan + 1);
2455
2456 if (cmd->start_arg & CR_INVERT)
2457 bits |= AI_START1_Polarity;
2458 if (cmd->start_arg & CR_EDGE)
2459 bits |= AI_START1_Edge;
2460 devpriv->stc_writew(dev, bits,
2461 AI_Trigger_Select_Register);
2462 break;
2463 }
2464 }
2465
2466 mode2 &= ~AI_Pre_Trigger;
2467 mode2 &= ~AI_SC_Initial_Load_Source;
2468 mode2 &= ~AI_SC_Reload_Mode;
2469 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2470
2471 if (cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x)
2472 || (boardtype.reg_type == ni_reg_6143)) {
2473 start_stop_select |= AI_STOP_Polarity;
2474 start_stop_select |= AI_STOP_Select(31); /* logic low */
2475 start_stop_select |= AI_STOP_Sync;
2476 } else {
2477 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2478 }
2479 devpriv->stc_writew(dev, start_stop_select,
2480 AI_START_STOP_Select_Register);
2481
2482 devpriv->ai_cmd2 = 0;
2483 switch (cmd->stop_src) {
2484 case TRIG_COUNT:
2485 stop_count = cmd->stop_arg - 1;
2486
2487 if (boardtype.reg_type == ni_reg_611x) {
2488 /* have to take 3 stage adc pipeline into account */
2489 stop_count += num_adc_stages_611x;
2490 }
2491 /* stage number of scans */
2492 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2493
2494 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2495 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2496 /* load SC (Scan Count) */
2497 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2498
2499 devpriv->ai_continuous = 0;
2500 if (stop_count == 0) {
2501 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2502 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2503 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2504 if (cmd->chanlist_len > 1)
2505 start_stop_select |=
2506 AI_STOP_Polarity | AI_STOP_Edge;
2507 }
2508 break;
2509 case TRIG_NONE:
2510 /* stage number of scans */
2511 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2512
2513 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2514 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2515
2516 /* load SC (Scan Count) */
2517 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2518
2519 devpriv->ai_continuous = 1;
2520
2521 break;
2522 }
2523
2524 switch (cmd->scan_begin_src) {
2525 case TRIG_TIMER:
2526 /*
2527 stop bits for non 611x boards
2528 AI_SI_Special_Trigger_Delay=0
2529 AI_Pre_Trigger=0
2530 AI_START_STOP_Select_Register:
2531 AI_START_Polarity=0 (?) rising edge
2532 AI_START_Edge=1 edge triggered
2533 AI_START_Sync=1 (?)
2534 AI_START_Select=0 SI_TC
2535 AI_STOP_Polarity=0 rising edge
2536 AI_STOP_Edge=0 level
2537 AI_STOP_Sync=1
2538 AI_STOP_Select=19 external pin (configuration mem)
2539 */
2540 start_stop_select |= AI_START_Edge | AI_START_Sync;
2541 devpriv->stc_writew(dev, start_stop_select,
2542 AI_START_STOP_Select_Register);
2543
2544 mode2 |= AI_SI_Reload_Mode(0);
2545 /* AI_SI_Initial_Load_Source=A */
2546 mode2 &= ~AI_SI_Initial_Load_Source;
2547 /* mode2 |= AI_SC_Reload_Mode; */
2548 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2549
2550 /* load SI */
2551 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2552 TRIG_ROUND_NEAREST);
2553 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2554 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2555 break;
2556 case TRIG_EXT:
2557 if (cmd->scan_begin_arg & CR_EDGE)
2558 start_stop_select |= AI_START_Edge;
2559 /* AI_START_Polarity==1 is falling edge */
2560 if (cmd->scan_begin_arg & CR_INVERT)
2561 start_stop_select |= AI_START_Polarity;
2562 if (cmd->scan_begin_src != cmd->convert_src ||
2563 (cmd->scan_begin_arg & ~CR_EDGE) !=
2564 (cmd->convert_arg & ~CR_EDGE))
2565 start_stop_select |= AI_START_Sync;
2566 start_stop_select |=
2567 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2568 devpriv->stc_writew(dev, start_stop_select,
2569 AI_START_STOP_Select_Register);
2570 break;
2571 }
2572
2573 switch (cmd->convert_src) {
2574 case TRIG_TIMER:
2575 case TRIG_NOW:
2576 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2577 timer = 1;
2578 else
2579 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2580 TRIG_ROUND_NEAREST);
2581 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2582 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2583
2584 /* AI_SI2_Reload_Mode = alternate */
2585 /* AI_SI2_Initial_Load_Source = A */
2586 mode2 &= ~AI_SI2_Initial_Load_Source;
2587 mode2 |= AI_SI2_Reload_Mode;
2588 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2589
2590 /* AI_SI2_Load */
2591 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2592
2593 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2594 mode2 |= AI_SI2_Initial_Load_Source; /* B */
2595
2596 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2597 break;
2598 case TRIG_EXT:
2599 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2600 if ((cmd->convert_arg & CR_INVERT) == 0)
2601 mode1 |= AI_CONVERT_Source_Polarity;
2602 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2603
2604 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2605 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2606
2607 break;
2608 }
2609
2610 if (dev->irq) {
2611
2612 /* interrupt on FIFO, errors, SC_TC */
2613 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2614 AI_SC_TC_Interrupt_Enable;
2615
2616 #ifndef PCIDMA
2617 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2618 #endif
2619
2620 if (cmd->flags & TRIG_WAKE_EOS
2621 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2622 /* wake on end-of-scan */
2623 devpriv->aimode = AIMODE_SCAN;
2624 } else {
2625 devpriv->aimode = AIMODE_HALF_FULL;
2626 }
2627
2628 switch (devpriv->aimode) {
2629 case AIMODE_HALF_FULL:
2630 /*generate FIFO interrupts and DMA requests on half-full */
2631 #ifdef PCIDMA
2632 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2633 AI_Mode_3_Register);
2634 #else
2635 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2636 AI_Mode_3_Register);
2637 #endif
2638 break;
2639 case AIMODE_SAMPLE:
2640 /*generate FIFO interrupts on non-empty */
2641 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2642 AI_Mode_3_Register);
2643 break;
2644 case AIMODE_SCAN:
2645 #ifdef PCIDMA
2646 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2647 AI_Mode_3_Register);
2648 #else
2649 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2650 AI_Mode_3_Register);
2651 #endif
2652 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2653 break;
2654 default:
2655 break;
2656 }
2657
2658 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2659
2660 ni_set_bits(dev, Interrupt_A_Enable_Register,
2661 interrupt_a_enable, 1);
2662
2663 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2664 devpriv->int_a_enable_reg);
2665 } else {
2666 /* interrupt on nothing */
2667 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2668
2669 /* XXX start polling if necessary */
2670 MDPRINTK("interrupting on nothing\n");
2671 }
2672
2673 /* end configuration */
2674 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2675
2676 switch (cmd->scan_begin_src) {
2677 case TRIG_TIMER:
2678 devpriv->stc_writew(dev,
2679 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2680 AI_SC_Arm, AI_Command_1_Register);
2681 break;
2682 case TRIG_EXT:
2683 /* XXX AI_SI_Arm? */
2684 devpriv->stc_writew(dev,
2685 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2686 AI_SC_Arm, AI_Command_1_Register);
2687 break;
2688 }
2689
2690 #ifdef PCIDMA
2691 {
2692 int retval = ni_ai_setup_MITE_dma(dev);
2693 if (retval)
2694 return retval;
2695 }
2696 /* mite_dump_regs(devpriv->mite); */
2697 #endif
2698
2699 switch (cmd->start_src) {
2700 case TRIG_NOW:
2701 /* AI_START1_Pulse */
2702 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2703 AI_Command_2_Register);
2704 s->async->inttrig = NULL;
2705 break;
2706 case TRIG_EXT:
2707 s->async->inttrig = NULL;
2708 break;
2709 case TRIG_INT:
2710 s->async->inttrig = &ni_ai_inttrig;
2711 break;
2712 }
2713
2714 MDPRINTK("exit ni_ai_cmd\n");
2715
2716 return 0;
2717 }
2718
2719 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2720 unsigned int trignum)
2721 {
2722 struct ni_private *devpriv = dev->private;
2723
2724 if (trignum != 0)
2725 return -EINVAL;
2726
2727 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2728 AI_Command_2_Register);
2729 s->async->inttrig = NULL;
2730
2731 return 1;
2732 }
2733
2734 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2735 struct comedi_subdevice *s,
2736 struct comedi_insn *insn,
2737 unsigned int *data);
2738
2739 static int ni_ai_insn_config(struct comedi_device *dev,
2740 struct comedi_subdevice *s,
2741 struct comedi_insn *insn, unsigned int *data)
2742 {
2743 struct ni_private *devpriv = dev->private;
2744
2745 if (insn->n < 1)
2746 return -EINVAL;
2747
2748 switch (data[0]) {
2749 case INSN_CONFIG_ANALOG_TRIG:
2750 return ni_ai_config_analog_trig(dev, s, insn, data);
2751 case INSN_CONFIG_ALT_SOURCE:
2752 if (boardtype.reg_type & ni_reg_m_series_mask) {
2753 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2754 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2755 MSeries_AI_Bypass_Mode_Mux_Mask |
2756 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2757 return -EINVAL;
2758 }
2759 devpriv->ai_calib_source = data[1];
2760 } else if (boardtype.reg_type == ni_reg_6143) {
2761 unsigned int calib_source;
2762
2763 calib_source = data[1] & 0xf;
2764
2765 if (calib_source > 0xF)
2766 return -EINVAL;
2767
2768 devpriv->ai_calib_source = calib_source;
2769 ni_writew(calib_source, Calibration_Channel_6143);
2770 } else {
2771 unsigned int calib_source;
2772 unsigned int calib_source_adjust;
2773
2774 calib_source = data[1] & 0xf;
2775 calib_source_adjust = (data[1] >> 4) & 0xff;
2776
2777 if (calib_source >= 8)
2778 return -EINVAL;
2779 devpriv->ai_calib_source = calib_source;
2780 if (boardtype.reg_type == ni_reg_611x) {
2781 ni_writeb(calib_source_adjust,
2782 Cal_Gain_Select_611x);
2783 }
2784 }
2785 return 2;
2786 default:
2787 break;
2788 }
2789
2790 return -EINVAL;
2791 }
2792
2793 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2794 struct comedi_subdevice *s,
2795 struct comedi_insn *insn,
2796 unsigned int *data)
2797 {
2798 struct ni_private *devpriv = dev->private;
2799 unsigned int a, b, modebits;
2800 int err = 0;
2801
2802 /* data[1] is flags
2803 * data[2] is analog line
2804 * data[3] is set level
2805 * data[4] is reset level */
2806 if (!boardtype.has_analog_trig)
2807 return -EINVAL;
2808 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2809 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2810 err++;
2811 }
2812 if (data[2] >= boardtype.n_adchan) {
2813 data[2] = boardtype.n_adchan - 1;
2814 err++;
2815 }
2816 if (data[3] > 255) { /* a */
2817 data[3] = 255;
2818 err++;
2819 }
2820 if (data[4] > 255) { /* b */
2821 data[4] = 255;
2822 err++;
2823 }
2824 /*
2825 * 00 ignore
2826 * 01 set
2827 * 10 reset
2828 *
2829 * modes:
2830 * 1 level: +b- +a-
2831 * high mode 00 00 01 10
2832 * low mode 00 00 10 01
2833 * 2 level: (a<b)
2834 * hysteresis low mode 10 00 00 01
2835 * hysteresis high mode 01 00 00 10
2836 * middle mode 10 01 01 10
2837 */
2838
2839 a = data[3];
2840 b = data[4];
2841 modebits = data[1] & 0xff;
2842 if (modebits & 0xf0) {
2843 /* two level mode */
2844 if (b < a) {
2845 /* swap order */
2846 a = data[4];
2847 b = data[3];
2848 modebits =
2849 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2850 }
2851 devpriv->atrig_low = a;
2852 devpriv->atrig_high = b;
2853 switch (modebits) {
2854 case 0x81: /* low hysteresis mode */
2855 devpriv->atrig_mode = 6;
2856 break;
2857 case 0x42: /* high hysteresis mode */
2858 devpriv->atrig_mode = 3;
2859 break;
2860 case 0x96: /* middle window mode */
2861 devpriv->atrig_mode = 2;
2862 break;
2863 default:
2864 data[1] &= ~0xff;
2865 err++;
2866 }
2867 } else {
2868 /* one level mode */
2869 if (b != 0) {
2870 data[4] = 0;
2871 err++;
2872 }
2873 switch (modebits) {
2874 case 0x06: /* high window mode */
2875 devpriv->atrig_high = a;
2876 devpriv->atrig_mode = 0;
2877 break;
2878 case 0x09: /* low window mode */
2879 devpriv->atrig_low = a;
2880 devpriv->atrig_mode = 1;
2881 break;
2882 default:
2883 data[1] &= ~0xff;
2884 err++;
2885 }
2886 }
2887 if (err)
2888 return -EAGAIN;
2889 return 5;
2890 }
2891
2892 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2893 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2894 void *data, unsigned int num_bytes,
2895 unsigned int chan_index)
2896 {
2897 struct comedi_async *async = s->async;
2898 unsigned int range;
2899 unsigned int i;
2900 unsigned int offset;
2901 unsigned int length = num_bytes / sizeof(short);
2902 short *array = data;
2903
2904 offset = 1 << (boardtype.aobits - 1);
2905 for (i = 0; i < length; i++) {
2906 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2907 if (boardtype.ao_unipolar == 0 || (range & 1) == 0)
2908 array[i] -= offset;
2909 #ifdef PCIDMA
2910 array[i] = cpu_to_le16(array[i]);
2911 #endif
2912 chan_index++;
2913 chan_index %= async->cmd.chanlist_len;
2914 }
2915 }
2916
2917 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2918 struct comedi_subdevice *s,
2919 unsigned int chanspec[],
2920 unsigned int n_chans, int timed)
2921 {
2922 struct ni_private *devpriv = dev->private;
2923 unsigned int range;
2924 unsigned int chan;
2925 unsigned int conf;
2926 int i;
2927 int invert = 0;
2928
2929 if (timed) {
2930 for (i = 0; i < boardtype.n_aochan; ++i) {
2931 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2932 ni_writeb(devpriv->ao_conf[i],
2933 M_Offset_AO_Config_Bank(i));
2934 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2935 }
2936 }
2937 for (i = 0; i < n_chans; i++) {
2938 const struct comedi_krange *krange;
2939 chan = CR_CHAN(chanspec[i]);
2940 range = CR_RANGE(chanspec[i]);
2941 krange = s->range_table->range + range;
2942 invert = 0;
2943 conf = 0;
2944 switch (krange->max - krange->min) {
2945 case 20000000:
2946 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2947 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2948 break;
2949 case 10000000:
2950 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2951 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2952 break;
2953 case 4000000:
2954 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2955 ni_writeb(MSeries_Attenuate_x5_Bit,
2956 M_Offset_AO_Reference_Attenuation(chan));
2957 break;
2958 case 2000000:
2959 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2960 ni_writeb(MSeries_Attenuate_x5_Bit,
2961 M_Offset_AO_Reference_Attenuation(chan));
2962 break;
2963 default:
2964 printk("%s: bug! unhandled ao reference voltage\n",
2965 __func__);
2966 break;
2967 }
2968 switch (krange->max + krange->min) {
2969 case 0:
2970 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2971 break;
2972 case 10000000:
2973 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2974 break;
2975 default:
2976 printk("%s: bug! unhandled ao offset voltage\n",
2977 __func__);
2978 break;
2979 }
2980 if (timed)
2981 conf |= MSeries_AO_Update_Timed_Bit;
2982 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2983 devpriv->ao_conf[chan] = conf;
2984 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2985 }
2986 return invert;
2987 }
2988
2989 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2990 struct comedi_subdevice *s,
2991 unsigned int chanspec[],
2992 unsigned int n_chans)
2993 {
2994 struct ni_private *devpriv = dev->private;
2995 unsigned int range;
2996 unsigned int chan;
2997 unsigned int conf;
2998 int i;
2999 int invert = 0;
3000
3001 for (i = 0; i < n_chans; i++) {
3002 chan = CR_CHAN(chanspec[i]);
3003 range = CR_RANGE(chanspec[i]);
3004 conf = AO_Channel(chan);
3005
3006 if (boardtype.ao_unipolar) {
3007 if ((range & 1) == 0) {
3008 conf |= AO_Bipolar;
3009 invert = (1 << (boardtype.aobits - 1));
3010 } else {
3011 invert = 0;
3012 }
3013 if (range & 2)
3014 conf |= AO_Ext_Ref;
3015 } else {
3016 conf |= AO_Bipolar;
3017 invert = (1 << (boardtype.aobits - 1));
3018 }
3019
3020 /* not all boards can deglitch, but this shouldn't hurt */
3021 if (chanspec[i] & CR_DEGLITCH)
3022 conf |= AO_Deglitch;
3023
3024 /* analog reference */
3025 /* AREF_OTHER connects AO ground to AI ground, i think */
3026 conf |= (CR_AREF(chanspec[i]) ==
3027 AREF_OTHER) ? AO_Ground_Ref : 0;
3028
3029 ni_writew(conf, AO_Configuration);
3030 devpriv->ao_conf[chan] = conf;
3031 }
3032 return invert;
3033 }
3034
3035 static int ni_ao_config_chanlist(struct comedi_device *dev,
3036 struct comedi_subdevice *s,
3037 unsigned int chanspec[], unsigned int n_chans,
3038 int timed)
3039 {
3040 if (boardtype.reg_type & ni_reg_m_series_mask)
3041 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3042 timed);
3043 else
3044 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3045 }
3046
3047 static int ni_ao_insn_read(struct comedi_device *dev,
3048 struct comedi_subdevice *s, struct comedi_insn *insn,
3049 unsigned int *data)
3050 {
3051 struct ni_private *devpriv = dev->private;
3052
3053 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3054
3055 return 1;
3056 }
3057
3058 static int ni_ao_insn_write(struct comedi_device *dev,
3059 struct comedi_subdevice *s,
3060 struct comedi_insn *insn, unsigned int *data)
3061 {
3062 struct ni_private *devpriv = dev->private;
3063 unsigned int chan = CR_CHAN(insn->chanspec);
3064 unsigned int invert;
3065
3066 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3067
3068 devpriv->ao[chan] = data[0];
3069
3070 if (boardtype.reg_type & ni_reg_m_series_mask) {
3071 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3072 } else
3073 ni_writew(data[0] ^ invert,
3074 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3075
3076 return 1;
3077 }
3078
3079 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3080 struct comedi_subdevice *s,
3081 struct comedi_insn *insn, unsigned int *data)
3082 {
3083 struct ni_private *devpriv = dev->private;
3084 unsigned int chan = CR_CHAN(insn->chanspec);
3085 unsigned int invert;
3086
3087 ao_win_out(1 << chan, AO_Immediate_671x);
3088 invert = 1 << (boardtype.aobits - 1);
3089
3090 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3091
3092 devpriv->ao[chan] = data[0];
3093 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3094
3095 return 1;
3096 }
3097
3098 static int ni_ao_insn_config(struct comedi_device *dev,
3099 struct comedi_subdevice *s,
3100 struct comedi_insn *insn, unsigned int *data)
3101 {
3102 struct ni_private *devpriv = dev->private;
3103
3104 switch (data[0]) {
3105 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3106 switch (data[1]) {
3107 case COMEDI_OUTPUT:
3108 data[2] = 1 + boardtype.ao_fifo_depth * sizeof(short);
3109 if (devpriv->mite)
3110 data[2] += devpriv->mite->fifo_size;
3111 break;
3112 case COMEDI_INPUT:
3113 data[2] = 0;
3114 break;
3115 default:
3116 return -EINVAL;
3117 break;
3118 }
3119 return 0;
3120 default:
3121 break;
3122 }
3123
3124 return -EINVAL;
3125 }
3126
3127 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3128 unsigned int trignum)
3129 {
3130 struct ni_private *devpriv = dev->private;
3131 int ret;
3132 int interrupt_b_bits;
3133 int i;
3134 static const int timeout = 1000;
3135
3136 if (trignum != 0)
3137 return -EINVAL;
3138
3139 /* Null trig at beginning prevent ao start trigger from executing more than
3140 once per command (and doing things like trying to allocate the ao dma channel
3141 multiple times) */
3142 s->async->inttrig = NULL;
3143
3144 ni_set_bits(dev, Interrupt_B_Enable_Register,
3145 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3146 interrupt_b_bits = AO_Error_Interrupt_Enable;
3147 #ifdef PCIDMA
3148 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3149 if (boardtype.reg_type & ni_reg_6xxx_mask)
3150 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3151 ret = ni_ao_setup_MITE_dma(dev);
3152 if (ret)
3153 return ret;
3154 ret = ni_ao_wait_for_dma_load(dev);
3155 if (ret < 0)
3156 return ret;
3157 #else
3158 ret = ni_ao_prep_fifo(dev, s);
3159 if (ret == 0)
3160 return -EPIPE;
3161
3162 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3163 #endif
3164
3165 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3166 AO_Mode_3_Register);
3167 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3168 /* wait for DACs to be loaded */
3169 for (i = 0; i < timeout; i++) {
3170 udelay(1);
3171 if ((devpriv->stc_readw(dev,
3172 Joint_Status_2_Register) &
3173 AO_TMRDACWRs_In_Progress_St) == 0)
3174 break;
3175 }
3176 if (i == timeout) {
3177 comedi_error(dev,
3178 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3179 return -EIO;
3180 }
3181 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3182 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3183 Interrupt_B_Ack_Register);
3184
3185 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3186
3187 devpriv->stc_writew(dev,
3188 devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3189 | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3190 AO_Command_1_Register);
3191
3192 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3193 AO_Command_2_Register);
3194
3195 return 0;
3196 }
3197
3198 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3199 {
3200 struct ni_private *devpriv = dev->private;
3201 const struct comedi_cmd *cmd = &s->async->cmd;
3202 int bits;
3203 int i;
3204 unsigned trigvar;
3205
3206 if (dev->irq == 0) {
3207 comedi_error(dev, "cannot run command without an irq");
3208 return -EIO;
3209 }
3210
3211 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3212
3213 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3214
3215 if (boardtype.reg_type & ni_reg_6xxx_mask) {
3216 ao_win_out(CLEAR_WG, AO_Misc_611x);
3217
3218 bits = 0;
3219 for (i = 0; i < cmd->chanlist_len; i++) {
3220 int chan;
3221
3222 chan = CR_CHAN(cmd->chanlist[i]);
3223 bits |= 1 << chan;
3224 ao_win_out(chan, AO_Waveform_Generation_611x);
3225 }
3226 ao_win_out(bits, AO_Timed_611x);
3227 }
3228
3229 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3230
3231 if (cmd->stop_src == TRIG_NONE) {
3232 devpriv->ao_mode1 |= AO_Continuous;
3233 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3234 } else {
3235 devpriv->ao_mode1 &= ~AO_Continuous;
3236 devpriv->ao_mode1 |= AO_Trigger_Once;
3237 }
3238 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3239 switch (cmd->start_src) {
3240 case TRIG_INT:
3241 case TRIG_NOW:
3242 devpriv->ao_trigger_select &=
3243 ~(AO_START1_Polarity | AO_START1_Select(-1));
3244 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3245 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3246 AO_Trigger_Select_Register);
3247 break;
3248 case TRIG_EXT:
3249 devpriv->ao_trigger_select =
3250 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3251 if (cmd->start_arg & CR_INVERT)
3252 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3253 if (cmd->start_arg & CR_EDGE)
3254 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3255 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3256 AO_Trigger_Select_Register);
3257 break;
3258 default:
3259 BUG();
3260 break;
3261 }
3262 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3263 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3264
3265 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3266 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3267 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3268 if (cmd->stop_src == TRIG_NONE) {
3269 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3270 } else {
3271 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3272 }
3273 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3274 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3275 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3276 switch (cmd->stop_src) {
3277 case TRIG_COUNT:
3278 if (boardtype.reg_type & ni_reg_m_series_mask) {
3279 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3280 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3281 AO_UC_Load_A_Register);
3282 devpriv->stc_writew(dev, AO_UC_Load,
3283 AO_Command_1_Register);
3284 } else {
3285 devpriv->stc_writel(dev, cmd->stop_arg,
3286 AO_UC_Load_A_Register);
3287 devpriv->stc_writew(dev, AO_UC_Load,
3288 AO_Command_1_Register);
3289 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3290 AO_UC_Load_A_Register);
3291 }
3292 break;
3293 case TRIG_NONE:
3294 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3295 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3296 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3297 break;
3298 default:
3299 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3300 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3301 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3302 }
3303
3304 devpriv->ao_mode1 &=
3305 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3306 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3307 switch (cmd->scan_begin_src) {
3308 case TRIG_TIMER:
3309 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3310 trigvar =
3311 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3312 TRIG_ROUND_NEAREST);
3313 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3314 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3315 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3316 break;
3317 case TRIG_EXT:
3318 devpriv->ao_mode1 |=
3319 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3320 if (cmd->scan_begin_arg & CR_INVERT)
3321 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3322 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3323 break;
3324 default:
3325 BUG();
3326 break;
3327 }
3328 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3329 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3330 devpriv->ao_mode2 &=
3331 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3332 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3333
3334 if (cmd->scan_end_arg > 1) {
3335 devpriv->ao_mode1 |= AO_Multiple_Channels;
3336 devpriv->stc_writew(dev,
3337 AO_Number_Of_Channels(cmd->scan_end_arg -
3338 1) |
3339 AO_UPDATE_Output_Select
3340 (AO_Update_Output_High_Z),
3341 AO_Output_Control_Register);
3342 } else {
3343 unsigned bits;
3344 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3345 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3346 if (boardtype.
3347 reg_type & (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3348 bits |= AO_Number_Of_Channels(0);
3349 } else {
3350 bits |=
3351 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3352 }
3353 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3354 }
3355 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3356
3357 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3358 AO_Command_1_Register);
3359
3360 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3361 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3362
3363 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3364 #ifdef PCIDMA
3365 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3366 #else
3367 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3368 #endif
3369 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3370 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3371
3372 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3373 AO_TMRDACWR_Pulse_Width;
3374 if (boardtype.ao_fifo_depth)
3375 bits |= AO_FIFO_Enable;
3376 else
3377 bits |= AO_DMA_PIO_Control;
3378 #if 0
3379 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3380 verified with bus analyzer. */
3381 if (boardtype.reg_type & ni_reg_m_series_mask)
3382 bits |= AO_Number_Of_DAC_Packages;
3383 #endif
3384 devpriv->stc_writew(dev, bits, AO_Personal_Register);
3385 /* enable sending of ao dma requests */
3386 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3387
3388 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3389
3390 if (cmd->stop_src == TRIG_COUNT) {
3391 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3392 Interrupt_B_Ack_Register);
3393 ni_set_bits(dev, Interrupt_B_Enable_Register,
3394 AO_BC_TC_Interrupt_Enable, 1);
3395 }
3396
3397 s->async->inttrig = &ni_ao_inttrig;
3398
3399 return 0;
3400 }
3401
3402 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3403 struct comedi_cmd *cmd)
3404 {
3405 struct ni_private *devpriv = dev->private;
3406 int err = 0;
3407 int tmp;
3408
3409 /* Step 1 : check if triggers are trivially valid */
3410
3411 if ((cmd->flags & CMDF_WRITE) == 0)
3412 cmd->flags |= CMDF_WRITE;
3413
3414 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3415 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3416 TRIG_TIMER | TRIG_EXT);
3417 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3418 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3419 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3420
3421 if (err)
3422 return 1;
3423
3424 /* Step 2a : make sure trigger sources are unique */
3425
3426 err |= cfc_check_trigger_is_unique(cmd->start_src);
3427 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3428 err |= cfc_check_trigger_is_unique(cmd->stop_src);
3429
3430 /* Step 2b : and mutually compatible */
3431
3432 if (err)
3433 return 2;
3434
3435 /* step 3: make sure arguments are trivially compatible */
3436
3437 if (cmd->start_src == TRIG_EXT) {
3438 /* external trigger */
3439 unsigned int tmp = CR_CHAN(cmd->start_arg);
3440
3441 if (tmp > 18)
3442 tmp = 18;
3443 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3444 if (cmd->start_arg != tmp) {
3445 cmd->start_arg = tmp;
3446 err++;
3447 }
3448 } else {
3449 if (cmd->start_arg != 0) {
3450 /* true for both TRIG_NOW and TRIG_INT */
3451 cmd->start_arg = 0;
3452 err++;
3453 }
3454 }
3455 if (cmd->scan_begin_src == TRIG_TIMER) {
3456 if (cmd->scan_begin_arg < boardtype.ao_speed) {
3457 cmd->scan_begin_arg = boardtype.ao_speed;
3458 err++;
3459 }
3460 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) { /* XXX check */
3461 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
3462 err++;
3463 }
3464 }
3465 if (cmd->convert_arg != 0) {
3466 cmd->convert_arg = 0;
3467 err++;
3468 }
3469 if (cmd->scan_end_arg != cmd->chanlist_len) {
3470 cmd->scan_end_arg = cmd->chanlist_len;
3471 err++;
3472 }
3473 if (cmd->stop_src == TRIG_COUNT) { /* XXX check */
3474 if (cmd->stop_arg > 0x00ffffff) {
3475 cmd->stop_arg = 0x00ffffff;
3476 err++;
3477 }
3478 } else {
3479 /* TRIG_NONE */
3480 if (cmd->stop_arg != 0) {
3481 cmd->stop_arg = 0;
3482 err++;
3483 }
3484 }
3485
3486 if (err)
3487 return 3;
3488
3489 /* step 4: fix up any arguments */
3490 if (cmd->scan_begin_src == TRIG_TIMER) {
3491 tmp = cmd->scan_begin_arg;
3492 cmd->scan_begin_arg =
3493 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3494 cmd->scan_begin_arg,
3495 cmd->
3496 flags &
3497 TRIG_ROUND_MASK));
3498 if (tmp != cmd->scan_begin_arg)
3499 err++;
3500 }
3501 if (err)
3502 return 4;
3503
3504 /* step 5: fix up chanlist */
3505
3506 if (err)
3507 return 5;
3508
3509 return 0;
3510 }
3511
3512 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3513 {
3514 struct ni_private *devpriv = dev->private;
3515
3516 /* devpriv->ao0p=0x0000; */
3517 /* ni_writew(devpriv->ao0p,AO_Configuration); */
3518
3519 /* devpriv->ao1p=AO_Channel(1); */
3520 /* ni_writew(devpriv->ao1p,AO_Configuration); */
3521
3522 ni_release_ao_mite_channel(dev);
3523
3524 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3525 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3526 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3527 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3528 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3529 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3530 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3531 devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3532 devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3533 devpriv->ao_cmd1 = 0;
3534 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3535 devpriv->ao_cmd2 = 0;
3536 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3537 devpriv->ao_mode1 = 0;
3538 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3539 devpriv->ao_mode2 = 0;
3540 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3541 if (boardtype.reg_type & ni_reg_m_series_mask)
3542 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3543 else
3544 devpriv->ao_mode3 = 0;
3545 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3546 devpriv->ao_trigger_select = 0;
3547 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3548 AO_Trigger_Select_Register);
3549 if (boardtype.reg_type & ni_reg_6xxx_mask) {
3550 unsigned immediate_bits = 0;
3551 unsigned i;
3552 for (i = 0; i < s->n_chan; ++i) {
3553 immediate_bits |= 1 << i;
3554 }
3555 ao_win_out(immediate_bits, AO_Immediate_671x);
3556 ao_win_out(CLEAR_WG, AO_Misc_611x);
3557 }
3558 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3559
3560 return 0;
3561 }
3562
3563 /* digital io */
3564
3565 static int ni_dio_insn_config(struct comedi_device *dev,
3566 struct comedi_subdevice *s,
3567 struct comedi_insn *insn, unsigned int *data)
3568 {
3569 struct ni_private *devpriv = dev->private;
3570
3571 #ifdef DEBUG_DIO
3572 printk("ni_dio_insn_config() chan=%d io=%d\n",
3573 CR_CHAN(insn->chanspec), data[0]);
3574 #endif
3575 switch (data[0]) {
3576 case INSN_CONFIG_DIO_OUTPUT:
3577 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3578 break;
3579 case INSN_CONFIG_DIO_INPUT:
3580 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3581 break;
3582 case INSN_CONFIG_DIO_QUERY:
3583 data[1] =
3584 (s->
3585 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3586 COMEDI_INPUT;
3587 return insn->n;
3588 break;
3589 default:
3590 return -EINVAL;
3591 }
3592
3593 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3594 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3595 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3596
3597 return 1;
3598 }
3599
3600 static int ni_dio_insn_bits(struct comedi_device *dev,
3601 struct comedi_subdevice *s,
3602 struct comedi_insn *insn, unsigned int *data)
3603 {
3604 struct ni_private *devpriv = dev->private;
3605
3606 #ifdef DEBUG_DIO
3607 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3608 #endif
3609
3610 if (data[0]) {
3611 /* Perform check to make sure we're not using the
3612 serial part of the dio */
3613 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3614 && devpriv->serial_interval_ns)
3615 return -EBUSY;
3616
3617 s->state &= ~data[0];
3618 s->state |= (data[0] & data[1]);
3619 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3620 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3621 devpriv->stc_writew(dev, devpriv->dio_output,
3622 DIO_Output_Register);
3623 }
3624 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3625
3626 return insn->n;
3627 }
3628
3629 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3630 struct comedi_subdevice *s,
3631 struct comedi_insn *insn,
3632 unsigned int *data)
3633 {
3634 struct ni_private *devpriv __maybe_unused = dev->private;
3635
3636 #ifdef DEBUG_DIO
3637 printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3638 CR_CHAN(insn->chanspec), data[0]);
3639 #endif
3640 switch (data[0]) {
3641 case INSN_CONFIG_DIO_OUTPUT:
3642 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3643 break;
3644 case INSN_CONFIG_DIO_INPUT:
3645 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3646 break;
3647 case INSN_CONFIG_DIO_QUERY:
3648 data[1] =
3649 (s->
3650 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3651 COMEDI_INPUT;
3652 return insn->n;
3653 break;
3654 default:
3655 return -EINVAL;
3656 }
3657
3658 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3659
3660 return 1;
3661 }
3662
3663 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3664 struct comedi_subdevice *s,
3665 struct comedi_insn *insn,
3666 unsigned int *data)
3667 {
3668 struct ni_private *devpriv __maybe_unused = dev->private;
3669
3670 #ifdef DEBUG_DIO
3671 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3672 data[1]);
3673 #endif
3674
3675 if (data[0]) {
3676 s->state &= ~data[0];
3677 s->state |= (data[0] & data[1]);
3678 ni_writel(s->state, M_Offset_Static_Digital_Output);
3679 }
3680 data[1] = ni_readl(M_Offset_Static_Digital_Input);
3681
3682 return insn->n;
3683 }
3684
3685 static int ni_cdio_cmdtest(struct comedi_device *dev,
3686 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3687 {
3688 int err = 0;
3689 int tmp;
3690 unsigned i;
3691
3692 /* Step 1 : check if triggers are trivially valid */
3693
3694 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3695 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3696 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3697 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3698 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3699
3700 if (err)
3701 return 1;
3702
3703 /* Step 2a : make sure trigger sources are unique */
3704 /* Step 2b : and mutually compatible */
3705
3706 if (err)
3707 return 2;
3708
3709 /* step 3: make sure arguments are trivially compatible */
3710 if (cmd->start_src == TRIG_INT) {
3711 if (cmd->start_arg != 0) {
3712 cmd->start_arg = 0;
3713 err++;
3714 }
3715 }
3716 if (cmd->scan_begin_src == TRIG_EXT) {
3717 tmp = cmd->scan_begin_arg;
3718 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0,
3719 CR_INVERT);
3720 if (tmp != cmd->scan_begin_arg) {
3721 err++;
3722 }
3723 }
3724 if (cmd->convert_src == TRIG_NOW) {
3725 if (cmd->convert_arg) {
3726 cmd->convert_arg = 0;
3727 err++;
3728 }
3729 }
3730
3731 if (cmd->scan_end_arg != cmd->chanlist_len) {
3732 cmd->scan_end_arg = cmd->chanlist_len;
3733 err++;
3734 }
3735
3736 if (cmd->stop_src == TRIG_NONE) {
3737 if (cmd->stop_arg != 0) {
3738 cmd->stop_arg = 0;
3739 err++;
3740 }
3741 }
3742
3743 if (err)
3744 return 3;
3745
3746 /* step 4: fix up any arguments */
3747
3748 if (err)
3749 return 4;
3750
3751 /* step 5: check chanlist */
3752
3753 for (i = 0; i < cmd->chanlist_len; ++i) {
3754 if (cmd->chanlist[i] != i)
3755 err = 1;
3756 }
3757
3758 if (err)
3759 return 5;
3760
3761 return 0;
3762 }
3763
3764 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3765 {
3766 struct ni_private *devpriv __maybe_unused = dev->private;
3767 const struct comedi_cmd *cmd = &s->async->cmd;
3768 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3769 int retval;
3770
3771 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3772 switch (cmd->scan_begin_src) {
3773 case TRIG_EXT:
3774 cdo_mode_bits |=
3775 CR_CHAN(cmd->scan_begin_arg) &
3776 CDO_Sample_Source_Select_Mask;
3777 break;
3778 default:
3779 BUG();
3780 break;
3781 }
3782 if (cmd->scan_begin_arg & CR_INVERT)
3783 cdo_mode_bits |= CDO_Polarity_Bit;
3784 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3785 if (s->io_bits) {
3786 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3787 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3788 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3789 } else {
3790 comedi_error(dev,
3791 "attempted to run digital output command with no lines configured as outputs");
3792 return -EIO;
3793 }
3794 retval = ni_request_cdo_mite_channel(dev);
3795 if (retval < 0) {
3796 return retval;
3797 }
3798 s->async->inttrig = &ni_cdo_inttrig;
3799 return 0;
3800 }
3801
3802 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3803 unsigned int trignum)
3804 {
3805 #ifdef PCIDMA
3806 struct ni_private *devpriv = dev->private;
3807 unsigned long flags;
3808 #endif
3809 int retval = 0;
3810 unsigned i;
3811 const unsigned timeout = 1000;
3812
3813 s->async->inttrig = NULL;
3814
3815 /* read alloc the entire buffer */
3816 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3817
3818 #ifdef PCIDMA
3819 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3820 if (devpriv->cdo_mite_chan) {
3821 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3822 mite_dma_arm(devpriv->cdo_mite_chan);
3823 } else {
3824 comedi_error(dev, "BUG: no cdo mite channel?");
3825 retval = -EIO;
3826 }
3827 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3828 if (retval < 0)
3829 return retval;
3830 #endif
3831 /*
3832 * XXX not sure what interrupt C group does
3833 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3834 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3835 */
3836 for (i = 0; i < timeout; ++i) {
3837 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3838 break;
3839 udelay(10);
3840 }
3841 if (i == timeout) {
3842 comedi_error(dev, "dma failed to fill cdo fifo!");
3843 ni_cdio_cancel(dev, s);
3844 return -EIO;
3845 }
3846 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3847 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3848 M_Offset_CDIO_Command);
3849 return retval;
3850 }
3851
3852 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3853 {
3854 struct ni_private *devpriv __maybe_unused = dev->private;
3855
3856 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3857 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3858 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3859 M_Offset_CDIO_Command);
3860 /*
3861 * XXX not sure what interrupt C group does ni_writeb(0,
3862 * M_Offset_Interrupt_C_Enable);
3863 */
3864 ni_writel(0, M_Offset_CDO_Mask_Enable);
3865 ni_release_cdo_mite_channel(dev);
3866 return 0;
3867 }
3868
3869 static void handle_cdio_interrupt(struct comedi_device *dev)
3870 {
3871 struct ni_private *devpriv __maybe_unused = dev->private;
3872 unsigned cdio_status;
3873 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3874 #ifdef PCIDMA
3875 unsigned long flags;
3876 #endif
3877
3878 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
3879 return;
3880 }
3881 #ifdef PCIDMA
3882 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3883 if (devpriv->cdo_mite_chan) {
3884 unsigned cdo_mite_status =
3885 mite_get_status(devpriv->cdo_mite_chan);
3886 if (cdo_mite_status & CHSR_LINKC) {
3887 writel(CHOR_CLRLC,
3888 devpriv->mite->mite_io_addr +
3889 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3890 }
3891 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3892 }
3893 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3894 #endif
3895
3896 cdio_status = ni_readl(M_Offset_CDIO_Status);
3897 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3898 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3899 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */
3900 s->async->events |= COMEDI_CB_OVERFLOW;
3901 }
3902 if (cdio_status & CDO_FIFO_Empty_Bit) {
3903 /* printk("cdio fifo empty\n"); */
3904 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3905 M_Offset_CDIO_Command);
3906 /* s->async->events |= COMEDI_CB_EOA; */
3907 }
3908 ni_event(dev, s);
3909 }
3910
3911 static int ni_serial_insn_config(struct comedi_device *dev,
3912 struct comedi_subdevice *s,
3913 struct comedi_insn *insn, unsigned int *data)
3914 {
3915 struct ni_private *devpriv = dev->private;
3916 int err = insn->n;
3917 unsigned char byte_out, byte_in = 0;
3918
3919 if (insn->n != 2)
3920 return -EINVAL;
3921
3922 switch (data[0]) {
3923 case INSN_CONFIG_SERIAL_CLOCK:
3924
3925 #ifdef DEBUG_DIO
3926 printk("SPI serial clock Config cd\n", data[1]);
3927 #endif
3928 devpriv->serial_hw_mode = 1;
3929 devpriv->dio_control |= DIO_HW_Serial_Enable;
3930
3931 if (data[1] == SERIAL_DISABLED) {
3932 devpriv->serial_hw_mode = 0;
3933 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3934 DIO_Software_Serial_Control);
3935 data[1] = SERIAL_DISABLED;
3936 devpriv->serial_interval_ns = data[1];
3937 } else if (data[1] <= SERIAL_600NS) {
3938 /* Warning: this clock speed is too fast to reliably
3939 control SCXI. */
3940 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3941 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3942 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3943 data[1] = SERIAL_600NS;
3944 devpriv->serial_interval_ns = data[1];
3945 } else if (data[1] <= SERIAL_1_2US) {
3946 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3947 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3948 DIO_Serial_Out_Divide_By_2;
3949 data[1] = SERIAL_1_2US;
3950 devpriv->serial_interval_ns = data[1];
3951 } else if (data[1] <= SERIAL_10US) {
3952 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3953 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3954 DIO_Serial_Out_Divide_By_2;
3955 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3956 600ns/1.2us. If you turn divide_by_2 off with the
3957 slow clock, you will still get 10us, except then
3958 all your delays are wrong. */
3959 data[1] = SERIAL_10US;
3960 devpriv->serial_interval_ns = data[1];
3961 } else {
3962 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3963 DIO_Software_Serial_Control);
3964 devpriv->serial_hw_mode = 0;
3965 data[1] = (data[1] / 1000) * 1000;
3966 devpriv->serial_interval_ns = data[1];
3967 }
3968
3969 devpriv->stc_writew(dev, devpriv->dio_control,
3970 DIO_Control_Register);
3971 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3972 Clock_and_FOUT_Register);
3973 return 1;
3974
3975 break;
3976
3977 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3978
3979 if (devpriv->serial_interval_ns == 0) {
3980 return -EINVAL;
3981 }
3982
3983 byte_out = data[1] & 0xFF;
3984
3985 if (devpriv->serial_hw_mode) {
3986 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3987 &byte_in);
3988 } else if (devpriv->serial_interval_ns > 0) {
3989 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3990 &byte_in);
3991 } else {
3992 printk("ni_serial_insn_config: serial disabled!\n");
3993 return -EINVAL;
3994 }
3995 if (err < 0)
3996 return err;
3997 data[1] = byte_in & 0xFF;
3998 return insn->n;
3999
4000 break;
4001 default:
4002 return -EINVAL;
4003 }
4004
4005 }
4006
4007 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
4008 struct comedi_subdevice *s,
4009 unsigned char data_out,
4010 unsigned char *data_in)
4011 {
4012 struct ni_private *devpriv = dev->private;
4013 unsigned int status1;
4014 int err = 0, count = 20;
4015
4016 #ifdef DEBUG_DIO
4017 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
4018 #endif
4019
4020 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
4021 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
4022 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
4023
4024 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
4025 if (status1 & DIO_Serial_IO_In_Progress_St) {
4026 err = -EBUSY;
4027 goto Error;
4028 }
4029
4030 devpriv->dio_control |= DIO_HW_Serial_Start;
4031 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4032 devpriv->dio_control &= ~DIO_HW_Serial_Start;
4033
4034 /* Wait until STC says we're done, but don't loop infinitely. */
4035 while ((status1 =
4036 devpriv->stc_readw(dev,
4037 Joint_Status_1_Register)) &
4038 DIO_Serial_IO_In_Progress_St) {
4039 /* Delay one bit per loop */
4040 udelay((devpriv->serial_interval_ns + 999) / 1000);
4041 if (--count < 0) {
4042 printk
4043 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
4044 err = -ETIME;
4045 goto Error;
4046 }
4047 }
4048
4049 /* Delay for last bit. This delay is absolutely necessary, because
4050 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
4051 udelay((devpriv->serial_interval_ns + 999) / 1000);
4052
4053 if (data_in != NULL) {
4054 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
4055 #ifdef DEBUG_DIO
4056 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
4057 #endif
4058 }
4059
4060 Error:
4061 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4062
4063 return err;
4064 }
4065
4066 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
4067 struct comedi_subdevice *s,
4068 unsigned char data_out,
4069 unsigned char *data_in)
4070 {
4071 struct ni_private *devpriv = dev->private;
4072 unsigned char mask, input = 0;
4073
4074 #ifdef DEBUG_DIO
4075 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
4076 #endif
4077
4078 /* Wait for one bit before transfer */
4079 udelay((devpriv->serial_interval_ns + 999) / 1000);
4080
4081 for (mask = 0x80; mask; mask >>= 1) {
4082 /* Output current bit; note that we cannot touch s->state
4083 because it is a per-subdevice field, and serial is
4084 a separate subdevice from DIO. */
4085 devpriv->dio_output &= ~DIO_SDOUT;
4086 if (data_out & mask) {
4087 devpriv->dio_output |= DIO_SDOUT;
4088 }
4089 devpriv->stc_writew(dev, devpriv->dio_output,
4090 DIO_Output_Register);
4091
4092 /* Assert SDCLK (active low, inverted), wait for half of
4093 the delay, deassert SDCLK, and wait for the other half. */
4094 devpriv->dio_control |= DIO_Software_Serial_Control;
4095 devpriv->stc_writew(dev, devpriv->dio_control,
4096 DIO_Control_Register);
4097
4098 udelay((devpriv->serial_interval_ns + 999) / 2000);
4099
4100 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4101 devpriv->stc_writew(dev, devpriv->dio_control,
4102 DIO_Control_Register);
4103
4104 udelay((devpriv->serial_interval_ns + 999) / 2000);
4105
4106 /* Input current bit */
4107 if (devpriv->stc_readw(dev,
4108 DIO_Parallel_Input_Register) & DIO_SDIN)
4109 {
4110 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4111 input |= mask;
4112 }
4113 }
4114 #ifdef DEBUG_DIO
4115 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4116 #endif
4117 if (data_in)
4118 *data_in = input;
4119
4120 return 0;
4121 }
4122
4123 static void mio_common_detach(struct comedi_device *dev)
4124 {
4125 struct ni_private *devpriv = dev->private;
4126 struct comedi_subdevice *s;
4127
4128 if (devpriv) {
4129 if (devpriv->counter_dev) {
4130 ni_gpct_device_destroy(devpriv->counter_dev);
4131 }
4132 }
4133 if (dev->subdevices && boardtype.has_8255) {
4134 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4135 subdev_8255_cleanup(dev, s);
4136 }
4137 }
4138
4139 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4140 {
4141 int i;
4142
4143 for (i = 0; i < s->n_chan; i++) {
4144 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4145 AO_Configuration_2_67xx);
4146 }
4147 ao_win_out(0x0, AO_Later_Single_Point_Updates);
4148 }
4149
4150 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4151 {
4152 unsigned stc_register;
4153 switch (reg) {
4154 case NITIO_G0_Autoincrement_Reg:
4155 stc_register = G_Autoincrement_Register(0);
4156 break;
4157 case NITIO_G1_Autoincrement_Reg:
4158 stc_register = G_Autoincrement_Register(1);
4159 break;
4160 case NITIO_G0_Command_Reg:
4161 stc_register = G_Command_Register(0);
4162 break;
4163 case NITIO_G1_Command_Reg:
4164 stc_register = G_Command_Register(1);
4165 break;
4166 case NITIO_G0_HW_Save_Reg:
4167 stc_register = G_HW_Save_Register(0);
4168 break;
4169 case NITIO_G1_HW_Save_Reg:
4170 stc_register = G_HW_Save_Register(1);
4171 break;
4172 case NITIO_G0_SW_Save_Reg:
4173 stc_register = G_Save_Register(0);
4174 break;
4175 case NITIO_G1_SW_Save_Reg:
4176 stc_register = G_Save_Register(1);
4177 break;
4178 case NITIO_G0_Mode_Reg:
4179 stc_register = G_Mode_Register(0);
4180 break;
4181 case NITIO_G1_Mode_Reg:
4182 stc_register = G_Mode_Register(1);
4183 break;
4184 case NITIO_G0_LoadA_Reg:
4185 stc_register = G_Load_A_Register(0);
4186 break;
4187 case NITIO_G1_LoadA_Reg:
4188 stc_register = G_Load_A_Register(1);
4189 break;
4190 case NITIO_G0_LoadB_Reg:
4191 stc_register = G_Load_B_Register(0);
4192 break;
4193 case NITIO_G1_LoadB_Reg:
4194 stc_register = G_Load_B_Register(1);
4195 break;
4196 case NITIO_G0_Input_Select_Reg:
4197 stc_register = G_Input_Select_Register(0);
4198 break;
4199 case NITIO_G1_Input_Select_Reg:
4200 stc_register = G_Input_Select_Register(1);
4201 break;
4202 case NITIO_G01_Status_Reg:
4203 stc_register = G_Status_Register;
4204 break;
4205 case NITIO_G01_Joint_Reset_Reg:
4206 stc_register = Joint_Reset_Register;
4207 break;
4208 case NITIO_G01_Joint_Status1_Reg:
4209 stc_register = Joint_Status_1_Register;
4210 break;
4211 case NITIO_G01_Joint_Status2_Reg:
4212 stc_register = Joint_Status_2_Register;
4213 break;
4214 case NITIO_G0_Interrupt_Acknowledge_Reg:
4215 stc_register = Interrupt_A_Ack_Register;
4216 break;
4217 case NITIO_G1_Interrupt_Acknowledge_Reg:
4218 stc_register = Interrupt_B_Ack_Register;
4219 break;
4220 case NITIO_G0_Status_Reg:
4221 stc_register = AI_Status_1_Register;
4222 break;
4223 case NITIO_G1_Status_Reg:
4224 stc_register = AO_Status_1_Register;
4225 break;
4226 case NITIO_G0_Interrupt_Enable_Reg:
4227 stc_register = Interrupt_A_Enable_Register;
4228 break;
4229 case NITIO_G1_Interrupt_Enable_Reg:
4230 stc_register = Interrupt_B_Enable_Register;
4231 break;
4232 default:
4233 printk("%s: unhandled register 0x%x in switch.\n",
4234 __func__, reg);
4235 BUG();
4236 return 0;
4237 break;
4238 }
4239 return stc_register;
4240 }
4241
4242 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4243 enum ni_gpct_register reg)
4244 {
4245 struct comedi_device *dev = counter->counter_dev->dev;
4246 struct ni_private *devpriv = dev->private;
4247 unsigned stc_register;
4248 /* bits in the join reset register which are relevant to counters */
4249 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4250 static const unsigned gpct_interrupt_a_enable_mask =
4251 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4252 static const unsigned gpct_interrupt_b_enable_mask =
4253 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4254
4255 switch (reg) {
4256 /* m-series-only registers */
4257 case NITIO_G0_Counting_Mode_Reg:
4258 ni_writew(bits, M_Offset_G0_Counting_Mode);
4259 break;
4260 case NITIO_G1_Counting_Mode_Reg:
4261 ni_writew(bits, M_Offset_G1_Counting_Mode);
4262 break;
4263 case NITIO_G0_Second_Gate_Reg:
4264 ni_writew(bits, M_Offset_G0_Second_Gate);
4265 break;
4266 case NITIO_G1_Second_Gate_Reg:
4267 ni_writew(bits, M_Offset_G1_Second_Gate);
4268 break;
4269 case NITIO_G0_DMA_Config_Reg:
4270 ni_writew(bits, M_Offset_G0_DMA_Config);
4271 break;
4272 case NITIO_G1_DMA_Config_Reg:
4273 ni_writew(bits, M_Offset_G1_DMA_Config);
4274 break;
4275 case NITIO_G0_ABZ_Reg:
4276 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4277 break;
4278 case NITIO_G1_ABZ_Reg:
4279 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4280 break;
4281
4282 /* 32 bit registers */
4283 case NITIO_G0_LoadA_Reg:
4284 case NITIO_G1_LoadA_Reg:
4285 case NITIO_G0_LoadB_Reg:
4286 case NITIO_G1_LoadB_Reg:
4287 stc_register = ni_gpct_to_stc_register(reg);
4288 devpriv->stc_writel(dev, bits, stc_register);
4289 break;
4290
4291 /* 16 bit registers */
4292 case NITIO_G0_Interrupt_Enable_Reg:
4293 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4294 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4295 gpct_interrupt_a_enable_mask, bits);
4296 break;
4297 case NITIO_G1_Interrupt_Enable_Reg:
4298 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4299 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4300 gpct_interrupt_b_enable_mask, bits);
4301 break;
4302 case NITIO_G01_Joint_Reset_Reg:
4303 BUG_ON(bits & ~gpct_joint_reset_mask);
4304 /* fall-through */
4305 default:
4306 stc_register = ni_gpct_to_stc_register(reg);
4307 devpriv->stc_writew(dev, bits, stc_register);
4308 }
4309 }
4310
4311 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4312 enum ni_gpct_register reg)
4313 {
4314 struct comedi_device *dev = counter->counter_dev->dev;
4315 struct ni_private *devpriv = dev->private;
4316 unsigned stc_register;
4317
4318 switch (reg) {
4319 /* m-series only registers */
4320 case NITIO_G0_DMA_Status_Reg:
4321 return ni_readw(M_Offset_G0_DMA_Status);
4322 break;
4323 case NITIO_G1_DMA_Status_Reg:
4324 return ni_readw(M_Offset_G1_DMA_Status);
4325 break;
4326
4327 /* 32 bit registers */
4328 case NITIO_G0_HW_Save_Reg:
4329 case NITIO_G1_HW_Save_Reg:
4330 case NITIO_G0_SW_Save_Reg:
4331 case NITIO_G1_SW_Save_Reg:
4332 stc_register = ni_gpct_to_stc_register(reg);
4333 return devpriv->stc_readl(dev, stc_register);
4334 break;
4335
4336 /* 16 bit registers */
4337 default:
4338 stc_register = ni_gpct_to_stc_register(reg);
4339 return devpriv->stc_readw(dev, stc_register);
4340 break;
4341 }
4342 return 0;
4343 }
4344
4345 static int ni_freq_out_insn_read(struct comedi_device *dev,
4346 struct comedi_subdevice *s,
4347 struct comedi_insn *insn, unsigned int *data)
4348 {
4349 struct ni_private *devpriv = dev->private;
4350
4351 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4352 return 1;
4353 }
4354
4355 static int ni_freq_out_insn_write(struct comedi_device *dev,
4356 struct comedi_subdevice *s,
4357 struct comedi_insn *insn, unsigned int *data)
4358 {
4359 struct ni_private *devpriv = dev->private;
4360
4361 devpriv->clock_and_fout &= ~FOUT_Enable;
4362 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4363 Clock_and_FOUT_Register);
4364 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4365 devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4366 devpriv->clock_and_fout |= FOUT_Enable;
4367 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4368 Clock_and_FOUT_Register);
4369 return insn->n;
4370 }
4371
4372 static int ni_set_freq_out_clock(struct comedi_device *dev,
4373 unsigned int clock_source)
4374 {
4375 struct ni_private *devpriv = dev->private;
4376
4377 switch (clock_source) {
4378 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4379 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4380 break;
4381 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4382 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4383 break;
4384 default:
4385 return -EINVAL;
4386 }
4387 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4388 Clock_and_FOUT_Register);
4389 return 3;
4390 }
4391
4392 static void ni_get_freq_out_clock(struct comedi_device *dev,
4393 unsigned int *clock_source,
4394 unsigned int *clock_period_ns)
4395 {
4396 struct ni_private *devpriv = dev->private;
4397
4398 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4399 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4400 *clock_period_ns = TIMEBASE_2_NS;
4401 } else {
4402 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4403 *clock_period_ns = TIMEBASE_1_NS * 2;
4404 }
4405 }
4406
4407 static int ni_freq_out_insn_config(struct comedi_device *dev,
4408 struct comedi_subdevice *s,
4409 struct comedi_insn *insn, unsigned int *data)
4410 {
4411 switch (data[0]) {
4412 case INSN_CONFIG_SET_CLOCK_SRC:
4413 return ni_set_freq_out_clock(dev, data[1]);
4414 break;
4415 case INSN_CONFIG_GET_CLOCK_SRC:
4416 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4417 return 3;
4418 default:
4419 break;
4420 }
4421 return -EINVAL;
4422 }
4423
4424 static int ni_alloc_private(struct comedi_device *dev)
4425 {
4426 struct ni_private *devpriv;
4427
4428 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4429 if (!devpriv)
4430 return -ENOMEM;
4431 dev->private = devpriv;
4432
4433 spin_lock_init(&devpriv->window_lock);
4434 spin_lock_init(&devpriv->soft_reg_copy_lock);
4435 spin_lock_init(&devpriv->mite_channel_lock);
4436
4437 return 0;
4438 };
4439
4440 static int ni_E_init(struct comedi_device *dev)
4441 {
4442 struct ni_private *devpriv = dev->private;
4443 struct comedi_subdevice *s;
4444 unsigned j;
4445 enum ni_gpct_variant counter_variant;
4446 int ret;
4447
4448 if (boardtype.n_aochan > MAX_N_AO_CHAN) {
4449 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
4450 return -EINVAL;
4451 }
4452
4453 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4454 if (ret)
4455 return ret;
4456
4457 /* analog input subdevice */
4458
4459 s = &dev->subdevices[NI_AI_SUBDEV];
4460 dev->read_subdev = s;
4461 if (boardtype.n_adchan) {
4462 s->type = COMEDI_SUBD_AI;
4463 s->subdev_flags =
4464 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4465 if (boardtype.reg_type != ni_reg_611x)
4466 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4467 if (boardtype.adbits > 16)
4468 s->subdev_flags |= SDF_LSAMPL;
4469 if (boardtype.reg_type & ni_reg_m_series_mask)
4470 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4471 s->n_chan = boardtype.n_adchan;
4472 s->len_chanlist = 512;
4473 s->maxdata = (1 << boardtype.adbits) - 1;
4474 s->range_table = ni_range_lkup[boardtype.gainlkup];
4475 s->insn_read = &ni_ai_insn_read;
4476 s->insn_config = &ni_ai_insn_config;
4477 s->do_cmdtest = &ni_ai_cmdtest;
4478 s->do_cmd = &ni_ai_cmd;
4479 s->cancel = &ni_ai_reset;
4480 s->poll = &ni_ai_poll;
4481 s->munge = &ni_ai_munge;
4482 #ifdef PCIDMA
4483 s->async_dma_dir = DMA_FROM_DEVICE;
4484 #endif
4485 } else {
4486 s->type = COMEDI_SUBD_UNUSED;
4487 }
4488
4489 /* analog output subdevice */
4490
4491 s = &dev->subdevices[NI_AO_SUBDEV];
4492 if (boardtype.n_aochan) {
4493 s->type = COMEDI_SUBD_AO;
4494 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4495 if (boardtype.reg_type & ni_reg_m_series_mask)
4496 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4497 s->n_chan = boardtype.n_aochan;
4498 s->maxdata = (1 << boardtype.aobits) - 1;
4499 s->range_table = boardtype.ao_range_table;
4500 s->insn_read = &ni_ao_insn_read;
4501 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4502 s->insn_write = &ni_ao_insn_write_671x;
4503 } else {
4504 s->insn_write = &ni_ao_insn_write;
4505 }
4506 s->insn_config = &ni_ao_insn_config;
4507 #ifdef PCIDMA
4508 if (boardtype.n_aochan) {
4509 s->async_dma_dir = DMA_TO_DEVICE;
4510 #else
4511 if (boardtype.ao_fifo_depth) {
4512 #endif
4513 dev->write_subdev = s;
4514 s->subdev_flags |= SDF_CMD_WRITE;
4515 s->do_cmd = &ni_ao_cmd;
4516 s->do_cmdtest = &ni_ao_cmdtest;
4517 s->len_chanlist = boardtype.n_aochan;
4518 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4519 s->munge = ni_ao_munge;
4520 }
4521 s->cancel = &ni_ao_reset;
4522 } else {
4523 s->type = COMEDI_SUBD_UNUSED;
4524 }
4525 if ((boardtype.reg_type & ni_reg_67xx_mask))
4526 init_ao_67xx(dev, s);
4527
4528 /* digital i/o subdevice */
4529
4530 s = &dev->subdevices[NI_DIO_SUBDEV];
4531 s->type = COMEDI_SUBD_DIO;
4532 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4533 s->maxdata = 1;
4534 s->io_bits = 0; /* all bits input */
4535 s->range_table = &range_digital;
4536 s->n_chan = boardtype.num_p0_dio_channels;
4537 if (boardtype.reg_type & ni_reg_m_series_mask) {
4538 s->subdev_flags |=
4539 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4540 s->insn_bits = &ni_m_series_dio_insn_bits;
4541 s->insn_config = &ni_m_series_dio_insn_config;
4542 s->do_cmd = &ni_cdio_cmd;
4543 s->do_cmdtest = &ni_cdio_cmdtest;
4544 s->cancel = &ni_cdio_cancel;
4545 s->async_dma_dir = DMA_BIDIRECTIONAL;
4546 s->len_chanlist = s->n_chan;
4547
4548 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4549 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4550 } else {
4551 s->insn_bits = &ni_dio_insn_bits;
4552 s->insn_config = &ni_dio_insn_config;
4553 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4554 ni_writew(devpriv->dio_control, DIO_Control_Register);
4555 }
4556
4557 /* 8255 device */
4558 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4559 if (boardtype.has_8255) {
4560 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4561 } else {
4562 s->type = COMEDI_SUBD_UNUSED;
4563 }
4564
4565 /* formerly general purpose counter/timer device, but no longer used */
4566 s = &dev->subdevices[NI_UNUSED_SUBDEV];
4567 s->type = COMEDI_SUBD_UNUSED;
4568
4569 /* calibration subdevice -- ai and ao */
4570 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4571 s->type = COMEDI_SUBD_CALIB;
4572 if (boardtype.reg_type & ni_reg_m_series_mask) {
4573 /* internal PWM analog output used for AI nonlinearity calibration */
4574 s->subdev_flags = SDF_INTERNAL;
4575 s->insn_config = &ni_m_series_pwm_config;
4576 s->n_chan = 1;
4577 s->maxdata = 0;
4578 ni_writel(0x0, M_Offset_Cal_PWM);
4579 } else if (boardtype.reg_type == ni_reg_6143) {
4580 /* internal PWM analog output used for AI nonlinearity calibration */
4581 s->subdev_flags = SDF_INTERNAL;
4582 s->insn_config = &ni_6143_pwm_config;
4583 s->n_chan = 1;
4584 s->maxdata = 0;
4585 } else {
4586 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4587 s->insn_read = &ni_calib_insn_read;
4588 s->insn_write = &ni_calib_insn_write;
4589 caldac_setup(dev, s);
4590 }
4591
4592 /* EEPROM */
4593 s = &dev->subdevices[NI_EEPROM_SUBDEV];
4594 s->type = COMEDI_SUBD_MEMORY;
4595 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4596 s->maxdata = 0xff;
4597 if (boardtype.reg_type & ni_reg_m_series_mask) {
4598 s->n_chan = M_SERIES_EEPROM_SIZE;
4599 s->insn_read = &ni_m_series_eeprom_insn_read;
4600 } else {
4601 s->n_chan = 512;
4602 s->insn_read = &ni_eeprom_insn_read;
4603 }
4604
4605 /* PFI */
4606 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4607 s->type = COMEDI_SUBD_DIO;
4608 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4609 if (boardtype.reg_type & ni_reg_m_series_mask) {
4610 unsigned i;
4611 s->n_chan = 16;
4612 ni_writew(s->state, M_Offset_PFI_DO);
4613 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4614 ni_writew(devpriv->pfi_output_select_reg[i],
4615 M_Offset_PFI_Output_Select(i + 1));
4616 }
4617 } else {
4618 s->n_chan = 10;
4619 }
4620 s->maxdata = 1;
4621 if (boardtype.reg_type & ni_reg_m_series_mask) {
4622 s->insn_bits = &ni_pfi_insn_bits;
4623 }
4624 s->insn_config = &ni_pfi_insn_config;
4625 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4626
4627 /* cs5529 calibration adc */
4628 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4629 if (boardtype.reg_type & ni_reg_67xx_mask) {
4630 s->type = COMEDI_SUBD_AI;
4631 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4632 /* one channel for each analog output channel */
4633 s->n_chan = boardtype.n_aochan;
4634 s->maxdata = (1 << 16) - 1;
4635 s->range_table = &range_unknown; /* XXX */
4636 s->insn_read = cs5529_ai_insn_read;
4637 s->insn_config = NULL;
4638 init_cs5529(dev);
4639 } else {
4640 s->type = COMEDI_SUBD_UNUSED;
4641 }
4642
4643 /* Serial */
4644 s = &dev->subdevices[NI_SERIAL_SUBDEV];
4645 s->type = COMEDI_SUBD_SERIAL;
4646 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4647 s->n_chan = 1;
4648 s->maxdata = 0xff;
4649 s->insn_config = ni_serial_insn_config;
4650 devpriv->serial_interval_ns = 0;
4651 devpriv->serial_hw_mode = 0;
4652
4653 /* RTSI */
4654 s = &dev->subdevices[NI_RTSI_SUBDEV];
4655 s->type = COMEDI_SUBD_DIO;
4656 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4657 s->n_chan = 8;
4658 s->maxdata = 1;
4659 s->insn_bits = ni_rtsi_insn_bits;
4660 s->insn_config = ni_rtsi_insn_config;
4661 ni_rtsi_init(dev);
4662
4663 if (boardtype.reg_type & ni_reg_m_series_mask) {
4664 counter_variant = ni_gpct_variant_m_series;
4665 } else {
4666 counter_variant = ni_gpct_variant_e_series;
4667 }
4668 devpriv->counter_dev = ni_gpct_device_construct(dev,
4669 &ni_gpct_write_register,
4670 &ni_gpct_read_register,
4671 counter_variant,
4672 NUM_GPCT);
4673 /* General purpose counters */
4674 for (j = 0; j < NUM_GPCT; ++j) {
4675 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4676 s->type = COMEDI_SUBD_COUNTER;
4677 s->subdev_flags =
4678 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4679 /* | SDF_CMD_WRITE */ ;
4680 s->n_chan = 3;
4681 if (boardtype.reg_type & ni_reg_m_series_mask)
4682 s->maxdata = 0xffffffff;
4683 else
4684 s->maxdata = 0xffffff;
4685 s->insn_read = &ni_gpct_insn_read;
4686 s->insn_write = &ni_gpct_insn_write;
4687 s->insn_config = &ni_gpct_insn_config;
4688 s->do_cmd = &ni_gpct_cmd;
4689 s->len_chanlist = 1;
4690 s->do_cmdtest = &ni_gpct_cmdtest;
4691 s->cancel = &ni_gpct_cancel;
4692 s->async_dma_dir = DMA_BIDIRECTIONAL;
4693 s->private = &devpriv->counter_dev->counters[j];
4694
4695 devpriv->counter_dev->counters[j].chip_index = 0;
4696 devpriv->counter_dev->counters[j].counter_index = j;
4697 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4698 }
4699
4700 /* Frequency output */
4701 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4702 s->type = COMEDI_SUBD_COUNTER;
4703 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4704 s->n_chan = 1;
4705 s->maxdata = 0xf;
4706 s->insn_read = &ni_freq_out_insn_read;
4707 s->insn_write = &ni_freq_out_insn_write;
4708 s->insn_config = &ni_freq_out_insn_config;
4709
4710 /* ai configuration */
4711 s = &dev->subdevices[NI_AI_SUBDEV];
4712 ni_ai_reset(dev, s);
4713 if ((boardtype.reg_type & ni_reg_6xxx_mask) == 0) {
4714 /* BEAM is this needed for PCI-6143 ?? */
4715 devpriv->clock_and_fout =
4716 Slow_Internal_Time_Divide_By_2 |
4717 Slow_Internal_Timebase |
4718 Clock_To_Board_Divide_By_2 |
4719 Clock_To_Board |
4720 AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4721 } else {
4722 devpriv->clock_and_fout =
4723 Slow_Internal_Time_Divide_By_2 |
4724 Slow_Internal_Timebase |
4725 Clock_To_Board_Divide_By_2 | Clock_To_Board;
4726 }
4727 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4728 Clock_and_FOUT_Register);
4729
4730 /* analog output configuration */
4731 s = &dev->subdevices[NI_AO_SUBDEV];
4732 ni_ao_reset(dev, s);
4733
4734 if (dev->irq) {
4735 devpriv->stc_writew(dev,
4736 (IRQ_POLARITY ? Interrupt_Output_Polarity :
4737 0) | (Interrupt_Output_On_3_Pins & 0) |
4738 Interrupt_A_Enable | Interrupt_B_Enable |
4739 Interrupt_A_Output_Select(interrupt_pin
4740 (dev->irq)) |
4741 Interrupt_B_Output_Select(interrupt_pin
4742 (dev->irq)),
4743 Interrupt_Control_Register);
4744 }
4745
4746 /* DMA setup */
4747 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4748 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4749
4750 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4751 ni_writeb(0, Magic_611x);
4752 } else if (boardtype.reg_type & ni_reg_m_series_mask) {
4753 int channel;
4754 for (channel = 0; channel < boardtype.n_aochan; ++channel) {
4755 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4756 ni_writeb(0x0,
4757 M_Offset_AO_Reference_Attenuation(channel));
4758 }
4759 ni_writeb(0x0, M_Offset_AO_Calibration);
4760 }
4761
4762 printk("\n");
4763 return 0;
4764 }
4765
4766 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4767 {
4768 struct comedi_device *dev = (struct comedi_device *)arg;
4769 struct ni_private *devpriv __maybe_unused = dev->private;
4770
4771 if (dir) {
4772 ni_writeb(data, Port_A + 2 * port);
4773 return 0;
4774 } else {
4775 return ni_readb(Port_A + 2 * port);
4776 }
4777 }
4778
4779 /*
4780 presents the EEPROM as a subdevice
4781 */
4782
4783 static int ni_eeprom_insn_read(struct comedi_device *dev,
4784 struct comedi_subdevice *s,
4785 struct comedi_insn *insn, unsigned int *data)
4786 {
4787 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4788
4789 return 1;
4790 }
4791
4792 /*
4793 reads bytes out of eeprom
4794 */
4795
4796 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4797 {
4798 struct ni_private *devpriv __maybe_unused = dev->private;
4799 int bit;
4800 int bitstring;
4801
4802 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4803 ni_writeb(0x04, Serial_Command);
4804 for (bit = 0x8000; bit; bit >>= 1) {
4805 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4806 Serial_Command);
4807 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4808 Serial_Command);
4809 }
4810 bitstring = 0;
4811 for (bit = 0x80; bit; bit >>= 1) {
4812 ni_writeb(0x04, Serial_Command);
4813 ni_writeb(0x05, Serial_Command);
4814 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4815 }
4816 ni_writeb(0x00, Serial_Command);
4817
4818 return bitstring;
4819 }
4820
4821 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4822 struct comedi_subdevice *s,
4823 struct comedi_insn *insn,
4824 unsigned int *data)
4825 {
4826 struct ni_private *devpriv = dev->private;
4827
4828 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4829
4830 return 1;
4831 }
4832
4833 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4834 {
4835 struct ni_private *devpriv = dev->private;
4836
4837 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4838 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4839 return 3;
4840 }
4841
4842 static int ni_m_series_pwm_config(struct comedi_device *dev,
4843 struct comedi_subdevice *s,
4844 struct comedi_insn *insn, unsigned int *data)
4845 {
4846 struct ni_private *devpriv = dev->private;
4847 unsigned up_count, down_count;
4848
4849 switch (data[0]) {
4850 case INSN_CONFIG_PWM_OUTPUT:
4851 switch (data[1]) {
4852 case TRIG_ROUND_NEAREST:
4853 up_count =
4854 (data[2] +
4855 devpriv->clock_ns / 2) / devpriv->clock_ns;
4856 break;
4857 case TRIG_ROUND_DOWN:
4858 up_count = data[2] / devpriv->clock_ns;
4859 break;
4860 case TRIG_ROUND_UP:
4861 up_count =
4862 (data[2] + devpriv->clock_ns -
4863 1) / devpriv->clock_ns;
4864 break;
4865 default:
4866 return -EINVAL;
4867 break;
4868 }
4869 switch (data[3]) {
4870 case TRIG_ROUND_NEAREST:
4871 down_count =
4872 (data[4] +
4873 devpriv->clock_ns / 2) / devpriv->clock_ns;
4874 break;
4875 case TRIG_ROUND_DOWN:
4876 down_count = data[4] / devpriv->clock_ns;
4877 break;
4878 case TRIG_ROUND_UP:
4879 down_count =
4880 (data[4] + devpriv->clock_ns -
4881 1) / devpriv->clock_ns;
4882 break;
4883 default:
4884 return -EINVAL;
4885 break;
4886 }
4887 if (up_count * devpriv->clock_ns != data[2] ||
4888 down_count * devpriv->clock_ns != data[4]) {
4889 data[2] = up_count * devpriv->clock_ns;
4890 data[4] = down_count * devpriv->clock_ns;
4891 return -EAGAIN;
4892 }
4893 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4894 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4895 M_Offset_Cal_PWM);
4896 devpriv->pwm_up_count = up_count;
4897 devpriv->pwm_down_count = down_count;
4898 return 5;
4899 break;
4900 case INSN_CONFIG_GET_PWM_OUTPUT:
4901 return ni_get_pwm_config(dev, data);
4902 break;
4903 default:
4904 return -EINVAL;
4905 break;
4906 }
4907 return 0;
4908 }
4909
4910 static int ni_6143_pwm_config(struct comedi_device *dev,
4911 struct comedi_subdevice *s,
4912 struct comedi_insn *insn, unsigned int *data)
4913 {
4914 struct ni_private *devpriv = dev->private;
4915 unsigned up_count, down_count;
4916
4917 switch (data[0]) {
4918 case INSN_CONFIG_PWM_OUTPUT:
4919 switch (data[1]) {
4920 case TRIG_ROUND_NEAREST:
4921 up_count =
4922 (data[2] +
4923 devpriv->clock_ns / 2) / devpriv->clock_ns;
4924 break;
4925 case TRIG_ROUND_DOWN:
4926 up_count = data[2] / devpriv->clock_ns;
4927 break;
4928 case TRIG_ROUND_UP:
4929 up_count =
4930 (data[2] + devpriv->clock_ns -
4931 1) / devpriv->clock_ns;
4932 break;
4933 default:
4934 return -EINVAL;
4935 break;
4936 }
4937 switch (data[3]) {
4938 case TRIG_ROUND_NEAREST:
4939 down_count =
4940 (data[4] +
4941 devpriv->clock_ns / 2) / devpriv->clock_ns;
4942 break;
4943 case TRIG_ROUND_DOWN:
4944 down_count = data[4] / devpriv->clock_ns;
4945 break;
4946 case TRIG_ROUND_UP:
4947 down_count =
4948 (data[4] + devpriv->clock_ns -
4949 1) / devpriv->clock_ns;
4950 break;
4951 default:
4952 return -EINVAL;
4953 break;
4954 }
4955 if (up_count * devpriv->clock_ns != data[2] ||
4956 down_count * devpriv->clock_ns != data[4]) {
4957 data[2] = up_count * devpriv->clock_ns;
4958 data[4] = down_count * devpriv->clock_ns;
4959 return -EAGAIN;
4960 }
4961 ni_writel(up_count, Calibration_HighTime_6143);
4962 devpriv->pwm_up_count = up_count;
4963 ni_writel(down_count, Calibration_LowTime_6143);
4964 devpriv->pwm_down_count = down_count;
4965 return 5;
4966 break;
4967 case INSN_CONFIG_GET_PWM_OUTPUT:
4968 return ni_get_pwm_config(dev, data);
4969 default:
4970 return -EINVAL;
4971 break;
4972 }
4973 return 0;
4974 }
4975
4976 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4977 /*
4978 calibration subdevice
4979 */
4980 static int ni_calib_insn_write(struct comedi_device *dev,
4981 struct comedi_subdevice *s,
4982 struct comedi_insn *insn, unsigned int *data)
4983 {
4984 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4985
4986 return 1;
4987 }
4988
4989 static int ni_calib_insn_read(struct comedi_device *dev,
4990 struct comedi_subdevice *s,
4991 struct comedi_insn *insn, unsigned int *data)
4992 {
4993 struct ni_private *devpriv = dev->private;
4994
4995 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4996
4997 return 1;
4998 }
4999
5000 static int pack_mb88341(int addr, int val, int *bitstring);
5001 static int pack_dac8800(int addr, int val, int *bitstring);
5002 static int pack_dac8043(int addr, int val, int *bitstring);
5003 static int pack_ad8522(int addr, int val, int *bitstring);
5004 static int pack_ad8804(int addr, int val, int *bitstring);
5005 static int pack_ad8842(int addr, int val, int *bitstring);
5006
5007 struct caldac_struct {
5008 int n_chans;
5009 int n_bits;
5010 int (*packbits) (int, int, int *);
5011 };
5012
5013 static struct caldac_struct caldacs[] = {
5014 [mb88341] = {12, 8, pack_mb88341},
5015 [dac8800] = {8, 8, pack_dac8800},
5016 [dac8043] = {1, 12, pack_dac8043},
5017 [ad8522] = {2, 12, pack_ad8522},
5018 [ad8804] = {12, 8, pack_ad8804},
5019 [ad8842] = {8, 8, pack_ad8842},
5020 [ad8804_debug] = {16, 8, pack_ad8804},
5021 };
5022
5023 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
5024 {
5025 struct ni_private *devpriv = dev->private;
5026 int i, j;
5027 int n_dacs;
5028 int n_chans = 0;
5029 int n_bits;
5030 int diffbits = 0;
5031 int type;
5032 int chan;
5033
5034 type = boardtype.caldac[0];
5035 if (type == caldac_none)
5036 return;
5037 n_bits = caldacs[type].n_bits;
5038 for (i = 0; i < 3; i++) {
5039 type = boardtype.caldac[i];
5040 if (type == caldac_none)
5041 break;
5042 if (caldacs[type].n_bits != n_bits)
5043 diffbits = 1;
5044 n_chans += caldacs[type].n_chans;
5045 }
5046 n_dacs = i;
5047 s->n_chan = n_chans;
5048
5049 if (diffbits) {
5050 unsigned int *maxdata_list;
5051
5052 if (n_chans > MAX_N_CALDACS) {
5053 printk("BUG! MAX_N_CALDACS too small\n");
5054 }
5055 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
5056 chan = 0;
5057 for (i = 0; i < n_dacs; i++) {
5058 type = boardtype.caldac[i];
5059 for (j = 0; j < caldacs[type].n_chans; j++) {
5060 maxdata_list[chan] =
5061 (1 << caldacs[type].n_bits) - 1;
5062 chan++;
5063 }
5064 }
5065
5066 for (chan = 0; chan < s->n_chan; chan++)
5067 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
5068 } else {
5069 type = boardtype.caldac[0];
5070 s->maxdata = (1 << caldacs[type].n_bits) - 1;
5071
5072 for (chan = 0; chan < s->n_chan; chan++)
5073 ni_write_caldac(dev, i, s->maxdata / 2);
5074 }
5075 }
5076
5077 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
5078 {
5079 struct ni_private *devpriv = dev->private;
5080 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
5081 int i;
5082 int type;
5083
5084 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5085 if (devpriv->caldacs[addr] == val)
5086 return;
5087 devpriv->caldacs[addr] = val;
5088
5089 for (i = 0; i < 3; i++) {
5090 type = boardtype.caldac[i];
5091 if (type == caldac_none)
5092 break;
5093 if (addr < caldacs[type].n_chans) {
5094 bits = caldacs[type].packbits(addr, val, &bitstring);
5095 loadbit = SerDacLd(i);
5096 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5097 break;
5098 }
5099 addr -= caldacs[type].n_chans;
5100 }
5101
5102 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5103 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5104 udelay(1);
5105 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5106 udelay(1);
5107 }
5108 ni_writeb(loadbit, Serial_Command);
5109 udelay(1);
5110 ni_writeb(0, Serial_Command);
5111 }
5112
5113 static int pack_mb88341(int addr, int val, int *bitstring)
5114 {
5115 /*
5116 Fujitsu MB 88341
5117 Note that address bits are reversed. Thanks to
5118 Ingo Keen for noticing this.
5119
5120 Note also that the 88341 expects address values from
5121 1-12, whereas we use channel numbers 0-11. The NI
5122 docs use 1-12, also, so be careful here.
5123 */
5124 addr++;
5125 *bitstring = ((addr & 0x1) << 11) |
5126 ((addr & 0x2) << 9) |
5127 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5128 return 12;
5129 }
5130
5131 static int pack_dac8800(int addr, int val, int *bitstring)
5132 {
5133 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5134 return 11;
5135 }
5136
5137 static int pack_dac8043(int addr, int val, int *bitstring)
5138 {
5139 *bitstring = val & 0xfff;
5140 return 12;
5141 }
5142
5143 static int pack_ad8522(int addr, int val, int *bitstring)
5144 {
5145 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5146 return 16;
5147 }
5148
5149 static int pack_ad8804(int addr, int val, int *bitstring)
5150 {
5151 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5152 return 12;
5153 }
5154
5155 static int pack_ad8842(int addr, int val, int *bitstring)
5156 {
5157 *bitstring = ((addr + 1) << 8) | (val & 0xff);
5158 return 12;
5159 }
5160
5161 #if 0
5162 /*
5163 * Read the GPCTs current value.
5164 */
5165 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5166 {
5167 unsigned int hi1, hi2, lo;
5168
5169 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5170 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5171 G_Command_Register(chan));
5172
5173 devpriv->gpct_command[chan] |= G_Save_Trace;
5174 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5175 G_Command_Register(chan));
5176
5177 /* This procedure is used because the two registers cannot
5178 * be read atomically. */
5179 do {
5180 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5181 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5182 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5183 } while (hi1 != hi2);
5184
5185 return (hi1 << 16) | lo;
5186 }
5187
5188 static void GPCT_Reset(struct comedi_device *dev, int chan)
5189 {
5190 int temp_ack_reg = 0;
5191
5192 /* printk("GPCT_Reset..."); */
5193 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5194
5195 switch (chan) {
5196 case 0:
5197 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5198 ni_set_bits(dev, Interrupt_A_Enable_Register,
5199 G0_TC_Interrupt_Enable, 0);
5200 ni_set_bits(dev, Interrupt_A_Enable_Register,
5201 G0_Gate_Interrupt_Enable, 0);
5202 temp_ack_reg |= G0_Gate_Error_Confirm;
5203 temp_ack_reg |= G0_TC_Error_Confirm;
5204 temp_ack_reg |= G0_TC_Interrupt_Ack;
5205 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5206 devpriv->stc_writew(dev, temp_ack_reg,
5207 Interrupt_A_Ack_Register);
5208
5209 /* problem...this interferes with the other ctr... */
5210 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5211 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5212 Analog_Trigger_Etc_Register);
5213 break;
5214 case 1:
5215 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5216 ni_set_bits(dev, Interrupt_B_Enable_Register,
5217 G1_TC_Interrupt_Enable, 0);
5218 ni_set_bits(dev, Interrupt_B_Enable_Register,
5219 G0_Gate_Interrupt_Enable, 0);
5220 temp_ack_reg |= G1_Gate_Error_Confirm;
5221 temp_ack_reg |= G1_TC_Error_Confirm;
5222 temp_ack_reg |= G1_TC_Interrupt_Ack;
5223 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5224 devpriv->stc_writew(dev, temp_ack_reg,
5225 Interrupt_B_Ack_Register);
5226
5227 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5228 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5229 Analog_Trigger_Etc_Register);
5230 break;
5231 }
5232
5233 devpriv->gpct_mode[chan] = 0;
5234 devpriv->gpct_input_select[chan] = 0;
5235 devpriv->gpct_command[chan] = 0;
5236
5237 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5238
5239 devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5240 G_Mode_Register(chan));
5241 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5242 G_Input_Select_Register(chan));
5243 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5244
5245 /* printk("exit GPCT_Reset\n"); */
5246 }
5247
5248 #endif
5249
5250 static int ni_gpct_insn_config(struct comedi_device *dev,
5251 struct comedi_subdevice *s,
5252 struct comedi_insn *insn, unsigned int *data)
5253 {
5254 struct ni_gpct *counter = s->private;
5255 return ni_tio_insn_config(counter, insn, data);
5256 }
5257
5258 static int ni_gpct_insn_read(struct comedi_device *dev,
5259 struct comedi_subdevice *s,
5260 struct comedi_insn *insn, unsigned int *data)
5261 {
5262 struct ni_gpct *counter = s->private;
5263 return ni_tio_rinsn(counter, insn, data);
5264 }
5265
5266 static int ni_gpct_insn_write(struct comedi_device *dev,
5267 struct comedi_subdevice *s,
5268 struct comedi_insn *insn, unsigned int *data)
5269 {
5270 struct ni_gpct *counter = s->private;
5271 return ni_tio_winsn(counter, insn, data);
5272 }
5273
5274 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5275 {
5276 int retval;
5277 #ifdef PCIDMA
5278 struct ni_gpct *counter = s->private;
5279 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5280
5281 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5282 COMEDI_INPUT);
5283 if (retval) {
5284 comedi_error(dev,
5285 "no dma channel available for use by counter");
5286 return retval;
5287 }
5288 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5289 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5290 retval = ni_tio_cmd(counter, s->async);
5291 #else
5292 retval = -ENOTSUPP;
5293 #endif
5294 return retval;
5295 }
5296
5297 static int ni_gpct_cmdtest(struct comedi_device *dev,
5298 struct comedi_subdevice *s, struct comedi_cmd *cmd)
5299 {
5300 #ifdef PCIDMA
5301 struct ni_gpct *counter = s->private;
5302
5303 return ni_tio_cmdtest(counter, cmd);
5304 #else
5305 return -ENOTSUPP;
5306 #endif
5307 }
5308
5309 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5310 {
5311 #ifdef PCIDMA
5312 struct ni_gpct *counter = s->private;
5313 int retval;
5314
5315 retval = ni_tio_cancel(counter);
5316 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5317 ni_release_gpct_mite_channel(dev, counter->counter_index);
5318 return retval;
5319 #else
5320 return 0;
5321 #endif
5322 }
5323
5324 /*
5325 *
5326 * Programmable Function Inputs
5327 *
5328 */
5329
5330 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5331 unsigned source)
5332 {
5333 struct ni_private *devpriv = dev->private;
5334 unsigned pfi_reg_index;
5335 unsigned array_offset;
5336
5337 if ((source & 0x1f) != source)
5338 return -EINVAL;
5339 pfi_reg_index = 1 + chan / 3;
5340 array_offset = pfi_reg_index - 1;
5341 devpriv->pfi_output_select_reg[array_offset] &=
5342 ~MSeries_PFI_Output_Select_Mask(chan);
5343 devpriv->pfi_output_select_reg[array_offset] |=
5344 MSeries_PFI_Output_Select_Bits(chan, source);
5345 ni_writew(devpriv->pfi_output_select_reg[array_offset],
5346 M_Offset_PFI_Output_Select(pfi_reg_index));
5347 return 2;
5348 }
5349
5350 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5351 unsigned source)
5352 {
5353 /* pre-m-series boards have fixed signals on pfi pins */
5354 if (source != ni_old_get_pfi_routing(dev, chan))
5355 return -EINVAL;
5356 return 2;
5357 }
5358
5359 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5360 unsigned source)
5361 {
5362 if (boardtype.reg_type & ni_reg_m_series_mask)
5363 return ni_m_series_set_pfi_routing(dev, chan, source);
5364 else
5365 return ni_old_set_pfi_routing(dev, chan, source);
5366 }
5367
5368 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5369 unsigned chan)
5370 {
5371 struct ni_private *devpriv = dev->private;
5372 const unsigned array_offset = chan / 3;
5373
5374 return MSeries_PFI_Output_Select_Source(chan,
5375 devpriv->
5376 pfi_output_select_reg
5377 [array_offset]);
5378 }
5379
5380 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5381 {
5382 /* pre-m-series boards have fixed signals on pfi pins */
5383 switch (chan) {
5384 case 0:
5385 return NI_PFI_OUTPUT_AI_START1;
5386 break;
5387 case 1:
5388 return NI_PFI_OUTPUT_AI_START2;
5389 break;
5390 case 2:
5391 return NI_PFI_OUTPUT_AI_CONVERT;
5392 break;
5393 case 3:
5394 return NI_PFI_OUTPUT_G_SRC1;
5395 break;
5396 case 4:
5397 return NI_PFI_OUTPUT_G_GATE1;
5398 break;
5399 case 5:
5400 return NI_PFI_OUTPUT_AO_UPDATE_N;
5401 break;
5402 case 6:
5403 return NI_PFI_OUTPUT_AO_START1;
5404 break;
5405 case 7:
5406 return NI_PFI_OUTPUT_AI_START_PULSE;
5407 break;
5408 case 8:
5409 return NI_PFI_OUTPUT_G_SRC0;
5410 break;
5411 case 9:
5412 return NI_PFI_OUTPUT_G_GATE0;
5413 break;
5414 default:
5415 printk("%s: bug, unhandled case in switch.\n", __func__);
5416 break;
5417 }
5418 return 0;
5419 }
5420
5421 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5422 {
5423 if (boardtype.reg_type & ni_reg_m_series_mask)
5424 return ni_m_series_get_pfi_routing(dev, chan);
5425 else
5426 return ni_old_get_pfi_routing(dev, chan);
5427 }
5428
5429 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5430 enum ni_pfi_filter_select filter)
5431 {
5432 struct ni_private *devpriv __maybe_unused = dev->private;
5433 unsigned bits;
5434
5435 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5436 return -ENOTSUPP;
5437 }
5438 bits = ni_readl(M_Offset_PFI_Filter);
5439 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5440 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5441 ni_writel(bits, M_Offset_PFI_Filter);
5442 return 0;
5443 }
5444
5445 static int ni_pfi_insn_bits(struct comedi_device *dev,
5446 struct comedi_subdevice *s,
5447 struct comedi_insn *insn, unsigned int *data)
5448 {
5449 struct ni_private *devpriv __maybe_unused = dev->private;
5450
5451 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5452 return -ENOTSUPP;
5453 }
5454 if (data[0]) {
5455 s->state &= ~data[0];
5456 s->state |= (data[0] & data[1]);
5457 ni_writew(s->state, M_Offset_PFI_DO);
5458 }
5459 data[1] = ni_readw(M_Offset_PFI_DI);
5460 return insn->n;
5461 }
5462
5463 static int ni_pfi_insn_config(struct comedi_device *dev,
5464 struct comedi_subdevice *s,
5465 struct comedi_insn *insn, unsigned int *data)
5466 {
5467 struct ni_private *devpriv = dev->private;
5468 unsigned int chan;
5469
5470 if (insn->n < 1)
5471 return -EINVAL;
5472
5473 chan = CR_CHAN(insn->chanspec);
5474
5475 switch (data[0]) {
5476 case COMEDI_OUTPUT:
5477 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5478 break;
5479 case COMEDI_INPUT:
5480 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5481 break;
5482 case INSN_CONFIG_DIO_QUERY:
5483 data[1] =
5484 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5485 COMEDI_OUTPUT : COMEDI_INPUT;
5486 return 0;
5487 break;
5488 case INSN_CONFIG_SET_ROUTING:
5489 return ni_set_pfi_routing(dev, chan, data[1]);
5490 break;
5491 case INSN_CONFIG_GET_ROUTING:
5492 data[1] = ni_get_pfi_routing(dev, chan);
5493 break;
5494 case INSN_CONFIG_FILTER:
5495 return ni_config_filter(dev, chan, data[1]);
5496 break;
5497 default:
5498 return -EINVAL;
5499 }
5500 return 0;
5501 }
5502
5503 /*
5504 *
5505 * NI RTSI Bus Functions
5506 *
5507 */
5508 static void ni_rtsi_init(struct comedi_device *dev)
5509 {
5510 struct ni_private *devpriv = dev->private;
5511
5512 /* Initialises the RTSI bus signal switch to a default state */
5513
5514 /* Set clock mode to internal */
5515 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5516 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5517 printk("ni_set_master_clock failed, bug?");
5518 }
5519 /* default internal lines routing to RTSI bus lines */
5520 devpriv->rtsi_trig_a_output_reg =
5521 RTSI_Trig_Output_Bits(0,
5522 NI_RTSI_OUTPUT_ADR_START1) |
5523 RTSI_Trig_Output_Bits(1,
5524 NI_RTSI_OUTPUT_ADR_START2) |
5525 RTSI_Trig_Output_Bits(2,
5526 NI_RTSI_OUTPUT_SCLKG) |
5527 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5528 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5529 RTSI_Trig_A_Output_Register);
5530 devpriv->rtsi_trig_b_output_reg =
5531 RTSI_Trig_Output_Bits(4,
5532 NI_RTSI_OUTPUT_DA_START1) |
5533 RTSI_Trig_Output_Bits(5,
5534 NI_RTSI_OUTPUT_G_SRC0) |
5535 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5536 if (boardtype.reg_type & ni_reg_m_series_mask)
5537 devpriv->rtsi_trig_b_output_reg |=
5538 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5539 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5540 RTSI_Trig_B_Output_Register);
5541
5542 /*
5543 * Sets the source and direction of the 4 on board lines
5544 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5545 */
5546 }
5547
5548 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5549 struct comedi_subdevice *s,
5550 struct comedi_insn *insn, unsigned int *data)
5551 {
5552 data[1] = 0;
5553
5554 return insn->n;
5555 }
5556
5557 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5558 * given an arbitrary frequency input clock */
5559 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5560 unsigned *freq_divider,
5561 unsigned *freq_multiplier,
5562 unsigned *actual_period_ns)
5563 {
5564 unsigned div;
5565 unsigned best_div = 1;
5566 static const unsigned max_div = 0x10;
5567 unsigned mult;
5568 unsigned best_mult = 1;
5569 static const unsigned max_mult = 0x100;
5570 static const unsigned pico_per_nano = 1000;
5571
5572 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5573 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5574 * 20 MHz for most timing clocks */
5575 static const unsigned target_picosec = 12500;
5576 static const unsigned fudge_factor_80_to_20Mhz = 4;
5577 int best_period_picosec = 0;
5578 for (div = 1; div <= max_div; ++div) {
5579 for (mult = 1; mult <= max_mult; ++mult) {
5580 unsigned new_period_ps =
5581 (reference_picosec * div) / mult;
5582 if (abs(new_period_ps - target_picosec) <
5583 abs(best_period_picosec - target_picosec)) {
5584 best_period_picosec = new_period_ps;
5585 best_div = div;
5586 best_mult = mult;
5587 }
5588 }
5589 }
5590 if (best_period_picosec == 0) {
5591 printk("%s: bug, failed to find pll parameters\n", __func__);
5592 return -EIO;
5593 }
5594 *freq_divider = best_div;
5595 *freq_multiplier = best_mult;
5596 *actual_period_ns =
5597 (best_period_picosec * fudge_factor_80_to_20Mhz +
5598 (pico_per_nano / 2)) / pico_per_nano;
5599 return 0;
5600 }
5601
5602 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5603 {
5604 if (boardtype.reg_type & ni_reg_m_series_mask)
5605 return 8;
5606 else
5607 return 7;
5608 }
5609
5610 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5611 unsigned source, unsigned period_ns)
5612 {
5613 struct ni_private *devpriv = dev->private;
5614 static const unsigned min_period_ns = 50;
5615 static const unsigned max_period_ns = 1000;
5616 static const unsigned timeout = 1000;
5617 unsigned pll_control_bits;
5618 unsigned freq_divider;
5619 unsigned freq_multiplier;
5620 unsigned i;
5621 int retval;
5622
5623 if (source == NI_MIO_PLL_PXI10_CLOCK)
5624 period_ns = 100;
5625 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5626 if (period_ns < min_period_ns || period_ns > max_period_ns) {
5627 printk
5628 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5629 "for the phased-lock loop.\n", __func__,
5630 min_period_ns, max_period_ns);
5631 return -EINVAL;
5632 }
5633 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5634 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5635 RTSI_Trig_Direction_Register);
5636 pll_control_bits =
5637 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5638 devpriv->clock_and_fout2 |=
5639 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5640 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5641 switch (source) {
5642 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5643 devpriv->clock_and_fout2 |=
5644 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5645 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5646 &freq_multiplier,
5647 &devpriv->clock_ns);
5648 if (retval < 0)
5649 return retval;
5650 break;
5651 case NI_MIO_PLL_PXI10_CLOCK:
5652 /* pxi clock is 10MHz */
5653 devpriv->clock_and_fout2 |=
5654 MSeries_PLL_In_Source_Select_PXI_Clock10;
5655 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5656 &freq_multiplier,
5657 &devpriv->clock_ns);
5658 if (retval < 0)
5659 return retval;
5660 break;
5661 default:
5662 {
5663 unsigned rtsi_channel;
5664 static const unsigned max_rtsi_channel = 7;
5665 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5666 ++rtsi_channel) {
5667 if (source ==
5668 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5669 devpriv->clock_and_fout2 |=
5670 MSeries_PLL_In_Source_Select_RTSI_Bits
5671 (rtsi_channel);
5672 break;
5673 }
5674 }
5675 if (rtsi_channel > max_rtsi_channel)
5676 return -EINVAL;
5677 retval = ni_mseries_get_pll_parameters(period_ns,
5678 &freq_divider,
5679 &freq_multiplier,
5680 &devpriv->
5681 clock_ns);
5682 if (retval < 0)
5683 return retval;
5684 }
5685 break;
5686 }
5687 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5688 pll_control_bits |=
5689 MSeries_PLL_Divisor_Bits(freq_divider) |
5690 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5691
5692 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5693 * freq_divider, freq_multiplier, pll_control_bits); */
5694 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5695 ni_writew(pll_control_bits, M_Offset_PLL_Control);
5696 devpriv->clock_source = source;
5697 /* it seems to typically take a few hundred microseconds for PLL to lock */
5698 for (i = 0; i < timeout; ++i) {
5699 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5700 break;
5701 }
5702 udelay(1);
5703 }
5704 if (i == timeout) {
5705 printk
5706 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5707 __func__, source, period_ns);
5708 return -ETIMEDOUT;
5709 }
5710 return 3;
5711 }
5712
5713 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5714 unsigned period_ns)
5715 {
5716 struct ni_private *devpriv = dev->private;
5717
5718 if (source == NI_MIO_INTERNAL_CLOCK) {
5719 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5720 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5721 RTSI_Trig_Direction_Register);
5722 devpriv->clock_ns = TIMEBASE_1_NS;
5723 if (boardtype.reg_type & ni_reg_m_series_mask) {
5724 devpriv->clock_and_fout2 &=
5725 ~(MSeries_Timebase1_Select_Bit |
5726 MSeries_Timebase3_Select_Bit);
5727 ni_writew(devpriv->clock_and_fout2,
5728 M_Offset_Clock_and_Fout2);
5729 ni_writew(0, M_Offset_PLL_Control);
5730 }
5731 devpriv->clock_source = source;
5732 } else {
5733 if (boardtype.reg_type & ni_reg_m_series_mask) {
5734 return ni_mseries_set_pll_master_clock(dev, source,
5735 period_ns);
5736 } else {
5737 if (source == NI_MIO_RTSI_CLOCK) {
5738 devpriv->rtsi_trig_direction_reg |=
5739 Use_RTSI_Clock_Bit;
5740 devpriv->stc_writew(dev,
5741 devpriv->
5742 rtsi_trig_direction_reg,
5743 RTSI_Trig_Direction_Register);
5744 if (period_ns == 0) {
5745 printk
5746 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5747 __func__);
5748 return -EINVAL;
5749 } else {
5750 devpriv->clock_ns = period_ns;
5751 }
5752 devpriv->clock_source = source;
5753 } else
5754 return -EINVAL;
5755 }
5756 }
5757 return 3;
5758 }
5759
5760 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5761 unsigned source)
5762 {
5763 if (chan >= num_configurable_rtsi_channels(dev)) {
5764 if (chan == old_RTSI_clock_channel) {
5765 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5766 return 1;
5767 else {
5768 printk
5769 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5770 __func__, chan, old_RTSI_clock_channel);
5771 return 0;
5772 }
5773 }
5774 return 0;
5775 }
5776 switch (source) {
5777 case NI_RTSI_OUTPUT_ADR_START1:
5778 case NI_RTSI_OUTPUT_ADR_START2:
5779 case NI_RTSI_OUTPUT_SCLKG:
5780 case NI_RTSI_OUTPUT_DACUPDN:
5781 case NI_RTSI_OUTPUT_DA_START1:
5782 case NI_RTSI_OUTPUT_G_SRC0:
5783 case NI_RTSI_OUTPUT_G_GATE0:
5784 case NI_RTSI_OUTPUT_RGOUT0:
5785 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5786 return 1;
5787 break;
5788 case NI_RTSI_OUTPUT_RTSI_OSC:
5789 if (boardtype.reg_type & ni_reg_m_series_mask)
5790 return 1;
5791 else
5792 return 0;
5793 break;
5794 default:
5795 return 0;
5796 break;
5797 }
5798 }
5799
5800 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5801 unsigned source)
5802 {
5803 struct ni_private *devpriv = dev->private;
5804
5805 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5806 return -EINVAL;
5807 if (chan < 4) {
5808 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5809 devpriv->rtsi_trig_a_output_reg |=
5810 RTSI_Trig_Output_Bits(chan, source);
5811 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5812 RTSI_Trig_A_Output_Register);
5813 } else if (chan < 8) {
5814 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5815 devpriv->rtsi_trig_b_output_reg |=
5816 RTSI_Trig_Output_Bits(chan, source);
5817 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5818 RTSI_Trig_B_Output_Register);
5819 }
5820 return 2;
5821 }
5822
5823 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5824 {
5825 struct ni_private *devpriv = dev->private;
5826
5827 if (chan < 4) {
5828 return RTSI_Trig_Output_Source(chan,
5829 devpriv->rtsi_trig_a_output_reg);
5830 } else if (chan < num_configurable_rtsi_channels(dev)) {
5831 return RTSI_Trig_Output_Source(chan,
5832 devpriv->rtsi_trig_b_output_reg);
5833 } else {
5834 if (chan == old_RTSI_clock_channel)
5835 return NI_RTSI_OUTPUT_RTSI_OSC;
5836 printk("%s: bug! should never get here?\n", __func__);
5837 return 0;
5838 }
5839 }
5840
5841 static int ni_rtsi_insn_config(struct comedi_device *dev,
5842 struct comedi_subdevice *s,
5843 struct comedi_insn *insn, unsigned int *data)
5844 {
5845 struct ni_private *devpriv = dev->private;
5846 unsigned int chan = CR_CHAN(insn->chanspec);
5847
5848 switch (data[0]) {
5849 case INSN_CONFIG_DIO_OUTPUT:
5850 if (chan < num_configurable_rtsi_channels(dev)) {
5851 devpriv->rtsi_trig_direction_reg |=
5852 RTSI_Output_Bit(chan,
5853 (boardtype.
5854 reg_type & ni_reg_m_series_mask) !=
5855 0);
5856 } else if (chan == old_RTSI_clock_channel) {
5857 devpriv->rtsi_trig_direction_reg |=
5858 Drive_RTSI_Clock_Bit;
5859 }
5860 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5861 RTSI_Trig_Direction_Register);
5862 break;
5863 case INSN_CONFIG_DIO_INPUT:
5864 if (chan < num_configurable_rtsi_channels(dev)) {
5865 devpriv->rtsi_trig_direction_reg &=
5866 ~RTSI_Output_Bit(chan,
5867 (boardtype.
5868 reg_type & ni_reg_m_series_mask)
5869 != 0);
5870 } else if (chan == old_RTSI_clock_channel) {
5871 devpriv->rtsi_trig_direction_reg &=
5872 ~Drive_RTSI_Clock_Bit;
5873 }
5874 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5875 RTSI_Trig_Direction_Register);
5876 break;
5877 case INSN_CONFIG_DIO_QUERY:
5878 if (chan < num_configurable_rtsi_channels(dev)) {
5879 data[1] =
5880 (devpriv->rtsi_trig_direction_reg &
5881 RTSI_Output_Bit(chan,
5882 (boardtype.reg_type &
5883 ni_reg_m_series_mask)
5884 != 0)) ? INSN_CONFIG_DIO_OUTPUT :
5885 INSN_CONFIG_DIO_INPUT;
5886 } else if (chan == old_RTSI_clock_channel) {
5887 data[1] =
5888 (devpriv->rtsi_trig_direction_reg &
5889 Drive_RTSI_Clock_Bit)
5890 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5891 }
5892 return 2;
5893 break;
5894 case INSN_CONFIG_SET_CLOCK_SRC:
5895 return ni_set_master_clock(dev, data[1], data[2]);
5896 break;
5897 case INSN_CONFIG_GET_CLOCK_SRC:
5898 data[1] = devpriv->clock_source;
5899 data[2] = devpriv->clock_ns;
5900 return 3;
5901 break;
5902 case INSN_CONFIG_SET_ROUTING:
5903 return ni_set_rtsi_routing(dev, chan, data[1]);
5904 break;
5905 case INSN_CONFIG_GET_ROUTING:
5906 data[1] = ni_get_rtsi_routing(dev, chan);
5907 return 2;
5908 break;
5909 default:
5910 return -EINVAL;
5911 break;
5912 }
5913 return 1;
5914 }
5915
5916 static int cs5529_wait_for_idle(struct comedi_device *dev)
5917 {
5918 unsigned short status;
5919 const int timeout = HZ;
5920 int i;
5921
5922 for (i = 0; i < timeout; i++) {
5923 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5924 if ((status & CSS_ADC_BUSY) == 0) {
5925 break;
5926 }
5927 set_current_state(TASK_INTERRUPTIBLE);
5928 if (schedule_timeout(1)) {
5929 return -EIO;
5930 }
5931 }
5932 /* printk("looped %i times waiting for idle\n", i); */
5933 if (i == timeout) {
5934 printk("%s: %s: timeout\n", __FILE__, __func__);
5935 return -ETIME;
5936 }
5937 return 0;
5938 }
5939
5940 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5941 {
5942 static const int timeout = 100;
5943 int i;
5944
5945 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5946 /* give time for command to start being serially clocked into cs5529.
5947 * this insures that the CSS_ADC_BUSY bit will get properly
5948 * set before we exit this function.
5949 */
5950 for (i = 0; i < timeout; i++) {
5951 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5952 break;
5953 udelay(1);
5954 }
5955 /* printk("looped %i times writing command to cs5529\n", i); */
5956 if (i == timeout) {
5957 comedi_error(dev, "possible problem - never saw adc go busy?");
5958 }
5959 }
5960
5961 /* write to cs5529 register */
5962 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5963 unsigned int reg_select_bits)
5964 {
5965 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5966 CAL_ADC_Config_Data_High_Word_67xx);
5967 ni_ao_win_outw(dev, (value & 0xffff),
5968 CAL_ADC_Config_Data_Low_Word_67xx);
5969 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5970 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5971 if (cs5529_wait_for_idle(dev))
5972 comedi_error(dev, "time or signal in cs5529_config_write()");
5973 }
5974
5975 #ifdef NI_CS5529_DEBUG
5976 /* read from cs5529 register */
5977 static unsigned int cs5529_config_read(struct comedi_device *dev,
5978 unsigned int reg_select_bits)
5979 {
5980 unsigned int value;
5981
5982 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5983 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5984 if (cs5529_wait_for_idle(dev))
5985 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5986 value = (ni_ao_win_inw(dev,
5987 CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5988 0xff0000;
5989 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5990 return value;
5991 }
5992 #endif
5993
5994 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5995 {
5996 int retval;
5997 unsigned short status;
5998
5999 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
6000 retval = cs5529_wait_for_idle(dev);
6001 if (retval) {
6002 comedi_error(dev,
6003 "timeout or signal in cs5529_do_conversion()");
6004 return -ETIME;
6005 }
6006 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
6007 if (status & CSS_OSC_DETECT) {
6008 printk
6009 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
6010 return -EIO;
6011 }
6012 if (status & CSS_OVERRANGE) {
6013 printk
6014 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
6015 }
6016 if (data) {
6017 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
6018 /* cs5529 returns 16 bit signed data in bipolar mode */
6019 *data ^= (1 << 15);
6020 }
6021 return 0;
6022 }
6023
6024 static int cs5529_ai_insn_read(struct comedi_device *dev,
6025 struct comedi_subdevice *s,
6026 struct comedi_insn *insn, unsigned int *data)
6027 {
6028 int n, retval;
6029 unsigned short sample;
6030 unsigned int channel_select;
6031 const unsigned int INTERNAL_REF = 0x1000;
6032
6033 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
6034 * do nothing. bit 12 seems to chooses internal reference voltage, bit
6035 * 13 causes the adc input to go overrange (maybe reads external reference?) */
6036 if (insn->chanspec & CR_ALT_SOURCE)
6037 channel_select = INTERNAL_REF;
6038 else
6039 channel_select = CR_CHAN(insn->chanspec);
6040 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
6041
6042 for (n = 0; n < insn->n; n++) {
6043 retval = cs5529_do_conversion(dev, &sample);
6044 if (retval < 0)
6045 return retval;
6046 data[n] = sample;
6047 }
6048 return insn->n;
6049 }
6050
6051 static int init_cs5529(struct comedi_device *dev)
6052 {
6053 unsigned int config_bits =
6054 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
6055
6056 #if 1
6057 /* do self-calibration */
6058 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
6059 CSCMD_CONFIG_REGISTER);
6060 /* need to force a conversion for calibration to run */
6061 cs5529_do_conversion(dev, NULL);
6062 #else
6063 /* force gain calibration to 1 */
6064 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
6065 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
6066 CSCMD_CONFIG_REGISTER);
6067 if (cs5529_wait_for_idle(dev))
6068 comedi_error(dev, "timeout or signal in init_cs5529()\n");
6069 #endif
6070 #ifdef NI_CS5529_DEBUG
6071 printk("config: 0x%x\n", cs5529_config_read(dev,
6072 CSCMD_CONFIG_REGISTER));
6073 printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
6074 printk("offset: 0x%x\n", cs5529_config_read(dev,
6075 CSCMD_OFFSET_REGISTER));
6076 #endif
6077 return 0;
6078 }
Linux kernel - Deliverables
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