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staging: comedi: remove FSF address from boilerplate text
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_mio_common.c
1 /*
2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18 */
19
20 /*
21 This file is meant to be included by another file, e.g.,
22 ni_atmio.c or ni_pcimio.c.
23
24 Interrupt support originally added by Truxton Fulton
25 <trux@truxton.com>
26
27 References (from ftp://ftp.natinst.com/support/manuals):
28
29 340747b.pdf AT-MIO E series Register Level Programmer Manual
30 341079b.pdf PCI E Series RLPM
31 340934b.pdf DAQ-STC reference manual
32 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
33 release_ni611x.pdf
34 release_ni67xx.pdf
35 Other possibly relevant info:
36
37 320517c.pdf User manual (obsolete)
38 320517f.pdf User manual (new)
39 320889a.pdf delete
40 320906c.pdf maximum signal ratings
41 321066a.pdf about 16x
42 321791a.pdf discontinuation of at-mio-16e-10 rev. c
43 321808a.pdf about at-mio-16e-10 rev P
44 321837a.pdf discontinuation of at-mio-16de-10 rev d
45 321838a.pdf about at-mio-16de-10 rev N
46
47 ISSUES:
48
49 - the interrupt routine needs to be cleaned up
50
51 2006-02-07: S-Series PCI-6143: Support has been added but is not
52 fully tested as yet. Terry Barnaby, BEAM Ltd.
53 */
54
55 /* #define DEBUG_INTERRUPT */
56 /* #define DEBUG_STATUS_A */
57 /* #define DEBUG_STATUS_B */
58
59 #include <linux/interrupt.h>
60 #include <linux/sched.h>
61 #include "8255.h"
62 #include "mite.h"
63 #include "comedi_fc.h"
64
65 #ifndef MDPRINTK
66 #define MDPRINTK(format, args...)
67 #endif
68
69 /* A timeout count */
70 #define NI_TIMEOUT 1000
71 static const unsigned old_RTSI_clock_channel = 7;
72
73 /* Note: this table must match the ai_gain_* definitions */
74 static const short ni_gainlkup[][16] = {
75 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
76 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
77 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
78 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
79 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
80 [ai_gain_4] = {0, 1, 4, 7},
81 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
82 0x003, 0x004, 0x005, 0x006},
83 [ai_gain_622x] = {0, 1, 4, 5},
84 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
85 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
86 };
87
88 static const struct comedi_lrange range_ni_E_ai = { 16, {
89 RANGE(-10, 10),
90 RANGE(-5, 5),
91 RANGE(-2.5, 2.5),
92 RANGE(-1, 1),
93 RANGE(-0.5, 0.5),
94 RANGE(-0.25, 0.25),
95 RANGE(-0.1, 0.1),
96 RANGE(-0.05, 0.05),
97 RANGE(0, 20),
98 RANGE(0, 10),
99 RANGE(0, 5),
100 RANGE(0, 2),
101 RANGE(0, 1),
102 RANGE(0, 0.5),
103 RANGE(0, 0.2),
104 RANGE(0, 0.1),
105 }
106 };
107
108 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
109 RANGE(-10, 10),
110 RANGE(-5, 5),
111 RANGE(-1, 1),
112 RANGE(-0.1,
113 0.1),
114 RANGE(0, 10),
115 RANGE(0, 5),
116 RANGE(0, 1),
117 RANGE(0, 0.1),
118 }
119 };
120
121 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
122 RANGE(-10,
123 10),
124 RANGE(-5, 5),
125 RANGE(-2, 2),
126 RANGE(-1, 1),
127 RANGE(-0.5,
128 0.5),
129 RANGE(-0.2,
130 0.2),
131 RANGE(-0.1,
132 0.1),
133 RANGE(0, 10),
134 RANGE(0, 5),
135 RANGE(0, 2),
136 RANGE(0, 1),
137 RANGE(0,
138 0.5),
139 RANGE(0,
140 0.2),
141 RANGE(0,
142 0.1),
143 }
144 };
145
146 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
147 RANGE(-10, 10),
148 RANGE(-5, 5),
149 RANGE(-0.5,
150 0.5),
151 RANGE(-0.05,
152 0.05),
153 }
154 };
155
156 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
157 RANGE(-50, 50),
158 RANGE(-20, 20),
159 RANGE(-10, 10),
160 RANGE(-5, 5),
161 RANGE(-2, 2),
162 RANGE(-1, 1),
163 RANGE(-0.5, 0.5),
164 RANGE(-0.2, 0.2),
165 }
166 };
167
168 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
169 RANGE(-10, 10),
170 RANGE(-5, 5),
171 RANGE(-1, 1),
172 RANGE(-0.2, 0.2),
173 }
174 };
175
176 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
177 RANGE(-10, 10),
178 RANGE(-5, 5),
179 RANGE(-2, 2),
180 RANGE(-1, 1),
181 RANGE(-0.5, 0.5),
182 RANGE(-0.2, 0.2),
183 RANGE(-0.1, 0.1),
184 }
185 };
186
187 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
188 RANGE(-10, 10),
189 RANGE(0, 10),
190 RANGE_ext(-1, 1),
191 RANGE_ext(0, 1),
192 }
193 };
194
195 static const struct comedi_lrange *const ni_range_lkup[] = {
196 [ai_gain_16] = &range_ni_E_ai,
197 [ai_gain_8] = &range_ni_E_ai_limited,
198 [ai_gain_14] = &range_ni_E_ai_limited14,
199 [ai_gain_4] = &range_ni_E_ai_bipolar4,
200 [ai_gain_611x] = &range_ni_E_ai_611x,
201 [ai_gain_622x] = &range_ni_M_ai_622x,
202 [ai_gain_628x] = &range_ni_M_ai_628x,
203 [ai_gain_6143] = &range_bipolar5
204 };
205
206 static int ni_dio_insn_config(struct comedi_device *dev,
207 struct comedi_subdevice *s,
208 struct comedi_insn *insn, unsigned int *data);
209 static int ni_dio_insn_bits(struct comedi_device *dev,
210 struct comedi_subdevice *s,
211 struct comedi_insn *insn, unsigned int *data);
212 static int ni_cdio_cmdtest(struct comedi_device *dev,
213 struct comedi_subdevice *s, struct comedi_cmd *cmd);
214 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
215 static int ni_cdio_cancel(struct comedi_device *dev,
216 struct comedi_subdevice *s);
217 static void handle_cdio_interrupt(struct comedi_device *dev);
218 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
219 unsigned int trignum);
220
221 static int ni_serial_insn_config(struct comedi_device *dev,
222 struct comedi_subdevice *s,
223 struct comedi_insn *insn, unsigned int *data);
224 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
225 struct comedi_subdevice *s,
226 unsigned char data_out,
227 unsigned char *data_in);
228 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
229 struct comedi_subdevice *s,
230 unsigned char data_out,
231 unsigned char *data_in);
232
233 static int ni_calib_insn_read(struct comedi_device *dev,
234 struct comedi_subdevice *s,
235 struct comedi_insn *insn, unsigned int *data);
236 static int ni_calib_insn_write(struct comedi_device *dev,
237 struct comedi_subdevice *s,
238 struct comedi_insn *insn, unsigned int *data);
239
240 static int ni_eeprom_insn_read(struct comedi_device *dev,
241 struct comedi_subdevice *s,
242 struct comedi_insn *insn, unsigned int *data);
243 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
244 struct comedi_subdevice *s,
245 struct comedi_insn *insn,
246 unsigned int *data);
247
248 static int ni_pfi_insn_bits(struct comedi_device *dev,
249 struct comedi_subdevice *s,
250 struct comedi_insn *insn, unsigned int *data);
251 static int ni_pfi_insn_config(struct comedi_device *dev,
252 struct comedi_subdevice *s,
253 struct comedi_insn *insn, unsigned int *data);
254 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
255 unsigned chan);
256
257 static void ni_rtsi_init(struct comedi_device *dev);
258 static int ni_rtsi_insn_bits(struct comedi_device *dev,
259 struct comedi_subdevice *s,
260 struct comedi_insn *insn, unsigned int *data);
261 static int ni_rtsi_insn_config(struct comedi_device *dev,
262 struct comedi_subdevice *s,
263 struct comedi_insn *insn, unsigned int *data);
264
265 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
266 static int ni_read_eeprom(struct comedi_device *dev, int addr);
267
268 #ifdef DEBUG_STATUS_A
269 static void ni_mio_print_status_a(int status);
270 #else
271 #define ni_mio_print_status_a(a)
272 #endif
273 #ifdef DEBUG_STATUS_B
274 static void ni_mio_print_status_b(int status);
275 #else
276 #define ni_mio_print_status_b(a)
277 #endif
278
279 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
280 #ifndef PCIDMA
281 static void ni_handle_fifo_half_full(struct comedi_device *dev);
282 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
283 struct comedi_subdevice *s);
284 #endif
285 static void ni_handle_fifo_dregs(struct comedi_device *dev);
286 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
287 unsigned int trignum);
288 static void ni_load_channelgain_list(struct comedi_device *dev,
289 unsigned int n_chan, unsigned int *list);
290 static void shutdown_ai_command(struct comedi_device *dev);
291
292 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
293 unsigned int trignum);
294
295 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
296
297 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
298
299 static int ni_gpct_insn_write(struct comedi_device *dev,
300 struct comedi_subdevice *s,
301 struct comedi_insn *insn, unsigned int *data);
302 static int ni_gpct_insn_read(struct comedi_device *dev,
303 struct comedi_subdevice *s,
304 struct comedi_insn *insn, unsigned int *data);
305 static int ni_gpct_insn_config(struct comedi_device *dev,
306 struct comedi_subdevice *s,
307 struct comedi_insn *insn, unsigned int *data);
308 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
309 static int ni_gpct_cmdtest(struct comedi_device *dev,
310 struct comedi_subdevice *s, struct comedi_cmd *cmd);
311 static int ni_gpct_cancel(struct comedi_device *dev,
312 struct comedi_subdevice *s);
313 static void handle_gpct_interrupt(struct comedi_device *dev,
314 unsigned short counter_index);
315
316 static int init_cs5529(struct comedi_device *dev);
317 static int cs5529_do_conversion(struct comedi_device *dev,
318 unsigned short *data);
319 static int cs5529_ai_insn_read(struct comedi_device *dev,
320 struct comedi_subdevice *s,
321 struct comedi_insn *insn, unsigned int *data);
322 #ifdef NI_CS5529_DEBUG
323 static unsigned int cs5529_config_read(struct comedi_device *dev,
324 unsigned int reg_select_bits);
325 #endif
326 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
327 unsigned int reg_select_bits);
328
329 static int ni_m_series_pwm_config(struct comedi_device *dev,
330 struct comedi_subdevice *s,
331 struct comedi_insn *insn, unsigned int *data);
332 static int ni_6143_pwm_config(struct comedi_device *dev,
333 struct comedi_subdevice *s,
334 struct comedi_insn *insn, unsigned int *data);
335
336 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
337 unsigned period_ns);
338 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
339 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
340
341 enum aimodes {
342 AIMODE_NONE = 0,
343 AIMODE_HALF_FULL = 1,
344 AIMODE_SCAN = 2,
345 AIMODE_SAMPLE = 3,
346 };
347
348 enum ni_common_subdevices {
349 NI_AI_SUBDEV,
350 NI_AO_SUBDEV,
351 NI_DIO_SUBDEV,
352 NI_8255_DIO_SUBDEV,
353 NI_UNUSED_SUBDEV,
354 NI_CALIBRATION_SUBDEV,
355 NI_EEPROM_SUBDEV,
356 NI_PFI_DIO_SUBDEV,
357 NI_CS5529_CALIBRATION_SUBDEV,
358 NI_SERIAL_SUBDEV,
359 NI_RTSI_SUBDEV,
360 NI_GPCT0_SUBDEV,
361 NI_GPCT1_SUBDEV,
362 NI_FREQ_OUT_SUBDEV,
363 NI_NUM_SUBDEVICES
364 };
365 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
366 {
367 switch (counter_index) {
368 case 0:
369 return NI_GPCT0_SUBDEV;
370 break;
371 case 1:
372 return NI_GPCT1_SUBDEV;
373 break;
374 default:
375 break;
376 }
377 BUG();
378 return NI_GPCT0_SUBDEV;
379 }
380
381 enum timebase_nanoseconds {
382 TIMEBASE_1_NS = 50,
383 TIMEBASE_2_NS = 10000
384 };
385
386 #define SERIAL_DISABLED 0
387 #define SERIAL_600NS 600
388 #define SERIAL_1_2US 1200
389 #define SERIAL_10US 10000
390
391 static const int num_adc_stages_611x = 3;
392
393 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
394 unsigned ai_mite_status);
395 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
396 unsigned ao_mite_status);
397 static void get_last_sample_611x(struct comedi_device *dev);
398 static void get_last_sample_6143(struct comedi_device *dev);
399
400 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
401 unsigned bit_mask, unsigned bit_values)
402 {
403 struct ni_private *devpriv = dev->private;
404 unsigned long flags;
405
406 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
407 switch (reg) {
408 case Interrupt_A_Enable_Register:
409 devpriv->int_a_enable_reg &= ~bit_mask;
410 devpriv->int_a_enable_reg |= bit_values & bit_mask;
411 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
412 Interrupt_A_Enable_Register);
413 break;
414 case Interrupt_B_Enable_Register:
415 devpriv->int_b_enable_reg &= ~bit_mask;
416 devpriv->int_b_enable_reg |= bit_values & bit_mask;
417 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
418 Interrupt_B_Enable_Register);
419 break;
420 case IO_Bidirection_Pin_Register:
421 devpriv->io_bidirection_pin_reg &= ~bit_mask;
422 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
423 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
424 IO_Bidirection_Pin_Register);
425 break;
426 case AI_AO_Select:
427 devpriv->ai_ao_select_reg &= ~bit_mask;
428 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
429 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
430 break;
431 case G0_G1_Select:
432 devpriv->g0_g1_select_reg &= ~bit_mask;
433 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
434 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
435 break;
436 default:
437 printk("Warning %s() called with invalid register\n", __func__);
438 printk("reg is %d\n", reg);
439 break;
440 }
441 mmiowb();
442 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
443 }
444
445 #ifdef PCIDMA
446 static int ni_ai_drain_dma(struct comedi_device *dev);
447
448 /* DMA channel setup */
449
450 /* negative channel means no channel */
451 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
452 {
453 unsigned bitfield;
454
455 if (channel >= 0) {
456 bitfield =
457 (ni_stc_dma_channel_select_bitfield(channel) <<
458 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
459 } else {
460 bitfield = 0;
461 }
462 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
463 }
464
465 /* negative channel means no channel */
466 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
467 {
468 unsigned bitfield;
469
470 if (channel >= 0) {
471 bitfield =
472 (ni_stc_dma_channel_select_bitfield(channel) <<
473 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
474 } else {
475 bitfield = 0;
476 }
477 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
478 }
479
480 /* negative mite_channel means no channel */
481 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
482 unsigned gpct_index,
483 int mite_channel)
484 {
485 unsigned bitfield;
486
487 if (mite_channel >= 0) {
488 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
489 } else {
490 bitfield = 0;
491 }
492 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
493 bitfield);
494 }
495
496 /* negative mite_channel means no channel */
497 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
498 int mite_channel)
499 {
500 struct ni_private *devpriv = dev->private;
501 unsigned long flags;
502
503 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
504 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
505 if (mite_channel >= 0) {
506 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
507 under the assumption the cdio dma selection works just like ai/ao/gpct.
508 Definitely works for dma channels 0 and 1. */
509 devpriv->cdio_dma_select_reg |=
510 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
511 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
512 }
513 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
514 mmiowb();
515 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
516 }
517
518 static int ni_request_ai_mite_channel(struct comedi_device *dev)
519 {
520 struct ni_private *devpriv = dev->private;
521 unsigned long flags;
522
523 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
524 BUG_ON(devpriv->ai_mite_chan);
525 devpriv->ai_mite_chan =
526 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
527 if (devpriv->ai_mite_chan == NULL) {
528 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
529 comedi_error(dev,
530 "failed to reserve mite dma channel for analog input.");
531 return -EBUSY;
532 }
533 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
534 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
535 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
536 return 0;
537 }
538
539 static int ni_request_ao_mite_channel(struct comedi_device *dev)
540 {
541 struct ni_private *devpriv = dev->private;
542 unsigned long flags;
543
544 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
545 BUG_ON(devpriv->ao_mite_chan);
546 devpriv->ao_mite_chan =
547 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
548 if (devpriv->ao_mite_chan == NULL) {
549 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
550 comedi_error(dev,
551 "failed to reserve mite dma channel for analog outut.");
552 return -EBUSY;
553 }
554 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
555 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
556 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
557 return 0;
558 }
559
560 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
561 unsigned gpct_index,
562 enum comedi_io_direction direction)
563 {
564 struct ni_private *devpriv = dev->private;
565 unsigned long flags;
566 struct mite_channel *mite_chan;
567
568 BUG_ON(gpct_index >= NUM_GPCT);
569 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
570 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
571 mite_chan =
572 mite_request_channel(devpriv->mite,
573 devpriv->gpct_mite_ring[gpct_index]);
574 if (mite_chan == NULL) {
575 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
576 comedi_error(dev,
577 "failed to reserve mite dma channel for counter.");
578 return -EBUSY;
579 }
580 mite_chan->dir = direction;
581 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
582 mite_chan);
583 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
584 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
585 return 0;
586 }
587
588 #endif /* PCIDMA */
589
590 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
591 {
592 #ifdef PCIDMA
593 struct ni_private *devpriv = dev->private;
594 unsigned long flags;
595
596 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
597 BUG_ON(devpriv->cdo_mite_chan);
598 devpriv->cdo_mite_chan =
599 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
600 if (devpriv->cdo_mite_chan == NULL) {
601 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
602 comedi_error(dev,
603 "failed to reserve mite dma channel for correlated digital outut.");
604 return -EBUSY;
605 }
606 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
607 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
608 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
609 #endif /* PCIDMA */
610 return 0;
611 }
612
613 static void ni_release_ai_mite_channel(struct comedi_device *dev)
614 {
615 #ifdef PCIDMA
616 struct ni_private *devpriv = dev->private;
617 unsigned long flags;
618
619 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
620 if (devpriv->ai_mite_chan) {
621 ni_set_ai_dma_channel(dev, -1);
622 mite_release_channel(devpriv->ai_mite_chan);
623 devpriv->ai_mite_chan = NULL;
624 }
625 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
626 #endif /* PCIDMA */
627 }
628
629 static void ni_release_ao_mite_channel(struct comedi_device *dev)
630 {
631 #ifdef PCIDMA
632 struct ni_private *devpriv = dev->private;
633 unsigned long flags;
634
635 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
636 if (devpriv->ao_mite_chan) {
637 ni_set_ao_dma_channel(dev, -1);
638 mite_release_channel(devpriv->ao_mite_chan);
639 devpriv->ao_mite_chan = NULL;
640 }
641 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
642 #endif /* PCIDMA */
643 }
644
645 #ifdef PCIDMA
646 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
647 unsigned gpct_index)
648 {
649 struct ni_private *devpriv = dev->private;
650 unsigned long flags;
651
652 BUG_ON(gpct_index >= NUM_GPCT);
653 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
654 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
655 struct mite_channel *mite_chan =
656 devpriv->counter_dev->counters[gpct_index].mite_chan;
657
658 ni_set_gpct_dma_channel(dev, gpct_index, -1);
659 ni_tio_set_mite_channel(&devpriv->
660 counter_dev->counters[gpct_index],
661 NULL);
662 mite_release_channel(mite_chan);
663 }
664 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
665 }
666 #endif /* PCIDMA */
667
668 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
669 {
670 #ifdef PCIDMA
671 struct ni_private *devpriv = dev->private;
672 unsigned long flags;
673
674 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
675 if (devpriv->cdo_mite_chan) {
676 ni_set_cdo_dma_channel(dev, -1);
677 mite_release_channel(devpriv->cdo_mite_chan);
678 devpriv->cdo_mite_chan = NULL;
679 }
680 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
681 #endif /* PCIDMA */
682 }
683
684 /* e-series boards use the second irq signals to generate dma requests for their counters */
685 #ifdef PCIDMA
686 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
687 unsigned gpct_index, short enable)
688 {
689 const struct ni_board_struct *board = comedi_board(dev);
690 struct ni_private *devpriv = dev->private;
691
692 if (board->reg_type & ni_reg_m_series_mask)
693 return;
694 switch (gpct_index) {
695 case 0:
696 if (enable) {
697 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
698 Second_IRQ_A_Enable_Register);
699 } else {
700 devpriv->stc_writew(dev, 0,
701 Second_IRQ_A_Enable_Register);
702 }
703 break;
704 case 1:
705 if (enable) {
706 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
707 Second_IRQ_B_Enable_Register);
708 } else {
709 devpriv->stc_writew(dev, 0,
710 Second_IRQ_B_Enable_Register);
711 }
712 break;
713 default:
714 BUG();
715 break;
716 }
717 }
718 #endif /* PCIDMA */
719
720 static void ni_clear_ai_fifo(struct comedi_device *dev)
721 {
722 const struct ni_board_struct *board = comedi_board(dev);
723 struct ni_private *devpriv = dev->private;
724
725 if (board->reg_type == ni_reg_6143) {
726 /* Flush the 6143 data FIFO */
727 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */
728 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */
729 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */
730 } else {
731 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
732 if (board->reg_type == ni_reg_625x) {
733 ni_writeb(0, M_Offset_Static_AI_Control(0));
734 ni_writeb(1, M_Offset_Static_AI_Control(0));
735 #if 0
736 /* the NI example code does 3 convert pulses for 625x boards,
737 but that appears to be wrong in practice. */
738 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
739 AI_Command_1_Register);
740 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
741 AI_Command_1_Register);
742 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
743 AI_Command_1_Register);
744 #endif
745 }
746 }
747 }
748
749 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
750 {
751 struct ni_private *devpriv = dev->private;
752
753 devpriv->stc_writew(dev, data >> 16, reg);
754 devpriv->stc_writew(dev, data & 0xffff, reg + 1);
755 }
756
757 static uint32_t win_in2(struct comedi_device *dev, int reg)
758 {
759 struct ni_private *devpriv = dev->private;
760 uint32_t bits;
761
762 bits = devpriv->stc_readw(dev, reg) << 16;
763 bits |= devpriv->stc_readw(dev, reg + 1);
764 return bits;
765 }
766
767 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
768 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
769 int addr)
770 {
771 struct ni_private *devpriv = dev->private;
772 unsigned long flags;
773
774 spin_lock_irqsave(&devpriv->window_lock, flags);
775 ni_writew(addr, AO_Window_Address_611x);
776 ni_writew(data, AO_Window_Data_611x);
777 spin_unlock_irqrestore(&devpriv->window_lock, flags);
778 }
779
780 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
781 int addr)
782 {
783 struct ni_private *devpriv = dev->private;
784 unsigned long flags;
785
786 spin_lock_irqsave(&devpriv->window_lock, flags);
787 ni_writew(addr, AO_Window_Address_611x);
788 ni_writel(data, AO_Window_Data_611x);
789 spin_unlock_irqrestore(&devpriv->window_lock, flags);
790 }
791
792 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
793 {
794 struct ni_private *devpriv = dev->private;
795 unsigned long flags;
796 unsigned short data;
797
798 spin_lock_irqsave(&devpriv->window_lock, flags);
799 ni_writew(addr, AO_Window_Address_611x);
800 data = ni_readw(AO_Window_Data_611x);
801 spin_unlock_irqrestore(&devpriv->window_lock, flags);
802 return data;
803 }
804
805 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
806 * share registers (such as Interrupt_A_Register) without interfering with
807 * each other.
808 *
809 * NOTE: the switch/case statements are optimized out for a constant argument
810 * so this is actually quite fast--- If you must wrap another function around this
811 * make it inline to avoid a large speed penalty.
812 *
813 * value should only be 1 or 0.
814 */
815 static inline void ni_set_bits(struct comedi_device *dev, int reg,
816 unsigned bits, unsigned value)
817 {
818 unsigned bit_values;
819
820 if (value)
821 bit_values = bits;
822 else
823 bit_values = 0;
824 ni_set_bitfield(dev, reg, bits, bit_values);
825 }
826
827 static irqreturn_t ni_E_interrupt(int irq, void *d)
828 {
829 struct comedi_device *dev = d;
830 struct ni_private *devpriv = dev->private;
831 unsigned short a_status;
832 unsigned short b_status;
833 unsigned int ai_mite_status = 0;
834 unsigned int ao_mite_status = 0;
835 unsigned long flags;
836 #ifdef PCIDMA
837 struct mite_struct *mite = devpriv->mite;
838 #endif
839
840 if (!dev->attached)
841 return IRQ_NONE;
842 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
843
844 /* lock to avoid race with comedi_poll */
845 spin_lock_irqsave(&dev->spinlock, flags);
846 a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
847 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
848 #ifdef PCIDMA
849 if (mite) {
850 unsigned long flags_too;
851
852 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
853 if (devpriv->ai_mite_chan) {
854 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
855 if (ai_mite_status & CHSR_LINKC)
856 writel(CHOR_CLRLC,
857 devpriv->mite->mite_io_addr +
858 MITE_CHOR(devpriv->
859 ai_mite_chan->channel));
860 }
861 if (devpriv->ao_mite_chan) {
862 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
863 if (ao_mite_status & CHSR_LINKC)
864 writel(CHOR_CLRLC,
865 mite->mite_io_addr +
866 MITE_CHOR(devpriv->
867 ao_mite_chan->channel));
868 }
869 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
870 }
871 #endif
872 ack_a_interrupt(dev, a_status);
873 ack_b_interrupt(dev, b_status);
874 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
875 handle_a_interrupt(dev, a_status, ai_mite_status);
876 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
877 handle_b_interrupt(dev, b_status, ao_mite_status);
878 handle_gpct_interrupt(dev, 0);
879 handle_gpct_interrupt(dev, 1);
880 handle_cdio_interrupt(dev);
881
882 spin_unlock_irqrestore(&dev->spinlock, flags);
883 return IRQ_HANDLED;
884 }
885
886 #ifdef PCIDMA
887 static void ni_sync_ai_dma(struct comedi_device *dev)
888 {
889 struct ni_private *devpriv = dev->private;
890 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
891 unsigned long flags;
892
893 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
894 if (devpriv->ai_mite_chan)
895 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
896 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
897 }
898
899 static void mite_handle_b_linkc(struct mite_struct *mite,
900 struct comedi_device *dev)
901 {
902 struct ni_private *devpriv = dev->private;
903 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
904 unsigned long flags;
905
906 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
907 if (devpriv->ao_mite_chan) {
908 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
909 }
910 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
911 }
912
913 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
914 {
915 struct ni_private *devpriv = dev->private;
916 static const int timeout = 10000;
917 int i;
918 for (i = 0; i < timeout; i++) {
919 unsigned short b_status;
920
921 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
922 if (b_status & AO_FIFO_Half_Full_St)
923 break;
924 /* if we poll too often, the pci bus activity seems
925 to slow the dma transfer down */
926 udelay(10);
927 }
928 if (i == timeout) {
929 comedi_error(dev, "timed out waiting for dma load");
930 return -EPIPE;
931 }
932 return 0;
933 }
934
935 #endif /* PCIDMA */
936 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
937 {
938 struct ni_private *devpriv = dev->private;
939
940 if (devpriv->aimode == AIMODE_SCAN) {
941 #ifdef PCIDMA
942 static const int timeout = 10;
943 int i;
944
945 for (i = 0; i < timeout; i++) {
946 ni_sync_ai_dma(dev);
947 if ((s->async->events & COMEDI_CB_EOS))
948 break;
949 udelay(1);
950 }
951 #else
952 ni_handle_fifo_dregs(dev);
953 s->async->events |= COMEDI_CB_EOS;
954 #endif
955 }
956 /* handle special case of single scan using AI_End_On_End_Of_Scan */
957 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
958 shutdown_ai_command(dev);
959 }
960 }
961
962 static void shutdown_ai_command(struct comedi_device *dev)
963 {
964 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
965
966 #ifdef PCIDMA
967 ni_ai_drain_dma(dev);
968 #endif
969 ni_handle_fifo_dregs(dev);
970 get_last_sample_611x(dev);
971 get_last_sample_6143(dev);
972
973 s->async->events |= COMEDI_CB_EOA;
974 }
975
976 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
977 {
978 if (s->
979 async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
980 COMEDI_CB_EOA)) {
981 switch (s->index) {
982 case NI_AI_SUBDEV:
983 ni_ai_reset(dev, s);
984 break;
985 case NI_AO_SUBDEV:
986 ni_ao_reset(dev, s);
987 break;
988 case NI_GPCT0_SUBDEV:
989 case NI_GPCT1_SUBDEV:
990 ni_gpct_cancel(dev, s);
991 break;
992 case NI_DIO_SUBDEV:
993 ni_cdio_cancel(dev, s);
994 break;
995 default:
996 break;
997 }
998 }
999 comedi_event(dev, s);
1000 }
1001
1002 static void handle_gpct_interrupt(struct comedi_device *dev,
1003 unsigned short counter_index)
1004 {
1005 #ifdef PCIDMA
1006 struct ni_private *devpriv = dev->private;
1007 struct comedi_subdevice *s;
1008
1009 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1010
1011 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1012 s);
1013 if (s->async->events)
1014 ni_event(dev, s);
1015 #endif
1016 }
1017
1018 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1019 {
1020 struct ni_private *devpriv = dev->private;
1021 unsigned short ack = 0;
1022
1023 if (a_status & AI_SC_TC_St) {
1024 ack |= AI_SC_TC_Interrupt_Ack;
1025 }
1026 if (a_status & AI_START1_St) {
1027 ack |= AI_START1_Interrupt_Ack;
1028 }
1029 if (a_status & AI_START_St) {
1030 ack |= AI_START_Interrupt_Ack;
1031 }
1032 if (a_status & AI_STOP_St) {
1033 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1034 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1035 }
1036 if (ack)
1037 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1038 }
1039
1040 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1041 unsigned ai_mite_status)
1042 {
1043 struct ni_private *devpriv = dev->private;
1044 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1045
1046 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1047 if (s->type == COMEDI_SUBD_UNUSED)
1048 return;
1049
1050 #ifdef DEBUG_INTERRUPT
1051 printk
1052 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1053 status, ai_mite_status);
1054 ni_mio_print_status_a(status);
1055 #endif
1056 #ifdef PCIDMA
1057 if (ai_mite_status & CHSR_LINKC) {
1058 ni_sync_ai_dma(dev);
1059 }
1060
1061 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1062 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1063 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1064 printk
1065 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1066 ai_mite_status);
1067 /* mite_print_chsr(ai_mite_status); */
1068 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1069 /* disable_irq(dev->irq); */
1070 }
1071 #endif
1072
1073 /* test for all uncommon interrupt events at the same time */
1074 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1075 AI_SC_TC_St | AI_START1_St)) {
1076 if (status == 0xffff) {
1077 printk
1078 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1079 /* we probably aren't even running a command now,
1080 * so it's a good idea to be careful. */
1081 if (comedi_is_subdevice_running(s)) {
1082 s->async->events |=
1083 COMEDI_CB_ERROR | COMEDI_CB_EOA;
1084 ni_event(dev, s);
1085 }
1086 return;
1087 }
1088 if (status & (AI_Overrun_St | AI_Overflow_St |
1089 AI_SC_TC_Error_St)) {
1090 printk("ni_mio_common: ai error a_status=%04x\n",
1091 status);
1092 ni_mio_print_status_a(status);
1093
1094 shutdown_ai_command(dev);
1095
1096 s->async->events |= COMEDI_CB_ERROR;
1097 if (status & (AI_Overrun_St | AI_Overflow_St))
1098 s->async->events |= COMEDI_CB_OVERFLOW;
1099
1100 ni_event(dev, s);
1101
1102 return;
1103 }
1104 if (status & AI_SC_TC_St) {
1105 #ifdef DEBUG_INTERRUPT
1106 printk("ni_mio_common: SC_TC interrupt\n");
1107 #endif
1108 if (!devpriv->ai_continuous) {
1109 shutdown_ai_command(dev);
1110 }
1111 }
1112 }
1113 #ifndef PCIDMA
1114 if (status & AI_FIFO_Half_Full_St) {
1115 int i;
1116 static const int timeout = 10;
1117 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1118 *fail to get the fifo less than half full, so loop to be sure.*/
1119 for (i = 0; i < timeout; ++i) {
1120 ni_handle_fifo_half_full(dev);
1121 if ((devpriv->stc_readw(dev,
1122 AI_Status_1_Register) &
1123 AI_FIFO_Half_Full_St) == 0)
1124 break;
1125 }
1126 }
1127 #endif /* !PCIDMA */
1128
1129 if ((status & AI_STOP_St)) {
1130 ni_handle_eos(dev, s);
1131 }
1132
1133 ni_event(dev, s);
1134
1135 #ifdef DEBUG_INTERRUPT
1136 status = devpriv->stc_readw(dev, AI_Status_1_Register);
1137 if (status & Interrupt_A_St) {
1138 printk
1139 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1140 status);
1141 }
1142 #endif
1143 }
1144
1145 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1146 {
1147 struct ni_private *devpriv = dev->private;
1148 unsigned short ack = 0;
1149
1150 if (b_status & AO_BC_TC_St) {
1151 ack |= AO_BC_TC_Interrupt_Ack;
1152 }
1153 if (b_status & AO_Overrun_St) {
1154 ack |= AO_Error_Interrupt_Ack;
1155 }
1156 if (b_status & AO_START_St) {
1157 ack |= AO_START_Interrupt_Ack;
1158 }
1159 if (b_status & AO_START1_St) {
1160 ack |= AO_START1_Interrupt_Ack;
1161 }
1162 if (b_status & AO_UC_TC_St) {
1163 ack |= AO_UC_TC_Interrupt_Ack;
1164 }
1165 if (b_status & AO_UI2_TC_St) {
1166 ack |= AO_UI2_TC_Interrupt_Ack;
1167 }
1168 if (b_status & AO_UPDATE_St) {
1169 ack |= AO_UPDATE_Interrupt_Ack;
1170 }
1171 if (ack)
1172 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1173 }
1174
1175 static void handle_b_interrupt(struct comedi_device *dev,
1176 unsigned short b_status, unsigned ao_mite_status)
1177 {
1178 struct ni_private *devpriv = dev->private;
1179 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1180 /* unsigned short ack=0; */
1181
1182 #ifdef DEBUG_INTERRUPT
1183 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1184 b_status, ao_mite_status);
1185 ni_mio_print_status_b(b_status);
1186 #endif
1187
1188 #ifdef PCIDMA
1189 /* Currently, mite.c requires us to handle LINKC */
1190 if (ao_mite_status & CHSR_LINKC) {
1191 mite_handle_b_linkc(devpriv->mite, dev);
1192 }
1193
1194 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1195 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1196 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1197 printk
1198 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1199 ao_mite_status);
1200 /* mite_print_chsr(ao_mite_status); */
1201 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1202 }
1203 #endif
1204
1205 if (b_status == 0xffff)
1206 return;
1207 if (b_status & AO_Overrun_St) {
1208 printk
1209 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1210 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1211 s->async->events |= COMEDI_CB_OVERFLOW;
1212 }
1213
1214 if (b_status & AO_BC_TC_St) {
1215 MDPRINTK
1216 ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1217 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1218 s->async->events |= COMEDI_CB_EOA;
1219 }
1220 #ifndef PCIDMA
1221 if (b_status & AO_FIFO_Request_St) {
1222 int ret;
1223
1224 ret = ni_ao_fifo_half_empty(dev, s);
1225 if (!ret) {
1226 printk("ni_mio_common: AO buffer underrun\n");
1227 ni_set_bits(dev, Interrupt_B_Enable_Register,
1228 AO_FIFO_Interrupt_Enable |
1229 AO_Error_Interrupt_Enable, 0);
1230 s->async->events |= COMEDI_CB_OVERFLOW;
1231 }
1232 }
1233 #endif
1234
1235 ni_event(dev, s);
1236 }
1237
1238 #ifdef DEBUG_STATUS_A
1239 static const char *const status_a_strings[] = {
1240 "passthru0", "fifo", "G0_gate", "G0_TC",
1241 "stop", "start", "sc_tc", "start1",
1242 "start2", "sc_tc_error", "overflow", "overrun",
1243 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1244 };
1245
1246 static void ni_mio_print_status_a(int status)
1247 {
1248 int i;
1249
1250 printk("A status:");
1251 for (i = 15; i >= 0; i--) {
1252 if (status & (1 << i)) {
1253 printk(" %s", status_a_strings[i]);
1254 }
1255 }
1256 printk("\n");
1257 }
1258 #endif
1259
1260 #ifdef DEBUG_STATUS_B
1261 static const char *const status_b_strings[] = {
1262 "passthru1", "fifo", "G1_gate", "G1_TC",
1263 "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1264 "start1", "overrun", "start", "bc_tc_error",
1265 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1266 };
1267
1268 static void ni_mio_print_status_b(int status)
1269 {
1270 int i;
1271
1272 printk("B status:");
1273 for (i = 15; i >= 0; i--) {
1274 if (status & (1 << i)) {
1275 printk(" %s", status_b_strings[i]);
1276 }
1277 }
1278 printk("\n");
1279 }
1280 #endif
1281
1282 #ifndef PCIDMA
1283
1284 static void ni_ao_fifo_load(struct comedi_device *dev,
1285 struct comedi_subdevice *s, int n)
1286 {
1287 const struct ni_board_struct *board = comedi_board(dev);
1288 struct comedi_async *async = s->async;
1289 struct comedi_cmd *cmd = &async->cmd;
1290 int chan;
1291 int i;
1292 short d;
1293 u32 packed_data;
1294 int range;
1295 int err = 1;
1296
1297 chan = async->cur_chan;
1298 for (i = 0; i < n; i++) {
1299 err &= comedi_buf_get(async, &d);
1300 if (err == 0)
1301 break;
1302
1303 range = CR_RANGE(cmd->chanlist[chan]);
1304
1305 if (board->reg_type & ni_reg_6xxx_mask) {
1306 packed_data = d & 0xffff;
1307 /* 6711 only has 16 bit wide ao fifo */
1308 if (board->reg_type != ni_reg_6711) {
1309 err &= comedi_buf_get(async, &d);
1310 if (err == 0)
1311 break;
1312 chan++;
1313 i++;
1314 packed_data |= (d << 16) & 0xffff0000;
1315 }
1316 ni_writel(packed_data, DAC_FIFO_Data_611x);
1317 } else {
1318 ni_writew(d, DAC_FIFO_Data);
1319 }
1320 chan++;
1321 chan %= cmd->chanlist_len;
1322 }
1323 async->cur_chan = chan;
1324 if (err == 0) {
1325 async->events |= COMEDI_CB_OVERFLOW;
1326 }
1327 }
1328
1329 /*
1330 * There's a small problem if the FIFO gets really low and we
1331 * don't have the data to fill it. Basically, if after we fill
1332 * the FIFO with all the data available, the FIFO is _still_
1333 * less than half full, we never clear the interrupt. If the
1334 * IRQ is in edge mode, we never get another interrupt, because
1335 * this one wasn't cleared. If in level mode, we get flooded
1336 * with interrupts that we can't fulfill, because nothing ever
1337 * gets put into the buffer.
1338 *
1339 * This kind of situation is recoverable, but it is easier to
1340 * just pretend we had a FIFO underrun, since there is a good
1341 * chance it will happen anyway. This is _not_ the case for
1342 * RT code, as RT code might purposely be running close to the
1343 * metal. Needs to be fixed eventually.
1344 */
1345 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1346 struct comedi_subdevice *s)
1347 {
1348 const struct ni_board_struct *board = comedi_board(dev);
1349 int n;
1350
1351 n = comedi_buf_read_n_available(s->async);
1352 if (n == 0) {
1353 s->async->events |= COMEDI_CB_OVERFLOW;
1354 return 0;
1355 }
1356
1357 n /= sizeof(short);
1358 if (n > board->ao_fifo_depth / 2)
1359 n = board->ao_fifo_depth / 2;
1360
1361 ni_ao_fifo_load(dev, s, n);
1362
1363 s->async->events |= COMEDI_CB_BLOCK;
1364
1365 return 1;
1366 }
1367
1368 static int ni_ao_prep_fifo(struct comedi_device *dev,
1369 struct comedi_subdevice *s)
1370 {
1371 const struct ni_board_struct *board = comedi_board(dev);
1372 struct ni_private *devpriv = dev->private;
1373 int n;
1374
1375 /* reset fifo */
1376 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1377 if (board->reg_type & ni_reg_6xxx_mask)
1378 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1379
1380 /* load some data */
1381 n = comedi_buf_read_n_available(s->async);
1382 if (n == 0)
1383 return 0;
1384
1385 n /= sizeof(short);
1386 if (n > board->ao_fifo_depth)
1387 n = board->ao_fifo_depth;
1388
1389 ni_ao_fifo_load(dev, s, n);
1390
1391 return n;
1392 }
1393
1394 static void ni_ai_fifo_read(struct comedi_device *dev,
1395 struct comedi_subdevice *s, int n)
1396 {
1397 const struct ni_board_struct *board = comedi_board(dev);
1398 struct ni_private *devpriv = dev->private;
1399 struct comedi_async *async = s->async;
1400 int i;
1401
1402 if (board->reg_type == ni_reg_611x) {
1403 short data[2];
1404 u32 dl;
1405
1406 for (i = 0; i < n / 2; i++) {
1407 dl = ni_readl(ADC_FIFO_Data_611x);
1408 /* This may get the hi/lo data in the wrong order */
1409 data[0] = (dl >> 16) & 0xffff;
1410 data[1] = dl & 0xffff;
1411 cfc_write_array_to_buffer(s, data, sizeof(data));
1412 }
1413 /* Check if there's a single sample stuck in the FIFO */
1414 if (n % 2) {
1415 dl = ni_readl(ADC_FIFO_Data_611x);
1416 data[0] = dl & 0xffff;
1417 cfc_write_to_buffer(s, data[0]);
1418 }
1419 } else if (board->reg_type == ni_reg_6143) {
1420 short data[2];
1421 u32 dl;
1422
1423 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1424 for (i = 0; i < n / 2; i++) {
1425 dl = ni_readl(AIFIFO_Data_6143);
1426
1427 data[0] = (dl >> 16) & 0xffff;
1428 data[1] = dl & 0xffff;
1429 cfc_write_array_to_buffer(s, data, sizeof(data));
1430 }
1431 if (n % 2) {
1432 /* Assume there is a single sample stuck in the FIFO */
1433 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1434 dl = ni_readl(AIFIFO_Data_6143);
1435 data[0] = (dl >> 16) & 0xffff;
1436 cfc_write_to_buffer(s, data[0]);
1437 }
1438 } else {
1439 if (n > sizeof(devpriv->ai_fifo_buffer) /
1440 sizeof(devpriv->ai_fifo_buffer[0])) {
1441 comedi_error(dev, "bug! ai_fifo_buffer too small");
1442 async->events |= COMEDI_CB_ERROR;
1443 return;
1444 }
1445 for (i = 0; i < n; i++) {
1446 devpriv->ai_fifo_buffer[i] =
1447 ni_readw(ADC_FIFO_Data_Register);
1448 }
1449 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1450 n *
1451 sizeof(devpriv->ai_fifo_buffer[0]));
1452 }
1453 }
1454
1455 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1456 {
1457 const struct ni_board_struct *board = comedi_board(dev);
1458 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1459 int n;
1460
1461 n = board->ai_fifo_depth / 2;
1462
1463 ni_ai_fifo_read(dev, s, n);
1464 }
1465 #endif
1466
1467 #ifdef PCIDMA
1468 static int ni_ai_drain_dma(struct comedi_device *dev)
1469 {
1470 struct ni_private *devpriv = dev->private;
1471 int i;
1472 static const int timeout = 10000;
1473 unsigned long flags;
1474 int retval = 0;
1475
1476 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1477 if (devpriv->ai_mite_chan) {
1478 for (i = 0; i < timeout; i++) {
1479 if ((devpriv->stc_readw(dev,
1480 AI_Status_1_Register) &
1481 AI_FIFO_Empty_St)
1482 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1483 0)
1484 break;
1485 udelay(5);
1486 }
1487 if (i == timeout) {
1488 printk("ni_mio_common: wait for dma drain timed out\n");
1489 printk
1490 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1491 mite_bytes_in_transit(devpriv->ai_mite_chan),
1492 devpriv->stc_readw(dev, AI_Status_1_Register));
1493 retval = -1;
1494 }
1495 }
1496 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1497
1498 ni_sync_ai_dma(dev);
1499
1500 return retval;
1501 }
1502 #endif
1503 /*
1504 Empties the AI fifo
1505 */
1506 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1507 {
1508 const struct ni_board_struct *board = comedi_board(dev);
1509 struct ni_private *devpriv = dev->private;
1510 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1511 short data[2];
1512 u32 dl;
1513 short fifo_empty;
1514 int i;
1515
1516 if (board->reg_type == ni_reg_611x) {
1517 while ((devpriv->stc_readw(dev,
1518 AI_Status_1_Register) &
1519 AI_FIFO_Empty_St) == 0) {
1520 dl = ni_readl(ADC_FIFO_Data_611x);
1521
1522 /* This may get the hi/lo data in the wrong order */
1523 data[0] = (dl >> 16);
1524 data[1] = (dl & 0xffff);
1525 cfc_write_array_to_buffer(s, data, sizeof(data));
1526 }
1527 } else if (board->reg_type == ni_reg_6143) {
1528 i = 0;
1529 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1530 dl = ni_readl(AIFIFO_Data_6143);
1531
1532 /* This may get the hi/lo data in the wrong order */
1533 data[0] = (dl >> 16);
1534 data[1] = (dl & 0xffff);
1535 cfc_write_array_to_buffer(s, data, sizeof(data));
1536 i += 2;
1537 }
1538 /* Check if stranded sample is present */
1539 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1540 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1541 dl = ni_readl(AIFIFO_Data_6143);
1542 data[0] = (dl >> 16) & 0xffff;
1543 cfc_write_to_buffer(s, data[0]);
1544 }
1545
1546 } else {
1547 fifo_empty =
1548 devpriv->stc_readw(dev,
1549 AI_Status_1_Register) & AI_FIFO_Empty_St;
1550 while (fifo_empty == 0) {
1551 for (i = 0;
1552 i <
1553 sizeof(devpriv->ai_fifo_buffer) /
1554 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1555 fifo_empty =
1556 devpriv->stc_readw(dev,
1557 AI_Status_1_Register) &
1558 AI_FIFO_Empty_St;
1559 if (fifo_empty)
1560 break;
1561 devpriv->ai_fifo_buffer[i] =
1562 ni_readw(ADC_FIFO_Data_Register);
1563 }
1564 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1565 i *
1566 sizeof(devpriv->
1567 ai_fifo_buffer[0]));
1568 }
1569 }
1570 }
1571
1572 static void get_last_sample_611x(struct comedi_device *dev)
1573 {
1574 const struct ni_board_struct *board = comedi_board(dev);
1575 struct ni_private *devpriv __maybe_unused = dev->private;
1576 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1577 short data;
1578 u32 dl;
1579
1580 if (board->reg_type != ni_reg_611x)
1581 return;
1582
1583 /* Check if there's a single sample stuck in the FIFO */
1584 if (ni_readb(XXX_Status) & 0x80) {
1585 dl = ni_readl(ADC_FIFO_Data_611x);
1586 data = (dl & 0xffff);
1587 cfc_write_to_buffer(s, data);
1588 }
1589 }
1590
1591 static void get_last_sample_6143(struct comedi_device *dev)
1592 {
1593 const struct ni_board_struct *board = comedi_board(dev);
1594 struct ni_private *devpriv __maybe_unused = dev->private;
1595 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1596 short data;
1597 u32 dl;
1598
1599 if (board->reg_type != ni_reg_6143)
1600 return;
1601
1602 /* Check if there's a single sample stuck in the FIFO */
1603 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1604 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1605 dl = ni_readl(AIFIFO_Data_6143);
1606
1607 /* This may get the hi/lo data in the wrong order */
1608 data = (dl >> 16) & 0xffff;
1609 cfc_write_to_buffer(s, data);
1610 }
1611 }
1612
1613 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1614 void *data, unsigned int num_bytes,
1615 unsigned int chan_index)
1616 {
1617 struct ni_private *devpriv = dev->private;
1618 struct comedi_async *async = s->async;
1619 unsigned int i;
1620 unsigned int length = num_bytes / bytes_per_sample(s);
1621 short *array = data;
1622 unsigned int *larray = data;
1623
1624 for (i = 0; i < length; i++) {
1625 #ifdef PCIDMA
1626 if (s->subdev_flags & SDF_LSAMPL)
1627 larray[i] = le32_to_cpu(larray[i]);
1628 else
1629 array[i] = le16_to_cpu(array[i]);
1630 #endif
1631 if (s->subdev_flags & SDF_LSAMPL)
1632 larray[i] += devpriv->ai_offset[chan_index];
1633 else
1634 array[i] += devpriv->ai_offset[chan_index];
1635 chan_index++;
1636 chan_index %= async->cmd.chanlist_len;
1637 }
1638 }
1639
1640 #ifdef PCIDMA
1641
1642 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1643 {
1644 const struct ni_board_struct *board = comedi_board(dev);
1645 struct ni_private *devpriv = dev->private;
1646 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1647 int retval;
1648 unsigned long flags;
1649
1650 retval = ni_request_ai_mite_channel(dev);
1651 if (retval)
1652 return retval;
1653 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1654
1655 /* write alloc the entire buffer */
1656 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1657
1658 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1659 if (devpriv->ai_mite_chan == NULL) {
1660 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1661 return -EIO;
1662 }
1663
1664 switch (board->reg_type) {
1665 case ni_reg_611x:
1666 case ni_reg_6143:
1667 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1668 break;
1669 case ni_reg_628x:
1670 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1671 break;
1672 default:
1673 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1674 break;
1675 }
1676 /*start the MITE */
1677 mite_dma_arm(devpriv->ai_mite_chan);
1678 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1679
1680 return 0;
1681 }
1682
1683 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1684 {
1685 const struct ni_board_struct *board = comedi_board(dev);
1686 struct ni_private *devpriv = dev->private;
1687 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1688 int retval;
1689 unsigned long flags;
1690
1691 retval = ni_request_ao_mite_channel(dev);
1692 if (retval)
1693 return retval;
1694
1695 /* read alloc the entire buffer */
1696 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1697
1698 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1699 if (devpriv->ao_mite_chan) {
1700 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
1701 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1702 } else {
1703 /* doing 32 instead of 16 bit wide transfers from memory
1704 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1705 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1706 }
1707 mite_dma_arm(devpriv->ao_mite_chan);
1708 } else
1709 retval = -EIO;
1710 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1711
1712 return retval;
1713 }
1714
1715 #endif /* PCIDMA */
1716
1717 /*
1718 used for both cancel ioctl and board initialization
1719
1720 this is pretty harsh for a cancel, but it works...
1721 */
1722
1723 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1724 {
1725 const struct ni_board_struct *board = comedi_board(dev);
1726 struct ni_private *devpriv = dev->private;
1727
1728 ni_release_ai_mite_channel(dev);
1729 /* ai configuration */
1730 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1731 Joint_Reset_Register);
1732
1733 ni_set_bits(dev, Interrupt_A_Enable_Register,
1734 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1735 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1736 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1737 AI_FIFO_Interrupt_Enable, 0);
1738
1739 ni_clear_ai_fifo(dev);
1740
1741 if (board->reg_type != ni_reg_6143)
1742 ni_writeb(0, Misc_Command);
1743
1744 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1745 devpriv->stc_writew(dev,
1746 AI_Start_Stop | AI_Mode_1_Reserved
1747 /*| AI_Trigger_Once */ ,
1748 AI_Mode_1_Register);
1749 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1750 /* generate FIFO interrupts on non-empty */
1751 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1752 if (board->reg_type == ni_reg_611x) {
1753 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1754 AI_SOC_Polarity |
1755 AI_LOCALMUX_CLK_Pulse_Width,
1756 AI_Personal_Register);
1757 devpriv->stc_writew(dev,
1758 AI_SCAN_IN_PROG_Output_Select(3) |
1759 AI_EXTMUX_CLK_Output_Select(0) |
1760 AI_LOCALMUX_CLK_Output_Select(2) |
1761 AI_SC_TC_Output_Select(3) |
1762 AI_CONVERT_Output_Select
1763 (AI_CONVERT_Output_Enable_High),
1764 AI_Output_Control_Register);
1765 } else if (board->reg_type == ni_reg_6143) {
1766 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1767 AI_SOC_Polarity |
1768 AI_LOCALMUX_CLK_Pulse_Width,
1769 AI_Personal_Register);
1770 devpriv->stc_writew(dev,
1771 AI_SCAN_IN_PROG_Output_Select(3) |
1772 AI_EXTMUX_CLK_Output_Select(0) |
1773 AI_LOCALMUX_CLK_Output_Select(2) |
1774 AI_SC_TC_Output_Select(3) |
1775 AI_CONVERT_Output_Select
1776 (AI_CONVERT_Output_Enable_Low),
1777 AI_Output_Control_Register);
1778 } else {
1779 unsigned ai_output_control_bits;
1780 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1781 AI_SOC_Polarity |
1782 AI_CONVERT_Pulse_Width |
1783 AI_LOCALMUX_CLK_Pulse_Width,
1784 AI_Personal_Register);
1785 ai_output_control_bits =
1786 AI_SCAN_IN_PROG_Output_Select(3) |
1787 AI_EXTMUX_CLK_Output_Select(0) |
1788 AI_LOCALMUX_CLK_Output_Select(2) |
1789 AI_SC_TC_Output_Select(3);
1790 if (board->reg_type == ni_reg_622x)
1791 ai_output_control_bits |=
1792 AI_CONVERT_Output_Select
1793 (AI_CONVERT_Output_Enable_High);
1794 else
1795 ai_output_control_bits |=
1796 AI_CONVERT_Output_Select
1797 (AI_CONVERT_Output_Enable_Low);
1798 devpriv->stc_writew(dev, ai_output_control_bits,
1799 AI_Output_Control_Register);
1800 }
1801 /* the following registers should not be changed, because there
1802 * are no backup registers in devpriv. If you want to change
1803 * any of these, add a backup register and other appropriate code:
1804 * AI_Mode_1_Register
1805 * AI_Mode_3_Register
1806 * AI_Personal_Register
1807 * AI_Output_Control_Register
1808 */
1809 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1810
1811 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1812
1813 return 0;
1814 }
1815
1816 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1817 {
1818 unsigned long flags;
1819 int count;
1820
1821 /* lock to avoid race with interrupt handler */
1822 spin_lock_irqsave(&dev->spinlock, flags);
1823 #ifndef PCIDMA
1824 ni_handle_fifo_dregs(dev);
1825 #else
1826 ni_sync_ai_dma(dev);
1827 #endif
1828 count = s->async->buf_write_count - s->async->buf_read_count;
1829 spin_unlock_irqrestore(&dev->spinlock, flags);
1830
1831 return count;
1832 }
1833
1834 static int ni_ai_insn_read(struct comedi_device *dev,
1835 struct comedi_subdevice *s, struct comedi_insn *insn,
1836 unsigned int *data)
1837 {
1838 const struct ni_board_struct *board = comedi_board(dev);
1839 struct ni_private *devpriv = dev->private;
1840 int i, n;
1841 const unsigned int mask = (1 << board->adbits) - 1;
1842 unsigned signbits;
1843 unsigned short d;
1844 unsigned long dl;
1845
1846 ni_load_channelgain_list(dev, 1, &insn->chanspec);
1847
1848 ni_clear_ai_fifo(dev);
1849
1850 signbits = devpriv->ai_offset[0];
1851 if (board->reg_type == ni_reg_611x) {
1852 for (n = 0; n < num_adc_stages_611x; n++) {
1853 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1854 AI_Command_1_Register);
1855 udelay(1);
1856 }
1857 for (n = 0; n < insn->n; n++) {
1858 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1859 AI_Command_1_Register);
1860 /* The 611x has screwy 32-bit FIFOs. */
1861 d = 0;
1862 for (i = 0; i < NI_TIMEOUT; i++) {
1863 if (ni_readb(XXX_Status) & 0x80) {
1864 d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1865 & 0xffff;
1866 break;
1867 }
1868 if (!(devpriv->stc_readw(dev,
1869 AI_Status_1_Register) &
1870 AI_FIFO_Empty_St)) {
1871 d = ni_readl(ADC_FIFO_Data_611x) &
1872 0xffff;
1873 break;
1874 }
1875 }
1876 if (i == NI_TIMEOUT) {
1877 printk
1878 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1879 return -ETIME;
1880 }
1881 d += signbits;
1882 data[n] = d;
1883 }
1884 } else if (board->reg_type == ni_reg_6143) {
1885 for (n = 0; n < insn->n; n++) {
1886 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1887 AI_Command_1_Register);
1888
1889 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1890 dl = 0;
1891 for (i = 0; i < NI_TIMEOUT; i++) {
1892 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1893 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1894 dl = ni_readl(AIFIFO_Data_6143);
1895 break;
1896 }
1897 }
1898 if (i == NI_TIMEOUT) {
1899 printk
1900 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1901 return -ETIME;
1902 }
1903 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1904 }
1905 } else {
1906 for (n = 0; n < insn->n; n++) {
1907 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1908 AI_Command_1_Register);
1909 for (i = 0; i < NI_TIMEOUT; i++) {
1910 if (!(devpriv->stc_readw(dev,
1911 AI_Status_1_Register) &
1912 AI_FIFO_Empty_St))
1913 break;
1914 }
1915 if (i == NI_TIMEOUT) {
1916 printk
1917 ("ni_mio_common: timeout in ni_ai_insn_read\n");
1918 return -ETIME;
1919 }
1920 if (board->reg_type & ni_reg_m_series_mask) {
1921 data[n] =
1922 ni_readl(M_Offset_AI_FIFO_Data) & mask;
1923 } else {
1924 d = ni_readw(ADC_FIFO_Data_Register);
1925 d += signbits; /* subtle: needs to be short addition */
1926 data[n] = d;
1927 }
1928 }
1929 }
1930 return insn->n;
1931 }
1932
1933 static void ni_prime_channelgain_list(struct comedi_device *dev)
1934 {
1935 struct ni_private *devpriv = dev->private;
1936 int i;
1937
1938 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1939 for (i = 0; i < NI_TIMEOUT; ++i) {
1940 if (!(devpriv->stc_readw(dev,
1941 AI_Status_1_Register) &
1942 AI_FIFO_Empty_St)) {
1943 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1944 return;
1945 }
1946 udelay(1);
1947 }
1948 printk("ni_mio_common: timeout loading channel/gain list\n");
1949 }
1950
1951 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1952 unsigned int n_chan,
1953 unsigned int *list)
1954 {
1955 const struct ni_board_struct *board = comedi_board(dev);
1956 struct ni_private *devpriv = dev->private;
1957 unsigned int chan, range, aref;
1958 unsigned int i;
1959 unsigned offset;
1960 unsigned int dither;
1961 unsigned range_code;
1962
1963 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1964
1965 /* offset = 1 << (board->adbits - 1); */
1966 if ((list[0] & CR_ALT_SOURCE)) {
1967 unsigned bypass_bits;
1968 chan = CR_CHAN(list[0]);
1969 range = CR_RANGE(list[0]);
1970 range_code = ni_gainlkup[board->gainlkup][range];
1971 dither = ((list[0] & CR_ALT_FILTER) != 0);
1972 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1973 bypass_bits |= chan;
1974 bypass_bits |=
1975 (devpriv->ai_calib_source) &
1976 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1977 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1978 MSeries_AI_Bypass_Mode_Mux_Mask |
1979 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1980 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1981 if (dither)
1982 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1983 /* don't use 2's complement encoding */
1984 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1985 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1986 } else {
1987 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1988 }
1989 offset = 0;
1990 for (i = 0; i < n_chan; i++) {
1991 unsigned config_bits = 0;
1992 chan = CR_CHAN(list[i]);
1993 aref = CR_AREF(list[i]);
1994 range = CR_RANGE(list[i]);
1995 dither = ((list[i] & CR_ALT_FILTER) != 0);
1996
1997 range_code = ni_gainlkup[board->gainlkup][range];
1998 devpriv->ai_offset[i] = offset;
1999 switch (aref) {
2000 case AREF_DIFF:
2001 config_bits |=
2002 MSeries_AI_Config_Channel_Type_Differential_Bits;
2003 break;
2004 case AREF_COMMON:
2005 config_bits |=
2006 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
2007 break;
2008 case AREF_GROUND:
2009 config_bits |=
2010 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
2011 break;
2012 case AREF_OTHER:
2013 break;
2014 }
2015 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
2016 config_bits |=
2017 MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
2018 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
2019 if (i == n_chan - 1)
2020 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
2021 if (dither)
2022 config_bits |= MSeries_AI_Config_Dither_Bit;
2023 /* don't use 2's complement encoding */
2024 config_bits |= MSeries_AI_Config_Polarity_Bit;
2025 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
2026 }
2027 ni_prime_channelgain_list(dev);
2028 }
2029
2030 /*
2031 * Notes on the 6110 and 6111:
2032 * These boards a slightly different than the rest of the series, since
2033 * they have multiple A/D converters.
2034 * From the driver side, the configuration memory is a
2035 * little different.
2036 * Configuration Memory Low:
2037 * bits 15-9: same
2038 * bit 8: unipolar/bipolar (should be 0 for bipolar)
2039 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
2040 * 1001 gain=0.1 (+/- 50)
2041 * 1010 0.2
2042 * 1011 0.1
2043 * 0001 1
2044 * 0010 2
2045 * 0011 5
2046 * 0100 10
2047 * 0101 20
2048 * 0110 50
2049 * Configuration Memory High:
2050 * bits 12-14: Channel Type
2051 * 001 for differential
2052 * 000 for calibration
2053 * bit 11: coupling (this is not currently handled)
2054 * 1 AC coupling
2055 * 0 DC coupling
2056 * bits 0-2: channel
2057 * valid channels are 0-3
2058 */
2059 static void ni_load_channelgain_list(struct comedi_device *dev,
2060 unsigned int n_chan, unsigned int *list)
2061 {
2062 const struct ni_board_struct *board = comedi_board(dev);
2063 struct ni_private *devpriv = dev->private;
2064 unsigned int chan, range, aref;
2065 unsigned int i;
2066 unsigned int hi, lo;
2067 unsigned offset;
2068 unsigned int dither;
2069
2070 if (board->reg_type & ni_reg_m_series_mask) {
2071 ni_m_series_load_channelgain_list(dev, n_chan, list);
2072 return;
2073 }
2074 if (n_chan == 1 && (board->reg_type != ni_reg_611x)
2075 && (board->reg_type != ni_reg_6143)) {
2076 if (devpriv->changain_state
2077 && devpriv->changain_spec == list[0]) {
2078 /* ready to go. */
2079 return;
2080 }
2081 devpriv->changain_state = 1;
2082 devpriv->changain_spec = list[0];
2083 } else {
2084 devpriv->changain_state = 0;
2085 }
2086
2087 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2088
2089 /* Set up Calibration mode if required */
2090 if (board->reg_type == ni_reg_6143) {
2091 if ((list[0] & CR_ALT_SOURCE)
2092 && !devpriv->ai_calib_source_enabled) {
2093 /* Strobe Relay enable bit */
2094 ni_writew(devpriv->ai_calib_source |
2095 Calibration_Channel_6143_RelayOn,
2096 Calibration_Channel_6143);
2097 ni_writew(devpriv->ai_calib_source,
2098 Calibration_Channel_6143);
2099 devpriv->ai_calib_source_enabled = 1;
2100 msleep_interruptible(100); /* Allow relays to change */
2101 } else if (!(list[0] & CR_ALT_SOURCE)
2102 && devpriv->ai_calib_source_enabled) {
2103 /* Strobe Relay disable bit */
2104 ni_writew(devpriv->ai_calib_source |
2105 Calibration_Channel_6143_RelayOff,
2106 Calibration_Channel_6143);
2107 ni_writew(devpriv->ai_calib_source,
2108 Calibration_Channel_6143);
2109 devpriv->ai_calib_source_enabled = 0;
2110 msleep_interruptible(100); /* Allow relays to change */
2111 }
2112 }
2113
2114 offset = 1 << (board->adbits - 1);
2115 for (i = 0; i < n_chan; i++) {
2116 if ((board->reg_type != ni_reg_6143)
2117 && (list[i] & CR_ALT_SOURCE)) {
2118 chan = devpriv->ai_calib_source;
2119 } else {
2120 chan = CR_CHAN(list[i]);
2121 }
2122 aref = CR_AREF(list[i]);
2123 range = CR_RANGE(list[i]);
2124 dither = ((list[i] & CR_ALT_FILTER) != 0);
2125
2126 /* fix the external/internal range differences */
2127 range = ni_gainlkup[board->gainlkup][range];
2128 if (board->reg_type == ni_reg_611x)
2129 devpriv->ai_offset[i] = offset;
2130 else
2131 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2132
2133 hi = 0;
2134 if ((list[i] & CR_ALT_SOURCE)) {
2135 if (board->reg_type == ni_reg_611x)
2136 ni_writew(CR_CHAN(list[i]) & 0x0003,
2137 Calibration_Channel_Select_611x);
2138 } else {
2139 if (board->reg_type == ni_reg_611x)
2140 aref = AREF_DIFF;
2141 else if (board->reg_type == ni_reg_6143)
2142 aref = AREF_OTHER;
2143 switch (aref) {
2144 case AREF_DIFF:
2145 hi |= AI_DIFFERENTIAL;
2146 break;
2147 case AREF_COMMON:
2148 hi |= AI_COMMON;
2149 break;
2150 case AREF_GROUND:
2151 hi |= AI_GROUND;
2152 break;
2153 case AREF_OTHER:
2154 break;
2155 }
2156 }
2157 hi |= AI_CONFIG_CHANNEL(chan);
2158
2159 ni_writew(hi, Configuration_Memory_High);
2160
2161 if (board->reg_type != ni_reg_6143) {
2162 lo = range;
2163 if (i == n_chan - 1)
2164 lo |= AI_LAST_CHANNEL;
2165 if (dither)
2166 lo |= AI_DITHER;
2167
2168 ni_writew(lo, Configuration_Memory_Low);
2169 }
2170 }
2171
2172 /* prime the channel/gain list */
2173 if ((board->reg_type != ni_reg_611x)
2174 && (board->reg_type != ni_reg_6143)) {
2175 ni_prime_channelgain_list(dev);
2176 }
2177 }
2178
2179 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2180 int round_mode)
2181 {
2182 struct ni_private *devpriv = dev->private;
2183 int divider;
2184
2185 switch (round_mode) {
2186 case TRIG_ROUND_NEAREST:
2187 default:
2188 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2189 break;
2190 case TRIG_ROUND_DOWN:
2191 divider = (nanosec) / devpriv->clock_ns;
2192 break;
2193 case TRIG_ROUND_UP:
2194 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2195 break;
2196 }
2197 return divider - 1;
2198 }
2199
2200 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2201 {
2202 struct ni_private *devpriv = dev->private;
2203
2204 return devpriv->clock_ns * (timer + 1);
2205 }
2206
2207 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2208 unsigned num_channels)
2209 {
2210 const struct ni_board_struct *board = comedi_board(dev);
2211
2212 switch (board->reg_type) {
2213 case ni_reg_611x:
2214 case ni_reg_6143:
2215 /* simultaneously-sampled inputs */
2216 return board->ai_speed;
2217 break;
2218 default:
2219 /* multiplexed inputs */
2220 break;
2221 }
2222 return board->ai_speed * num_channels;
2223 }
2224
2225 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2226 struct comedi_cmd *cmd)
2227 {
2228 const struct ni_board_struct *board = comedi_board(dev);
2229 struct ni_private *devpriv = dev->private;
2230 int err = 0;
2231 int tmp;
2232 unsigned int sources;
2233
2234 /* Step 1 : check if triggers are trivially valid */
2235
2236 if ((cmd->flags & CMDF_WRITE))
2237 cmd->flags &= ~CMDF_WRITE;
2238
2239 err |= cfc_check_trigger_src(&cmd->start_src,
2240 TRIG_NOW | TRIG_INT | TRIG_EXT);
2241 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2242 TRIG_TIMER | TRIG_EXT);
2243
2244 sources = TRIG_TIMER | TRIG_EXT;
2245 if (board->reg_type == ni_reg_611x ||
2246 board->reg_type == ni_reg_6143)
2247 sources |= TRIG_NOW;
2248 err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2249
2250 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2251 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2252
2253 if (err)
2254 return 1;
2255
2256 /* Step 2a : make sure trigger sources are unique */
2257
2258 err |= cfc_check_trigger_is_unique(cmd->start_src);
2259 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2260 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2261 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2262
2263 /* Step 2b : and mutually compatible */
2264
2265 if (err)
2266 return 2;
2267
2268 /* Step 3: check if arguments are trivially valid */
2269
2270 if (cmd->start_src == TRIG_EXT) {
2271 /* external trigger */
2272 unsigned int tmp = CR_CHAN(cmd->start_arg);
2273
2274 if (tmp > 16)
2275 tmp = 16;
2276 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2277 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2278 } else {
2279 /* true for both TRIG_NOW and TRIG_INT */
2280 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2281 }
2282
2283 if (cmd->scan_begin_src == TRIG_TIMER) {
2284 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2285 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2286 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2287 devpriv->clock_ns * 0xffffff);
2288 } else if (cmd->scan_begin_src == TRIG_EXT) {
2289 /* external trigger */
2290 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2291
2292 if (tmp > 16)
2293 tmp = 16;
2294 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2295 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2296 } else { /* TRIG_OTHER */
2297 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2298 }
2299
2300 if (cmd->convert_src == TRIG_TIMER) {
2301 if ((board->reg_type == ni_reg_611x)
2302 || (board->reg_type == ni_reg_6143)) {
2303 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2304 } else {
2305 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2306 board->ai_speed);
2307 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2308 devpriv->clock_ns * 0xffff);
2309 }
2310 } else if (cmd->convert_src == TRIG_EXT) {
2311 /* external trigger */
2312 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2313
2314 if (tmp > 16)
2315 tmp = 16;
2316 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2317 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2318 } else if (cmd->convert_src == TRIG_NOW) {
2319 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2320 }
2321
2322 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2323
2324 if (cmd->stop_src == TRIG_COUNT) {
2325 unsigned int max_count = 0x01000000;
2326
2327 if (board->reg_type == ni_reg_611x)
2328 max_count -= num_adc_stages_611x;
2329 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2330 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2331 } else {
2332 /* TRIG_NONE */
2333 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2334 }
2335
2336 if (err)
2337 return 3;
2338
2339 /* step 4: fix up any arguments */
2340
2341 if (cmd->scan_begin_src == TRIG_TIMER) {
2342 tmp = cmd->scan_begin_arg;
2343 cmd->scan_begin_arg =
2344 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2345 cmd->scan_begin_arg,
2346 cmd->
2347 flags &
2348 TRIG_ROUND_MASK));
2349 if (tmp != cmd->scan_begin_arg)
2350 err++;
2351 }
2352 if (cmd->convert_src == TRIG_TIMER) {
2353 if ((board->reg_type != ni_reg_611x)
2354 && (board->reg_type != ni_reg_6143)) {
2355 tmp = cmd->convert_arg;
2356 cmd->convert_arg =
2357 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2358 cmd->convert_arg,
2359 cmd->
2360 flags &
2361 TRIG_ROUND_MASK));
2362 if (tmp != cmd->convert_arg)
2363 err++;
2364 if (cmd->scan_begin_src == TRIG_TIMER &&
2365 cmd->scan_begin_arg <
2366 cmd->convert_arg * cmd->scan_end_arg) {
2367 cmd->scan_begin_arg =
2368 cmd->convert_arg * cmd->scan_end_arg;
2369 err++;
2370 }
2371 }
2372 }
2373
2374 if (err)
2375 return 4;
2376
2377 return 0;
2378 }
2379
2380 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2381 {
2382 const struct ni_board_struct *board = comedi_board(dev);
2383 struct ni_private *devpriv = dev->private;
2384 const struct comedi_cmd *cmd = &s->async->cmd;
2385 int timer;
2386 int mode1 = 0; /* mode1 is needed for both stop and convert */
2387 int mode2 = 0;
2388 int start_stop_select = 0;
2389 unsigned int stop_count;
2390 int interrupt_a_enable = 0;
2391
2392 MDPRINTK("ni_ai_cmd\n");
2393 if (dev->irq == 0) {
2394 comedi_error(dev, "cannot run command without an irq");
2395 return -EIO;
2396 }
2397 ni_clear_ai_fifo(dev);
2398
2399 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2400
2401 /* start configuration */
2402 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2403
2404 /* disable analog triggering for now, since it
2405 * interferes with the use of pfi0 */
2406 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2407 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2408 Analog_Trigger_Etc_Register);
2409
2410 switch (cmd->start_src) {
2411 case TRIG_INT:
2412 case TRIG_NOW:
2413 devpriv->stc_writew(dev, AI_START2_Select(0) |
2414 AI_START1_Sync | AI_START1_Edge |
2415 AI_START1_Select(0),
2416 AI_Trigger_Select_Register);
2417 break;
2418 case TRIG_EXT:
2419 {
2420 int chan = CR_CHAN(cmd->start_arg);
2421 unsigned int bits = AI_START2_Select(0) |
2422 AI_START1_Sync | AI_START1_Select(chan + 1);
2423
2424 if (cmd->start_arg & CR_INVERT)
2425 bits |= AI_START1_Polarity;
2426 if (cmd->start_arg & CR_EDGE)
2427 bits |= AI_START1_Edge;
2428 devpriv->stc_writew(dev, bits,
2429 AI_Trigger_Select_Register);
2430 break;
2431 }
2432 }
2433
2434 mode2 &= ~AI_Pre_Trigger;
2435 mode2 &= ~AI_SC_Initial_Load_Source;
2436 mode2 &= ~AI_SC_Reload_Mode;
2437 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2438
2439 if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2440 || (board->reg_type == ni_reg_6143)) {
2441 start_stop_select |= AI_STOP_Polarity;
2442 start_stop_select |= AI_STOP_Select(31); /* logic low */
2443 start_stop_select |= AI_STOP_Sync;
2444 } else {
2445 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2446 }
2447 devpriv->stc_writew(dev, start_stop_select,
2448 AI_START_STOP_Select_Register);
2449
2450 devpriv->ai_cmd2 = 0;
2451 switch (cmd->stop_src) {
2452 case TRIG_COUNT:
2453 stop_count = cmd->stop_arg - 1;
2454
2455 if (board->reg_type == ni_reg_611x) {
2456 /* have to take 3 stage adc pipeline into account */
2457 stop_count += num_adc_stages_611x;
2458 }
2459 /* stage number of scans */
2460 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2461
2462 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2463 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2464 /* load SC (Scan Count) */
2465 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2466
2467 devpriv->ai_continuous = 0;
2468 if (stop_count == 0) {
2469 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2470 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2471 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2472 if (cmd->chanlist_len > 1)
2473 start_stop_select |=
2474 AI_STOP_Polarity | AI_STOP_Edge;
2475 }
2476 break;
2477 case TRIG_NONE:
2478 /* stage number of scans */
2479 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2480
2481 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2482 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2483
2484 /* load SC (Scan Count) */
2485 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2486
2487 devpriv->ai_continuous = 1;
2488
2489 break;
2490 }
2491
2492 switch (cmd->scan_begin_src) {
2493 case TRIG_TIMER:
2494 /*
2495 stop bits for non 611x boards
2496 AI_SI_Special_Trigger_Delay=0
2497 AI_Pre_Trigger=0
2498 AI_START_STOP_Select_Register:
2499 AI_START_Polarity=0 (?) rising edge
2500 AI_START_Edge=1 edge triggered
2501 AI_START_Sync=1 (?)
2502 AI_START_Select=0 SI_TC
2503 AI_STOP_Polarity=0 rising edge
2504 AI_STOP_Edge=0 level
2505 AI_STOP_Sync=1
2506 AI_STOP_Select=19 external pin (configuration mem)
2507 */
2508 start_stop_select |= AI_START_Edge | AI_START_Sync;
2509 devpriv->stc_writew(dev, start_stop_select,
2510 AI_START_STOP_Select_Register);
2511
2512 mode2 |= AI_SI_Reload_Mode(0);
2513 /* AI_SI_Initial_Load_Source=A */
2514 mode2 &= ~AI_SI_Initial_Load_Source;
2515 /* mode2 |= AI_SC_Reload_Mode; */
2516 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2517
2518 /* load SI */
2519 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2520 TRIG_ROUND_NEAREST);
2521 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2522 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2523 break;
2524 case TRIG_EXT:
2525 if (cmd->scan_begin_arg & CR_EDGE)
2526 start_stop_select |= AI_START_Edge;
2527 /* AI_START_Polarity==1 is falling edge */
2528 if (cmd->scan_begin_arg & CR_INVERT)
2529 start_stop_select |= AI_START_Polarity;
2530 if (cmd->scan_begin_src != cmd->convert_src ||
2531 (cmd->scan_begin_arg & ~CR_EDGE) !=
2532 (cmd->convert_arg & ~CR_EDGE))
2533 start_stop_select |= AI_START_Sync;
2534 start_stop_select |=
2535 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2536 devpriv->stc_writew(dev, start_stop_select,
2537 AI_START_STOP_Select_Register);
2538 break;
2539 }
2540
2541 switch (cmd->convert_src) {
2542 case TRIG_TIMER:
2543 case TRIG_NOW:
2544 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2545 timer = 1;
2546 else
2547 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2548 TRIG_ROUND_NEAREST);
2549 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2550 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2551
2552 /* AI_SI2_Reload_Mode = alternate */
2553 /* AI_SI2_Initial_Load_Source = A */
2554 mode2 &= ~AI_SI2_Initial_Load_Source;
2555 mode2 |= AI_SI2_Reload_Mode;
2556 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2557
2558 /* AI_SI2_Load */
2559 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2560
2561 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2562 mode2 |= AI_SI2_Initial_Load_Source; /* B */
2563
2564 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2565 break;
2566 case TRIG_EXT:
2567 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2568 if ((cmd->convert_arg & CR_INVERT) == 0)
2569 mode1 |= AI_CONVERT_Source_Polarity;
2570 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2571
2572 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2573 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2574
2575 break;
2576 }
2577
2578 if (dev->irq) {
2579
2580 /* interrupt on FIFO, errors, SC_TC */
2581 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2582 AI_SC_TC_Interrupt_Enable;
2583
2584 #ifndef PCIDMA
2585 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2586 #endif
2587
2588 if (cmd->flags & TRIG_WAKE_EOS
2589 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2590 /* wake on end-of-scan */
2591 devpriv->aimode = AIMODE_SCAN;
2592 } else {
2593 devpriv->aimode = AIMODE_HALF_FULL;
2594 }
2595
2596 switch (devpriv->aimode) {
2597 case AIMODE_HALF_FULL:
2598 /*generate FIFO interrupts and DMA requests on half-full */
2599 #ifdef PCIDMA
2600 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2601 AI_Mode_3_Register);
2602 #else
2603 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2604 AI_Mode_3_Register);
2605 #endif
2606 break;
2607 case AIMODE_SAMPLE:
2608 /*generate FIFO interrupts on non-empty */
2609 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2610 AI_Mode_3_Register);
2611 break;
2612 case AIMODE_SCAN:
2613 #ifdef PCIDMA
2614 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2615 AI_Mode_3_Register);
2616 #else
2617 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2618 AI_Mode_3_Register);
2619 #endif
2620 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2621 break;
2622 default:
2623 break;
2624 }
2625
2626 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2627
2628 ni_set_bits(dev, Interrupt_A_Enable_Register,
2629 interrupt_a_enable, 1);
2630
2631 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2632 devpriv->int_a_enable_reg);
2633 } else {
2634 /* interrupt on nothing */
2635 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2636
2637 /* XXX start polling if necessary */
2638 MDPRINTK("interrupting on nothing\n");
2639 }
2640
2641 /* end configuration */
2642 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2643
2644 switch (cmd->scan_begin_src) {
2645 case TRIG_TIMER:
2646 devpriv->stc_writew(dev,
2647 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2648 AI_SC_Arm, AI_Command_1_Register);
2649 break;
2650 case TRIG_EXT:
2651 /* XXX AI_SI_Arm? */
2652 devpriv->stc_writew(dev,
2653 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2654 AI_SC_Arm, AI_Command_1_Register);
2655 break;
2656 }
2657
2658 #ifdef PCIDMA
2659 {
2660 int retval = ni_ai_setup_MITE_dma(dev);
2661 if (retval)
2662 return retval;
2663 }
2664 /* mite_dump_regs(devpriv->mite); */
2665 #endif
2666
2667 switch (cmd->start_src) {
2668 case TRIG_NOW:
2669 /* AI_START1_Pulse */
2670 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2671 AI_Command_2_Register);
2672 s->async->inttrig = NULL;
2673 break;
2674 case TRIG_EXT:
2675 s->async->inttrig = NULL;
2676 break;
2677 case TRIG_INT:
2678 s->async->inttrig = &ni_ai_inttrig;
2679 break;
2680 }
2681
2682 MDPRINTK("exit ni_ai_cmd\n");
2683
2684 return 0;
2685 }
2686
2687 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2688 unsigned int trignum)
2689 {
2690 struct ni_private *devpriv = dev->private;
2691
2692 if (trignum != 0)
2693 return -EINVAL;
2694
2695 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2696 AI_Command_2_Register);
2697 s->async->inttrig = NULL;
2698
2699 return 1;
2700 }
2701
2702 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2703 struct comedi_subdevice *s,
2704 struct comedi_insn *insn,
2705 unsigned int *data);
2706
2707 static int ni_ai_insn_config(struct comedi_device *dev,
2708 struct comedi_subdevice *s,
2709 struct comedi_insn *insn, unsigned int *data)
2710 {
2711 const struct ni_board_struct *board = comedi_board(dev);
2712 struct ni_private *devpriv = dev->private;
2713
2714 if (insn->n < 1)
2715 return -EINVAL;
2716
2717 switch (data[0]) {
2718 case INSN_CONFIG_ANALOG_TRIG:
2719 return ni_ai_config_analog_trig(dev, s, insn, data);
2720 case INSN_CONFIG_ALT_SOURCE:
2721 if (board->reg_type & ni_reg_m_series_mask) {
2722 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2723 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2724 MSeries_AI_Bypass_Mode_Mux_Mask |
2725 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2726 return -EINVAL;
2727 }
2728 devpriv->ai_calib_source = data[1];
2729 } else if (board->reg_type == ni_reg_6143) {
2730 unsigned int calib_source;
2731
2732 calib_source = data[1] & 0xf;
2733
2734 if (calib_source > 0xF)
2735 return -EINVAL;
2736
2737 devpriv->ai_calib_source = calib_source;
2738 ni_writew(calib_source, Calibration_Channel_6143);
2739 } else {
2740 unsigned int calib_source;
2741 unsigned int calib_source_adjust;
2742
2743 calib_source = data[1] & 0xf;
2744 calib_source_adjust = (data[1] >> 4) & 0xff;
2745
2746 if (calib_source >= 8)
2747 return -EINVAL;
2748 devpriv->ai_calib_source = calib_source;
2749 if (board->reg_type == ni_reg_611x) {
2750 ni_writeb(calib_source_adjust,
2751 Cal_Gain_Select_611x);
2752 }
2753 }
2754 return 2;
2755 default:
2756 break;
2757 }
2758
2759 return -EINVAL;
2760 }
2761
2762 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2763 struct comedi_subdevice *s,
2764 struct comedi_insn *insn,
2765 unsigned int *data)
2766 {
2767 const struct ni_board_struct *board = comedi_board(dev);
2768 struct ni_private *devpriv = dev->private;
2769 unsigned int a, b, modebits;
2770 int err = 0;
2771
2772 /* data[1] is flags
2773 * data[2] is analog line
2774 * data[3] is set level
2775 * data[4] is reset level */
2776 if (!board->has_analog_trig)
2777 return -EINVAL;
2778 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2779 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2780 err++;
2781 }
2782 if (data[2] >= board->n_adchan) {
2783 data[2] = board->n_adchan - 1;
2784 err++;
2785 }
2786 if (data[3] > 255) { /* a */
2787 data[3] = 255;
2788 err++;
2789 }
2790 if (data[4] > 255) { /* b */
2791 data[4] = 255;
2792 err++;
2793 }
2794 /*
2795 * 00 ignore
2796 * 01 set
2797 * 10 reset
2798 *
2799 * modes:
2800 * 1 level: +b- +a-
2801 * high mode 00 00 01 10
2802 * low mode 00 00 10 01
2803 * 2 level: (a<b)
2804 * hysteresis low mode 10 00 00 01
2805 * hysteresis high mode 01 00 00 10
2806 * middle mode 10 01 01 10
2807 */
2808
2809 a = data[3];
2810 b = data[4];
2811 modebits = data[1] & 0xff;
2812 if (modebits & 0xf0) {
2813 /* two level mode */
2814 if (b < a) {
2815 /* swap order */
2816 a = data[4];
2817 b = data[3];
2818 modebits =
2819 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2820 }
2821 devpriv->atrig_low = a;
2822 devpriv->atrig_high = b;
2823 switch (modebits) {
2824 case 0x81: /* low hysteresis mode */
2825 devpriv->atrig_mode = 6;
2826 break;
2827 case 0x42: /* high hysteresis mode */
2828 devpriv->atrig_mode = 3;
2829 break;
2830 case 0x96: /* middle window mode */
2831 devpriv->atrig_mode = 2;
2832 break;
2833 default:
2834 data[1] &= ~0xff;
2835 err++;
2836 }
2837 } else {
2838 /* one level mode */
2839 if (b != 0) {
2840 data[4] = 0;
2841 err++;
2842 }
2843 switch (modebits) {
2844 case 0x06: /* high window mode */
2845 devpriv->atrig_high = a;
2846 devpriv->atrig_mode = 0;
2847 break;
2848 case 0x09: /* low window mode */
2849 devpriv->atrig_low = a;
2850 devpriv->atrig_mode = 1;
2851 break;
2852 default:
2853 data[1] &= ~0xff;
2854 err++;
2855 }
2856 }
2857 if (err)
2858 return -EAGAIN;
2859 return 5;
2860 }
2861
2862 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2863 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2864 void *data, unsigned int num_bytes,
2865 unsigned int chan_index)
2866 {
2867 const struct ni_board_struct *board = comedi_board(dev);
2868 struct comedi_async *async = s->async;
2869 unsigned int range;
2870 unsigned int i;
2871 unsigned int offset;
2872 unsigned int length = num_bytes / sizeof(short);
2873 short *array = data;
2874
2875 offset = 1 << (board->aobits - 1);
2876 for (i = 0; i < length; i++) {
2877 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2878 if (board->ao_unipolar == 0 || (range & 1) == 0)
2879 array[i] -= offset;
2880 #ifdef PCIDMA
2881 array[i] = cpu_to_le16(array[i]);
2882 #endif
2883 chan_index++;
2884 chan_index %= async->cmd.chanlist_len;
2885 }
2886 }
2887
2888 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2889 struct comedi_subdevice *s,
2890 unsigned int chanspec[],
2891 unsigned int n_chans, int timed)
2892 {
2893 const struct ni_board_struct *board = comedi_board(dev);
2894 struct ni_private *devpriv = dev->private;
2895 unsigned int range;
2896 unsigned int chan;
2897 unsigned int conf;
2898 int i;
2899 int invert = 0;
2900
2901 if (timed) {
2902 for (i = 0; i < board->n_aochan; ++i) {
2903 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2904 ni_writeb(devpriv->ao_conf[i],
2905 M_Offset_AO_Config_Bank(i));
2906 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2907 }
2908 }
2909 for (i = 0; i < n_chans; i++) {
2910 const struct comedi_krange *krange;
2911 chan = CR_CHAN(chanspec[i]);
2912 range = CR_RANGE(chanspec[i]);
2913 krange = s->range_table->range + range;
2914 invert = 0;
2915 conf = 0;
2916 switch (krange->max - krange->min) {
2917 case 20000000:
2918 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2919 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2920 break;
2921 case 10000000:
2922 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2923 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2924 break;
2925 case 4000000:
2926 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2927 ni_writeb(MSeries_Attenuate_x5_Bit,
2928 M_Offset_AO_Reference_Attenuation(chan));
2929 break;
2930 case 2000000:
2931 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2932 ni_writeb(MSeries_Attenuate_x5_Bit,
2933 M_Offset_AO_Reference_Attenuation(chan));
2934 break;
2935 default:
2936 printk("%s: bug! unhandled ao reference voltage\n",
2937 __func__);
2938 break;
2939 }
2940 switch (krange->max + krange->min) {
2941 case 0:
2942 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2943 break;
2944 case 10000000:
2945 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2946 break;
2947 default:
2948 printk("%s: bug! unhandled ao offset voltage\n",
2949 __func__);
2950 break;
2951 }
2952 if (timed)
2953 conf |= MSeries_AO_Update_Timed_Bit;
2954 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2955 devpriv->ao_conf[chan] = conf;
2956 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2957 }
2958 return invert;
2959 }
2960
2961 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2962 struct comedi_subdevice *s,
2963 unsigned int chanspec[],
2964 unsigned int n_chans)
2965 {
2966 const struct ni_board_struct *board = comedi_board(dev);
2967 struct ni_private *devpriv = dev->private;
2968 unsigned int range;
2969 unsigned int chan;
2970 unsigned int conf;
2971 int i;
2972 int invert = 0;
2973
2974 for (i = 0; i < n_chans; i++) {
2975 chan = CR_CHAN(chanspec[i]);
2976 range = CR_RANGE(chanspec[i]);
2977 conf = AO_Channel(chan);
2978
2979 if (board->ao_unipolar) {
2980 if ((range & 1) == 0) {
2981 conf |= AO_Bipolar;
2982 invert = (1 << (board->aobits - 1));
2983 } else {
2984 invert = 0;
2985 }
2986 if (range & 2)
2987 conf |= AO_Ext_Ref;
2988 } else {
2989 conf |= AO_Bipolar;
2990 invert = (1 << (board->aobits - 1));
2991 }
2992
2993 /* not all boards can deglitch, but this shouldn't hurt */
2994 if (chanspec[i] & CR_DEGLITCH)
2995 conf |= AO_Deglitch;
2996
2997 /* analog reference */
2998 /* AREF_OTHER connects AO ground to AI ground, i think */
2999 conf |= (CR_AREF(chanspec[i]) ==
3000 AREF_OTHER) ? AO_Ground_Ref : 0;
3001
3002 ni_writew(conf, AO_Configuration);
3003 devpriv->ao_conf[chan] = conf;
3004 }
3005 return invert;
3006 }
3007
3008 static int ni_ao_config_chanlist(struct comedi_device *dev,
3009 struct comedi_subdevice *s,
3010 unsigned int chanspec[], unsigned int n_chans,
3011 int timed)
3012 {
3013 const struct ni_board_struct *board = comedi_board(dev);
3014
3015 if (board->reg_type & ni_reg_m_series_mask)
3016 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3017 timed);
3018 else
3019 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3020 }
3021
3022 static int ni_ao_insn_read(struct comedi_device *dev,
3023 struct comedi_subdevice *s, struct comedi_insn *insn,
3024 unsigned int *data)
3025 {
3026 struct ni_private *devpriv = dev->private;
3027
3028 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3029
3030 return 1;
3031 }
3032
3033 static int ni_ao_insn_write(struct comedi_device *dev,
3034 struct comedi_subdevice *s,
3035 struct comedi_insn *insn, unsigned int *data)
3036 {
3037 const struct ni_board_struct *board = comedi_board(dev);
3038 struct ni_private *devpriv = dev->private;
3039 unsigned int chan = CR_CHAN(insn->chanspec);
3040 unsigned int invert;
3041
3042 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3043
3044 devpriv->ao[chan] = data[0];
3045
3046 if (board->reg_type & ni_reg_m_series_mask) {
3047 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3048 } else
3049 ni_writew(data[0] ^ invert,
3050 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3051
3052 return 1;
3053 }
3054
3055 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3056 struct comedi_subdevice *s,
3057 struct comedi_insn *insn, unsigned int *data)
3058 {
3059 const struct ni_board_struct *board = comedi_board(dev);
3060 struct ni_private *devpriv = dev->private;
3061 unsigned int chan = CR_CHAN(insn->chanspec);
3062 unsigned int invert;
3063
3064 ao_win_out(1 << chan, AO_Immediate_671x);
3065 invert = 1 << (board->aobits - 1);
3066
3067 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3068
3069 devpriv->ao[chan] = data[0];
3070 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3071
3072 return 1;
3073 }
3074
3075 static int ni_ao_insn_config(struct comedi_device *dev,
3076 struct comedi_subdevice *s,
3077 struct comedi_insn *insn, unsigned int *data)
3078 {
3079 const struct ni_board_struct *board = comedi_board(dev);
3080 struct ni_private *devpriv = dev->private;
3081
3082 switch (data[0]) {
3083 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3084 switch (data[1]) {
3085 case COMEDI_OUTPUT:
3086 data[2] = 1 + board->ao_fifo_depth * sizeof(short);
3087 if (devpriv->mite)
3088 data[2] += devpriv->mite->fifo_size;
3089 break;
3090 case COMEDI_INPUT:
3091 data[2] = 0;
3092 break;
3093 default:
3094 return -EINVAL;
3095 break;
3096 }
3097 return 0;
3098 default:
3099 break;
3100 }
3101
3102 return -EINVAL;
3103 }
3104
3105 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3106 unsigned int trignum)
3107 {
3108 const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
3109 struct ni_private *devpriv = dev->private;
3110 int ret;
3111 int interrupt_b_bits;
3112 int i;
3113 static const int timeout = 1000;
3114
3115 if (trignum != 0)
3116 return -EINVAL;
3117
3118 /* Null trig at beginning prevent ao start trigger from executing more than
3119 once per command (and doing things like trying to allocate the ao dma channel
3120 multiple times) */
3121 s->async->inttrig = NULL;
3122
3123 ni_set_bits(dev, Interrupt_B_Enable_Register,
3124 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3125 interrupt_b_bits = AO_Error_Interrupt_Enable;
3126 #ifdef PCIDMA
3127 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3128 if (board->reg_type & ni_reg_6xxx_mask)
3129 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3130 ret = ni_ao_setup_MITE_dma(dev);
3131 if (ret)
3132 return ret;
3133 ret = ni_ao_wait_for_dma_load(dev);
3134 if (ret < 0)
3135 return ret;
3136 #else
3137 ret = ni_ao_prep_fifo(dev, s);
3138 if (ret == 0)
3139 return -EPIPE;
3140
3141 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3142 #endif
3143
3144 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3145 AO_Mode_3_Register);
3146 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3147 /* wait for DACs to be loaded */
3148 for (i = 0; i < timeout; i++) {
3149 udelay(1);
3150 if ((devpriv->stc_readw(dev,
3151 Joint_Status_2_Register) &
3152 AO_TMRDACWRs_In_Progress_St) == 0)
3153 break;
3154 }
3155 if (i == timeout) {
3156 comedi_error(dev,
3157 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3158 return -EIO;
3159 }
3160 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3161 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3162 Interrupt_B_Ack_Register);
3163
3164 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3165
3166 devpriv->stc_writew(dev,
3167 devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3168 | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3169 AO_Command_1_Register);
3170
3171 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3172 AO_Command_2_Register);
3173
3174 return 0;
3175 }
3176
3177 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3178 {
3179 const struct ni_board_struct *board = comedi_board(dev);
3180 struct ni_private *devpriv = dev->private;
3181 const struct comedi_cmd *cmd = &s->async->cmd;
3182 int bits;
3183 int i;
3184 unsigned trigvar;
3185
3186 if (dev->irq == 0) {
3187 comedi_error(dev, "cannot run command without an irq");
3188 return -EIO;
3189 }
3190
3191 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3192
3193 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3194
3195 if (board->reg_type & ni_reg_6xxx_mask) {
3196 ao_win_out(CLEAR_WG, AO_Misc_611x);
3197
3198 bits = 0;
3199 for (i = 0; i < cmd->chanlist_len; i++) {
3200 int chan;
3201
3202 chan = CR_CHAN(cmd->chanlist[i]);
3203 bits |= 1 << chan;
3204 ao_win_out(chan, AO_Waveform_Generation_611x);
3205 }
3206 ao_win_out(bits, AO_Timed_611x);
3207 }
3208
3209 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3210
3211 if (cmd->stop_src == TRIG_NONE) {
3212 devpriv->ao_mode1 |= AO_Continuous;
3213 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3214 } else {
3215 devpriv->ao_mode1 &= ~AO_Continuous;
3216 devpriv->ao_mode1 |= AO_Trigger_Once;
3217 }
3218 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3219 switch (cmd->start_src) {
3220 case TRIG_INT:
3221 case TRIG_NOW:
3222 devpriv->ao_trigger_select &=
3223 ~(AO_START1_Polarity | AO_START1_Select(-1));
3224 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3225 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3226 AO_Trigger_Select_Register);
3227 break;
3228 case TRIG_EXT:
3229 devpriv->ao_trigger_select =
3230 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3231 if (cmd->start_arg & CR_INVERT)
3232 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3233 if (cmd->start_arg & CR_EDGE)
3234 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3235 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3236 AO_Trigger_Select_Register);
3237 break;
3238 default:
3239 BUG();
3240 break;
3241 }
3242 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3243 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3244
3245 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3246 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3247 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3248 if (cmd->stop_src == TRIG_NONE) {
3249 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3250 } else {
3251 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3252 }
3253 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3254 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3255 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3256 switch (cmd->stop_src) {
3257 case TRIG_COUNT:
3258 if (board->reg_type & ni_reg_m_series_mask) {
3259 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3260 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3261 AO_UC_Load_A_Register);
3262 devpriv->stc_writew(dev, AO_UC_Load,
3263 AO_Command_1_Register);
3264 } else {
3265 devpriv->stc_writel(dev, cmd->stop_arg,
3266 AO_UC_Load_A_Register);
3267 devpriv->stc_writew(dev, AO_UC_Load,
3268 AO_Command_1_Register);
3269 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3270 AO_UC_Load_A_Register);
3271 }
3272 break;
3273 case TRIG_NONE:
3274 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3275 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3276 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3277 break;
3278 default:
3279 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3280 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3281 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3282 }
3283
3284 devpriv->ao_mode1 &=
3285 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3286 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3287 switch (cmd->scan_begin_src) {
3288 case TRIG_TIMER:
3289 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3290 trigvar =
3291 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3292 TRIG_ROUND_NEAREST);
3293 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3294 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3295 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3296 break;
3297 case TRIG_EXT:
3298 devpriv->ao_mode1 |=
3299 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3300 if (cmd->scan_begin_arg & CR_INVERT)
3301 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3302 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3303 break;
3304 default:
3305 BUG();
3306 break;
3307 }
3308 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3309 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3310 devpriv->ao_mode2 &=
3311 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3312 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3313
3314 if (cmd->scan_end_arg > 1) {
3315 devpriv->ao_mode1 |= AO_Multiple_Channels;
3316 devpriv->stc_writew(dev,
3317 AO_Number_Of_Channels(cmd->scan_end_arg -
3318 1) |
3319 AO_UPDATE_Output_Select
3320 (AO_Update_Output_High_Z),
3321 AO_Output_Control_Register);
3322 } else {
3323 unsigned bits;
3324 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3325 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3326 if (board->reg_type &
3327 (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3328 bits |= AO_Number_Of_Channels(0);
3329 } else {
3330 bits |=
3331 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3332 }
3333 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3334 }
3335 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3336
3337 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3338 AO_Command_1_Register);
3339
3340 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3341 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3342
3343 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3344 #ifdef PCIDMA
3345 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3346 #else
3347 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3348 #endif
3349 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3350 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3351
3352 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3353 AO_TMRDACWR_Pulse_Width;
3354 if (board->ao_fifo_depth)
3355 bits |= AO_FIFO_Enable;
3356 else
3357 bits |= AO_DMA_PIO_Control;
3358 #if 0
3359 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3360 verified with bus analyzer. */
3361 if (board->reg_type & ni_reg_m_series_mask)
3362 bits |= AO_Number_Of_DAC_Packages;
3363 #endif
3364 devpriv->stc_writew(dev, bits, AO_Personal_Register);
3365 /* enable sending of ao dma requests */
3366 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3367
3368 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3369
3370 if (cmd->stop_src == TRIG_COUNT) {
3371 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3372 Interrupt_B_Ack_Register);
3373 ni_set_bits(dev, Interrupt_B_Enable_Register,
3374 AO_BC_TC_Interrupt_Enable, 1);
3375 }
3376
3377 s->async->inttrig = &ni_ao_inttrig;
3378
3379 return 0;
3380 }
3381
3382 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3383 struct comedi_cmd *cmd)
3384 {
3385 const struct ni_board_struct *board = comedi_board(dev);
3386 struct ni_private *devpriv = dev->private;
3387 int err = 0;
3388 int tmp;
3389
3390 /* Step 1 : check if triggers are trivially valid */
3391
3392 if ((cmd->flags & CMDF_WRITE) == 0)
3393 cmd->flags |= CMDF_WRITE;
3394
3395 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3396 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3397 TRIG_TIMER | TRIG_EXT);
3398 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3399 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3400 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3401
3402 if (err)
3403 return 1;
3404
3405 /* Step 2a : make sure trigger sources are unique */
3406
3407 err |= cfc_check_trigger_is_unique(cmd->start_src);
3408 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3409 err |= cfc_check_trigger_is_unique(cmd->stop_src);
3410
3411 /* Step 2b : and mutually compatible */
3412
3413 if (err)
3414 return 2;
3415
3416 /* Step 3: check if arguments are trivially valid */
3417
3418 if (cmd->start_src == TRIG_EXT) {
3419 /* external trigger */
3420 unsigned int tmp = CR_CHAN(cmd->start_arg);
3421
3422 if (tmp > 18)
3423 tmp = 18;
3424 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3425 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3426 } else {
3427 /* true for both TRIG_NOW and TRIG_INT */
3428 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3429 }
3430
3431 if (cmd->scan_begin_src == TRIG_TIMER) {
3432 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3433 board->ao_speed);
3434 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3435 devpriv->clock_ns * 0xffffff);
3436 }
3437
3438 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3439 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3440
3441 if (cmd->stop_src == TRIG_COUNT)
3442 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3443 else /* TRIG_NONE */
3444 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3445
3446 if (err)
3447 return 3;
3448
3449 /* step 4: fix up any arguments */
3450 if (cmd->scan_begin_src == TRIG_TIMER) {
3451 tmp = cmd->scan_begin_arg;
3452 cmd->scan_begin_arg =
3453 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3454 cmd->scan_begin_arg,
3455 cmd->
3456 flags &
3457 TRIG_ROUND_MASK));
3458 if (tmp != cmd->scan_begin_arg)
3459 err++;
3460 }
3461 if (err)
3462 return 4;
3463
3464 /* step 5: fix up chanlist */
3465
3466 if (err)
3467 return 5;
3468
3469 return 0;
3470 }
3471
3472 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3473 {
3474 const struct ni_board_struct *board = comedi_board(dev);
3475 struct ni_private *devpriv = dev->private;
3476
3477 /* devpriv->ao0p=0x0000; */
3478 /* ni_writew(devpriv->ao0p,AO_Configuration); */
3479
3480 /* devpriv->ao1p=AO_Channel(1); */
3481 /* ni_writew(devpriv->ao1p,AO_Configuration); */
3482
3483 ni_release_ao_mite_channel(dev);
3484
3485 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3486 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3487 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3488 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3489 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3490 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3491 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3492 devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3493 devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3494 devpriv->ao_cmd1 = 0;
3495 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3496 devpriv->ao_cmd2 = 0;
3497 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3498 devpriv->ao_mode1 = 0;
3499 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3500 devpriv->ao_mode2 = 0;
3501 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3502 if (board->reg_type & ni_reg_m_series_mask)
3503 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3504 else
3505 devpriv->ao_mode3 = 0;
3506 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3507 devpriv->ao_trigger_select = 0;
3508 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3509 AO_Trigger_Select_Register);
3510 if (board->reg_type & ni_reg_6xxx_mask) {
3511 unsigned immediate_bits = 0;
3512 unsigned i;
3513 for (i = 0; i < s->n_chan; ++i) {
3514 immediate_bits |= 1 << i;
3515 }
3516 ao_win_out(immediate_bits, AO_Immediate_671x);
3517 ao_win_out(CLEAR_WG, AO_Misc_611x);
3518 }
3519 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3520
3521 return 0;
3522 }
3523
3524 /* digital io */
3525
3526 static int ni_dio_insn_config(struct comedi_device *dev,
3527 struct comedi_subdevice *s,
3528 struct comedi_insn *insn, unsigned int *data)
3529 {
3530 struct ni_private *devpriv = dev->private;
3531
3532 #ifdef DEBUG_DIO
3533 printk("ni_dio_insn_config() chan=%d io=%d\n",
3534 CR_CHAN(insn->chanspec), data[0]);
3535 #endif
3536 switch (data[0]) {
3537 case INSN_CONFIG_DIO_OUTPUT:
3538 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3539 break;
3540 case INSN_CONFIG_DIO_INPUT:
3541 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3542 break;
3543 case INSN_CONFIG_DIO_QUERY:
3544 data[1] =
3545 (s->
3546 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3547 COMEDI_INPUT;
3548 return insn->n;
3549 break;
3550 default:
3551 return -EINVAL;
3552 }
3553
3554 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3555 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3556 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3557
3558 return 1;
3559 }
3560
3561 static int ni_dio_insn_bits(struct comedi_device *dev,
3562 struct comedi_subdevice *s,
3563 struct comedi_insn *insn, unsigned int *data)
3564 {
3565 struct ni_private *devpriv = dev->private;
3566
3567 #ifdef DEBUG_DIO
3568 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3569 #endif
3570
3571 if (data[0]) {
3572 /* Perform check to make sure we're not using the
3573 serial part of the dio */
3574 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3575 && devpriv->serial_interval_ns)
3576 return -EBUSY;
3577
3578 s->state &= ~data[0];
3579 s->state |= (data[0] & data[1]);
3580 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3581 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3582 devpriv->stc_writew(dev, devpriv->dio_output,
3583 DIO_Output_Register);
3584 }
3585 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3586
3587 return insn->n;
3588 }
3589
3590 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3591 struct comedi_subdevice *s,
3592 struct comedi_insn *insn,
3593 unsigned int *data)
3594 {
3595 struct ni_private *devpriv __maybe_unused = dev->private;
3596
3597 #ifdef DEBUG_DIO
3598 printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3599 CR_CHAN(insn->chanspec), data[0]);
3600 #endif
3601 switch (data[0]) {
3602 case INSN_CONFIG_DIO_OUTPUT:
3603 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3604 break;
3605 case INSN_CONFIG_DIO_INPUT:
3606 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3607 break;
3608 case INSN_CONFIG_DIO_QUERY:
3609 data[1] =
3610 (s->
3611 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3612 COMEDI_INPUT;
3613 return insn->n;
3614 break;
3615 default:
3616 return -EINVAL;
3617 }
3618
3619 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3620
3621 return 1;
3622 }
3623
3624 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3625 struct comedi_subdevice *s,
3626 struct comedi_insn *insn,
3627 unsigned int *data)
3628 {
3629 struct ni_private *devpriv __maybe_unused = dev->private;
3630
3631 #ifdef DEBUG_DIO
3632 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3633 data[1]);
3634 #endif
3635
3636 if (data[0]) {
3637 s->state &= ~data[0];
3638 s->state |= (data[0] & data[1]);
3639 ni_writel(s->state, M_Offset_Static_Digital_Output);
3640 }
3641 data[1] = ni_readl(M_Offset_Static_Digital_Input);
3642
3643 return insn->n;
3644 }
3645
3646 static int ni_cdio_cmdtest(struct comedi_device *dev,
3647 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3648 {
3649 int err = 0;
3650 int tmp;
3651 unsigned i;
3652
3653 /* Step 1 : check if triggers are trivially valid */
3654
3655 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3656 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3657 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3658 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3659 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3660
3661 if (err)
3662 return 1;
3663
3664 /* Step 2a : make sure trigger sources are unique */
3665 /* Step 2b : and mutually compatible */
3666
3667 if (err)
3668 return 2;
3669
3670 /* Step 3: check if arguments are trivially valid */
3671
3672 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3673
3674 tmp = cmd->scan_begin_arg;
3675 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3676 if (tmp != cmd->scan_begin_arg)
3677 err |= -EINVAL;
3678
3679 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3680 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3681 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3682
3683 if (err)
3684 return 3;
3685
3686 /* step 4: fix up any arguments */
3687
3688 if (err)
3689 return 4;
3690
3691 /* step 5: check chanlist */
3692
3693 for (i = 0; i < cmd->chanlist_len; ++i) {
3694 if (cmd->chanlist[i] != i)
3695 err = 1;
3696 }
3697
3698 if (err)
3699 return 5;
3700
3701 return 0;
3702 }
3703
3704 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3705 {
3706 struct ni_private *devpriv __maybe_unused = dev->private;
3707 const struct comedi_cmd *cmd = &s->async->cmd;
3708 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3709 int retval;
3710
3711 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3712 switch (cmd->scan_begin_src) {
3713 case TRIG_EXT:
3714 cdo_mode_bits |=
3715 CR_CHAN(cmd->scan_begin_arg) &
3716 CDO_Sample_Source_Select_Mask;
3717 break;
3718 default:
3719 BUG();
3720 break;
3721 }
3722 if (cmd->scan_begin_arg & CR_INVERT)
3723 cdo_mode_bits |= CDO_Polarity_Bit;
3724 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3725 if (s->io_bits) {
3726 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3727 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3728 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3729 } else {
3730 comedi_error(dev,
3731 "attempted to run digital output command with no lines configured as outputs");
3732 return -EIO;
3733 }
3734 retval = ni_request_cdo_mite_channel(dev);
3735 if (retval < 0) {
3736 return retval;
3737 }
3738 s->async->inttrig = &ni_cdo_inttrig;
3739 return 0;
3740 }
3741
3742 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3743 unsigned int trignum)
3744 {
3745 #ifdef PCIDMA
3746 struct ni_private *devpriv = dev->private;
3747 unsigned long flags;
3748 #endif
3749 int retval = 0;
3750 unsigned i;
3751 const unsigned timeout = 1000;
3752
3753 s->async->inttrig = NULL;
3754
3755 /* read alloc the entire buffer */
3756 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3757
3758 #ifdef PCIDMA
3759 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3760 if (devpriv->cdo_mite_chan) {
3761 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3762 mite_dma_arm(devpriv->cdo_mite_chan);
3763 } else {
3764 comedi_error(dev, "BUG: no cdo mite channel?");
3765 retval = -EIO;
3766 }
3767 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3768 if (retval < 0)
3769 return retval;
3770 #endif
3771 /*
3772 * XXX not sure what interrupt C group does
3773 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3774 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3775 */
3776 for (i = 0; i < timeout; ++i) {
3777 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3778 break;
3779 udelay(10);
3780 }
3781 if (i == timeout) {
3782 comedi_error(dev, "dma failed to fill cdo fifo!");
3783 ni_cdio_cancel(dev, s);
3784 return -EIO;
3785 }
3786 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3787 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3788 M_Offset_CDIO_Command);
3789 return retval;
3790 }
3791
3792 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3793 {
3794 struct ni_private *devpriv __maybe_unused = dev->private;
3795
3796 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3797 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3798 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3799 M_Offset_CDIO_Command);
3800 /*
3801 * XXX not sure what interrupt C group does ni_writeb(0,
3802 * M_Offset_Interrupt_C_Enable);
3803 */
3804 ni_writel(0, M_Offset_CDO_Mask_Enable);
3805 ni_release_cdo_mite_channel(dev);
3806 return 0;
3807 }
3808
3809 static void handle_cdio_interrupt(struct comedi_device *dev)
3810 {
3811 const struct ni_board_struct *board = comedi_board(dev);
3812 struct ni_private *devpriv __maybe_unused = dev->private;
3813 unsigned cdio_status;
3814 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3815 #ifdef PCIDMA
3816 unsigned long flags;
3817 #endif
3818
3819 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
3820 return;
3821 }
3822 #ifdef PCIDMA
3823 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3824 if (devpriv->cdo_mite_chan) {
3825 unsigned cdo_mite_status =
3826 mite_get_status(devpriv->cdo_mite_chan);
3827 if (cdo_mite_status & CHSR_LINKC) {
3828 writel(CHOR_CLRLC,
3829 devpriv->mite->mite_io_addr +
3830 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3831 }
3832 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3833 }
3834 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3835 #endif
3836
3837 cdio_status = ni_readl(M_Offset_CDIO_Status);
3838 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3839 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3840 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */
3841 s->async->events |= COMEDI_CB_OVERFLOW;
3842 }
3843 if (cdio_status & CDO_FIFO_Empty_Bit) {
3844 /* printk("cdio fifo empty\n"); */
3845 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3846 M_Offset_CDIO_Command);
3847 /* s->async->events |= COMEDI_CB_EOA; */
3848 }
3849 ni_event(dev, s);
3850 }
3851
3852 static int ni_serial_insn_config(struct comedi_device *dev,
3853 struct comedi_subdevice *s,
3854 struct comedi_insn *insn, unsigned int *data)
3855 {
3856 struct ni_private *devpriv = dev->private;
3857 int err = insn->n;
3858 unsigned char byte_out, byte_in = 0;
3859
3860 if (insn->n != 2)
3861 return -EINVAL;
3862
3863 switch (data[0]) {
3864 case INSN_CONFIG_SERIAL_CLOCK:
3865
3866 #ifdef DEBUG_DIO
3867 printk("SPI serial clock Config cd\n", data[1]);
3868 #endif
3869 devpriv->serial_hw_mode = 1;
3870 devpriv->dio_control |= DIO_HW_Serial_Enable;
3871
3872 if (data[1] == SERIAL_DISABLED) {
3873 devpriv->serial_hw_mode = 0;
3874 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3875 DIO_Software_Serial_Control);
3876 data[1] = SERIAL_DISABLED;
3877 devpriv->serial_interval_ns = data[1];
3878 } else if (data[1] <= SERIAL_600NS) {
3879 /* Warning: this clock speed is too fast to reliably
3880 control SCXI. */
3881 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3882 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3883 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3884 data[1] = SERIAL_600NS;
3885 devpriv->serial_interval_ns = data[1];
3886 } else if (data[1] <= SERIAL_1_2US) {
3887 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3888 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3889 DIO_Serial_Out_Divide_By_2;
3890 data[1] = SERIAL_1_2US;
3891 devpriv->serial_interval_ns = data[1];
3892 } else if (data[1] <= SERIAL_10US) {
3893 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3894 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3895 DIO_Serial_Out_Divide_By_2;
3896 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3897 600ns/1.2us. If you turn divide_by_2 off with the
3898 slow clock, you will still get 10us, except then
3899 all your delays are wrong. */
3900 data[1] = SERIAL_10US;
3901 devpriv->serial_interval_ns = data[1];
3902 } else {
3903 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3904 DIO_Software_Serial_Control);
3905 devpriv->serial_hw_mode = 0;
3906 data[1] = (data[1] / 1000) * 1000;
3907 devpriv->serial_interval_ns = data[1];
3908 }
3909
3910 devpriv->stc_writew(dev, devpriv->dio_control,
3911 DIO_Control_Register);
3912 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3913 Clock_and_FOUT_Register);
3914 return 1;
3915
3916 break;
3917
3918 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3919
3920 if (devpriv->serial_interval_ns == 0) {
3921 return -EINVAL;
3922 }
3923
3924 byte_out = data[1] & 0xFF;
3925
3926 if (devpriv->serial_hw_mode) {
3927 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3928 &byte_in);
3929 } else if (devpriv->serial_interval_ns > 0) {
3930 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3931 &byte_in);
3932 } else {
3933 printk("ni_serial_insn_config: serial disabled!\n");
3934 return -EINVAL;
3935 }
3936 if (err < 0)
3937 return err;
3938 data[1] = byte_in & 0xFF;
3939 return insn->n;
3940
3941 break;
3942 default:
3943 return -EINVAL;
3944 }
3945
3946 }
3947
3948 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3949 struct comedi_subdevice *s,
3950 unsigned char data_out,
3951 unsigned char *data_in)
3952 {
3953 struct ni_private *devpriv = dev->private;
3954 unsigned int status1;
3955 int err = 0, count = 20;
3956
3957 #ifdef DEBUG_DIO
3958 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3959 #endif
3960
3961 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3962 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3963 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3964
3965 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3966 if (status1 & DIO_Serial_IO_In_Progress_St) {
3967 err = -EBUSY;
3968 goto Error;
3969 }
3970
3971 devpriv->dio_control |= DIO_HW_Serial_Start;
3972 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3973 devpriv->dio_control &= ~DIO_HW_Serial_Start;
3974
3975 /* Wait until STC says we're done, but don't loop infinitely. */
3976 while ((status1 =
3977 devpriv->stc_readw(dev,
3978 Joint_Status_1_Register)) &
3979 DIO_Serial_IO_In_Progress_St) {
3980 /* Delay one bit per loop */
3981 udelay((devpriv->serial_interval_ns + 999) / 1000);
3982 if (--count < 0) {
3983 printk
3984 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3985 err = -ETIME;
3986 goto Error;
3987 }
3988 }
3989
3990 /* Delay for last bit. This delay is absolutely necessary, because
3991 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3992 udelay((devpriv->serial_interval_ns + 999) / 1000);
3993
3994 if (data_in != NULL) {
3995 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3996 #ifdef DEBUG_DIO
3997 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3998 #endif
3999 }
4000
4001 Error:
4002 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4003
4004 return err;
4005 }
4006
4007 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
4008 struct comedi_subdevice *s,
4009 unsigned char data_out,
4010 unsigned char *data_in)
4011 {
4012 struct ni_private *devpriv = dev->private;
4013 unsigned char mask, input = 0;
4014
4015 #ifdef DEBUG_DIO
4016 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
4017 #endif
4018
4019 /* Wait for one bit before transfer */
4020 udelay((devpriv->serial_interval_ns + 999) / 1000);
4021
4022 for (mask = 0x80; mask; mask >>= 1) {
4023 /* Output current bit; note that we cannot touch s->state
4024 because it is a per-subdevice field, and serial is
4025 a separate subdevice from DIO. */
4026 devpriv->dio_output &= ~DIO_SDOUT;
4027 if (data_out & mask) {
4028 devpriv->dio_output |= DIO_SDOUT;
4029 }
4030 devpriv->stc_writew(dev, devpriv->dio_output,
4031 DIO_Output_Register);
4032
4033 /* Assert SDCLK (active low, inverted), wait for half of
4034 the delay, deassert SDCLK, and wait for the other half. */
4035 devpriv->dio_control |= DIO_Software_Serial_Control;
4036 devpriv->stc_writew(dev, devpriv->dio_control,
4037 DIO_Control_Register);
4038
4039 udelay((devpriv->serial_interval_ns + 999) / 2000);
4040
4041 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4042 devpriv->stc_writew(dev, devpriv->dio_control,
4043 DIO_Control_Register);
4044
4045 udelay((devpriv->serial_interval_ns + 999) / 2000);
4046
4047 /* Input current bit */
4048 if (devpriv->stc_readw(dev,
4049 DIO_Parallel_Input_Register) & DIO_SDIN)
4050 {
4051 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4052 input |= mask;
4053 }
4054 }
4055 #ifdef DEBUG_DIO
4056 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4057 #endif
4058 if (data_in)
4059 *data_in = input;
4060
4061 return 0;
4062 }
4063
4064 static void mio_common_detach(struct comedi_device *dev)
4065 {
4066 struct ni_private *devpriv = dev->private;
4067
4068 if (devpriv) {
4069 if (devpriv->counter_dev) {
4070 ni_gpct_device_destroy(devpriv->counter_dev);
4071 }
4072 }
4073 comedi_spriv_free(dev, NI_8255_DIO_SUBDEV);
4074 }
4075
4076 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4077 {
4078 int i;
4079
4080 for (i = 0; i < s->n_chan; i++) {
4081 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4082 AO_Configuration_2_67xx);
4083 }
4084 ao_win_out(0x0, AO_Later_Single_Point_Updates);
4085 }
4086
4087 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4088 {
4089 unsigned stc_register;
4090 switch (reg) {
4091 case NITIO_G0_Autoincrement_Reg:
4092 stc_register = G_Autoincrement_Register(0);
4093 break;
4094 case NITIO_G1_Autoincrement_Reg:
4095 stc_register = G_Autoincrement_Register(1);
4096 break;
4097 case NITIO_G0_Command_Reg:
4098 stc_register = G_Command_Register(0);
4099 break;
4100 case NITIO_G1_Command_Reg:
4101 stc_register = G_Command_Register(1);
4102 break;
4103 case NITIO_G0_HW_Save_Reg:
4104 stc_register = G_HW_Save_Register(0);
4105 break;
4106 case NITIO_G1_HW_Save_Reg:
4107 stc_register = G_HW_Save_Register(1);
4108 break;
4109 case NITIO_G0_SW_Save_Reg:
4110 stc_register = G_Save_Register(0);
4111 break;
4112 case NITIO_G1_SW_Save_Reg:
4113 stc_register = G_Save_Register(1);
4114 break;
4115 case NITIO_G0_Mode_Reg:
4116 stc_register = G_Mode_Register(0);
4117 break;
4118 case NITIO_G1_Mode_Reg:
4119 stc_register = G_Mode_Register(1);
4120 break;
4121 case NITIO_G0_LoadA_Reg:
4122 stc_register = G_Load_A_Register(0);
4123 break;
4124 case NITIO_G1_LoadA_Reg:
4125 stc_register = G_Load_A_Register(1);
4126 break;
4127 case NITIO_G0_LoadB_Reg:
4128 stc_register = G_Load_B_Register(0);
4129 break;
4130 case NITIO_G1_LoadB_Reg:
4131 stc_register = G_Load_B_Register(1);
4132 break;
4133 case NITIO_G0_Input_Select_Reg:
4134 stc_register = G_Input_Select_Register(0);
4135 break;
4136 case NITIO_G1_Input_Select_Reg:
4137 stc_register = G_Input_Select_Register(1);
4138 break;
4139 case NITIO_G01_Status_Reg:
4140 stc_register = G_Status_Register;
4141 break;
4142 case NITIO_G01_Joint_Reset_Reg:
4143 stc_register = Joint_Reset_Register;
4144 break;
4145 case NITIO_G01_Joint_Status1_Reg:
4146 stc_register = Joint_Status_1_Register;
4147 break;
4148 case NITIO_G01_Joint_Status2_Reg:
4149 stc_register = Joint_Status_2_Register;
4150 break;
4151 case NITIO_G0_Interrupt_Acknowledge_Reg:
4152 stc_register = Interrupt_A_Ack_Register;
4153 break;
4154 case NITIO_G1_Interrupt_Acknowledge_Reg:
4155 stc_register = Interrupt_B_Ack_Register;
4156 break;
4157 case NITIO_G0_Status_Reg:
4158 stc_register = AI_Status_1_Register;
4159 break;
4160 case NITIO_G1_Status_Reg:
4161 stc_register = AO_Status_1_Register;
4162 break;
4163 case NITIO_G0_Interrupt_Enable_Reg:
4164 stc_register = Interrupt_A_Enable_Register;
4165 break;
4166 case NITIO_G1_Interrupt_Enable_Reg:
4167 stc_register = Interrupt_B_Enable_Register;
4168 break;
4169 default:
4170 printk("%s: unhandled register 0x%x in switch.\n",
4171 __func__, reg);
4172 BUG();
4173 return 0;
4174 break;
4175 }
4176 return stc_register;
4177 }
4178
4179 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4180 enum ni_gpct_register reg)
4181 {
4182 struct comedi_device *dev = counter->counter_dev->dev;
4183 struct ni_private *devpriv = dev->private;
4184 unsigned stc_register;
4185 /* bits in the join reset register which are relevant to counters */
4186 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4187 static const unsigned gpct_interrupt_a_enable_mask =
4188 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4189 static const unsigned gpct_interrupt_b_enable_mask =
4190 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4191
4192 switch (reg) {
4193 /* m-series-only registers */
4194 case NITIO_G0_Counting_Mode_Reg:
4195 ni_writew(bits, M_Offset_G0_Counting_Mode);
4196 break;
4197 case NITIO_G1_Counting_Mode_Reg:
4198 ni_writew(bits, M_Offset_G1_Counting_Mode);
4199 break;
4200 case NITIO_G0_Second_Gate_Reg:
4201 ni_writew(bits, M_Offset_G0_Second_Gate);
4202 break;
4203 case NITIO_G1_Second_Gate_Reg:
4204 ni_writew(bits, M_Offset_G1_Second_Gate);
4205 break;
4206 case NITIO_G0_DMA_Config_Reg:
4207 ni_writew(bits, M_Offset_G0_DMA_Config);
4208 break;
4209 case NITIO_G1_DMA_Config_Reg:
4210 ni_writew(bits, M_Offset_G1_DMA_Config);
4211 break;
4212 case NITIO_G0_ABZ_Reg:
4213 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4214 break;
4215 case NITIO_G1_ABZ_Reg:
4216 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4217 break;
4218
4219 /* 32 bit registers */
4220 case NITIO_G0_LoadA_Reg:
4221 case NITIO_G1_LoadA_Reg:
4222 case NITIO_G0_LoadB_Reg:
4223 case NITIO_G1_LoadB_Reg:
4224 stc_register = ni_gpct_to_stc_register(reg);
4225 devpriv->stc_writel(dev, bits, stc_register);
4226 break;
4227
4228 /* 16 bit registers */
4229 case NITIO_G0_Interrupt_Enable_Reg:
4230 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4231 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4232 gpct_interrupt_a_enable_mask, bits);
4233 break;
4234 case NITIO_G1_Interrupt_Enable_Reg:
4235 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4236 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4237 gpct_interrupt_b_enable_mask, bits);
4238 break;
4239 case NITIO_G01_Joint_Reset_Reg:
4240 BUG_ON(bits & ~gpct_joint_reset_mask);
4241 /* fall-through */
4242 default:
4243 stc_register = ni_gpct_to_stc_register(reg);
4244 devpriv->stc_writew(dev, bits, stc_register);
4245 }
4246 }
4247
4248 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4249 enum ni_gpct_register reg)
4250 {
4251 struct comedi_device *dev = counter->counter_dev->dev;
4252 struct ni_private *devpriv = dev->private;
4253 unsigned stc_register;
4254
4255 switch (reg) {
4256 /* m-series only registers */
4257 case NITIO_G0_DMA_Status_Reg:
4258 return ni_readw(M_Offset_G0_DMA_Status);
4259 break;
4260 case NITIO_G1_DMA_Status_Reg:
4261 return ni_readw(M_Offset_G1_DMA_Status);
4262 break;
4263
4264 /* 32 bit registers */
4265 case NITIO_G0_HW_Save_Reg:
4266 case NITIO_G1_HW_Save_Reg:
4267 case NITIO_G0_SW_Save_Reg:
4268 case NITIO_G1_SW_Save_Reg:
4269 stc_register = ni_gpct_to_stc_register(reg);
4270 return devpriv->stc_readl(dev, stc_register);
4271 break;
4272
4273 /* 16 bit registers */
4274 default:
4275 stc_register = ni_gpct_to_stc_register(reg);
4276 return devpriv->stc_readw(dev, stc_register);
4277 break;
4278 }
4279 return 0;
4280 }
4281
4282 static int ni_freq_out_insn_read(struct comedi_device *dev,
4283 struct comedi_subdevice *s,
4284 struct comedi_insn *insn, unsigned int *data)
4285 {
4286 struct ni_private *devpriv = dev->private;
4287
4288 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4289 return 1;
4290 }
4291
4292 static int ni_freq_out_insn_write(struct comedi_device *dev,
4293 struct comedi_subdevice *s,
4294 struct comedi_insn *insn, unsigned int *data)
4295 {
4296 struct ni_private *devpriv = dev->private;
4297
4298 devpriv->clock_and_fout &= ~FOUT_Enable;
4299 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4300 Clock_and_FOUT_Register);
4301 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4302 devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4303 devpriv->clock_and_fout |= FOUT_Enable;
4304 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4305 Clock_and_FOUT_Register);
4306 return insn->n;
4307 }
4308
4309 static int ni_set_freq_out_clock(struct comedi_device *dev,
4310 unsigned int clock_source)
4311 {
4312 struct ni_private *devpriv = dev->private;
4313
4314 switch (clock_source) {
4315 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4316 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4317 break;
4318 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4319 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4320 break;
4321 default:
4322 return -EINVAL;
4323 }
4324 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4325 Clock_and_FOUT_Register);
4326 return 3;
4327 }
4328
4329 static void ni_get_freq_out_clock(struct comedi_device *dev,
4330 unsigned int *clock_source,
4331 unsigned int *clock_period_ns)
4332 {
4333 struct ni_private *devpriv = dev->private;
4334
4335 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4336 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4337 *clock_period_ns = TIMEBASE_2_NS;
4338 } else {
4339 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4340 *clock_period_ns = TIMEBASE_1_NS * 2;
4341 }
4342 }
4343
4344 static int ni_freq_out_insn_config(struct comedi_device *dev,
4345 struct comedi_subdevice *s,
4346 struct comedi_insn *insn, unsigned int *data)
4347 {
4348 switch (data[0]) {
4349 case INSN_CONFIG_SET_CLOCK_SRC:
4350 return ni_set_freq_out_clock(dev, data[1]);
4351 break;
4352 case INSN_CONFIG_GET_CLOCK_SRC:
4353 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4354 return 3;
4355 default:
4356 break;
4357 }
4358 return -EINVAL;
4359 }
4360
4361 static int ni_alloc_private(struct comedi_device *dev)
4362 {
4363 struct ni_private *devpriv;
4364
4365 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4366 if (!devpriv)
4367 return -ENOMEM;
4368 dev->private = devpriv;
4369
4370 spin_lock_init(&devpriv->window_lock);
4371 spin_lock_init(&devpriv->soft_reg_copy_lock);
4372 spin_lock_init(&devpriv->mite_channel_lock);
4373
4374 return 0;
4375 };
4376
4377 static int ni_E_init(struct comedi_device *dev)
4378 {
4379 const struct ni_board_struct *board = comedi_board(dev);
4380 struct ni_private *devpriv = dev->private;
4381 struct comedi_subdevice *s;
4382 unsigned j;
4383 enum ni_gpct_variant counter_variant;
4384 int ret;
4385
4386 if (board->n_aochan > MAX_N_AO_CHAN) {
4387 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
4388 return -EINVAL;
4389 }
4390
4391 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4392 if (ret)
4393 return ret;
4394
4395 /* analog input subdevice */
4396
4397 s = &dev->subdevices[NI_AI_SUBDEV];
4398 dev->read_subdev = s;
4399 if (board->n_adchan) {
4400 s->type = COMEDI_SUBD_AI;
4401 s->subdev_flags =
4402 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4403 if (board->reg_type != ni_reg_611x)
4404 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4405 if (board->adbits > 16)
4406 s->subdev_flags |= SDF_LSAMPL;
4407 if (board->reg_type & ni_reg_m_series_mask)
4408 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4409 s->n_chan = board->n_adchan;
4410 s->len_chanlist = 512;
4411 s->maxdata = (1 << board->adbits) - 1;
4412 s->range_table = ni_range_lkup[board->gainlkup];
4413 s->insn_read = &ni_ai_insn_read;
4414 s->insn_config = &ni_ai_insn_config;
4415 s->do_cmdtest = &ni_ai_cmdtest;
4416 s->do_cmd = &ni_ai_cmd;
4417 s->cancel = &ni_ai_reset;
4418 s->poll = &ni_ai_poll;
4419 s->munge = &ni_ai_munge;
4420 #ifdef PCIDMA
4421 s->async_dma_dir = DMA_FROM_DEVICE;
4422 #endif
4423 } else {
4424 s->type = COMEDI_SUBD_UNUSED;
4425 }
4426
4427 /* analog output subdevice */
4428
4429 s = &dev->subdevices[NI_AO_SUBDEV];
4430 if (board->n_aochan) {
4431 s->type = COMEDI_SUBD_AO;
4432 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4433 if (board->reg_type & ni_reg_m_series_mask)
4434 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4435 s->n_chan = board->n_aochan;
4436 s->maxdata = (1 << board->aobits) - 1;
4437 s->range_table = board->ao_range_table;
4438 s->insn_read = &ni_ao_insn_read;
4439 if (board->reg_type & ni_reg_6xxx_mask) {
4440 s->insn_write = &ni_ao_insn_write_671x;
4441 } else {
4442 s->insn_write = &ni_ao_insn_write;
4443 }
4444 s->insn_config = &ni_ao_insn_config;
4445 #ifdef PCIDMA
4446 if (board->n_aochan) {
4447 s->async_dma_dir = DMA_TO_DEVICE;
4448 #else
4449 if (board->ao_fifo_depth) {
4450 #endif
4451 dev->write_subdev = s;
4452 s->subdev_flags |= SDF_CMD_WRITE;
4453 s->do_cmd = &ni_ao_cmd;
4454 s->do_cmdtest = &ni_ao_cmdtest;
4455 s->len_chanlist = board->n_aochan;
4456 if ((board->reg_type & ni_reg_m_series_mask) == 0)
4457 s->munge = ni_ao_munge;
4458 }
4459 s->cancel = &ni_ao_reset;
4460 } else {
4461 s->type = COMEDI_SUBD_UNUSED;
4462 }
4463 if ((board->reg_type & ni_reg_67xx_mask))
4464 init_ao_67xx(dev, s);
4465
4466 /* digital i/o subdevice */
4467
4468 s = &dev->subdevices[NI_DIO_SUBDEV];
4469 s->type = COMEDI_SUBD_DIO;
4470 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4471 s->maxdata = 1;
4472 s->io_bits = 0; /* all bits input */
4473 s->range_table = &range_digital;
4474 s->n_chan = board->num_p0_dio_channels;
4475 if (board->reg_type & ni_reg_m_series_mask) {
4476 s->subdev_flags |=
4477 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4478 s->insn_bits = &ni_m_series_dio_insn_bits;
4479 s->insn_config = &ni_m_series_dio_insn_config;
4480 s->do_cmd = &ni_cdio_cmd;
4481 s->do_cmdtest = &ni_cdio_cmdtest;
4482 s->cancel = &ni_cdio_cancel;
4483 s->async_dma_dir = DMA_BIDIRECTIONAL;
4484 s->len_chanlist = s->n_chan;
4485
4486 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4487 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4488 } else {
4489 s->insn_bits = &ni_dio_insn_bits;
4490 s->insn_config = &ni_dio_insn_config;
4491 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4492 ni_writew(devpriv->dio_control, DIO_Control_Register);
4493 }
4494
4495 /* 8255 device */
4496 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4497 if (board->has_8255) {
4498 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4499 } else {
4500 s->type = COMEDI_SUBD_UNUSED;
4501 }
4502
4503 /* formerly general purpose counter/timer device, but no longer used */
4504 s = &dev->subdevices[NI_UNUSED_SUBDEV];
4505 s->type = COMEDI_SUBD_UNUSED;
4506
4507 /* calibration subdevice -- ai and ao */
4508 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4509 s->type = COMEDI_SUBD_CALIB;
4510 if (board->reg_type & ni_reg_m_series_mask) {
4511 /* internal PWM analog output used for AI nonlinearity calibration */
4512 s->subdev_flags = SDF_INTERNAL;
4513 s->insn_config = &ni_m_series_pwm_config;
4514 s->n_chan = 1;
4515 s->maxdata = 0;
4516 ni_writel(0x0, M_Offset_Cal_PWM);
4517 } else if (board->reg_type == ni_reg_6143) {
4518 /* internal PWM analog output used for AI nonlinearity calibration */
4519 s->subdev_flags = SDF_INTERNAL;
4520 s->insn_config = &ni_6143_pwm_config;
4521 s->n_chan = 1;
4522 s->maxdata = 0;
4523 } else {
4524 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4525 s->insn_read = &ni_calib_insn_read;
4526 s->insn_write = &ni_calib_insn_write;
4527 caldac_setup(dev, s);
4528 }
4529
4530 /* EEPROM */
4531 s = &dev->subdevices[NI_EEPROM_SUBDEV];
4532 s->type = COMEDI_SUBD_MEMORY;
4533 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4534 s->maxdata = 0xff;
4535 if (board->reg_type & ni_reg_m_series_mask) {
4536 s->n_chan = M_SERIES_EEPROM_SIZE;
4537 s->insn_read = &ni_m_series_eeprom_insn_read;
4538 } else {
4539 s->n_chan = 512;
4540 s->insn_read = &ni_eeprom_insn_read;
4541 }
4542
4543 /* PFI */
4544 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4545 s->type = COMEDI_SUBD_DIO;
4546 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4547 if (board->reg_type & ni_reg_m_series_mask) {
4548 unsigned i;
4549 s->n_chan = 16;
4550 ni_writew(s->state, M_Offset_PFI_DO);
4551 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4552 ni_writew(devpriv->pfi_output_select_reg[i],
4553 M_Offset_PFI_Output_Select(i + 1));
4554 }
4555 } else {
4556 s->n_chan = 10;
4557 }
4558 s->maxdata = 1;
4559 if (board->reg_type & ni_reg_m_series_mask) {
4560 s->insn_bits = &ni_pfi_insn_bits;
4561 }
4562 s->insn_config = &ni_pfi_insn_config;
4563 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4564
4565 /* cs5529 calibration adc */
4566 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4567 if (board->reg_type & ni_reg_67xx_mask) {
4568 s->type = COMEDI_SUBD_AI;
4569 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4570 /* one channel for each analog output channel */
4571 s->n_chan = board->n_aochan;
4572 s->maxdata = (1 << 16) - 1;
4573 s->range_table = &range_unknown; /* XXX */
4574 s->insn_read = cs5529_ai_insn_read;
4575 s->insn_config = NULL;
4576 init_cs5529(dev);
4577 } else {
4578 s->type = COMEDI_SUBD_UNUSED;
4579 }
4580
4581 /* Serial */
4582 s = &dev->subdevices[NI_SERIAL_SUBDEV];
4583 s->type = COMEDI_SUBD_SERIAL;
4584 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4585 s->n_chan = 1;
4586 s->maxdata = 0xff;
4587 s->insn_config = ni_serial_insn_config;
4588 devpriv->serial_interval_ns = 0;
4589 devpriv->serial_hw_mode = 0;
4590
4591 /* RTSI */
4592 s = &dev->subdevices[NI_RTSI_SUBDEV];
4593 s->type = COMEDI_SUBD_DIO;
4594 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4595 s->n_chan = 8;
4596 s->maxdata = 1;
4597 s->insn_bits = ni_rtsi_insn_bits;
4598 s->insn_config = ni_rtsi_insn_config;
4599 ni_rtsi_init(dev);
4600
4601 if (board->reg_type & ni_reg_m_series_mask) {
4602 counter_variant = ni_gpct_variant_m_series;
4603 } else {
4604 counter_variant = ni_gpct_variant_e_series;
4605 }
4606 devpriv->counter_dev = ni_gpct_device_construct(dev,
4607 &ni_gpct_write_register,
4608 &ni_gpct_read_register,
4609 counter_variant,
4610 NUM_GPCT);
4611 /* General purpose counters */
4612 for (j = 0; j < NUM_GPCT; ++j) {
4613 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4614 s->type = COMEDI_SUBD_COUNTER;
4615 s->subdev_flags =
4616 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4617 /* | SDF_CMD_WRITE */ ;
4618 s->n_chan = 3;
4619 if (board->reg_type & ni_reg_m_series_mask)
4620 s->maxdata = 0xffffffff;
4621 else
4622 s->maxdata = 0xffffff;
4623 s->insn_read = &ni_gpct_insn_read;
4624 s->insn_write = &ni_gpct_insn_write;
4625 s->insn_config = &ni_gpct_insn_config;
4626 s->do_cmd = &ni_gpct_cmd;
4627 s->len_chanlist = 1;
4628 s->do_cmdtest = &ni_gpct_cmdtest;
4629 s->cancel = &ni_gpct_cancel;
4630 s->async_dma_dir = DMA_BIDIRECTIONAL;
4631 s->private = &devpriv->counter_dev->counters[j];
4632
4633 devpriv->counter_dev->counters[j].chip_index = 0;
4634 devpriv->counter_dev->counters[j].counter_index = j;
4635 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4636 }
4637
4638 /* Frequency output */
4639 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4640 s->type = COMEDI_SUBD_COUNTER;
4641 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4642 s->n_chan = 1;
4643 s->maxdata = 0xf;
4644 s->insn_read = &ni_freq_out_insn_read;
4645 s->insn_write = &ni_freq_out_insn_write;
4646 s->insn_config = &ni_freq_out_insn_config;
4647
4648 /* ai configuration */
4649 s = &dev->subdevices[NI_AI_SUBDEV];
4650 ni_ai_reset(dev, s);
4651 if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
4652 /* BEAM is this needed for PCI-6143 ?? */
4653 devpriv->clock_and_fout =
4654 Slow_Internal_Time_Divide_By_2 |
4655 Slow_Internal_Timebase |
4656 Clock_To_Board_Divide_By_2 |
4657 Clock_To_Board |
4658 AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4659 } else {
4660 devpriv->clock_and_fout =
4661 Slow_Internal_Time_Divide_By_2 |
4662 Slow_Internal_Timebase |
4663 Clock_To_Board_Divide_By_2 | Clock_To_Board;
4664 }
4665 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4666 Clock_and_FOUT_Register);
4667
4668 /* analog output configuration */
4669 s = &dev->subdevices[NI_AO_SUBDEV];
4670 ni_ao_reset(dev, s);
4671
4672 if (dev->irq) {
4673 devpriv->stc_writew(dev,
4674 (IRQ_POLARITY ? Interrupt_Output_Polarity :
4675 0) | (Interrupt_Output_On_3_Pins & 0) |
4676 Interrupt_A_Enable | Interrupt_B_Enable |
4677 Interrupt_A_Output_Select(interrupt_pin
4678 (dev->irq)) |
4679 Interrupt_B_Output_Select(interrupt_pin
4680 (dev->irq)),
4681 Interrupt_Control_Register);
4682 }
4683
4684 /* DMA setup */
4685 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4686 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4687
4688 if (board->reg_type & ni_reg_6xxx_mask) {
4689 ni_writeb(0, Magic_611x);
4690 } else if (board->reg_type & ni_reg_m_series_mask) {
4691 int channel;
4692 for (channel = 0; channel < board->n_aochan; ++channel) {
4693 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4694 ni_writeb(0x0,
4695 M_Offset_AO_Reference_Attenuation(channel));
4696 }
4697 ni_writeb(0x0, M_Offset_AO_Calibration);
4698 }
4699
4700 printk("\n");
4701 return 0;
4702 }
4703
4704 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4705 {
4706 struct comedi_device *dev = (struct comedi_device *)arg;
4707 struct ni_private *devpriv __maybe_unused = dev->private;
4708
4709 if (dir) {
4710 ni_writeb(data, Port_A + 2 * port);
4711 return 0;
4712 } else {
4713 return ni_readb(Port_A + 2 * port);
4714 }
4715 }
4716
4717 /*
4718 presents the EEPROM as a subdevice
4719 */
4720
4721 static int ni_eeprom_insn_read(struct comedi_device *dev,
4722 struct comedi_subdevice *s,
4723 struct comedi_insn *insn, unsigned int *data)
4724 {
4725 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4726
4727 return 1;
4728 }
4729
4730 /*
4731 reads bytes out of eeprom
4732 */
4733
4734 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4735 {
4736 struct ni_private *devpriv __maybe_unused = dev->private;
4737 int bit;
4738 int bitstring;
4739
4740 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4741 ni_writeb(0x04, Serial_Command);
4742 for (bit = 0x8000; bit; bit >>= 1) {
4743 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4744 Serial_Command);
4745 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4746 Serial_Command);
4747 }
4748 bitstring = 0;
4749 for (bit = 0x80; bit; bit >>= 1) {
4750 ni_writeb(0x04, Serial_Command);
4751 ni_writeb(0x05, Serial_Command);
4752 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4753 }
4754 ni_writeb(0x00, Serial_Command);
4755
4756 return bitstring;
4757 }
4758
4759 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4760 struct comedi_subdevice *s,
4761 struct comedi_insn *insn,
4762 unsigned int *data)
4763 {
4764 struct ni_private *devpriv = dev->private;
4765
4766 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4767
4768 return 1;
4769 }
4770
4771 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4772 {
4773 struct ni_private *devpriv = dev->private;
4774
4775 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4776 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4777 return 3;
4778 }
4779
4780 static int ni_m_series_pwm_config(struct comedi_device *dev,
4781 struct comedi_subdevice *s,
4782 struct comedi_insn *insn, unsigned int *data)
4783 {
4784 struct ni_private *devpriv = dev->private;
4785 unsigned up_count, down_count;
4786
4787 switch (data[0]) {
4788 case INSN_CONFIG_PWM_OUTPUT:
4789 switch (data[1]) {
4790 case TRIG_ROUND_NEAREST:
4791 up_count =
4792 (data[2] +
4793 devpriv->clock_ns / 2) / devpriv->clock_ns;
4794 break;
4795 case TRIG_ROUND_DOWN:
4796 up_count = data[2] / devpriv->clock_ns;
4797 break;
4798 case TRIG_ROUND_UP:
4799 up_count =
4800 (data[2] + devpriv->clock_ns -
4801 1) / devpriv->clock_ns;
4802 break;
4803 default:
4804 return -EINVAL;
4805 break;
4806 }
4807 switch (data[3]) {
4808 case TRIG_ROUND_NEAREST:
4809 down_count =
4810 (data[4] +
4811 devpriv->clock_ns / 2) / devpriv->clock_ns;
4812 break;
4813 case TRIG_ROUND_DOWN:
4814 down_count = data[4] / devpriv->clock_ns;
4815 break;
4816 case TRIG_ROUND_UP:
4817 down_count =
4818 (data[4] + devpriv->clock_ns -
4819 1) / devpriv->clock_ns;
4820 break;
4821 default:
4822 return -EINVAL;
4823 break;
4824 }
4825 if (up_count * devpriv->clock_ns != data[2] ||
4826 down_count * devpriv->clock_ns != data[4]) {
4827 data[2] = up_count * devpriv->clock_ns;
4828 data[4] = down_count * devpriv->clock_ns;
4829 return -EAGAIN;
4830 }
4831 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4832 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4833 M_Offset_Cal_PWM);
4834 devpriv->pwm_up_count = up_count;
4835 devpriv->pwm_down_count = down_count;
4836 return 5;
4837 break;
4838 case INSN_CONFIG_GET_PWM_OUTPUT:
4839 return ni_get_pwm_config(dev, data);
4840 break;
4841 default:
4842 return -EINVAL;
4843 break;
4844 }
4845 return 0;
4846 }
4847
4848 static int ni_6143_pwm_config(struct comedi_device *dev,
4849 struct comedi_subdevice *s,
4850 struct comedi_insn *insn, unsigned int *data)
4851 {
4852 struct ni_private *devpriv = dev->private;
4853 unsigned up_count, down_count;
4854
4855 switch (data[0]) {
4856 case INSN_CONFIG_PWM_OUTPUT:
4857 switch (data[1]) {
4858 case TRIG_ROUND_NEAREST:
4859 up_count =
4860 (data[2] +
4861 devpriv->clock_ns / 2) / devpriv->clock_ns;
4862 break;
4863 case TRIG_ROUND_DOWN:
4864 up_count = data[2] / devpriv->clock_ns;
4865 break;
4866 case TRIG_ROUND_UP:
4867 up_count =
4868 (data[2] + devpriv->clock_ns -
4869 1) / devpriv->clock_ns;
4870 break;
4871 default:
4872 return -EINVAL;
4873 break;
4874 }
4875 switch (data[3]) {
4876 case TRIG_ROUND_NEAREST:
4877 down_count =
4878 (data[4] +
4879 devpriv->clock_ns / 2) / devpriv->clock_ns;
4880 break;
4881 case TRIG_ROUND_DOWN:
4882 down_count = data[4] / devpriv->clock_ns;
4883 break;
4884 case TRIG_ROUND_UP:
4885 down_count =
4886 (data[4] + devpriv->clock_ns -
4887 1) / devpriv->clock_ns;
4888 break;
4889 default:
4890 return -EINVAL;
4891 break;
4892 }
4893 if (up_count * devpriv->clock_ns != data[2] ||
4894 down_count * devpriv->clock_ns != data[4]) {
4895 data[2] = up_count * devpriv->clock_ns;
4896 data[4] = down_count * devpriv->clock_ns;
4897 return -EAGAIN;
4898 }
4899 ni_writel(up_count, Calibration_HighTime_6143);
4900 devpriv->pwm_up_count = up_count;
4901 ni_writel(down_count, Calibration_LowTime_6143);
4902 devpriv->pwm_down_count = down_count;
4903 return 5;
4904 break;
4905 case INSN_CONFIG_GET_PWM_OUTPUT:
4906 return ni_get_pwm_config(dev, data);
4907 default:
4908 return -EINVAL;
4909 break;
4910 }
4911 return 0;
4912 }
4913
4914 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4915 /*
4916 calibration subdevice
4917 */
4918 static int ni_calib_insn_write(struct comedi_device *dev,
4919 struct comedi_subdevice *s,
4920 struct comedi_insn *insn, unsigned int *data)
4921 {
4922 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4923
4924 return 1;
4925 }
4926
4927 static int ni_calib_insn_read(struct comedi_device *dev,
4928 struct comedi_subdevice *s,
4929 struct comedi_insn *insn, unsigned int *data)
4930 {
4931 struct ni_private *devpriv = dev->private;
4932
4933 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4934
4935 return 1;
4936 }
4937
4938 static int pack_mb88341(int addr, int val, int *bitstring);
4939 static int pack_dac8800(int addr, int val, int *bitstring);
4940 static int pack_dac8043(int addr, int val, int *bitstring);
4941 static int pack_ad8522(int addr, int val, int *bitstring);
4942 static int pack_ad8804(int addr, int val, int *bitstring);
4943 static int pack_ad8842(int addr, int val, int *bitstring);
4944
4945 struct caldac_struct {
4946 int n_chans;
4947 int n_bits;
4948 int (*packbits) (int, int, int *);
4949 };
4950
4951 static struct caldac_struct caldacs[] = {
4952 [mb88341] = {12, 8, pack_mb88341},
4953 [dac8800] = {8, 8, pack_dac8800},
4954 [dac8043] = {1, 12, pack_dac8043},
4955 [ad8522] = {2, 12, pack_ad8522},
4956 [ad8804] = {12, 8, pack_ad8804},
4957 [ad8842] = {8, 8, pack_ad8842},
4958 [ad8804_debug] = {16, 8, pack_ad8804},
4959 };
4960
4961 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4962 {
4963 const struct ni_board_struct *board = comedi_board(dev);
4964 struct ni_private *devpriv = dev->private;
4965 int i, j;
4966 int n_dacs;
4967 int n_chans = 0;
4968 int n_bits;
4969 int diffbits = 0;
4970 int type;
4971 int chan;
4972
4973 type = board->caldac[0];
4974 if (type == caldac_none)
4975 return;
4976 n_bits = caldacs[type].n_bits;
4977 for (i = 0; i < 3; i++) {
4978 type = board->caldac[i];
4979 if (type == caldac_none)
4980 break;
4981 if (caldacs[type].n_bits != n_bits)
4982 diffbits = 1;
4983 n_chans += caldacs[type].n_chans;
4984 }
4985 n_dacs = i;
4986 s->n_chan = n_chans;
4987
4988 if (diffbits) {
4989 unsigned int *maxdata_list;
4990
4991 if (n_chans > MAX_N_CALDACS) {
4992 printk("BUG! MAX_N_CALDACS too small\n");
4993 }
4994 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4995 chan = 0;
4996 for (i = 0; i < n_dacs; i++) {
4997 type = board->caldac[i];
4998 for (j = 0; j < caldacs[type].n_chans; j++) {
4999 maxdata_list[chan] =
5000 (1 << caldacs[type].n_bits) - 1;
5001 chan++;
5002 }
5003 }
5004
5005 for (chan = 0; chan < s->n_chan; chan++)
5006 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
5007 } else {
5008 type = board->caldac[0];
5009 s->maxdata = (1 << caldacs[type].n_bits) - 1;
5010
5011 for (chan = 0; chan < s->n_chan; chan++)
5012 ni_write_caldac(dev, i, s->maxdata / 2);
5013 }
5014 }
5015
5016 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
5017 {
5018 const struct ni_board_struct *board = comedi_board(dev);
5019 struct ni_private *devpriv = dev->private;
5020 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
5021 int i;
5022 int type;
5023
5024 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5025 if (devpriv->caldacs[addr] == val)
5026 return;
5027 devpriv->caldacs[addr] = val;
5028
5029 for (i = 0; i < 3; i++) {
5030 type = board->caldac[i];
5031 if (type == caldac_none)
5032 break;
5033 if (addr < caldacs[type].n_chans) {
5034 bits = caldacs[type].packbits(addr, val, &bitstring);
5035 loadbit = SerDacLd(i);
5036 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5037 break;
5038 }
5039 addr -= caldacs[type].n_chans;
5040 }
5041
5042 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5043 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5044 udelay(1);
5045 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5046 udelay(1);
5047 }
5048 ni_writeb(loadbit, Serial_Command);
5049 udelay(1);
5050 ni_writeb(0, Serial_Command);
5051 }
5052
5053 static int pack_mb88341(int addr, int val, int *bitstring)
5054 {
5055 /*
5056 Fujitsu MB 88341
5057 Note that address bits are reversed. Thanks to
5058 Ingo Keen for noticing this.
5059
5060 Note also that the 88341 expects address values from
5061 1-12, whereas we use channel numbers 0-11. The NI
5062 docs use 1-12, also, so be careful here.
5063 */
5064 addr++;
5065 *bitstring = ((addr & 0x1) << 11) |
5066 ((addr & 0x2) << 9) |
5067 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5068 return 12;
5069 }
5070
5071 static int pack_dac8800(int addr, int val, int *bitstring)
5072 {
5073 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5074 return 11;
5075 }
5076
5077 static int pack_dac8043(int addr, int val, int *bitstring)
5078 {
5079 *bitstring = val & 0xfff;
5080 return 12;
5081 }
5082
5083 static int pack_ad8522(int addr, int val, int *bitstring)
5084 {
5085 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5086 return 16;
5087 }
5088
5089 static int pack_ad8804(int addr, int val, int *bitstring)
5090 {
5091 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5092 return 12;
5093 }
5094
5095 static int pack_ad8842(int addr, int val, int *bitstring)
5096 {
5097 *bitstring = ((addr + 1) << 8) | (val & 0xff);
5098 return 12;
5099 }
5100
5101 #if 0
5102 /*
5103 * Read the GPCTs current value.
5104 */
5105 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5106 {
5107 unsigned int hi1, hi2, lo;
5108
5109 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5110 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5111 G_Command_Register(chan));
5112
5113 devpriv->gpct_command[chan] |= G_Save_Trace;
5114 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5115 G_Command_Register(chan));
5116
5117 /* This procedure is used because the two registers cannot
5118 * be read atomically. */
5119 do {
5120 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5121 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5122 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5123 } while (hi1 != hi2);
5124
5125 return (hi1 << 16) | lo;
5126 }
5127
5128 static void GPCT_Reset(struct comedi_device *dev, int chan)
5129 {
5130 int temp_ack_reg = 0;
5131
5132 /* printk("GPCT_Reset..."); */
5133 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5134
5135 switch (chan) {
5136 case 0:
5137 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5138 ni_set_bits(dev, Interrupt_A_Enable_Register,
5139 G0_TC_Interrupt_Enable, 0);
5140 ni_set_bits(dev, Interrupt_A_Enable_Register,
5141 G0_Gate_Interrupt_Enable, 0);
5142 temp_ack_reg |= G0_Gate_Error_Confirm;
5143 temp_ack_reg |= G0_TC_Error_Confirm;
5144 temp_ack_reg |= G0_TC_Interrupt_Ack;
5145 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5146 devpriv->stc_writew(dev, temp_ack_reg,
5147 Interrupt_A_Ack_Register);
5148
5149 /* problem...this interferes with the other ctr... */
5150 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5151 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5152 Analog_Trigger_Etc_Register);
5153 break;
5154 case 1:
5155 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5156 ni_set_bits(dev, Interrupt_B_Enable_Register,
5157 G1_TC_Interrupt_Enable, 0);
5158 ni_set_bits(dev, Interrupt_B_Enable_Register,
5159 G0_Gate_Interrupt_Enable, 0);
5160 temp_ack_reg |= G1_Gate_Error_Confirm;
5161 temp_ack_reg |= G1_TC_Error_Confirm;
5162 temp_ack_reg |= G1_TC_Interrupt_Ack;
5163 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5164 devpriv->stc_writew(dev, temp_ack_reg,
5165 Interrupt_B_Ack_Register);
5166
5167 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5168 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5169 Analog_Trigger_Etc_Register);
5170 break;
5171 }
5172
5173 devpriv->gpct_mode[chan] = 0;
5174 devpriv->gpct_input_select[chan] = 0;
5175 devpriv->gpct_command[chan] = 0;
5176
5177 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5178
5179 devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5180 G_Mode_Register(chan));
5181 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5182 G_Input_Select_Register(chan));
5183 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5184
5185 /* printk("exit GPCT_Reset\n"); */
5186 }
5187
5188 #endif
5189
5190 static int ni_gpct_insn_config(struct comedi_device *dev,
5191 struct comedi_subdevice *s,
5192 struct comedi_insn *insn, unsigned int *data)
5193 {
5194 struct ni_gpct *counter = s->private;
5195 return ni_tio_insn_config(counter, insn, data);
5196 }
5197
5198 static int ni_gpct_insn_read(struct comedi_device *dev,
5199 struct comedi_subdevice *s,
5200 struct comedi_insn *insn, unsigned int *data)
5201 {
5202 struct ni_gpct *counter = s->private;
5203 return ni_tio_rinsn(counter, insn, data);
5204 }
5205
5206 static int ni_gpct_insn_write(struct comedi_device *dev,
5207 struct comedi_subdevice *s,
5208 struct comedi_insn *insn, unsigned int *data)
5209 {
5210 struct ni_gpct *counter = s->private;
5211 return ni_tio_winsn(counter, insn, data);
5212 }
5213
5214 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5215 {
5216 int retval;
5217 #ifdef PCIDMA
5218 struct ni_gpct *counter = s->private;
5219 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5220
5221 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5222 COMEDI_INPUT);
5223 if (retval) {
5224 comedi_error(dev,
5225 "no dma channel available for use by counter");
5226 return retval;
5227 }
5228 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5229 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5230 retval = ni_tio_cmd(counter, s->async);
5231 #else
5232 retval = -ENOTSUPP;
5233 #endif
5234 return retval;
5235 }
5236
5237 static int ni_gpct_cmdtest(struct comedi_device *dev,
5238 struct comedi_subdevice *s, struct comedi_cmd *cmd)
5239 {
5240 #ifdef PCIDMA
5241 struct ni_gpct *counter = s->private;
5242
5243 return ni_tio_cmdtest(counter, cmd);
5244 #else
5245 return -ENOTSUPP;
5246 #endif
5247 }
5248
5249 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5250 {
5251 #ifdef PCIDMA
5252 struct ni_gpct *counter = s->private;
5253 int retval;
5254
5255 retval = ni_tio_cancel(counter);
5256 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5257 ni_release_gpct_mite_channel(dev, counter->counter_index);
5258 return retval;
5259 #else
5260 return 0;
5261 #endif
5262 }
5263
5264 /*
5265 *
5266 * Programmable Function Inputs
5267 *
5268 */
5269
5270 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5271 unsigned source)
5272 {
5273 struct ni_private *devpriv = dev->private;
5274 unsigned pfi_reg_index;
5275 unsigned array_offset;
5276
5277 if ((source & 0x1f) != source)
5278 return -EINVAL;
5279 pfi_reg_index = 1 + chan / 3;
5280 array_offset = pfi_reg_index - 1;
5281 devpriv->pfi_output_select_reg[array_offset] &=
5282 ~MSeries_PFI_Output_Select_Mask(chan);
5283 devpriv->pfi_output_select_reg[array_offset] |=
5284 MSeries_PFI_Output_Select_Bits(chan, source);
5285 ni_writew(devpriv->pfi_output_select_reg[array_offset],
5286 M_Offset_PFI_Output_Select(pfi_reg_index));
5287 return 2;
5288 }
5289
5290 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5291 unsigned source)
5292 {
5293 /* pre-m-series boards have fixed signals on pfi pins */
5294 if (source != ni_old_get_pfi_routing(dev, chan))
5295 return -EINVAL;
5296 return 2;
5297 }
5298
5299 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5300 unsigned source)
5301 {
5302 const struct ni_board_struct *board = comedi_board(dev);
5303
5304 if (board->reg_type & ni_reg_m_series_mask)
5305 return ni_m_series_set_pfi_routing(dev, chan, source);
5306 else
5307 return ni_old_set_pfi_routing(dev, chan, source);
5308 }
5309
5310 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5311 unsigned chan)
5312 {
5313 struct ni_private *devpriv = dev->private;
5314 const unsigned array_offset = chan / 3;
5315
5316 return MSeries_PFI_Output_Select_Source(chan,
5317 devpriv->
5318 pfi_output_select_reg
5319 [array_offset]);
5320 }
5321
5322 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5323 {
5324 /* pre-m-series boards have fixed signals on pfi pins */
5325 switch (chan) {
5326 case 0:
5327 return NI_PFI_OUTPUT_AI_START1;
5328 break;
5329 case 1:
5330 return NI_PFI_OUTPUT_AI_START2;
5331 break;
5332 case 2:
5333 return NI_PFI_OUTPUT_AI_CONVERT;
5334 break;
5335 case 3:
5336 return NI_PFI_OUTPUT_G_SRC1;
5337 break;
5338 case 4:
5339 return NI_PFI_OUTPUT_G_GATE1;
5340 break;
5341 case 5:
5342 return NI_PFI_OUTPUT_AO_UPDATE_N;
5343 break;
5344 case 6:
5345 return NI_PFI_OUTPUT_AO_START1;
5346 break;
5347 case 7:
5348 return NI_PFI_OUTPUT_AI_START_PULSE;
5349 break;
5350 case 8:
5351 return NI_PFI_OUTPUT_G_SRC0;
5352 break;
5353 case 9:
5354 return NI_PFI_OUTPUT_G_GATE0;
5355 break;
5356 default:
5357 printk("%s: bug, unhandled case in switch.\n", __func__);
5358 break;
5359 }
5360 return 0;
5361 }
5362
5363 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5364 {
5365 const struct ni_board_struct *board = comedi_board(dev);
5366
5367 if (board->reg_type & ni_reg_m_series_mask)
5368 return ni_m_series_get_pfi_routing(dev, chan);
5369 else
5370 return ni_old_get_pfi_routing(dev, chan);
5371 }
5372
5373 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5374 enum ni_pfi_filter_select filter)
5375 {
5376 const struct ni_board_struct *board = comedi_board(dev);
5377 struct ni_private *devpriv __maybe_unused = dev->private;
5378 unsigned bits;
5379
5380 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5381 return -ENOTSUPP;
5382 }
5383 bits = ni_readl(M_Offset_PFI_Filter);
5384 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5385 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5386 ni_writel(bits, M_Offset_PFI_Filter);
5387 return 0;
5388 }
5389
5390 static int ni_pfi_insn_bits(struct comedi_device *dev,
5391 struct comedi_subdevice *s,
5392 struct comedi_insn *insn, unsigned int *data)
5393 {
5394 const struct ni_board_struct *board = comedi_board(dev);
5395 struct ni_private *devpriv __maybe_unused = dev->private;
5396
5397 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5398 return -ENOTSUPP;
5399 }
5400 if (data[0]) {
5401 s->state &= ~data[0];
5402 s->state |= (data[0] & data[1]);
5403 ni_writew(s->state, M_Offset_PFI_DO);
5404 }
5405 data[1] = ni_readw(M_Offset_PFI_DI);
5406 return insn->n;
5407 }
5408
5409 static int ni_pfi_insn_config(struct comedi_device *dev,
5410 struct comedi_subdevice *s,
5411 struct comedi_insn *insn, unsigned int *data)
5412 {
5413 struct ni_private *devpriv = dev->private;
5414 unsigned int chan;
5415
5416 if (insn->n < 1)
5417 return -EINVAL;
5418
5419 chan = CR_CHAN(insn->chanspec);
5420
5421 switch (data[0]) {
5422 case COMEDI_OUTPUT:
5423 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5424 break;
5425 case COMEDI_INPUT:
5426 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5427 break;
5428 case INSN_CONFIG_DIO_QUERY:
5429 data[1] =
5430 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5431 COMEDI_OUTPUT : COMEDI_INPUT;
5432 return 0;
5433 break;
5434 case INSN_CONFIG_SET_ROUTING:
5435 return ni_set_pfi_routing(dev, chan, data[1]);
5436 break;
5437 case INSN_CONFIG_GET_ROUTING:
5438 data[1] = ni_get_pfi_routing(dev, chan);
5439 break;
5440 case INSN_CONFIG_FILTER:
5441 return ni_config_filter(dev, chan, data[1]);
5442 break;
5443 default:
5444 return -EINVAL;
5445 }
5446 return 0;
5447 }
5448
5449 /*
5450 *
5451 * NI RTSI Bus Functions
5452 *
5453 */
5454 static void ni_rtsi_init(struct comedi_device *dev)
5455 {
5456 const struct ni_board_struct *board = comedi_board(dev);
5457 struct ni_private *devpriv = dev->private;
5458
5459 /* Initialises the RTSI bus signal switch to a default state */
5460
5461 /* Set clock mode to internal */
5462 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5463 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5464 printk("ni_set_master_clock failed, bug?");
5465 }
5466 /* default internal lines routing to RTSI bus lines */
5467 devpriv->rtsi_trig_a_output_reg =
5468 RTSI_Trig_Output_Bits(0,
5469 NI_RTSI_OUTPUT_ADR_START1) |
5470 RTSI_Trig_Output_Bits(1,
5471 NI_RTSI_OUTPUT_ADR_START2) |
5472 RTSI_Trig_Output_Bits(2,
5473 NI_RTSI_OUTPUT_SCLKG) |
5474 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5475 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5476 RTSI_Trig_A_Output_Register);
5477 devpriv->rtsi_trig_b_output_reg =
5478 RTSI_Trig_Output_Bits(4,
5479 NI_RTSI_OUTPUT_DA_START1) |
5480 RTSI_Trig_Output_Bits(5,
5481 NI_RTSI_OUTPUT_G_SRC0) |
5482 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5483 if (board->reg_type & ni_reg_m_series_mask)
5484 devpriv->rtsi_trig_b_output_reg |=
5485 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5486 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5487 RTSI_Trig_B_Output_Register);
5488
5489 /*
5490 * Sets the source and direction of the 4 on board lines
5491 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5492 */
5493 }
5494
5495 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5496 struct comedi_subdevice *s,
5497 struct comedi_insn *insn, unsigned int *data)
5498 {
5499 data[1] = 0;
5500
5501 return insn->n;
5502 }
5503
5504 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5505 * given an arbitrary frequency input clock */
5506 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5507 unsigned *freq_divider,
5508 unsigned *freq_multiplier,
5509 unsigned *actual_period_ns)
5510 {
5511 unsigned div;
5512 unsigned best_div = 1;
5513 static const unsigned max_div = 0x10;
5514 unsigned mult;
5515 unsigned best_mult = 1;
5516 static const unsigned max_mult = 0x100;
5517 static const unsigned pico_per_nano = 1000;
5518
5519 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5520 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5521 * 20 MHz for most timing clocks */
5522 static const unsigned target_picosec = 12500;
5523 static const unsigned fudge_factor_80_to_20Mhz = 4;
5524 int best_period_picosec = 0;
5525 for (div = 1; div <= max_div; ++div) {
5526 for (mult = 1; mult <= max_mult; ++mult) {
5527 unsigned new_period_ps =
5528 (reference_picosec * div) / mult;
5529 if (abs(new_period_ps - target_picosec) <
5530 abs(best_period_picosec - target_picosec)) {
5531 best_period_picosec = new_period_ps;
5532 best_div = div;
5533 best_mult = mult;
5534 }
5535 }
5536 }
5537 if (best_period_picosec == 0) {
5538 printk("%s: bug, failed to find pll parameters\n", __func__);
5539 return -EIO;
5540 }
5541 *freq_divider = best_div;
5542 *freq_multiplier = best_mult;
5543 *actual_period_ns =
5544 (best_period_picosec * fudge_factor_80_to_20Mhz +
5545 (pico_per_nano / 2)) / pico_per_nano;
5546 return 0;
5547 }
5548
5549 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5550 {
5551 const struct ni_board_struct *board = comedi_board(dev);
5552
5553 if (board->reg_type & ni_reg_m_series_mask)
5554 return 8;
5555 else
5556 return 7;
5557 }
5558
5559 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5560 unsigned source, unsigned period_ns)
5561 {
5562 struct ni_private *devpriv = dev->private;
5563 static const unsigned min_period_ns = 50;
5564 static const unsigned max_period_ns = 1000;
5565 static const unsigned timeout = 1000;
5566 unsigned pll_control_bits;
5567 unsigned freq_divider;
5568 unsigned freq_multiplier;
5569 unsigned i;
5570 int retval;
5571
5572 if (source == NI_MIO_PLL_PXI10_CLOCK)
5573 period_ns = 100;
5574 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5575 if (period_ns < min_period_ns || period_ns > max_period_ns) {
5576 printk
5577 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5578 "for the phased-lock loop.\n", __func__,
5579 min_period_ns, max_period_ns);
5580 return -EINVAL;
5581 }
5582 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5583 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5584 RTSI_Trig_Direction_Register);
5585 pll_control_bits =
5586 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5587 devpriv->clock_and_fout2 |=
5588 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5589 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5590 switch (source) {
5591 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5592 devpriv->clock_and_fout2 |=
5593 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5594 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5595 &freq_multiplier,
5596 &devpriv->clock_ns);
5597 if (retval < 0)
5598 return retval;
5599 break;
5600 case NI_MIO_PLL_PXI10_CLOCK:
5601 /* pxi clock is 10MHz */
5602 devpriv->clock_and_fout2 |=
5603 MSeries_PLL_In_Source_Select_PXI_Clock10;
5604 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5605 &freq_multiplier,
5606 &devpriv->clock_ns);
5607 if (retval < 0)
5608 return retval;
5609 break;
5610 default:
5611 {
5612 unsigned rtsi_channel;
5613 static const unsigned max_rtsi_channel = 7;
5614 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5615 ++rtsi_channel) {
5616 if (source ==
5617 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5618 devpriv->clock_and_fout2 |=
5619 MSeries_PLL_In_Source_Select_RTSI_Bits
5620 (rtsi_channel);
5621 break;
5622 }
5623 }
5624 if (rtsi_channel > max_rtsi_channel)
5625 return -EINVAL;
5626 retval = ni_mseries_get_pll_parameters(period_ns,
5627 &freq_divider,
5628 &freq_multiplier,
5629 &devpriv->
5630 clock_ns);
5631 if (retval < 0)
5632 return retval;
5633 }
5634 break;
5635 }
5636 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5637 pll_control_bits |=
5638 MSeries_PLL_Divisor_Bits(freq_divider) |
5639 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5640
5641 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5642 * freq_divider, freq_multiplier, pll_control_bits); */
5643 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5644 ni_writew(pll_control_bits, M_Offset_PLL_Control);
5645 devpriv->clock_source = source;
5646 /* it seems to typically take a few hundred microseconds for PLL to lock */
5647 for (i = 0; i < timeout; ++i) {
5648 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5649 break;
5650 }
5651 udelay(1);
5652 }
5653 if (i == timeout) {
5654 printk
5655 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5656 __func__, source, period_ns);
5657 return -ETIMEDOUT;
5658 }
5659 return 3;
5660 }
5661
5662 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5663 unsigned period_ns)
5664 {
5665 const struct ni_board_struct *board = comedi_board(dev);
5666 struct ni_private *devpriv = dev->private;
5667
5668 if (source == NI_MIO_INTERNAL_CLOCK) {
5669 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5670 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5671 RTSI_Trig_Direction_Register);
5672 devpriv->clock_ns = TIMEBASE_1_NS;
5673 if (board->reg_type & ni_reg_m_series_mask) {
5674 devpriv->clock_and_fout2 &=
5675 ~(MSeries_Timebase1_Select_Bit |
5676 MSeries_Timebase3_Select_Bit);
5677 ni_writew(devpriv->clock_and_fout2,
5678 M_Offset_Clock_and_Fout2);
5679 ni_writew(0, M_Offset_PLL_Control);
5680 }
5681 devpriv->clock_source = source;
5682 } else {
5683 if (board->reg_type & ni_reg_m_series_mask) {
5684 return ni_mseries_set_pll_master_clock(dev, source,
5685 period_ns);
5686 } else {
5687 if (source == NI_MIO_RTSI_CLOCK) {
5688 devpriv->rtsi_trig_direction_reg |=
5689 Use_RTSI_Clock_Bit;
5690 devpriv->stc_writew(dev,
5691 devpriv->
5692 rtsi_trig_direction_reg,
5693 RTSI_Trig_Direction_Register);
5694 if (period_ns == 0) {
5695 printk
5696 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5697 __func__);
5698 return -EINVAL;
5699 } else {
5700 devpriv->clock_ns = period_ns;
5701 }
5702 devpriv->clock_source = source;
5703 } else
5704 return -EINVAL;
5705 }
5706 }
5707 return 3;
5708 }
5709
5710 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5711 unsigned source)
5712 {
5713 const struct ni_board_struct *board = comedi_board(dev);
5714
5715 if (chan >= num_configurable_rtsi_channels(dev)) {
5716 if (chan == old_RTSI_clock_channel) {
5717 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5718 return 1;
5719 else {
5720 printk
5721 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5722 __func__, chan, old_RTSI_clock_channel);
5723 return 0;
5724 }
5725 }
5726 return 0;
5727 }
5728 switch (source) {
5729 case NI_RTSI_OUTPUT_ADR_START1:
5730 case NI_RTSI_OUTPUT_ADR_START2:
5731 case NI_RTSI_OUTPUT_SCLKG:
5732 case NI_RTSI_OUTPUT_DACUPDN:
5733 case NI_RTSI_OUTPUT_DA_START1:
5734 case NI_RTSI_OUTPUT_G_SRC0:
5735 case NI_RTSI_OUTPUT_G_GATE0:
5736 case NI_RTSI_OUTPUT_RGOUT0:
5737 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5738 return 1;
5739 break;
5740 case NI_RTSI_OUTPUT_RTSI_OSC:
5741 if (board->reg_type & ni_reg_m_series_mask)
5742 return 1;
5743 else
5744 return 0;
5745 break;
5746 default:
5747 return 0;
5748 break;
5749 }
5750 }
5751
5752 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5753 unsigned source)
5754 {
5755 struct ni_private *devpriv = dev->private;
5756
5757 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5758 return -EINVAL;
5759 if (chan < 4) {
5760 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5761 devpriv->rtsi_trig_a_output_reg |=
5762 RTSI_Trig_Output_Bits(chan, source);
5763 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5764 RTSI_Trig_A_Output_Register);
5765 } else if (chan < 8) {
5766 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5767 devpriv->rtsi_trig_b_output_reg |=
5768 RTSI_Trig_Output_Bits(chan, source);
5769 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5770 RTSI_Trig_B_Output_Register);
5771 }
5772 return 2;
5773 }
5774
5775 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5776 {
5777 struct ni_private *devpriv = dev->private;
5778
5779 if (chan < 4) {
5780 return RTSI_Trig_Output_Source(chan,
5781 devpriv->rtsi_trig_a_output_reg);
5782 } else if (chan < num_configurable_rtsi_channels(dev)) {
5783 return RTSI_Trig_Output_Source(chan,
5784 devpriv->rtsi_trig_b_output_reg);
5785 } else {
5786 if (chan == old_RTSI_clock_channel)
5787 return NI_RTSI_OUTPUT_RTSI_OSC;
5788 printk("%s: bug! should never get here?\n", __func__);
5789 return 0;
5790 }
5791 }
5792
5793 static int ni_rtsi_insn_config(struct comedi_device *dev,
5794 struct comedi_subdevice *s,
5795 struct comedi_insn *insn, unsigned int *data)
5796 {
5797 const struct ni_board_struct *board = comedi_board(dev);
5798 struct ni_private *devpriv = dev->private;
5799 unsigned int chan = CR_CHAN(insn->chanspec);
5800
5801 switch (data[0]) {
5802 case INSN_CONFIG_DIO_OUTPUT:
5803 if (chan < num_configurable_rtsi_channels(dev)) {
5804 devpriv->rtsi_trig_direction_reg |=
5805 RTSI_Output_Bit(chan,
5806 (board->reg_type & ni_reg_m_series_mask) != 0);
5807 } else if (chan == old_RTSI_clock_channel) {
5808 devpriv->rtsi_trig_direction_reg |=
5809 Drive_RTSI_Clock_Bit;
5810 }
5811 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5812 RTSI_Trig_Direction_Register);
5813 break;
5814 case INSN_CONFIG_DIO_INPUT:
5815 if (chan < num_configurable_rtsi_channels(dev)) {
5816 devpriv->rtsi_trig_direction_reg &=
5817 ~RTSI_Output_Bit(chan,
5818 (board->reg_type & ni_reg_m_series_mask) != 0);
5819 } else if (chan == old_RTSI_clock_channel) {
5820 devpriv->rtsi_trig_direction_reg &=
5821 ~Drive_RTSI_Clock_Bit;
5822 }
5823 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5824 RTSI_Trig_Direction_Register);
5825 break;
5826 case INSN_CONFIG_DIO_QUERY:
5827 if (chan < num_configurable_rtsi_channels(dev)) {
5828 data[1] =
5829 (devpriv->rtsi_trig_direction_reg &
5830 RTSI_Output_Bit(chan,
5831 (board->reg_type & ni_reg_m_series_mask) != 0))
5832 ? INSN_CONFIG_DIO_OUTPUT
5833 : INSN_CONFIG_DIO_INPUT;
5834 } else if (chan == old_RTSI_clock_channel) {
5835 data[1] =
5836 (devpriv->rtsi_trig_direction_reg &
5837 Drive_RTSI_Clock_Bit)
5838 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5839 }
5840 return 2;
5841 break;
5842 case INSN_CONFIG_SET_CLOCK_SRC:
5843 return ni_set_master_clock(dev, data[1], data[2]);
5844 break;
5845 case INSN_CONFIG_GET_CLOCK_SRC:
5846 data[1] = devpriv->clock_source;
5847 data[2] = devpriv->clock_ns;
5848 return 3;
5849 break;
5850 case INSN_CONFIG_SET_ROUTING:
5851 return ni_set_rtsi_routing(dev, chan, data[1]);
5852 break;
5853 case INSN_CONFIG_GET_ROUTING:
5854 data[1] = ni_get_rtsi_routing(dev, chan);
5855 return 2;
5856 break;
5857 default:
5858 return -EINVAL;
5859 break;
5860 }
5861 return 1;
5862 }
5863
5864 static int cs5529_wait_for_idle(struct comedi_device *dev)
5865 {
5866 unsigned short status;
5867 const int timeout = HZ;
5868 int i;
5869
5870 for (i = 0; i < timeout; i++) {
5871 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5872 if ((status & CSS_ADC_BUSY) == 0) {
5873 break;
5874 }
5875 set_current_state(TASK_INTERRUPTIBLE);
5876 if (schedule_timeout(1)) {
5877 return -EIO;
5878 }
5879 }
5880 /* printk("looped %i times waiting for idle\n", i); */
5881 if (i == timeout) {
5882 printk("%s: %s: timeout\n", __FILE__, __func__);
5883 return -ETIME;
5884 }
5885 return 0;
5886 }
5887
5888 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5889 {
5890 static const int timeout = 100;
5891 int i;
5892
5893 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5894 /* give time for command to start being serially clocked into cs5529.
5895 * this insures that the CSS_ADC_BUSY bit will get properly
5896 * set before we exit this function.
5897 */
5898 for (i = 0; i < timeout; i++) {
5899 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5900 break;
5901 udelay(1);
5902 }
5903 /* printk("looped %i times writing command to cs5529\n", i); */
5904 if (i == timeout) {
5905 comedi_error(dev, "possible problem - never saw adc go busy?");
5906 }
5907 }
5908
5909 /* write to cs5529 register */
5910 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5911 unsigned int reg_select_bits)
5912 {
5913 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5914 CAL_ADC_Config_Data_High_Word_67xx);
5915 ni_ao_win_outw(dev, (value & 0xffff),
5916 CAL_ADC_Config_Data_Low_Word_67xx);
5917 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5918 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5919 if (cs5529_wait_for_idle(dev))
5920 comedi_error(dev, "time or signal in cs5529_config_write()");
5921 }
5922
5923 #ifdef NI_CS5529_DEBUG
5924 /* read from cs5529 register */
5925 static unsigned int cs5529_config_read(struct comedi_device *dev,
5926 unsigned int reg_select_bits)
5927 {
5928 unsigned int value;
5929
5930 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5931 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5932 if (cs5529_wait_for_idle(dev))
5933 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5934 value = (ni_ao_win_inw(dev,
5935 CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5936 0xff0000;
5937 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5938 return value;
5939 }
5940 #endif
5941
5942 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5943 {
5944 int retval;
5945 unsigned short status;
5946
5947 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5948 retval = cs5529_wait_for_idle(dev);
5949 if (retval) {
5950 comedi_error(dev,
5951 "timeout or signal in cs5529_do_conversion()");
5952 return -ETIME;
5953 }
5954 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5955 if (status & CSS_OSC_DETECT) {
5956 printk
5957 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5958 return -EIO;
5959 }
5960 if (status & CSS_OVERRANGE) {
5961 printk
5962 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5963 }
5964 if (data) {
5965 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5966 /* cs5529 returns 16 bit signed data in bipolar mode */
5967 *data ^= (1 << 15);
5968 }
5969 return 0;
5970 }
5971
5972 static int cs5529_ai_insn_read(struct comedi_device *dev,
5973 struct comedi_subdevice *s,
5974 struct comedi_insn *insn, unsigned int *data)
5975 {
5976 int n, retval;
5977 unsigned short sample;
5978 unsigned int channel_select;
5979 const unsigned int INTERNAL_REF = 0x1000;
5980
5981 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
5982 * do nothing. bit 12 seems to chooses internal reference voltage, bit
5983 * 13 causes the adc input to go overrange (maybe reads external reference?) */
5984 if (insn->chanspec & CR_ALT_SOURCE)
5985 channel_select = INTERNAL_REF;
5986 else
5987 channel_select = CR_CHAN(insn->chanspec);
5988 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5989
5990 for (n = 0; n < insn->n; n++) {
5991 retval = cs5529_do_conversion(dev, &sample);
5992 if (retval < 0)
5993 return retval;
5994 data[n] = sample;
5995 }
5996 return insn->n;
5997 }
5998
5999 static int init_cs5529(struct comedi_device *dev)
6000 {
6001 unsigned int config_bits =
6002 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
6003
6004 #if 1
6005 /* do self-calibration */
6006 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
6007 CSCMD_CONFIG_REGISTER);
6008 /* need to force a conversion for calibration to run */
6009 cs5529_do_conversion(dev, NULL);
6010 #else
6011 /* force gain calibration to 1 */
6012 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
6013 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
6014 CSCMD_CONFIG_REGISTER);
6015 if (cs5529_wait_for_idle(dev))
6016 comedi_error(dev, "timeout or signal in init_cs5529()\n");
6017 #endif
6018 #ifdef NI_CS5529_DEBUG
6019 printk("config: 0x%x\n", cs5529_config_read(dev,
6020 CSCMD_CONFIG_REGISTER));
6021 printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
6022 printk("offset: 0x%x\n", cs5529_config_read(dev,
6023 CSCMD_OFFSET_REGISTER));
6024 #endif
6025 return 0;
6026 }
Linux kernel - Deliverables
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