staging: comedi: comedi_test: rename waveform members
[deliverable/linux.git] / drivers / staging / comedi / drivers / plx9052.h
1 /*
2 comedi/drivers/plx9052.h
3 Definitions for the PLX-9052 PCI interface chip
4
5 Copyright (C) 2002 MEV Ltd. <http://www.mev.co.uk/>
6
7 COMEDI - Linux Control and Measurement Device Interface
8 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19 */
20
21 #ifndef _PLX9052_H_
22 #define _PLX9052_H_
23
24 /*
25 * INTCSR - Interrupt Control/Status register
26 */
27 #define PLX9052_INTCSR 0x4c
28 #define PLX9052_INTCSR_LI1ENAB (1 << 0) /* LI1 enabled */
29 #define PLX9052_INTCSR_LI1POL (1 << 1) /* LI1 active high */
30 #define PLX9052_INTCSR_LI1STAT (1 << 2) /* LI1 active */
31 #define PLX9052_INTCSR_LI2ENAB (1 << 3) /* LI2 enabled */
32 #define PLX9052_INTCSR_LI2POL (1 << 4) /* LI2 active high */
33 #define PLX9052_INTCSR_LI2STAT (1 << 5) /* LI2 active */
34 #define PLX9052_INTCSR_PCIENAB (1 << 6) /* PCIINT enabled */
35 #define PLX9052_INTCSR_SOFTINT (1 << 7) /* generate soft int */
36 #define PLX9052_INTCSR_LI1SEL (1 << 8) /* LI1 edge */
37 #define PLX9052_INTCSR_LI2SEL (1 << 9) /* LI2 edge */
38 #define PLX9052_INTCSR_LI1CLRINT (1 << 10) /* LI1 clear int */
39 #define PLX9052_INTCSR_LI2CLRINT (1 << 11) /* LI2 clear int */
40 #define PLX9052_INTCSR_ISAMODE (1 << 12) /* ISA interface mode */
41
42 /*
43 * CNTRL - User I/O, Direct Slave Response, Serial EEPROM, and
44 * Initialization Control register
45 */
46 #define PLX9052_CNTRL 0x50
47 #define PLX9052_CNTRL_WAITO (1 << 0) /* UIO0 or WAITO# select */
48 #define PLX9052_CNTRL_UIO0_DIR (1 << 1) /* UIO0 direction */
49 #define PLX9052_CNTRL_UIO0_DATA (1 << 2) /* UIO0 data */
50 #define PLX9052_CNTRL_LLOCKO (1 << 3) /* UIO1 or LLOCKo# select */
51 #define PLX9052_CNTRL_UIO1_DIR (1 << 4) /* UIO1 direction */
52 #define PLX9052_CNTRL_UIO1_DATA (1 << 5) /* UIO1 data */
53 #define PLX9052_CNTRL_CS2 (1 << 6) /* UIO2 or CS2# select */
54 #define PLX9052_CNTRL_UIO2_DIR (1 << 7) /* UIO2 direction */
55 #define PLX9052_CNTRL_UIO2_DATA (1 << 8) /* UIO2 data */
56 #define PLX9052_CNTRL_CS3 (1 << 9) /* UIO3 or CS3# select */
57 #define PLX9052_CNTRL_UIO3_DIR (1 << 10) /* UIO3 direction */
58 #define PLX9052_CNTRL_UIO3_DATA (1 << 11) /* UIO3 data */
59 #define PLX9052_CNTRL_PCIBAR01 (0 << 12) /* bar 0 (mem) and 1 (I/O) */
60 #define PLX9052_CNTRL_PCIBAR0 (1 << 12) /* bar 0 (mem) only */
61 #define PLX9052_CNTRL_PCIBAR1 (2 << 12) /* bar 1 (I/O) only */
62 #define PLX9052_CNTRL_PCI2_1_FEATURES (1 << 14) /* PCI r2.1 features enabled */
63 #define PLX9052_CNTRL_PCI_R_W_FLUSH (1 << 15) /* read w/write flush mode */
64 #define PLX9052_CNTRL_PCI_R_NO_FLUSH (1 << 16) /* read no flush mode */
65 #define PLX9052_CNTRL_PCI_R_NO_WRITE (1 << 17) /* read no write mode */
66 #define PLX9052_CNTRL_PCI_W_RELEASE (1 << 18) /* write release bus mode */
67 #define PLX9052_CNTRL_RETRY_CLKS(x) (((x) & 0xf) << 19) /* slave retry clks */
68 #define PLX9052_CNTRL_LOCK_ENAB (1 << 23) /* slave LOCK# enable */
69 #define PLX9052_CNTRL_EEPROM_MASK (0x1f << 24) /* EEPROM bits */
70 #define PLX9052_CNTRL_EEPROM_CLK (1 << 24) /* EEPROM clock */
71 #define PLX9052_CNTRL_EEPROM_CS (1 << 25) /* EEPROM chip select */
72 #define PLX9052_CNTRL_EEPROM_DOUT (1 << 26) /* EEPROM write bit */
73 #define PLX9052_CNTRL_EEPROM_DIN (1 << 27) /* EEPROM read bit */
74 #define PLX9052_CNTRL_EEPROM_PRESENT (1 << 28) /* EEPROM present */
75 #define PLX9052_CNTRL_RELOAD_CFG (1 << 29) /* reload configuration */
76 #define PLX9052_CNTRL_PCI_RESET (1 << 30) /* PCI adapter reset */
77 #define PLX9052_CNTRL_MASK_REV (1 << 31) /* mask revision */
78
79 #endif /* _PLX9052_H_ */
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