drivers/staging/cxt1e1/pmcc4_private.h

   1 #ifndef _INC_PMCC4_PRIVATE_H_
   2 #define _INC_PMCC4_PRIVATE_H_
   3
   4 /*-----------------------------------------------------------------------------
   5  * pmcc4_private.h -
   6  *
   7  * Copyright (C) 2005  SBE, Inc.
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  */
  19
  20
  21 #include <linux/kernel.h>
  22 #include <linux/sched.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>    /* support for tasklets */
  25 #include <linux/timer.h>        /* support for timer */
  26 #include <linux/workqueue.h>
  27 #include <linux/hdlc.h>
  28
  29 #include "libsbew.h"
  30 #include "pmcc4_defs.h"
  31 #include "pmcc4_cpld.h"
  32 #include "musycc.h"
  33 #include "sbe_promformat.h"
  34 #include "comet.h"
  35
  36
  37 /* driver state */
  38 #define SBE_DRVR_INIT        0x0
  39 #define SBE_DRVR_AVAILABLE   0x69734F4E
  40 #define SBE_DRVR_DOWN        0x1
  41
  42 /******************************************************************************
  43  * MUSYCC Message Descriptor - coupled to hardware implementation, the first
  44  * three u_int32 must not be reordered.
  45  */
  46
  47 struct mdesc
  48 {
  49     volatile u_int32_t status;  /* Buffer Descriptor */
  50     u_int32_t   data;           /* Data Pointer */
  51     u_int32_t   next;           /* MUSYCC view of Next Pointer */
  52     void       *mem_token;      /* Data */
  53     struct mdesc *snext;
  54 };
  55
  56
  57 /*************************************************************************
  58  * Private driver data structures, internal use only.
  59  */
  60
  61 struct c4_chan_info
  62 {
  63     int         gchan;          /* channel number within group/port 0-31 */
  64     int         channum;        /* absolute channel number 0-128 */
  65     u_int8_t    status;
  66 #define TX_RECOVERY_MASK   0x0f
  67 #define TX_ONR_RECOVERY    0x01
  68 #define TX_BUFF_RECOVERY   0x02
  69 #define RX_RECOVERY_MASK   0xf0
  70 #define RX_ONR_RECOVERY    0x10
  71
  72     unsigned char ch_start_rx;
  73 #define CH_START_RX_NOW    1
  74 #define CH_START_RX_ONR    2
  75 #define CH_START_RX_BUF    3
  76
  77     unsigned char ch_start_tx;
  78 #define CH_START_TX_1ST    1
  79 #define CH_START_TX_ONR    2
  80 #define CH_START_TX_BUF    3
  81
  82     char        tx_full;        /* boolean */
  83     short       txd_free;       /* count of TX Desc available */
  84     short       txd_required;   /* count of TX Desc needed by mesg */
  85     unsigned short rxd_num;     /* must support range up to 2000 */
  86     unsigned short txd_num;     /* must support range up to 1000 */
  87     int         rxix_irq_srv;
  88
  89     enum
  90     {
  91         UNASSIGNED,             /* AVAILABLE, NOTINUSE */
  92         DOWN,                   /* ASSIGNED, NOTINUSE */
  93         UP                      /* ASSIGNED and INUSE */
  94     }           state;
  95
  96     struct c4_port_info *up;
  97     void       *user;
  98
  99     struct work_struct ch_work;
 100     struct mdesc *mdt;
 101     struct mdesc *mdr;
 102     struct mdesc *txd_irq_srv;
 103     struct mdesc *txd_usr_add;
 104
 105 #if 0
 106     /*
 107      * FUTURE CODE MIGHT SEPARATE TIMESLOT MAP SETUPS INTO SINGLE IOCTL and
 108      * REMOVE MAPS FROM CHANNEL PARAMETER STRUCTURE
 109      */
 110     /*
 111      * each byte in bitmask below represents one timeslot (bitmask[0] is for
 112      * timeslot 0 and so on), each bit in the byte selects timeslot bits for
 113      * this channel (0xff - whole timeslot, 0x7f - 56kbps mode)
 114      */
 115
 116     u_int8_t    ts_bitmask[32];
 117 #endif
 118     spinlock_t  ch_rxlock;
 119     spinlock_t  ch_txlock;
 120     atomic_t    tx_pending;
 121
 122     struct sbecom_chan_stats s;
 123     struct sbecom_chan_param p;
 124 };
 125 typedef struct c4_chan_info mch_t;
 126
 127 struct c4_port_info
 128 {
 129
 130     struct musycc_globalr *reg;
 131     struct musycc_groupr *regram;
 132     void       *regram_saved;   /* Original malloc value may have non-2KB
 133                                  * boundary.  Need to save for use when
 134                                  * freeing. */
 135     comet_t    *cometbase;
 136     struct sbe_card_info *up;
 137
 138     /*
 139      * The workqueue is used for TX restart of ONR'd channels when in
 140      * Transparent mode.
 141      */
 142
 143     struct workqueue_struct *wq_port;   /* chan restart work queue */
 144     struct semaphore sr_sem_busy;       /* service request exclusion
 145                                          * semaphore */
 146     struct semaphore sr_sem_wait;       /* service request handshake
 147                                          * semaphore */
 148     u_int32_t   sr_last;
 149     short       openchans;
 150     char        portnum;
 151     char        group_is_set;   /* GROUP_INIT command issued to MUSYCC,
 152                                  * otherwise SET_CHAN Ioctl fails */
 153
 154     mch_t      *chan[MUSYCC_NCHANS];
 155     struct sbecom_port_param p;
 156
 157     /*
 158      * The MUSYCC timeslot mappings are maintained within the driver and are
 159      * modified and reloaded as each of a group's channels are configured.
 160      */
 161     u_int8_t    tsm[32];        /* tsm (time slot map) */
 162     int         fifomap[32];
 163 };
 164 typedef struct c4_port_info mpi_t;
 165
 166
 167 #define COMET_OFFSET(x) (0x80000+(x)*0x10000)
 168 #define EEPROM_OFFSET   0xC0000
 169 #define ISPLD_OFFSET    0xD0000
 170
 171 /* iSPLD control chip registers */
 172 #define ISPLD_MCSR  0x0
 173 #define ISPLD_MCLK  0x1
 174 #define ISPLD_LEDS  0x2
 175 #define ISPLD_INTR  0x3
 176 #define ISPLD_MAX   0x3
 177
 178 struct sbe_card_info
 179 {
 180     struct musycc_globalr *reg;
 181     struct musycc_groupr *regram;
 182     u_int32_t  *iqd_p;          /* pointer to dword aligned interrupt queue
 183                                  * descriptors */
 184     void       *iqd_p_saved;    /* Original malloc value may have non-dword
 185                                  * aligned boundary.  Need to save for use
 186                                  * when freeing. */
 187     unsigned int iqp_headx, iqp_tailx;
 188
 189     struct semaphore sem_wdbusy;/* watchdog exclusion semaphore */
 190     struct watchdog wd;         /* statically allocated watchdog structure */
 191     atomic_t    bh_pending;     /* bh queued, but not yet running */
 192     u_int32_t   brd_id;         /* unique PCI ID */
 193     u_int16_t   hdw_bid;      /* on/board hardware ID */
 194     unsigned short wdcount;
 195     unsigned char max_port;
 196     unsigned char brdno;        /* our board number */
 197     unsigned char wd_notify;
 198 #define WD_NOTIFY_1TX       1
 199 #define WD_NOTIFY_BUF       2
 200 #define WD_NOTIFY_ONR       4
 201     enum                        /* state as regards interrupt processing */
 202     {
 203         C_INIT,                 /* of-board-address not configured or are in
 204                                  * process of being removed, don't access
 205                                  * hardware */
 206         C_IDLE,                 /* off-board-addresses are configured, but
 207                                  * don't service interrupts, just clear them
 208                                  * from hardware */
 209         C_RUNNING               /* life is good, service away */
 210     }           state;
 211
 212     struct sbe_card_info *next;
 213     u_int32_t  *eeprombase;     /* mapped address of board's EEPROM */
 214     c4cpld_t   *cpldbase;       /* mapped address of board's CPLD hardware */
 215     char       *release;        /* SBE ID string w/in sbeRelease.c */
 216     void       *hdw_info;
 217 #ifdef CONFIG_PROC_FS
 218     struct proc_dir_entry *dir_dev;
 219 #endif
 220
 221     /* saved off interface assignments which bound a board */
 222     hdlc_device *first_if;
 223     hdlc_device *last_if;
 224     short       first_channum, last_channum;
 225
 226     struct intlog
 227     {
 228         u_int32_t   this_status_new;
 229         u_int32_t   last_status_new;
 230         u_int32_t   drvr_intr_thcount;
 231         u_int32_t   drvr_intr_bhcount;
 232         u_int32_t   drvr_int_failure;
 233     }           intlog;
 234
 235     mpi_t       port[MUSYCC_NPORTS];
 236     char        devname[SBE_IFACETMPL_SIZE + 1];
 237     atomic_t    tx_pending;
 238     u_int32_t   alarmed[4];     /* dpm211 */
 239
 240 #if defined(SBE_ISR_TASKLET)
 241     struct tasklet_struct ci_musycc_isr_tasklet;
 242 #elif defined(SBE_ISR_IMMEDIATE)
 243     struct tq_struct ci_musycc_isr_tq;
 244 #endif
 245 };
 246 typedef struct sbe_card_info ci_t;
 247
 248 struct s_hdw_info
 249 {
 250     u_int8_t    pci_busno;
 251     u_int8_t    pci_slot;
 252     u_int8_t    pci_pin[2];
 253     u_int8_t    revid[2];
 254     u_int8_t    mfg_info_sts;
 255 #define EEPROM_OK          0x00
 256 #define EEPROM_CRCERR      0x01
 257     char        promfmt;        /* prom type, from sbe_promformat.h */
 258
 259     char        devname[SBE_IFACETMPL_SIZE];
 260     struct pci_bus *bus;
 261     struct net_device *ndev;
 262     struct pci_dev *pdev[2];
 263
 264     unsigned long addr[2];
 265     unsigned long addr_mapped[2];
 266     unsigned long len[2];
 267
 268     union
 269     {
 270         char        data[128];
 271         FLD_TYPE1   pft1;       /* prom field, type #1 */
 272         FLD_TYPE2   pft2;       /* prom field, type #2 */
 273     }           mfg_info;
 274 };
 275 typedef struct s_hdw_info hdw_info_t;
 276
 277 /*****************************************************************/
 278
 279 struct c4_priv
 280 {
 281     int         channum;
 282     struct sbe_card_info *ci;
 283 };
 284
 285
 286 /*****************************************************************/
 287
 288 extern ci_t *c4_list;
 289
 290 mch_t      *c4_find_chan (int);
 291 int         c4_set_chan (int channum, struct sbecom_chan_param *);
 292 int         c4_get_chan (int channum, struct sbecom_chan_param *);
 293 int         c4_get_chan_stats (int channum, struct sbecom_chan_stats *);
 294
 295 #endif                          /* _INC_PMCC4_PRIVATE_H_ */