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staging: et131x: Remove struct tcb->flags
[deliverable/linux.git] / drivers / staging / et131x / et131x.c
1 /* Agere Systems Inc.
2 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
3 *
4 * Copyright © 2005 Agere Systems Inc.
5 * All rights reserved.
6 * http://www.agere.com
7 *
8 * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
9 *
10 *------------------------------------------------------------------------------
11 *
12 * SOFTWARE LICENSE
13 *
14 * This software is provided subject to the following terms and conditions,
15 * which you should read carefully before using the software. Using this
16 * software indicates your acceptance of these terms and conditions. If you do
17 * not agree with these terms and conditions, do not use the software.
18 *
19 * Copyright © 2005 Agere Systems Inc.
20 * All rights reserved.
21 *
22 * Redistribution and use in source or binary forms, with or without
23 * modifications, are permitted provided that the following conditions are met:
24 *
25 * . Redistributions of source code must retain the above copyright notice, this
26 * list of conditions and the following Disclaimer as comments in the code as
27 * well as in the documentation and/or other materials provided with the
28 * distribution.
29 *
30 * . Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following Disclaimer in the documentation
32 * and/or other materials provided with the distribution.
33 *
34 * . Neither the name of Agere Systems Inc. nor the names of the contributors
35 * may be used to endorse or promote products derived from this software
36 * without specific prior written permission.
37 *
38 * Disclaimer
39 *
40 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
41 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
42 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
43 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
44 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
47 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
48 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
50 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
51 * DAMAGE.
52 */
53
54 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
55
56 #include <linux/pci.h>
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/kernel.h>
60
61 #include <linux/sched.h>
62 #include <linux/ptrace.h>
63 #include <linux/slab.h>
64 #include <linux/ctype.h>
65 #include <linux/string.h>
66 #include <linux/timer.h>
67 #include <linux/interrupt.h>
68 #include <linux/in.h>
69 #include <linux/delay.h>
70 #include <linux/bitops.h>
71 #include <linux/io.h>
72
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/if_arp.h>
77 #include <linux/ioport.h>
78 #include <linux/crc32.h>
79 #include <linux/random.h>
80 #include <linux/phy.h>
81
82 #include "et131x.h"
83
84 MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
85 MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
86 MODULE_LICENSE("Dual BSD/GPL");
87 MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems");
88
89 /* EEPROM defines */
90 #define MAX_NUM_REGISTER_POLLS 1000
91 #define MAX_NUM_WRITE_RETRIES 2
92
93 /* MAC defines */
94 #define COUNTER_WRAP_16_BIT 0x10000
95 #define COUNTER_WRAP_12_BIT 0x1000
96
97 /* PCI defines */
98 #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
99 #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
100
101 /* ISR defines */
102 /* For interrupts, normal running is:
103 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
104 * watchdog_interrupt & txdma_xfer_done
105 *
106 * In both cases, when flow control is enabled for either Tx or bi-direction,
107 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
108 * buffer rings are running low.
109 */
110 #define INT_MASK_DISABLE 0xffffffff
111
112 /* NOTE: Masking out MAC_STAT Interrupt for now...
113 * #define INT_MASK_ENABLE 0xfff6bf17
114 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
115 */
116 #define INT_MASK_ENABLE 0xfffebf17
117 #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
118
119 /* General defines */
120 /* Packet and header sizes */
121 #define NIC_MIN_PACKET_SIZE 60
122
123 /* Multicast list size */
124 #define NIC_MAX_MCAST_LIST 128
125
126 /* Supported Filters */
127 #define ET131X_PACKET_TYPE_DIRECTED 0x0001
128 #define ET131X_PACKET_TYPE_MULTICAST 0x0002
129 #define ET131X_PACKET_TYPE_BROADCAST 0x0004
130 #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
131 #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
132
133 /* Tx Timeout */
134 #define ET131X_TX_TIMEOUT (1 * HZ)
135 #define NIC_SEND_HANG_THRESHOLD 0
136
137 /* MP_TCB flags */
138 #define FMP_DEST_MULTI 0x00000001
139 #define FMP_DEST_BROAD 0x00000002
140
141 /* MP_ADAPTER flags */
142 #define FMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
143
144 /* MP_SHARED flags */
145 #define FMP_ADAPTER_LOWER_POWER 0x00200000
146
147 #define FMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
148 #define FMP_ADAPTER_HARDWARE_ERROR 0x04000000
149
150 #define FMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
151
152 /* Some offsets in PCI config space that are actually used. */
153 #define ET1310_PCI_MAC_ADDRESS 0xA4
154 #define ET1310_PCI_EEPROM_STATUS 0xB2
155 #define ET1310_PCI_ACK_NACK 0xC0
156 #define ET1310_PCI_REPLAY 0xC2
157 #define ET1310_PCI_L0L1LATENCY 0xCF
158
159 /* PCI Product IDs */
160 #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
161 #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
162
163 /* Define order of magnitude converter */
164 #define NANO_IN_A_MICRO 1000
165
166 #define PARM_RX_NUM_BUFS_DEF 4
167 #define PARM_RX_TIME_INT_DEF 10
168 #define PARM_RX_MEM_END_DEF 0x2bc
169 #define PARM_TX_TIME_INT_DEF 40
170 #define PARM_TX_NUM_BUFS_DEF 4
171 #define PARM_DMA_CACHE_DEF 0
172
173 /* RX defines */
174 #define FBR_CHUNKS 32
175 #define MAX_DESC_PER_RING_RX 1024
176
177 /* number of RFDs - default and min */
178 #define RFD_LOW_WATER_MARK 40
179 #define NIC_DEFAULT_NUM_RFD 1024
180 #define NUM_FBRS 2
181
182 #define MAX_PACKETS_HANDLED 256
183
184 #define ALCATEL_MULTICAST_PKT 0x01000000
185 #define ALCATEL_BROADCAST_PKT 0x02000000
186
187 /* typedefs for Free Buffer Descriptors */
188 struct fbr_desc {
189 u32 addr_lo;
190 u32 addr_hi;
191 u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
192 };
193
194 /* Packet Status Ring Descriptors
195 *
196 * Word 0:
197 *
198 * top 16 bits are from the Alcatel Status Word as enumerated in
199 * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
200 *
201 * 0: hp hash pass
202 * 1: ipa IP checksum assist
203 * 2: ipp IP checksum pass
204 * 3: tcpa TCP checksum assist
205 * 4: tcpp TCP checksum pass
206 * 5: wol WOL Event
207 * 6: rxmac_error RXMAC Error Indicator
208 * 7: drop Drop packet
209 * 8: ft Frame Truncated
210 * 9: jp Jumbo Packet
211 * 10: vp VLAN Packet
212 * 11-15: unused
213 * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
214 * 17: asw_RX_DV_event short receive event detected
215 * 18: asw_false_carrier_event bad carrier since last good packet
216 * 19: asw_code_err one or more nibbles signalled as errors
217 * 20: asw_CRC_err CRC error
218 * 21: asw_len_chk_err frame length field incorrect
219 * 22: asw_too_long frame length > 1518 bytes
220 * 23: asw_OK valid CRC + no code error
221 * 24: asw_multicast has a multicast address
222 * 25: asw_broadcast has a broadcast address
223 * 26: asw_dribble_nibble spurious bits after EOP
224 * 27: asw_control_frame is a control frame
225 * 28: asw_pause_frame is a pause frame
226 * 29: asw_unsupported_op unsupported OP code
227 * 30: asw_VLAN_tag VLAN tag detected
228 * 31: asw_long_evt Rx long event
229 *
230 * Word 1:
231 * 0-15: length length in bytes
232 * 16-25: bi Buffer Index
233 * 26-27: ri Ring Index
234 * 28-31: reserved
235 */
236
237 struct pkt_stat_desc {
238 u32 word0;
239 u32 word1;
240 };
241
242 /* Typedefs for the RX DMA status word */
243
244 /* rx status word 0 holds part of the status bits of the Rx DMA engine
245 * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
246 * which contains the Free Buffer ring 0 and 1 available offset.
247 *
248 * bit 0-9 FBR1 offset
249 * bit 10 Wrap flag for FBR1
250 * bit 16-25 FBR0 offset
251 * bit 26 Wrap flag for FBR0
252 */
253
254 /* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
255 * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
256 * which contains the Packet Status Ring available offset.
257 *
258 * bit 0-15 reserved
259 * bit 16-27 PSRoffset
260 * bit 28 PSRwrap
261 * bit 29-31 unused
262 */
263
264 /* struct rx_status_block is a structure representing the status of the Rx
265 * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
266 */
267 struct rx_status_block {
268 u32 word0;
269 u32 word1;
270 };
271
272 /* Structure for look-up table holding free buffer ring pointers, addresses
273 * and state.
274 */
275 struct fbr_lookup {
276 void *virt[MAX_DESC_PER_RING_RX];
277 u32 bus_high[MAX_DESC_PER_RING_RX];
278 u32 bus_low[MAX_DESC_PER_RING_RX];
279 void *ring_virtaddr;
280 dma_addr_t ring_physaddr;
281 void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
282 dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
283 u32 local_full;
284 u32 num_entries;
285 dma_addr_t buffsize;
286 };
287
288 /* struct rx_ring is the structure representing the adaptor's local
289 * reference(s) to the rings
290 */
291 struct rx_ring {
292 struct fbr_lookup *fbr[NUM_FBRS];
293 void *ps_ring_virtaddr;
294 dma_addr_t ps_ring_physaddr;
295 u32 local_psr_full;
296 u32 psr_num_entries;
297
298 struct rx_status_block *rx_status_block;
299 dma_addr_t rx_status_bus;
300
301 /* RECV */
302 struct list_head recv_list;
303 u32 num_ready_recv;
304
305 u32 num_rfd;
306
307 bool unfinished_receives;
308 };
309
310 /* TX defines */
311 /* word 2 of the control bits in the Tx Descriptor ring for the ET-1310
312 *
313 * 0-15: length of packet
314 * 16-27: VLAN tag
315 * 28: VLAN CFI
316 * 29-31: VLAN priority
317 *
318 * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
319 *
320 * 0: last packet in the sequence
321 * 1: first packet in the sequence
322 * 2: interrupt the processor when this pkt sent
323 * 3: Control word - no packet data
324 * 4: Issue half-duplex backpressure : XON/XOFF
325 * 5: send pause frame
326 * 6: Tx frame has error
327 * 7: append CRC
328 * 8: MAC override
329 * 9: pad packet
330 * 10: Packet is a Huge packet
331 * 11: append VLAN tag
332 * 12: IP checksum assist
333 * 13: TCP checksum assist
334 * 14: UDP checksum assist
335 */
336
337 #define TXDESC_FLAG_LASTPKT 0x0001
338 #define TXDESC_FLAG_FIRSTPKT 0x0002
339 #define TXDESC_FLAG_INTPROC 0x0004
340
341 /* struct tx_desc represents each descriptor on the ring */
342 struct tx_desc {
343 u32 addr_hi;
344 u32 addr_lo;
345 u32 len_vlan; /* control words how to xmit the */
346 u32 flags; /* data (detailed above) */
347 };
348
349 /* The status of the Tx DMA engine it sits in free memory, and is pointed to
350 * by 0x101c / 0x1020. This is a DMA10 type
351 */
352
353 /* TCB (Transmit Control Block: Host Side) */
354 struct tcb {
355 struct tcb *next; /* Next entry in ring */
356 u32 count; /* Used to spot stuck/lost packets */
357 u32 stale; /* Used to spot stuck/lost packets */
358 struct sk_buff *skb; /* Network skb we are tied to */
359 u32 index; /* Ring indexes */
360 u32 index_start;
361 };
362
363 /* Structure representing our local reference(s) to the ring */
364 struct tx_ring {
365 /* TCB (Transmit Control Block) memory and lists */
366 struct tcb *tcb_ring;
367
368 /* List of TCBs that are ready to be used */
369 struct tcb *tcb_qhead;
370 struct tcb *tcb_qtail;
371
372 /* list of TCBs that are currently being sent. NOTE that access to all
373 * three of these (including used) are controlled via the
374 * TCBSendQLock. This lock should be secured prior to incementing /
375 * decrementing used, or any queue manipulation on send_head /
376 * tail
377 */
378 struct tcb *send_head;
379 struct tcb *send_tail;
380 int used;
381
382 /* The actual descriptor ring */
383 struct tx_desc *tx_desc_ring;
384 dma_addr_t tx_desc_ring_pa;
385
386 /* send_idx indicates where we last wrote to in the descriptor ring. */
387 u32 send_idx;
388
389 /* The location of the write-back status block */
390 u32 *tx_status;
391 dma_addr_t tx_status_pa;
392
393 /* Packets since the last IRQ: used for interrupt coalescing */
394 int since_irq;
395 };
396
397 /* Do not change these values: if changed, then change also in respective
398 * TXdma and Rxdma engines
399 */
400 #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
401 #define NUM_TCB 64
402
403 /* These values are all superseded by registry entries to facilitate tuning.
404 * Once the desired performance has been achieved, the optimal registry values
405 * should be re-populated to these #defines:
406 */
407 #define TX_ERROR_PERIOD 1000
408
409 #define LO_MARK_PERCENT_FOR_PSR 15
410 #define LO_MARK_PERCENT_FOR_RX 15
411
412 /* RFD (Receive Frame Descriptor) */
413 struct rfd {
414 struct list_head list_node;
415 struct sk_buff *skb;
416 u32 len; /* total size of receive frame */
417 u16 bufferindex;
418 u8 ringindex;
419 };
420
421 /* Flow Control */
422 #define FLOW_BOTH 0
423 #define FLOW_TXONLY 1
424 #define FLOW_RXONLY 2
425 #define FLOW_NONE 3
426
427 /* Struct to define some device statistics */
428 struct ce_stats {
429 /* MIB II variables
430 *
431 * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
432 * MUST have 32, then we'll need another way to perform atomic
433 * operations
434 */
435 u32 multicast_pkts_rcvd;
436 u32 rcvd_pkts_dropped;
437
438 /* Tx Statistics. */
439 u32 tx_underflows;
440
441 u32 tx_collisions;
442 u32 tx_excessive_collisions;
443 u32 tx_first_collisions;
444 u32 tx_late_collisions;
445 u32 tx_max_pkt_errs;
446 u32 tx_deferred;
447
448 /* Rx Statistics. */
449 u32 rx_overflows;
450
451 u32 rx_length_errs;
452 u32 rx_align_errs;
453 u32 rx_crc_errs;
454 u32 rx_code_violations;
455 u32 rx_other_errs;
456
457 u32 synchronous_iterations;
458 u32 interrupt_status;
459 };
460
461 /* The private adapter structure */
462 struct et131x_adapter {
463 struct net_device *netdev;
464 struct pci_dev *pdev;
465 struct mii_bus *mii_bus;
466 struct phy_device *phydev;
467 struct napi_struct napi;
468
469 /* Flags that indicate current state of the adapter */
470 u32 flags;
471
472 /* local link state, to determine if a state change has occurred */
473 int link;
474
475 /* Configuration */
476 u8 rom_addr[ETH_ALEN];
477 u8 addr[ETH_ALEN];
478 bool has_eeprom;
479 u8 eeprom_data[2];
480
481 /* Spinlocks */
482 spinlock_t tcb_send_qlock;
483 spinlock_t tcb_ready_qlock;
484 spinlock_t send_hw_lock;
485
486 spinlock_t rcv_lock;
487
488 /* Packet Filter and look ahead size */
489 u32 packet_filter;
490
491 /* multicast list */
492 u32 multicast_addr_count;
493 u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
494
495 /* Pointer to the device's PCI register space */
496 struct address_map __iomem *regs;
497
498 /* Registry parameters */
499 u8 wanted_flow; /* Flow we want for 802.3x flow control */
500 u32 registry_jumbo_packet; /* Max supported ethernet packet size */
501
502 /* Derived from the registry: */
503 u8 flowcontrol; /* flow control validated by the far-end */
504
505 /* Minimize init-time */
506 struct timer_list error_timer;
507
508 /* variable putting the phy into coma mode when boot up with no cable
509 * plugged in after 5 seconds
510 */
511 u8 boot_coma;
512
513 /* Next two used to save power information at power down. This
514 * information will be used during power up to set up parts of Power
515 * Management in JAGCore
516 */
517 u16 pdown_speed;
518 u8 pdown_duplex;
519
520 /* Tx Memory Variables */
521 struct tx_ring tx_ring;
522
523 /* Rx Memory Variables */
524 struct rx_ring rx_ring;
525
526 /* Stats */
527 struct ce_stats stats;
528 };
529
530 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
531 {
532 u32 reg;
533 int i;
534
535 /* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
536 * bits 7,1:0 both equal to 1, at least once after reset.
537 * Subsequent operations need only to check that bits 1:0 are equal
538 * to 1 prior to starting a single byte read/write
539 */
540
541 for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
542 /* Read registers grouped in DWORD1 */
543 if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, &reg))
544 return -EIO;
545
546 /* I2C idle and Phy Queue Avail both true */
547 if ((reg & 0x3000) == 0x3000) {
548 if (status)
549 *status = reg;
550 return reg & 0xFF;
551 }
552 }
553 return -ETIMEDOUT;
554 }
555
556 /* eeprom_write - Write a byte to the ET1310's EEPROM
557 * @adapter: pointer to our private adapter structure
558 * @addr: the address to write
559 * @data: the value to write
560 *
561 * Returns 1 for a successful write.
562 */
563 static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
564 {
565 struct pci_dev *pdev = adapter->pdev;
566 int index = 0;
567 int retries;
568 int err = 0;
569 int writeok = 0;
570 u32 status;
571 u32 val = 0;
572
573 /* For an EEPROM, an I2C single byte write is defined as a START
574 * condition followed by the device address, EEPROM address, one byte
575 * of data and a STOP condition. The STOP condition will trigger the
576 * EEPROM's internally timed write cycle to the nonvolatile memory.
577 * All inputs are disabled during this write cycle and the EEPROM will
578 * not respond to any access until the internal write is complete.
579 */
580
581 err = eeprom_wait_ready(pdev, NULL);
582 if (err < 0)
583 return err;
584
585 /* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
586 * and bits 1:0 both =0. Bit 5 should be set according to the
587 * type of EEPROM being accessed (1=two byte addressing, 0=one
588 * byte addressing).
589 */
590 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
591 LBCIF_CONTROL_LBCIF_ENABLE |
592 LBCIF_CONTROL_I2C_WRITE))
593 return -EIO;
594
595 /* Prepare EEPROM address for Step 3 */
596 for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
597 /* Write the address to the LBCIF Address Register */
598 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
599 break;
600 /* Write the data to the LBCIF Data Register (the I2C write
601 * will begin).
602 */
603 if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
604 break;
605 /* Monitor bit 1:0 of the LBCIF Status Register. When bits
606 * 1:0 are both equal to 1, the I2C write has completed and the
607 * internal write cycle of the EEPROM is about to start.
608 * (bits 1:0 = 01 is a legal state while waiting from both
609 * equal to 1, but bits 1:0 = 10 is invalid and implies that
610 * something is broken).
611 */
612 err = eeprom_wait_ready(pdev, &status);
613 if (err < 0)
614 return 0;
615
616 /* Check bit 3 of the LBCIF Status Register. If equal to 1,
617 * an error has occurred.Don't break here if we are revision
618 * 1, this is so we do a blind write for load bug.
619 */
620 if ((status & LBCIF_STATUS_GENERAL_ERROR)
621 && adapter->pdev->revision == 0)
622 break;
623
624 /* Check bit 2 of the LBCIF Status Register. If equal to 1 an
625 * ACK error has occurred on the address phase of the write.
626 * This could be due to an actual hardware failure or the
627 * EEPROM may still be in its internal write cycle from a
628 * previous write. This write operation was ignored and must be
629 *repeated later.
630 */
631 if (status & LBCIF_STATUS_ACK_ERROR) {
632 /* This could be due to an actual hardware failure
633 * or the EEPROM may still be in its internal write
634 * cycle from a previous write. This write operation
635 * was ignored and must be repeated later.
636 */
637 udelay(10);
638 continue;
639 }
640
641 writeok = 1;
642 break;
643 }
644
645 /* Set bit 6 of the LBCIF Control Register = 0.
646 */
647 udelay(10);
648
649 while (1) {
650 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
651 LBCIF_CONTROL_LBCIF_ENABLE))
652 writeok = 0;
653
654 /* Do read until internal ACK_ERROR goes away meaning write
655 * completed
656 */
657 do {
658 pci_write_config_dword(pdev,
659 LBCIF_ADDRESS_REGISTER,
660 addr);
661 do {
662 pci_read_config_dword(pdev,
663 LBCIF_DATA_REGISTER,
664 &val);
665 } while ((val & 0x00010000) == 0);
666 } while (val & 0x00040000);
667
668 if ((val & 0xFF00) != 0xC000 || index == 10000)
669 break;
670 index++;
671 }
672 return writeok ? 0 : -EIO;
673 }
674
675 /* eeprom_read - Read a byte from the ET1310's EEPROM
676 * @adapter: pointer to our private adapter structure
677 * @addr: the address from which to read
678 * @pdata: a pointer to a byte in which to store the value of the read
679 * @eeprom_id: the ID of the EEPROM
680 * @addrmode: how the EEPROM is to be accessed
681 *
682 * Returns 1 for a successful read
683 */
684 static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
685 {
686 struct pci_dev *pdev = adapter->pdev;
687 int err;
688 u32 status;
689
690 /* A single byte read is similar to the single byte write, with the
691 * exception of the data flow:
692 */
693
694 err = eeprom_wait_ready(pdev, NULL);
695 if (err < 0)
696 return err;
697 /* Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
698 * and bits 1:0 both =0. Bit 5 should be set according to the type
699 * of EEPROM being accessed (1=two byte addressing, 0=one byte
700 * addressing).
701 */
702 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
703 LBCIF_CONTROL_LBCIF_ENABLE))
704 return -EIO;
705 /* Write the address to the LBCIF Address Register (I2C read will
706 * begin).
707 */
708 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
709 return -EIO;
710 /* Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
711 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
712 * has occurred).
713 */
714 err = eeprom_wait_ready(pdev, &status);
715 if (err < 0)
716 return err;
717 /* Regardless of error status, read data byte from LBCIF Data
718 * Register.
719 */
720 *pdata = err;
721 /* Check bit 2 of the LBCIF Status Register. If = 1,
722 * then an error has occurred.
723 */
724 return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
725 }
726
727 static int et131x_init_eeprom(struct et131x_adapter *adapter)
728 {
729 struct pci_dev *pdev = adapter->pdev;
730 u8 eestatus;
731
732 /* We first need to check the EEPROM Status code located at offset
733 * 0xB2 of config space
734 */
735 pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus);
736
737 /* THIS IS A WORKAROUND:
738 * I need to call this function twice to get my card in a
739 * LG M1 Express Dual running. I tried also a msleep before this
740 * function, because I thought there could be some time conditions
741 * but it didn't work. Call the whole function twice also work.
742 */
743 if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
744 dev_err(&pdev->dev,
745 "Could not read PCI config space for EEPROM Status\n");
746 return -EIO;
747 }
748
749 /* Determine if the error(s) we care about are present. If they are
750 * present we need to fail.
751 */
752 if (eestatus & 0x4C) {
753 int write_failed = 0;
754
755 if (pdev->revision == 0x01) {
756 int i;
757 static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
758
759 /* Re-write the first 4 bytes if we have an eeprom
760 * present and the revision id is 1, this fixes the
761 * corruption seen with 1310 B Silicon
762 */
763 for (i = 0; i < 3; i++)
764 if (eeprom_write(adapter, i, eedata[i]) < 0)
765 write_failed = 1;
766 }
767 if (pdev->revision != 0x01 || write_failed) {
768 dev_err(&pdev->dev,
769 "Fatal EEPROM Status Error - 0x%04x\n",
770 eestatus);
771
772 /* This error could mean that there was an error
773 * reading the eeprom or that the eeprom doesn't exist.
774 * We will treat each case the same and not try to
775 * gather additional information that normally would
776 * come from the eeprom, like MAC Address
777 */
778 adapter->has_eeprom = 0;
779 return -EIO;
780 }
781 }
782 adapter->has_eeprom = 1;
783
784 /* Read the EEPROM for information regarding LED behavior. Refer to
785 * ET1310_phy.c, et131x_xcvr_init(), for its use.
786 */
787 eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
788 eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
789
790 if (adapter->eeprom_data[0] != 0xcd)
791 /* Disable all optional features */
792 adapter->eeprom_data[1] = 0x00;
793
794 return 0;
795 }
796
797 /* et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
798 * @adapter: pointer to our adapter structure
799 */
800 static void et131x_rx_dma_enable(struct et131x_adapter *adapter)
801 {
802 /* Setup the receive dma configuration register for normal operation */
803 u32 csr = ET_RXDMA_CSR_FBR1_ENABLE;
804 struct rx_ring *rx_ring = &adapter->rx_ring;
805
806 if (rx_ring->fbr[1]->buffsize == 4096)
807 csr |= ET_RXDMA_CSR_FBR1_SIZE_LO;
808 else if (rx_ring->fbr[1]->buffsize == 8192)
809 csr |= ET_RXDMA_CSR_FBR1_SIZE_HI;
810 else if (rx_ring->fbr[1]->buffsize == 16384)
811 csr |= ET_RXDMA_CSR_FBR1_SIZE_LO | ET_RXDMA_CSR_FBR1_SIZE_HI;
812
813 csr |= ET_RXDMA_CSR_FBR0_ENABLE;
814 if (rx_ring->fbr[0]->buffsize == 256)
815 csr |= ET_RXDMA_CSR_FBR0_SIZE_LO;
816 else if (rx_ring->fbr[0]->buffsize == 512)
817 csr |= ET_RXDMA_CSR_FBR0_SIZE_HI;
818 else if (rx_ring->fbr[0]->buffsize == 1024)
819 csr |= ET_RXDMA_CSR_FBR0_SIZE_LO | ET_RXDMA_CSR_FBR0_SIZE_HI;
820 writel(csr, &adapter->regs->rxdma.csr);
821
822 csr = readl(&adapter->regs->rxdma.csr);
823 if (csr & ET_RXDMA_CSR_HALT_STATUS) {
824 udelay(5);
825 csr = readl(&adapter->regs->rxdma.csr);
826 if (csr & ET_RXDMA_CSR_HALT_STATUS) {
827 dev_err(&adapter->pdev->dev,
828 "RX Dma failed to exit halt state. CSR 0x%08x\n",
829 csr);
830 }
831 }
832 }
833
834 /* et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
835 * @adapter: pointer to our adapter structure
836 */
837 static void et131x_rx_dma_disable(struct et131x_adapter *adapter)
838 {
839 u32 csr;
840 /* Setup the receive dma configuration register */
841 writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE,
842 &adapter->regs->rxdma.csr);
843 csr = readl(&adapter->regs->rxdma.csr);
844 if (!(csr & ET_RXDMA_CSR_HALT_STATUS)) {
845 udelay(5);
846 csr = readl(&adapter->regs->rxdma.csr);
847 if (!(csr & ET_RXDMA_CSR_HALT_STATUS))
848 dev_err(&adapter->pdev->dev,
849 "RX Dma failed to enter halt state. CSR 0x%08x\n",
850 csr);
851 }
852 }
853
854 /* et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
855 * @adapter: pointer to our adapter structure
856 *
857 * Mainly used after a return to the D0 (full-power) state from a lower state.
858 */
859 static void et131x_tx_dma_enable(struct et131x_adapter *adapter)
860 {
861 /* Setup the transmit dma configuration register for normal
862 * operation
863 */
864 writel(ET_TXDMA_SNGL_EPKT | (PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
865 &adapter->regs->txdma.csr);
866 }
867
868 static inline void add_10bit(u32 *v, int n)
869 {
870 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
871 }
872
873 static inline void add_12bit(u32 *v, int n)
874 {
875 *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
876 }
877
878 /* et1310_config_mac_regs1 - Initialize the first part of MAC regs
879 * @adapter: pointer to our adapter structure
880 */
881 static void et1310_config_mac_regs1(struct et131x_adapter *adapter)
882 {
883 struct mac_regs __iomem *macregs = &adapter->regs->mac;
884 u32 station1;
885 u32 station2;
886 u32 ipg;
887
888 /* First we need to reset everything. Write to MAC configuration
889 * register 1 to perform reset.
890 */
891 writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
892 ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
893 ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC,
894 &macregs->cfg1);
895
896 /* Next lets configure the MAC Inter-packet gap register */
897 ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
898 ipg |= 0x50 << 8; /* ifg enforce 0x50 */
899 writel(ipg, &macregs->ipg);
900
901 /* Next lets configure the MAC Half Duplex register */
902 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
903 writel(0x00A1F037, &macregs->hfdp);
904
905 /* Next lets configure the MAC Interface Control register */
906 writel(0, &macregs->if_ctrl);
907
908 /* Let's move on to setting up the mii management configuration */
909 writel(ET_MAC_MIIMGMT_CLK_RST, &macregs->mii_mgmt_cfg);
910
911 /* Next lets configure the MAC Station Address register. These
912 * values are read from the EEPROM during initialization and stored
913 * in the adapter structure. We write what is stored in the adapter
914 * structure to the MAC Station Address registers high and low. This
915 * station address is used for generating and checking pause control
916 * packets.
917 */
918 station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
919 (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
920 station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
921 (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
922 (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
923 adapter->addr[2];
924 writel(station1, &macregs->station_addr_1);
925 writel(station2, &macregs->station_addr_2);
926
927 /* Max ethernet packet in bytes that will be passed by the mac without
928 * being truncated. Allow the MAC to pass 4 more than our max packet
929 * size. This is 4 for the Ethernet CRC.
930 *
931 * Packets larger than (registry_jumbo_packet) that do not contain a
932 * VLAN ID will be dropped by the Rx function.
933 */
934 writel(adapter->registry_jumbo_packet + 4, &macregs->max_fm_len);
935
936 /* clear out MAC config reset */
937 writel(0, &macregs->cfg1);
938 }
939
940 /* et1310_config_mac_regs2 - Initialize the second part of MAC regs
941 * @adapter: pointer to our adapter structure
942 */
943 static void et1310_config_mac_regs2(struct et131x_adapter *adapter)
944 {
945 int32_t delay = 0;
946 struct mac_regs __iomem *mac = &adapter->regs->mac;
947 struct phy_device *phydev = adapter->phydev;
948 u32 cfg1;
949 u32 cfg2;
950 u32 ifctrl;
951 u32 ctl;
952
953 ctl = readl(&adapter->regs->txmac.ctl);
954 cfg1 = readl(&mac->cfg1);
955 cfg2 = readl(&mac->cfg2);
956 ifctrl = readl(&mac->if_ctrl);
957
958 /* Set up the if mode bits */
959 cfg2 &= ~ET_MAC_CFG2_IFMODE_MASK;
960 if (phydev->speed == SPEED_1000) {
961 cfg2 |= ET_MAC_CFG2_IFMODE_1000;
962 /* Phy mode bit */
963 ifctrl &= ~ET_MAC_IFCTRL_PHYMODE;
964 } else {
965 cfg2 |= ET_MAC_CFG2_IFMODE_100;
966 ifctrl |= ET_MAC_IFCTRL_PHYMODE;
967 }
968
969 /* We need to enable Rx/Tx */
970 cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE |
971 ET_MAC_CFG1_TX_FLOW;
972 /* Initialize loop back to off */
973 cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW);
974 if (adapter->flowcontrol == FLOW_RXONLY ||
975 adapter->flowcontrol == FLOW_BOTH)
976 cfg1 |= ET_MAC_CFG1_RX_FLOW;
977 writel(cfg1, &mac->cfg1);
978
979 /* Now we need to initialize the MAC Configuration 2 register */
980 /* preamble 7, check length, huge frame off, pad crc, crc enable
981 * full duplex off
982 */
983 cfg2 |= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT;
984 cfg2 |= ET_MAC_CFG2_IFMODE_LEN_CHECK;
985 cfg2 |= ET_MAC_CFG2_IFMODE_PAD_CRC;
986 cfg2 |= ET_MAC_CFG2_IFMODE_CRC_ENABLE;
987 cfg2 &= ~ET_MAC_CFG2_IFMODE_HUGE_FRAME;
988 cfg2 &= ~ET_MAC_CFG2_IFMODE_FULL_DPLX;
989
990 /* Turn on duplex if needed */
991 if (phydev->duplex == DUPLEX_FULL)
992 cfg2 |= ET_MAC_CFG2_IFMODE_FULL_DPLX;
993
994 ifctrl &= ~ET_MAC_IFCTRL_GHDMODE;
995 if (phydev->duplex == DUPLEX_HALF)
996 ifctrl |= ET_MAC_IFCTRL_GHDMODE;
997
998 writel(ifctrl, &mac->if_ctrl);
999 writel(cfg2, &mac->cfg2);
1000
1001 do {
1002 udelay(10);
1003 delay++;
1004 cfg1 = readl(&mac->cfg1);
1005 } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100);
1006
1007 if (delay == 100) {
1008 dev_warn(&adapter->pdev->dev,
1009 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
1010 cfg1);
1011 }
1012
1013 /* Enable txmac */
1014 ctl |= ET_TX_CTRL_TXMAC_ENABLE | ET_TX_CTRL_FC_DISABLE;
1015 writel(ctl, &adapter->regs->txmac.ctl);
1016
1017 /* Ready to start the RXDMA/TXDMA engine */
1018 if (adapter->flags & FMP_ADAPTER_LOWER_POWER) {
1019 et131x_rx_dma_enable(adapter);
1020 et131x_tx_dma_enable(adapter);
1021 }
1022 }
1023
1024 /* et1310_in_phy_coma - check if the device is in phy coma
1025 * @adapter: pointer to our adapter structure
1026 *
1027 * Returns 0 if the device is not in phy coma, 1 if it is in phy coma
1028 */
1029 static int et1310_in_phy_coma(struct et131x_adapter *adapter)
1030 {
1031 u32 pmcsr = readl(&adapter->regs->global.pm_csr);
1032
1033 return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
1034 }
1035
1036 static void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
1037 {
1038 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1039 u32 hash1 = 0;
1040 u32 hash2 = 0;
1041 u32 hash3 = 0;
1042 u32 hash4 = 0;
1043 u32 pm_csr;
1044
1045 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
1046 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
1047 * specified) then we should pass NO multi-cast addresses to the
1048 * driver.
1049 */
1050 if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) {
1051 int i;
1052
1053 /* Loop through our multicast array and set up the device */
1054 for (i = 0; i < adapter->multicast_addr_count; i++) {
1055 u32 result;
1056
1057 result = ether_crc(6, adapter->multicast_list[i]);
1058
1059 result = (result & 0x3F800000) >> 23;
1060
1061 if (result < 32) {
1062 hash1 |= (1 << result);
1063 } else if ((31 < result) && (result < 64)) {
1064 result -= 32;
1065 hash2 |= (1 << result);
1066 } else if ((63 < result) && (result < 96)) {
1067 result -= 64;
1068 hash3 |= (1 << result);
1069 } else {
1070 result -= 96;
1071 hash4 |= (1 << result);
1072 }
1073 }
1074 }
1075
1076 /* Write out the new hash to the device */
1077 pm_csr = readl(&adapter->regs->global.pm_csr);
1078 if (!et1310_in_phy_coma(adapter)) {
1079 writel(hash1, &rxmac->multi_hash1);
1080 writel(hash2, &rxmac->multi_hash2);
1081 writel(hash3, &rxmac->multi_hash3);
1082 writel(hash4, &rxmac->multi_hash4);
1083 }
1084 }
1085
1086 static void et1310_setup_device_for_unicast(struct et131x_adapter *adapter)
1087 {
1088 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1089 u32 uni_pf1;
1090 u32 uni_pf2;
1091 u32 uni_pf3;
1092 u32 pm_csr;
1093
1094 /* Set up unicast packet filter reg 3 to be the first two octets of
1095 * the MAC address for both address
1096 *
1097 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
1098 * MAC address for second address
1099 *
1100 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
1101 * MAC address for first address
1102 */
1103 uni_pf3 = (adapter->addr[0] << ET_RX_UNI_PF_ADDR2_1_SHIFT) |
1104 (adapter->addr[1] << ET_RX_UNI_PF_ADDR2_2_SHIFT) |
1105 (adapter->addr[0] << ET_RX_UNI_PF_ADDR1_1_SHIFT) |
1106 adapter->addr[1];
1107
1108 uni_pf2 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR2_3_SHIFT) |
1109 (adapter->addr[3] << ET_RX_UNI_PF_ADDR2_4_SHIFT) |
1110 (adapter->addr[4] << ET_RX_UNI_PF_ADDR2_5_SHIFT) |
1111 adapter->addr[5];
1112
1113 uni_pf1 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR1_3_SHIFT) |
1114 (adapter->addr[3] << ET_RX_UNI_PF_ADDR1_4_SHIFT) |
1115 (adapter->addr[4] << ET_RX_UNI_PF_ADDR1_5_SHIFT) |
1116 adapter->addr[5];
1117
1118 pm_csr = readl(&adapter->regs->global.pm_csr);
1119 if (!et1310_in_phy_coma(adapter)) {
1120 writel(uni_pf1, &rxmac->uni_pf_addr1);
1121 writel(uni_pf2, &rxmac->uni_pf_addr2);
1122 writel(uni_pf3, &rxmac->uni_pf_addr3);
1123 }
1124 }
1125
1126 static void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
1127 {
1128 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1129 struct phy_device *phydev = adapter->phydev;
1130 u32 sa_lo;
1131 u32 sa_hi = 0;
1132 u32 pf_ctrl = 0;
1133 u32 __iomem *wolw;
1134
1135 /* Disable the MAC while it is being configured (also disable WOL) */
1136 writel(0x8, &rxmac->ctrl);
1137
1138 /* Initialize WOL to disabled. */
1139 writel(0, &rxmac->crc0);
1140 writel(0, &rxmac->crc12);
1141 writel(0, &rxmac->crc34);
1142
1143 /* We need to set the WOL mask0 - mask4 next. We initialize it to
1144 * its default Values of 0x00000000 because there are not WOL masks
1145 * as of this time.
1146 */
1147 for (wolw = &rxmac->mask0_word0; wolw <= &rxmac->mask4_word3; wolw++)
1148 writel(0, wolw);
1149
1150 /* Lets setup the WOL Source Address */
1151 sa_lo = (adapter->addr[2] << ET_RX_WOL_LO_SA3_SHIFT) |
1152 (adapter->addr[3] << ET_RX_WOL_LO_SA4_SHIFT) |
1153 (adapter->addr[4] << ET_RX_WOL_LO_SA5_SHIFT) |
1154 adapter->addr[5];
1155 writel(sa_lo, &rxmac->sa_lo);
1156
1157 sa_hi = (u32) (adapter->addr[0] << ET_RX_WOL_HI_SA1_SHIFT) |
1158 adapter->addr[1];
1159 writel(sa_hi, &rxmac->sa_hi);
1160
1161 /* Disable all Packet Filtering */
1162 writel(0, &rxmac->pf_ctrl);
1163
1164 /* Let's initialize the Unicast Packet filtering address */
1165 if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
1166 et1310_setup_device_for_unicast(adapter);
1167 pf_ctrl |= ET_RX_PFCTRL_UNICST_FILTER_ENABLE;
1168 } else {
1169 writel(0, &rxmac->uni_pf_addr1);
1170 writel(0, &rxmac->uni_pf_addr2);
1171 writel(0, &rxmac->uni_pf_addr3);
1172 }
1173
1174 /* Let's initialize the Multicast hash */
1175 if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
1176 pf_ctrl |= ET_RX_PFCTRL_MLTCST_FILTER_ENABLE;
1177 et1310_setup_device_for_multicast(adapter);
1178 }
1179
1180 /* Runt packet filtering. Didn't work in version A silicon. */
1181 pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT;
1182 pf_ctrl |= ET_RX_PFCTRL_FRAG_FILTER_ENABLE;
1183
1184 if (adapter->registry_jumbo_packet > 8192)
1185 /* In order to transmit jumbo packets greater than 8k, the
1186 * FIFO between RxMAC and RxDMA needs to be reduced in size
1187 * to (16k - Jumbo packet size). In order to implement this,
1188 * we must use "cut through" mode in the RxMAC, which chops
1189 * packets down into segments which are (max_size * 16). In
1190 * this case we selected 256 bytes, since this is the size of
1191 * the PCI-Express TLP's that the 1310 uses.
1192 *
1193 * seg_en on, fc_en off, size 0x10
1194 */
1195 writel(0x41, &rxmac->mcif_ctrl_max_seg);
1196 else
1197 writel(0, &rxmac->mcif_ctrl_max_seg);
1198
1199 /* Initialize the MCIF water marks */
1200 writel(0, &rxmac->mcif_water_mark);
1201
1202 /* Initialize the MIF control */
1203 writel(0, &rxmac->mif_ctrl);
1204
1205 /* Initialize the Space Available Register */
1206 writel(0, &rxmac->space_avail);
1207
1208 /* Initialize the the mif_ctrl register
1209 * bit 3: Receive code error. One or more nibbles were signaled as
1210 * errors during the reception of the packet. Clear this
1211 * bit in Gigabit, set it in 100Mbit. This was derived
1212 * experimentally at UNH.
1213 * bit 4: Receive CRC error. The packet's CRC did not match the
1214 * internally generated CRC.
1215 * bit 5: Receive length check error. Indicates that frame length
1216 * field value in the packet does not match the actual data
1217 * byte length and is not a type field.
1218 * bit 16: Receive frame truncated.
1219 * bit 17: Drop packet enable
1220 */
1221 if (phydev && phydev->speed == SPEED_100)
1222 writel(0x30038, &rxmac->mif_ctrl);
1223 else
1224 writel(0x30030, &rxmac->mif_ctrl);
1225
1226 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
1227 * filter is always enabled since it is where the runt packets are
1228 * supposed to be dropped. For version A silicon, runt packet
1229 * dropping doesn't work, so it is disabled in the pf_ctrl register,
1230 * but we still leave the packet filter on.
1231 */
1232 writel(pf_ctrl, &rxmac->pf_ctrl);
1233 writel(ET_RX_CTRL_RXMAC_ENABLE | ET_RX_CTRL_WOL_DISABLE, &rxmac->ctrl);
1234 }
1235
1236 static void et1310_config_txmac_regs(struct et131x_adapter *adapter)
1237 {
1238 struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
1239
1240 /* We need to update the Control Frame Parameters
1241 * cfpt - control frame pause timer set to 64 (0x40)
1242 * cfep - control frame extended pause timer set to 0x0
1243 */
1244 if (adapter->flowcontrol == FLOW_NONE)
1245 writel(0, &txmac->cf_param);
1246 else
1247 writel(0x40, &txmac->cf_param);
1248 }
1249
1250 static void et1310_config_macstat_regs(struct et131x_adapter *adapter)
1251 {
1252 struct macstat_regs __iomem *macstat = &adapter->regs->macstat;
1253 u32 __iomem *reg;
1254
1255 /* initialize all the macstat registers to zero on the device */
1256 for (reg = &macstat->txrx_0_64_byte_frames;
1257 reg <= &macstat->carry_reg2; reg++)
1258 writel(0, reg);
1259
1260 /* Unmask any counters that we want to track the overflow of.
1261 * Initially this will be all counters. It may become clear later
1262 * that we do not need to track all counters.
1263 */
1264 writel(0xFFFFBE32, &macstat->carry_reg1_mask);
1265 writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
1266 }
1267
1268 /* et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
1269 * @adapter: pointer to our private adapter structure
1270 * @addr: the address of the transceiver
1271 * @reg: the register to read
1272 * @value: pointer to a 16-bit value in which the value will be stored
1273 */
1274 static int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
1275 u8 reg, u16 *value)
1276 {
1277 struct mac_regs __iomem *mac = &adapter->regs->mac;
1278 int status = 0;
1279 u32 delay = 0;
1280 u32 mii_addr;
1281 u32 mii_cmd;
1282 u32 mii_indicator;
1283
1284 /* Save a local copy of the registers we are dealing with so we can
1285 * set them back
1286 */
1287 mii_addr = readl(&mac->mii_mgmt_addr);
1288 mii_cmd = readl(&mac->mii_mgmt_cmd);
1289
1290 /* Stop the current operation */
1291 writel(0, &mac->mii_mgmt_cmd);
1292
1293 /* Set up the register we need to read from on the correct PHY */
1294 writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1295
1296 writel(0x1, &mac->mii_mgmt_cmd);
1297
1298 do {
1299 udelay(50);
1300 delay++;
1301 mii_indicator = readl(&mac->mii_mgmt_indicator);
1302 } while ((mii_indicator & ET_MAC_MGMT_WAIT) && delay < 50);
1303
1304 /* If we hit the max delay, we could not read the register */
1305 if (delay == 50) {
1306 dev_warn(&adapter->pdev->dev,
1307 "reg 0x%08x could not be read\n", reg);
1308 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1309 mii_indicator);
1310
1311 status = -EIO;
1312 goto out;
1313 }
1314
1315 /* If we hit here we were able to read the register and we need to
1316 * return the value to the caller
1317 */
1318 *value = readl(&mac->mii_mgmt_stat) & ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK;
1319
1320 out:
1321 /* Stop the read operation */
1322 writel(0, &mac->mii_mgmt_cmd);
1323
1324 /* set the registers we touched back to the state at which we entered
1325 * this function
1326 */
1327 writel(mii_addr, &mac->mii_mgmt_addr);
1328 writel(mii_cmd, &mac->mii_mgmt_cmd);
1329
1330 return status;
1331 }
1332
1333 static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
1334 {
1335 struct phy_device *phydev = adapter->phydev;
1336
1337 if (!phydev)
1338 return -EIO;
1339
1340 return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
1341 }
1342
1343 /* et131x_mii_write - Write to a PHY reg through the MII interface of the MAC
1344 * @adapter: pointer to our private adapter structure
1345 * @reg: the register to read
1346 * @value: 16-bit value to write
1347 */
1348 static int et131x_mii_write(struct et131x_adapter *adapter, u8 addr, u8 reg,
1349 u16 value)
1350 {
1351 struct mac_regs __iomem *mac = &adapter->regs->mac;
1352 int status = 0;
1353 u32 delay = 0;
1354 u32 mii_addr;
1355 u32 mii_cmd;
1356 u32 mii_indicator;
1357
1358 /* Save a local copy of the registers we are dealing with so we can
1359 * set them back
1360 */
1361 mii_addr = readl(&mac->mii_mgmt_addr);
1362 mii_cmd = readl(&mac->mii_mgmt_cmd);
1363
1364 /* Stop the current operation */
1365 writel(0, &mac->mii_mgmt_cmd);
1366
1367 /* Set up the register we need to write to on the correct PHY */
1368 writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1369
1370 /* Add the value to write to the registers to the mac */
1371 writel(value, &mac->mii_mgmt_ctrl);
1372
1373 do {
1374 udelay(50);
1375 delay++;
1376 mii_indicator = readl(&mac->mii_mgmt_indicator);
1377 } while ((mii_indicator & ET_MAC_MGMT_BUSY) && delay < 100);
1378
1379 /* If we hit the max delay, we could not write the register */
1380 if (delay == 100) {
1381 u16 tmp;
1382
1383 dev_warn(&adapter->pdev->dev,
1384 "reg 0x%08x could not be written", reg);
1385 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1386 mii_indicator);
1387 dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
1388 readl(&mac->mii_mgmt_cmd));
1389
1390 et131x_mii_read(adapter, reg, &tmp);
1391
1392 status = -EIO;
1393 }
1394 /* Stop the write operation */
1395 writel(0, &mac->mii_mgmt_cmd);
1396
1397 /* set the registers we touched back to the state at which we entered
1398 * this function
1399 */
1400 writel(mii_addr, &mac->mii_mgmt_addr);
1401 writel(mii_cmd, &mac->mii_mgmt_cmd);
1402
1403 return status;
1404 }
1405
1406 static void et1310_phy_read_mii_bit(struct et131x_adapter *adapter,
1407 u16 regnum,
1408 u16 bitnum,
1409 u8 *value)
1410 {
1411 u16 reg;
1412 u16 mask = 1 << bitnum;
1413
1414 /* Read the requested register */
1415 et131x_mii_read(adapter, regnum, &reg);
1416
1417 *value = (reg & mask) >> bitnum;
1418 }
1419
1420 static void et1310_config_flow_control(struct et131x_adapter *adapter)
1421 {
1422 struct phy_device *phydev = adapter->phydev;
1423
1424 if (phydev->duplex == DUPLEX_HALF) {
1425 adapter->flowcontrol = FLOW_NONE;
1426 } else {
1427 char remote_pause, remote_async_pause;
1428
1429 et1310_phy_read_mii_bit(adapter, 5, 10, &remote_pause);
1430 et1310_phy_read_mii_bit(adapter, 5, 11, &remote_async_pause);
1431
1432 if (remote_pause && remote_async_pause) {
1433 adapter->flowcontrol = adapter->wanted_flow;
1434 } else if (remote_pause && !remote_async_pause) {
1435 if (adapter->wanted_flow == FLOW_BOTH)
1436 adapter->flowcontrol = FLOW_BOTH;
1437 else
1438 adapter->flowcontrol = FLOW_NONE;
1439 } else if (!remote_pause && !remote_async_pause) {
1440 adapter->flowcontrol = FLOW_NONE;
1441 } else {
1442 if (adapter->wanted_flow == FLOW_BOTH)
1443 adapter->flowcontrol = FLOW_RXONLY;
1444 else
1445 adapter->flowcontrol = FLOW_NONE;
1446 }
1447 }
1448 }
1449
1450 /* et1310_update_macstat_host_counters - Update local copy of the statistics */
1451 static void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
1452 {
1453 struct ce_stats *stats = &adapter->stats;
1454 struct macstat_regs __iomem *macstat =
1455 &adapter->regs->macstat;
1456
1457 stats->tx_collisions += readl(&macstat->tx_total_collisions);
1458 stats->tx_first_collisions += readl(&macstat->tx_single_collisions);
1459 stats->tx_deferred += readl(&macstat->tx_deferred);
1460 stats->tx_excessive_collisions +=
1461 readl(&macstat->tx_multiple_collisions);
1462 stats->tx_late_collisions += readl(&macstat->tx_late_collisions);
1463 stats->tx_underflows += readl(&macstat->tx_undersize_frames);
1464 stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames);
1465
1466 stats->rx_align_errs += readl(&macstat->rx_align_errs);
1467 stats->rx_crc_errs += readl(&macstat->rx_code_errs);
1468 stats->rcvd_pkts_dropped += readl(&macstat->rx_drops);
1469 stats->rx_overflows += readl(&macstat->rx_oversize_packets);
1470 stats->rx_code_violations += readl(&macstat->rx_fcs_errs);
1471 stats->rx_length_errs += readl(&macstat->rx_frame_len_errs);
1472 stats->rx_other_errs += readl(&macstat->rx_fragment_packets);
1473 }
1474
1475 /* et1310_handle_macstat_interrupt
1476 *
1477 * One of the MACSTAT counters has wrapped. Update the local copy of
1478 * the statistics held in the adapter structure, checking the "wrap"
1479 * bit for each counter.
1480 */
1481 static void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter)
1482 {
1483 u32 carry_reg1;
1484 u32 carry_reg2;
1485
1486 /* Read the interrupt bits from the register(s). These are Clear On
1487 * Write.
1488 */
1489 carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);
1490 carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);
1491
1492 writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
1493 writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
1494
1495 /* We need to do update the host copy of all the MAC_STAT counters.
1496 * For each counter, check it's overflow bit. If the overflow bit is
1497 * set, then increment the host version of the count by one complete
1498 * revolution of the counter. This routine is called when the counter
1499 * block indicates that one of the counters has wrapped.
1500 */
1501 if (carry_reg1 & (1 << 14))
1502 adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT;
1503 if (carry_reg1 & (1 << 8))
1504 adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT;
1505 if (carry_reg1 & (1 << 7))
1506 adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT;
1507 if (carry_reg1 & (1 << 2))
1508 adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT;
1509 if (carry_reg1 & (1 << 6))
1510 adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT;
1511 if (carry_reg1 & (1 << 3))
1512 adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT;
1513 if (carry_reg1 & (1 << 0))
1514 adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT;
1515 if (carry_reg2 & (1 << 16))
1516 adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT;
1517 if (carry_reg2 & (1 << 15))
1518 adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT;
1519 if (carry_reg2 & (1 << 6))
1520 adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT;
1521 if (carry_reg2 & (1 << 8))
1522 adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT;
1523 if (carry_reg2 & (1 << 5))
1524 adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT;
1525 if (carry_reg2 & (1 << 4))
1526 adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT;
1527 if (carry_reg2 & (1 << 2))
1528 adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT;
1529 }
1530
1531 static int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
1532 {
1533 struct net_device *netdev = bus->priv;
1534 struct et131x_adapter *adapter = netdev_priv(netdev);
1535 u16 value;
1536 int ret;
1537
1538 ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
1539
1540 if (ret < 0)
1541 return ret;
1542 else
1543 return value;
1544 }
1545
1546 static int et131x_mdio_write(struct mii_bus *bus, int phy_addr,
1547 int reg, u16 value)
1548 {
1549 struct net_device *netdev = bus->priv;
1550 struct et131x_adapter *adapter = netdev_priv(netdev);
1551
1552 return et131x_mii_write(adapter, phy_addr, reg, value);
1553 }
1554
1555 /* et1310_phy_power_switch - PHY power control
1556 * @adapter: device to control
1557 * @down: true for off/false for back on
1558 *
1559 * one hundred, ten, one thousand megs
1560 * How would you like to have your LAN accessed
1561 * Can't you see that this code processed
1562 * Phy power, phy power..
1563 */
1564 static void et1310_phy_power_switch(struct et131x_adapter *adapter, bool down)
1565 {
1566 u16 data;
1567 struct phy_device *phydev = adapter->phydev;
1568
1569 et131x_mii_read(adapter, MII_BMCR, &data);
1570 data &= ~BMCR_PDOWN;
1571 if (down)
1572 data |= BMCR_PDOWN;
1573 et131x_mii_write(adapter, phydev->addr, MII_BMCR, data);
1574 }
1575
1576 /* et131x_xcvr_init - Init the phy if we are setting it into force mode */
1577 static void et131x_xcvr_init(struct et131x_adapter *adapter)
1578 {
1579 u16 lcr2;
1580 struct phy_device *phydev = adapter->phydev;
1581
1582 /* Set the LED behavior such that LED 1 indicates speed (off =
1583 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
1584 * link and activity (on for link, blink off for activity).
1585 *
1586 * NOTE: Some customizations have been added here for specific
1587 * vendors; The LED behavior is now determined by vendor data in the
1588 * EEPROM. However, the above description is the default.
1589 */
1590 if ((adapter->eeprom_data[1] & 0x4) == 0) {
1591 et131x_mii_read(adapter, PHY_LED_2, &lcr2);
1592
1593 lcr2 &= (ET_LED2_LED_100TX | ET_LED2_LED_1000T);
1594 lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
1595
1596 if ((adapter->eeprom_data[1] & 0x8) == 0)
1597 lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
1598 else
1599 lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
1600
1601 et131x_mii_write(adapter, phydev->addr, PHY_LED_2, lcr2);
1602 }
1603 }
1604
1605 /* et131x_configure_global_regs - configure JAGCore global regs
1606 *
1607 * Used to configure the global registers on the JAGCore
1608 */
1609 static void et131x_configure_global_regs(struct et131x_adapter *adapter)
1610 {
1611 struct global_regs __iomem *regs = &adapter->regs->global;
1612
1613 writel(0, &regs->rxq_start_addr);
1614 writel(INTERNAL_MEM_SIZE - 1, &regs->txq_end_addr);
1615
1616 if (adapter->registry_jumbo_packet < 2048) {
1617 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
1618 * block of RAM that the driver can split between Tx
1619 * and Rx as it desires. Our default is to split it
1620 * 50/50:
1621 */
1622 writel(PARM_RX_MEM_END_DEF, &regs->rxq_end_addr);
1623 writel(PARM_RX_MEM_END_DEF + 1, &regs->txq_start_addr);
1624 } else if (adapter->registry_jumbo_packet < 8192) {
1625 /* For jumbo packets > 2k but < 8k, split 50-50. */
1626 writel(INTERNAL_MEM_RX_OFFSET, &regs->rxq_end_addr);
1627 writel(INTERNAL_MEM_RX_OFFSET + 1, &regs->txq_start_addr);
1628 } else {
1629 /* 9216 is the only packet size greater than 8k that
1630 * is available. The Tx buffer has to be big enough
1631 * for one whole packet on the Tx side. We'll make
1632 * the Tx 9408, and give the rest to Rx
1633 */
1634 writel(0x01b3, &regs->rxq_end_addr);
1635 writel(0x01b4, &regs->txq_start_addr);
1636 }
1637
1638 /* Initialize the loopback register. Disable all loopbacks. */
1639 writel(0, &regs->loopback);
1640
1641 /* MSI Register */
1642 writel(0, &regs->msi_config);
1643
1644 /* By default, disable the watchdog timer. It will be enabled when
1645 * a packet is queued.
1646 */
1647 writel(0, &regs->watchdog_timer);
1648 }
1649
1650 /* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence */
1651 static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
1652 {
1653 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
1654 struct rx_ring *rx_local = &adapter->rx_ring;
1655 struct fbr_desc *fbr_entry;
1656 u32 entry;
1657 u32 psr_num_des;
1658 unsigned long flags;
1659 u8 id;
1660
1661 /* Halt RXDMA to perform the reconfigure. */
1662 et131x_rx_dma_disable(adapter);
1663
1664 /* Load the completion writeback physical address */
1665 writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi);
1666 writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo);
1667
1668 memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
1669
1670 /* Set the address and parameters of the packet status ring into the
1671 * 1310's registers
1672 */
1673 writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi);
1674 writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo);
1675 writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des);
1676 writel(0, &rx_dma->psr_full_offset);
1677
1678 psr_num_des = readl(&rx_dma->psr_num_des) & ET_RXDMA_PSR_NUM_DES_MASK;
1679 writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
1680 &rx_dma->psr_min_des);
1681
1682 spin_lock_irqsave(&adapter->rcv_lock, flags);
1683
1684 /* These local variables track the PSR in the adapter structure */
1685 rx_local->local_psr_full = 0;
1686
1687 for (id = 0; id < NUM_FBRS; id++) {
1688 u32 __iomem *num_des;
1689 u32 __iomem *full_offset;
1690 u32 __iomem *min_des;
1691 u32 __iomem *base_hi;
1692 u32 __iomem *base_lo;
1693 struct fbr_lookup *fbr = rx_local->fbr[id];
1694
1695 if (id == 0) {
1696 num_des = &rx_dma->fbr0_num_des;
1697 full_offset = &rx_dma->fbr0_full_offset;
1698 min_des = &rx_dma->fbr0_min_des;
1699 base_hi = &rx_dma->fbr0_base_hi;
1700 base_lo = &rx_dma->fbr0_base_lo;
1701 } else {
1702 num_des = &rx_dma->fbr1_num_des;
1703 full_offset = &rx_dma->fbr1_full_offset;
1704 min_des = &rx_dma->fbr1_min_des;
1705 base_hi = &rx_dma->fbr1_base_hi;
1706 base_lo = &rx_dma->fbr1_base_lo;
1707 }
1708
1709 /* Now's the best time to initialize FBR contents */
1710 fbr_entry = fbr->ring_virtaddr;
1711 for (entry = 0; entry < fbr->num_entries; entry++) {
1712 fbr_entry->addr_hi = fbr->bus_high[entry];
1713 fbr_entry->addr_lo = fbr->bus_low[entry];
1714 fbr_entry->word2 = entry;
1715 fbr_entry++;
1716 }
1717
1718 /* Set the address and parameters of Free buffer ring 1 and 0
1719 * into the 1310's registers
1720 */
1721 writel(upper_32_bits(fbr->ring_physaddr), base_hi);
1722 writel(lower_32_bits(fbr->ring_physaddr), base_lo);
1723 writel(fbr->num_entries - 1, num_des);
1724 writel(ET_DMA10_WRAP, full_offset);
1725
1726 /* This variable tracks the free buffer ring 1 full position,
1727 * so it has to match the above.
1728 */
1729 fbr->local_full = ET_DMA10_WRAP;
1730 writel(((fbr->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
1731 min_des);
1732 }
1733
1734 /* Program the number of packets we will receive before generating an
1735 * interrupt.
1736 * For version B silicon, this value gets updated once autoneg is
1737 *complete.
1738 */
1739 writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
1740
1741 /* The "time_done" is not working correctly to coalesce interrupts
1742 * after a given time period, but rather is giving us an interrupt
1743 * regardless of whether we have received packets.
1744 * This value gets updated once autoneg is complete.
1745 */
1746 writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
1747
1748 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
1749 }
1750
1751 /* et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
1752 *
1753 * Configure the transmit engine with the ring buffers we have created
1754 * and prepare it for use.
1755 */
1756 static void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
1757 {
1758 struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
1759 struct tx_ring *tx_ring = &adapter->tx_ring;
1760
1761 /* Load the hardware with the start of the transmit descriptor ring. */
1762 writel(upper_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_hi);
1763 writel(lower_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_lo);
1764
1765 /* Initialise the transmit DMA engine */
1766 writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
1767
1768 /* Load the completion writeback physical address */
1769 writel(upper_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_hi);
1770 writel(lower_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_lo);
1771
1772 *tx_ring->tx_status = 0;
1773
1774 writel(0, &txdma->service_request);
1775 tx_ring->send_idx = 0;
1776 }
1777
1778 /* et131x_adapter_setup - Set the adapter up as per cassini+ documentation */
1779 static void et131x_adapter_setup(struct et131x_adapter *adapter)
1780 {
1781 /* Configure the JAGCore */
1782 et131x_configure_global_regs(adapter);
1783
1784 et1310_config_mac_regs1(adapter);
1785
1786 /* Configure the MMC registers */
1787 /* All we need to do is initialize the Memory Control Register */
1788 writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
1789
1790 et1310_config_rxmac_regs(adapter);
1791 et1310_config_txmac_regs(adapter);
1792
1793 et131x_config_rx_dma_regs(adapter);
1794 et131x_config_tx_dma_regs(adapter);
1795
1796 et1310_config_macstat_regs(adapter);
1797
1798 et1310_phy_power_switch(adapter, 0);
1799 et131x_xcvr_init(adapter);
1800 }
1801
1802 /* et131x_soft_reset - Issue soft reset to the hardware, complete for ET1310 */
1803 static void et131x_soft_reset(struct et131x_adapter *adapter)
1804 {
1805 u32 reg;
1806
1807 /* Disable MAC Core */
1808 reg = ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
1809 ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
1810 ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
1811 writel(reg, &adapter->regs->mac.cfg1);
1812
1813 reg = ET_RESET_ALL;
1814 writel(reg, &adapter->regs->global.sw_reset);
1815
1816 reg = ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
1817 ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
1818 writel(reg, &adapter->regs->mac.cfg1);
1819 writel(0, &adapter->regs->mac.cfg1);
1820 }
1821
1822 /* et131x_enable_interrupts - enable interrupt
1823 *
1824 * Enable the appropriate interrupts on the ET131x according to our
1825 * configuration
1826 */
1827 static void et131x_enable_interrupts(struct et131x_adapter *adapter)
1828 {
1829 u32 mask;
1830
1831 /* Enable all global interrupts */
1832 if (adapter->flowcontrol == FLOW_TXONLY ||
1833 adapter->flowcontrol == FLOW_BOTH)
1834 mask = INT_MASK_ENABLE;
1835 else
1836 mask = INT_MASK_ENABLE_NO_FLOW;
1837
1838 writel(mask, &adapter->regs->global.int_mask);
1839 }
1840
1841 /* et131x_disable_interrupts - interrupt disable
1842 *
1843 * Block all interrupts from the et131x device at the device itself
1844 */
1845 static void et131x_disable_interrupts(struct et131x_adapter *adapter)
1846 {
1847 /* Disable all global interrupts */
1848 writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
1849 }
1850
1851 /* et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310 */
1852 static void et131x_tx_dma_disable(struct et131x_adapter *adapter)
1853 {
1854 /* Setup the transmit dma configuration register */
1855 writel(ET_TXDMA_CSR_HALT | ET_TXDMA_SNGL_EPKT,
1856 &adapter->regs->txdma.csr);
1857 }
1858
1859 /* et131x_enable_txrx - Enable tx/rx queues */
1860 static void et131x_enable_txrx(struct net_device *netdev)
1861 {
1862 struct et131x_adapter *adapter = netdev_priv(netdev);
1863
1864 /* Enable the Tx and Rx DMA engines (if not already enabled) */
1865 et131x_rx_dma_enable(adapter);
1866 et131x_tx_dma_enable(adapter);
1867
1868 /* Enable device interrupts */
1869 if (adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE)
1870 et131x_enable_interrupts(adapter);
1871
1872 /* We're ready to move some data, so start the queue */
1873 netif_start_queue(netdev);
1874 }
1875
1876 /* et131x_disable_txrx - Disable tx/rx queues */
1877 static void et131x_disable_txrx(struct net_device *netdev)
1878 {
1879 struct et131x_adapter *adapter = netdev_priv(netdev);
1880
1881 /* First thing is to stop the queue */
1882 netif_stop_queue(netdev);
1883
1884 /* Stop the Tx and Rx DMA engines */
1885 et131x_rx_dma_disable(adapter);
1886 et131x_tx_dma_disable(adapter);
1887
1888 /* Disable device interrupts */
1889 et131x_disable_interrupts(adapter);
1890 }
1891
1892 /* et131x_init_send - Initialize send data structures */
1893 static void et131x_init_send(struct et131x_adapter *adapter)
1894 {
1895 u32 ct;
1896 struct tx_ring *tx_ring = &adapter->tx_ring;
1897 struct tcb *tcb = tx_ring->tcb_ring;
1898
1899 tx_ring->tcb_qhead = tcb;
1900
1901 memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
1902
1903 /* Go through and set up each TCB */
1904 for (ct = 0; ct++ < NUM_TCB; tcb++)
1905 /* Set the link pointer in HW TCB to the next TCB in the
1906 * chain
1907 */
1908 tcb->next = tcb + 1;
1909
1910 /* Set the tail pointer */
1911 tcb--;
1912 tx_ring->tcb_qtail = tcb;
1913 tcb->next = NULL;
1914 /* Curr send queue should now be empty */
1915 tx_ring->send_head = NULL;
1916 tx_ring->send_tail = NULL;
1917 }
1918
1919 /* et1310_enable_phy_coma - called when network cable is unplugged
1920 *
1921 * driver receive an phy status change interrupt while in D0 and check that
1922 * phy_status is down.
1923 *
1924 * -- gate off JAGCore;
1925 * -- set gigE PHY in Coma mode
1926 * -- wake on phy_interrupt; Perform software reset JAGCore,
1927 * re-initialize jagcore and gigE PHY
1928 *
1929 * Add D0-ASPM-PhyLinkDown Support:
1930 * -- while in D0, when there is a phy_interrupt indicating phy link
1931 * down status, call the MPSetPhyComa routine to enter this active
1932 * state power saving mode
1933 * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
1934 * indicating linkup status, call the MPDisablePhyComa routine to
1935 * restore JAGCore and gigE PHY
1936 */
1937 static void et1310_enable_phy_coma(struct et131x_adapter *adapter)
1938 {
1939 unsigned long flags;
1940 u32 pmcsr;
1941
1942 pmcsr = readl(&adapter->regs->global.pm_csr);
1943
1944 /* Save the GbE PHY speed and duplex modes. Need to restore this
1945 * when cable is plugged back in
1946 */
1947
1948 /* Stop sending packets. */
1949 spin_lock_irqsave(&adapter->send_hw_lock, flags);
1950 adapter->flags |= FMP_ADAPTER_LOWER_POWER;
1951 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
1952
1953 /* Wait for outstanding Receive packets */
1954
1955 et131x_disable_txrx(adapter->netdev);
1956
1957 /* Gate off JAGCore 3 clock domains */
1958 pmcsr &= ~ET_PMCSR_INIT;
1959 writel(pmcsr, &adapter->regs->global.pm_csr);
1960
1961 /* Program gigE PHY in to Coma mode */
1962 pmcsr |= ET_PM_PHY_SW_COMA;
1963 writel(pmcsr, &adapter->regs->global.pm_csr);
1964 }
1965
1966 /* et1310_disable_phy_coma - Disable the Phy Coma Mode */
1967 static void et1310_disable_phy_coma(struct et131x_adapter *adapter)
1968 {
1969 u32 pmcsr;
1970
1971 pmcsr = readl(&adapter->regs->global.pm_csr);
1972
1973 /* Disable phy_sw_coma register and re-enable JAGCore clocks */
1974 pmcsr |= ET_PMCSR_INIT;
1975 pmcsr &= ~ET_PM_PHY_SW_COMA;
1976 writel(pmcsr, &adapter->regs->global.pm_csr);
1977
1978 /* Restore the GbE PHY speed and duplex modes;
1979 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
1980 */
1981
1982 /* Re-initialize the send structures */
1983 et131x_init_send(adapter);
1984
1985 /* Bring the device back to the state it was during init prior to
1986 * autonegotiation being complete. This way, when we get the auto-neg
1987 * complete interrupt, we can complete init by calling ConfigMacREGS2.
1988 */
1989 et131x_soft_reset(adapter);
1990
1991 /* setup et1310 as per the documentation ?? */
1992 et131x_adapter_setup(adapter);
1993
1994 /* Allow Tx to restart */
1995 adapter->flags &= ~FMP_ADAPTER_LOWER_POWER;
1996
1997 et131x_enable_txrx(adapter->netdev);
1998 }
1999
2000 static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
2001 {
2002 u32 tmp_free_buff_ring = *free_buff_ring;
2003
2004 tmp_free_buff_ring++;
2005 /* This works for all cases where limit < 1024. The 1023 case
2006 * works because 1023++ is 1024 which means the if condition is not
2007 * taken but the carry of the bit into the wrap bit toggles the wrap
2008 * value correctly
2009 */
2010 if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) {
2011 tmp_free_buff_ring &= ~ET_DMA10_MASK;
2012 tmp_free_buff_ring ^= ET_DMA10_WRAP;
2013 }
2014 /* For the 1023 case */
2015 tmp_free_buff_ring &= (ET_DMA10_MASK | ET_DMA10_WRAP);
2016 *free_buff_ring = tmp_free_buff_ring;
2017 return tmp_free_buff_ring;
2018 }
2019
2020 /* et131x_rx_dma_memory_alloc
2021 *
2022 * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
2023 * and the Packet Status Ring.
2024 */
2025 static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
2026 {
2027 u8 id;
2028 u32 i, j;
2029 u32 bufsize;
2030 u32 pktstat_ringsize;
2031 u32 fbr_chunksize;
2032 struct rx_ring *rx_ring = &adapter->rx_ring;
2033 struct fbr_lookup *fbr;
2034
2035 /* Alloc memory for the lookup table */
2036 rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2037 if (rx_ring->fbr[0] == NULL)
2038 return -ENOMEM;
2039 rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2040 if (rx_ring->fbr[1] == NULL)
2041 return -ENOMEM;
2042
2043 /* The first thing we will do is configure the sizes of the buffer
2044 * rings. These will change based on jumbo packet support. Larger
2045 * jumbo packets increases the size of each entry in FBR0, and the
2046 * number of entries in FBR0, while at the same time decreasing the
2047 * number of entries in FBR1.
2048 *
2049 * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
2050 * entries are huge in order to accommodate a "jumbo" frame, then it
2051 * will have less entries. Conversely, FBR1 will now be relied upon
2052 * to carry more "normal" frames, thus it's entry size also increases
2053 * and the number of entries goes up too (since it now carries
2054 * "small" + "regular" packets.
2055 *
2056 * In this scheme, we try to maintain 512 entries between the two
2057 * rings. Also, FBR1 remains a constant size - when it's size doubles
2058 * the number of entries halves. FBR0 increases in size, however.
2059 */
2060
2061 if (adapter->registry_jumbo_packet < 2048) {
2062 rx_ring->fbr[0]->buffsize = 256;
2063 rx_ring->fbr[0]->num_entries = 512;
2064 rx_ring->fbr[1]->buffsize = 2048;
2065 rx_ring->fbr[1]->num_entries = 512;
2066 } else if (adapter->registry_jumbo_packet < 4096) {
2067 rx_ring->fbr[0]->buffsize = 512;
2068 rx_ring->fbr[0]->num_entries = 1024;
2069 rx_ring->fbr[1]->buffsize = 4096;
2070 rx_ring->fbr[1]->num_entries = 512;
2071 } else {
2072 rx_ring->fbr[0]->buffsize = 1024;
2073 rx_ring->fbr[0]->num_entries = 768;
2074 rx_ring->fbr[1]->buffsize = 16384;
2075 rx_ring->fbr[1]->num_entries = 128;
2076 }
2077
2078 rx_ring->psr_num_entries = rx_ring->fbr[0]->num_entries +
2079 rx_ring->fbr[1]->num_entries;
2080
2081 for (id = 0; id < NUM_FBRS; id++) {
2082 fbr = rx_ring->fbr[id];
2083 /* Allocate an area of memory for Free Buffer Ring */
2084 bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
2085 fbr->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2086 bufsize,
2087 &fbr->ring_physaddr,
2088 GFP_KERNEL);
2089 if (!fbr->ring_virtaddr) {
2090 dev_err(&adapter->pdev->dev,
2091 "Cannot alloc memory for Free Buffer Ring %d\n",
2092 id);
2093 return -ENOMEM;
2094 }
2095 }
2096
2097 for (id = 0; id < NUM_FBRS; id++) {
2098 fbr = rx_ring->fbr[id];
2099 fbr_chunksize = (FBR_CHUNKS * fbr->buffsize);
2100
2101 for (i = 0; i < fbr->num_entries / FBR_CHUNKS; i++) {
2102 dma_addr_t fbr_tmp_physaddr;
2103
2104 fbr->mem_virtaddrs[i] = dma_alloc_coherent(
2105 &adapter->pdev->dev, fbr_chunksize,
2106 &fbr->mem_physaddrs[i],
2107 GFP_KERNEL);
2108
2109 if (!fbr->mem_virtaddrs[i]) {
2110 dev_err(&adapter->pdev->dev,
2111 "Could not alloc memory\n");
2112 return -ENOMEM;
2113 }
2114
2115 /* See NOTE in "Save Physical Address" comment above */
2116 fbr_tmp_physaddr = fbr->mem_physaddrs[i];
2117
2118 for (j = 0; j < FBR_CHUNKS; j++) {
2119 u32 index = (i * FBR_CHUNKS) + j;
2120
2121 /* Save the Virtual address of this index for
2122 * quick access later
2123 */
2124 fbr->virt[index] = (u8 *)fbr->mem_virtaddrs[i] +
2125 (j * fbr->buffsize);
2126
2127 /* now store the physical address in the
2128 * descriptor so the device can access it
2129 */
2130 fbr->bus_high[index] =
2131 upper_32_bits(fbr_tmp_physaddr);
2132 fbr->bus_low[index] =
2133 lower_32_bits(fbr_tmp_physaddr);
2134
2135 fbr_tmp_physaddr += fbr->buffsize;
2136 }
2137 }
2138 }
2139
2140 /* Allocate an area of memory for FIFO of Packet Status ring entries */
2141 pktstat_ringsize =
2142 sizeof(struct pkt_stat_desc) * rx_ring->psr_num_entries;
2143
2144 rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2145 pktstat_ringsize,
2146 &rx_ring->ps_ring_physaddr,
2147 GFP_KERNEL);
2148
2149 if (!rx_ring->ps_ring_virtaddr) {
2150 dev_err(&adapter->pdev->dev,
2151 "Cannot alloc memory for Packet Status Ring\n");
2152 return -ENOMEM;
2153 }
2154
2155 /* NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
2156 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2157 * are ever returned, make sure the high part is retrieved here before
2158 * storing the adjusted address.
2159 */
2160
2161 /* Allocate an area of memory for writeback of status information */
2162 rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev,
2163 sizeof(struct rx_status_block),
2164 &rx_ring->rx_status_bus,
2165 GFP_KERNEL);
2166 if (!rx_ring->rx_status_block) {
2167 dev_err(&adapter->pdev->dev,
2168 "Cannot alloc memory for Status Block\n");
2169 return -ENOMEM;
2170 }
2171 rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
2172
2173 /* The RFDs are going to be put on lists later on, so initialize the
2174 * lists now.
2175 */
2176 INIT_LIST_HEAD(&rx_ring->recv_list);
2177 return 0;
2178 }
2179
2180 /* et131x_rx_dma_memory_free - Free all memory allocated within this module */
2181 static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
2182 {
2183 u8 id;
2184 u32 index;
2185 u32 bufsize;
2186 u32 pktstat_ringsize;
2187 struct rfd *rfd;
2188 struct rx_ring *rx_ring = &adapter->rx_ring;
2189 struct fbr_lookup *fbr;
2190
2191 /* Free RFDs and associated packet descriptors */
2192 WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd);
2193
2194 while (!list_empty(&rx_ring->recv_list)) {
2195 rfd = list_entry(rx_ring->recv_list.next,
2196 struct rfd, list_node);
2197
2198 list_del(&rfd->list_node);
2199 rfd->skb = NULL;
2200 kfree(rfd);
2201 }
2202
2203 /* Free Free Buffer Rings */
2204 for (id = 0; id < NUM_FBRS; id++) {
2205 fbr = rx_ring->fbr[id];
2206
2207 if (!fbr || !fbr->ring_virtaddr)
2208 continue;
2209
2210 /* First the packet memory */
2211 for (index = 0;
2212 index < fbr->num_entries / FBR_CHUNKS;
2213 index++) {
2214 if (fbr->mem_virtaddrs[index]) {
2215 bufsize = fbr->buffsize * FBR_CHUNKS;
2216
2217 dma_free_coherent(&adapter->pdev->dev,
2218 bufsize,
2219 fbr->mem_virtaddrs[index],
2220 fbr->mem_physaddrs[index]);
2221
2222 fbr->mem_virtaddrs[index] = NULL;
2223 }
2224 }
2225
2226 bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
2227
2228 dma_free_coherent(&adapter->pdev->dev,
2229 bufsize,
2230 fbr->ring_virtaddr,
2231 fbr->ring_physaddr);
2232
2233 fbr->ring_virtaddr = NULL;
2234 }
2235
2236 /* Free Packet Status Ring */
2237 if (rx_ring->ps_ring_virtaddr) {
2238 pktstat_ringsize = sizeof(struct pkt_stat_desc) *
2239 rx_ring->psr_num_entries;
2240
2241 dma_free_coherent(&adapter->pdev->dev, pktstat_ringsize,
2242 rx_ring->ps_ring_virtaddr,
2243 rx_ring->ps_ring_physaddr);
2244
2245 rx_ring->ps_ring_virtaddr = NULL;
2246 }
2247
2248 /* Free area of memory for the writeback of status information */
2249 if (rx_ring->rx_status_block) {
2250 dma_free_coherent(&adapter->pdev->dev,
2251 sizeof(struct rx_status_block),
2252 rx_ring->rx_status_block,
2253 rx_ring->rx_status_bus);
2254 rx_ring->rx_status_block = NULL;
2255 }
2256
2257 /* Free the FBR Lookup Table */
2258 kfree(rx_ring->fbr[0]);
2259 kfree(rx_ring->fbr[1]);
2260
2261 /* Reset Counters */
2262 rx_ring->num_ready_recv = 0;
2263 }
2264
2265 /* et131x_init_recv - Initialize receive data structures */
2266 static int et131x_init_recv(struct et131x_adapter *adapter)
2267 {
2268 struct rfd *rfd;
2269 u32 rfdct;
2270 struct rx_ring *rx_ring = &adapter->rx_ring;
2271
2272 /* Setup each RFD */
2273 for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) {
2274 rfd = kzalloc(sizeof(struct rfd), GFP_ATOMIC | GFP_DMA);
2275 if (!rfd)
2276 return -ENOMEM;
2277
2278 rfd->skb = NULL;
2279
2280 /* Add this RFD to the recv_list */
2281 list_add_tail(&rfd->list_node, &rx_ring->recv_list);
2282
2283 /* Increment the available RFD's */
2284 rx_ring->num_ready_recv++;
2285 }
2286
2287 return 0;
2288 }
2289
2290 /* et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate */
2291 static void et131x_set_rx_dma_timer(struct et131x_adapter *adapter)
2292 {
2293 struct phy_device *phydev = adapter->phydev;
2294
2295 /* For version B silicon, we do not use the RxDMA timer for 10 and 100
2296 * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
2297 */
2298 if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) {
2299 writel(0, &adapter->regs->rxdma.max_pkt_time);
2300 writel(1, &adapter->regs->rxdma.num_pkt_done);
2301 }
2302 }
2303
2304 /* NICReturnRFD - Recycle a RFD and put it back onto the receive list
2305 * @adapter: pointer to our adapter
2306 * @rfd: pointer to the RFD
2307 */
2308 static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
2309 {
2310 struct rx_ring *rx_local = &adapter->rx_ring;
2311 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
2312 u16 buff_index = rfd->bufferindex;
2313 u8 ring_index = rfd->ringindex;
2314 unsigned long flags;
2315 struct fbr_lookup *fbr = rx_local->fbr[ring_index];
2316
2317 /* We don't use any of the OOB data besides status. Otherwise, we
2318 * need to clean up OOB data
2319 */
2320 if (buff_index < fbr->num_entries) {
2321 u32 free_buff_ring;
2322 u32 __iomem *offset;
2323 struct fbr_desc *next;
2324
2325 if (ring_index == 0)
2326 offset = &rx_dma->fbr0_full_offset;
2327 else
2328 offset = &rx_dma->fbr1_full_offset;
2329
2330 next = (struct fbr_desc *)(fbr->ring_virtaddr) +
2331 INDEX10(fbr->local_full);
2332
2333 /* Handle the Free Buffer Ring advancement here. Write
2334 * the PA / Buffer Index for the returned buffer into
2335 * the oldest (next to be freed)FBR entry
2336 */
2337 next->addr_hi = fbr->bus_high[buff_index];
2338 next->addr_lo = fbr->bus_low[buff_index];
2339 next->word2 = buff_index;
2340
2341 free_buff_ring = bump_free_buff_ring(&fbr->local_full,
2342 fbr->num_entries - 1);
2343 writel(free_buff_ring, offset);
2344 } else {
2345 dev_err(&adapter->pdev->dev,
2346 "%s illegal Buffer Index returned\n", __func__);
2347 }
2348
2349 /* The processing on this RFD is done, so put it back on the tail of
2350 * our list
2351 */
2352 spin_lock_irqsave(&adapter->rcv_lock, flags);
2353 list_add_tail(&rfd->list_node, &rx_local->recv_list);
2354 rx_local->num_ready_recv++;
2355 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2356
2357 WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd);
2358 }
2359
2360 /* nic_rx_pkts - Checks the hardware for available packets
2361 *
2362 * Returns rfd, a pointer to our MPRFD.
2363 *
2364 * Checks the hardware for available packets, using completion ring
2365 * If packets are available, it gets an RFD from the recv_list, attaches
2366 * the packet to it, puts the RFD in the RecvPendList, and also returns
2367 * the pointer to the RFD.
2368 */
2369 static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
2370 {
2371 struct rx_ring *rx_local = &adapter->rx_ring;
2372 struct rx_status_block *status;
2373 struct pkt_stat_desc *psr;
2374 struct rfd *rfd;
2375 u32 i;
2376 u8 *buf;
2377 unsigned long flags;
2378 struct list_head *element;
2379 u8 ring_index;
2380 u16 buff_index;
2381 u32 len;
2382 u32 word0;
2383 u32 word1;
2384 struct sk_buff *skb;
2385 struct fbr_lookup *fbr;
2386
2387 /* RX Status block is written by the DMA engine prior to every
2388 * interrupt. It contains the next to be used entry in the Packet
2389 * Status Ring, and also the two Free Buffer rings.
2390 */
2391 status = rx_local->rx_status_block;
2392 word1 = status->word1 >> 16; /* Get the useful bits */
2393
2394 /* Check the PSR and wrap bits do not match */
2395 if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
2396 return NULL; /* Looks like this ring is not updated yet */
2397
2398 /* The packet status ring indicates that data is available. */
2399 psr = (struct pkt_stat_desc *) (rx_local->ps_ring_virtaddr) +
2400 (rx_local->local_psr_full & 0xFFF);
2401
2402 /* Grab any information that is required once the PSR is advanced,
2403 * since we can no longer rely on the memory being accurate
2404 */
2405 len = psr->word1 & 0xFFFF;
2406 ring_index = (psr->word1 >> 26) & 0x03;
2407 fbr = rx_local->fbr[ring_index];
2408 buff_index = (psr->word1 >> 16) & 0x3FF;
2409 word0 = psr->word0;
2410
2411 /* Indicate that we have used this PSR entry. */
2412 /* FIXME wrap 12 */
2413 add_12bit(&rx_local->local_psr_full, 1);
2414 if (
2415 (rx_local->local_psr_full & 0xFFF) > rx_local->psr_num_entries - 1) {
2416 /* Clear psr full and toggle the wrap bit */
2417 rx_local->local_psr_full &= ~0xFFF;
2418 rx_local->local_psr_full ^= 0x1000;
2419 }
2420
2421 writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset);
2422
2423 if (ring_index > 1 || buff_index > fbr->num_entries - 1) {
2424 /* Illegal buffer or ring index cannot be used by S/W*/
2425 dev_err(&adapter->pdev->dev,
2426 "NICRxPkts PSR Entry %d indicates length of %d and/or bad bi(%d)\n",
2427 rx_local->local_psr_full & 0xFFF, len, buff_index);
2428 return NULL;
2429 }
2430
2431 /* Get and fill the RFD. */
2432 spin_lock_irqsave(&adapter->rcv_lock, flags);
2433
2434 element = rx_local->recv_list.next;
2435 rfd = list_entry(element, struct rfd, list_node);
2436
2437 if (!rfd) {
2438 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2439 return NULL;
2440 }
2441
2442 list_del(&rfd->list_node);
2443 rx_local->num_ready_recv--;
2444
2445 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2446
2447 rfd->bufferindex = buff_index;
2448 rfd->ringindex = ring_index;
2449
2450 /* In V1 silicon, there is a bug which screws up filtering of runt
2451 * packets. Therefore runt packet filtering is disabled in the MAC and
2452 * the packets are dropped here. They are also counted here.
2453 */
2454 if (len < (NIC_MIN_PACKET_SIZE + 4)) {
2455 adapter->stats.rx_other_errs++;
2456 len = 0;
2457 }
2458
2459 if (len == 0) {
2460 rfd->len = 0;
2461 goto out;
2462 }
2463
2464 /* Determine if this is a multicast packet coming in */
2465 if ((word0 & ALCATEL_MULTICAST_PKT) &&
2466 !(word0 & ALCATEL_BROADCAST_PKT)) {
2467 /* Promiscuous mode and Multicast mode are not mutually
2468 * exclusive as was first thought. I guess Promiscuous is just
2469 * considered a super-set of the other filters. Generally filter
2470 * is 0x2b when in promiscuous mode.
2471 */
2472 if ((adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST)
2473 && !(adapter->packet_filter & ET131X_PACKET_TYPE_PROMISCUOUS)
2474 && !(adapter->packet_filter &
2475 ET131X_PACKET_TYPE_ALL_MULTICAST)) {
2476 buf = fbr->virt[buff_index];
2477
2478 /* Loop through our list to see if the destination
2479 * address of this packet matches one in our list.
2480 */
2481 for (i = 0; i < adapter->multicast_addr_count; i++) {
2482 if (buf[0] == adapter->multicast_list[i][0]
2483 && buf[1] == adapter->multicast_list[i][1]
2484 && buf[2] == adapter->multicast_list[i][2]
2485 && buf[3] == adapter->multicast_list[i][3]
2486 && buf[4] == adapter->multicast_list[i][4]
2487 && buf[5] == adapter->multicast_list[i][5]) {
2488 break;
2489 }
2490 }
2491
2492 /* If our index is equal to the number of Multicast
2493 * address we have, then this means we did not find this
2494 * packet's matching address in our list. Set the len to
2495 * zero, so we free our RFD when we return from this
2496 * function.
2497 */
2498 if (i == adapter->multicast_addr_count)
2499 len = 0;
2500 }
2501
2502 if (len > 0)
2503 adapter->stats.multicast_pkts_rcvd++;
2504 }
2505
2506 if (!len) {
2507 rfd->len = 0;
2508 goto out;
2509 }
2510
2511 rfd->len = len;
2512
2513 skb = dev_alloc_skb(rfd->len + 2);
2514 if (!skb) {
2515 dev_err(&adapter->pdev->dev, "Couldn't alloc an SKB for Rx\n");
2516 return NULL;
2517 }
2518
2519 adapter->netdev->stats.rx_bytes += rfd->len;
2520
2521 memcpy(skb_put(skb, rfd->len), fbr->virt[buff_index], rfd->len);
2522
2523 skb->protocol = eth_type_trans(skb, adapter->netdev);
2524 skb->ip_summed = CHECKSUM_NONE;
2525 netif_receive_skb(skb);
2526
2527 out:
2528 nic_return_rfd(adapter, rfd);
2529 return rfd;
2530 }
2531
2532 /* et131x_handle_recv_pkts - Interrupt handler for receive processing
2533 *
2534 * Assumption, Rcv spinlock has been acquired.
2535 */
2536 static int et131x_handle_recv_pkts(struct et131x_adapter *adapter, int budget)
2537 {
2538 struct rfd *rfd = NULL;
2539 int count = 0;
2540 int limit = budget;
2541 bool done = true;
2542 struct rx_ring *rx_ring = &adapter->rx_ring;
2543
2544 if (budget > MAX_PACKETS_HANDLED)
2545 limit = MAX_PACKETS_HANDLED;
2546
2547 /* Process up to available RFD's */
2548 while (count < limit) {
2549 if (list_empty(&rx_ring->recv_list)) {
2550 WARN_ON(rx_ring->num_ready_recv != 0);
2551 done = false;
2552 break;
2553 }
2554
2555 rfd = nic_rx_pkts(adapter);
2556
2557 if (rfd == NULL)
2558 break;
2559
2560 /* Do not receive any packets until a filter has been set.
2561 * Do not receive any packets until we have link.
2562 * If length is zero, return the RFD in order to advance the
2563 * Free buffer ring.
2564 */
2565 if (!adapter->packet_filter ||
2566 !netif_carrier_ok(adapter->netdev) ||
2567 rfd->len == 0)
2568 continue;
2569
2570 /* Increment the number of packets we received */
2571 adapter->netdev->stats.rx_packets++;
2572
2573 /* Set the status on the packet, either resources or success */
2574 if (rx_ring->num_ready_recv < RFD_LOW_WATER_MARK)
2575 dev_warn(&adapter->pdev->dev, "RFD's are running out\n");
2576
2577 count++;
2578 }
2579
2580 if (count == limit || !done) {
2581 rx_ring->unfinished_receives = true;
2582 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2583 &adapter->regs->global.watchdog_timer);
2584 } else
2585 /* Watchdog timer will disable itself if appropriate. */
2586 rx_ring->unfinished_receives = false;
2587
2588 return count;
2589 }
2590
2591 /* et131x_tx_dma_memory_alloc
2592 *
2593 * Allocates memory that will be visible both to the device and to the CPU.
2594 * The OS will pass us packets, pointers to which we will insert in the Tx
2595 * Descriptor queue. The device will read this queue to find the packets in
2596 * memory. The device will update the "status" in memory each time it xmits a
2597 * packet.
2598 */
2599 static int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
2600 {
2601 int desc_size = 0;
2602 struct tx_ring *tx_ring = &adapter->tx_ring;
2603
2604 /* Allocate memory for the TCB's (Transmit Control Block) */
2605 tx_ring->tcb_ring = kcalloc(NUM_TCB, sizeof(struct tcb),
2606 GFP_ATOMIC | GFP_DMA);
2607 if (!tx_ring->tcb_ring)
2608 return -ENOMEM;
2609
2610 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
2611 tx_ring->tx_desc_ring = dma_alloc_coherent(&adapter->pdev->dev,
2612 desc_size,
2613 &tx_ring->tx_desc_ring_pa,
2614 GFP_KERNEL);
2615 if (!tx_ring->tx_desc_ring) {
2616 dev_err(&adapter->pdev->dev,
2617 "Cannot alloc memory for Tx Ring\n");
2618 return -ENOMEM;
2619 }
2620
2621 /* Save physical address
2622 *
2623 * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
2624 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2625 * are ever returned, make sure the high part is retrieved here before
2626 * storing the adjusted address.
2627 */
2628 /* Allocate memory for the Tx status block */
2629 tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev,
2630 sizeof(u32),
2631 &tx_ring->tx_status_pa,
2632 GFP_KERNEL);
2633 if (!tx_ring->tx_status_pa) {
2634 dev_err(&adapter->pdev->dev,
2635 "Cannot alloc memory for Tx status block\n");
2636 return -ENOMEM;
2637 }
2638 return 0;
2639 }
2640
2641 /* et131x_tx_dma_memory_free - Free all memory allocated within this module */
2642 static void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
2643 {
2644 int desc_size = 0;
2645 struct tx_ring *tx_ring = &adapter->tx_ring;
2646
2647 if (tx_ring->tx_desc_ring) {
2648 /* Free memory relating to Tx rings here */
2649 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
2650 dma_free_coherent(&adapter->pdev->dev,
2651 desc_size,
2652 tx_ring->tx_desc_ring,
2653 tx_ring->tx_desc_ring_pa);
2654 tx_ring->tx_desc_ring = NULL;
2655 }
2656
2657 /* Free memory for the Tx status block */
2658 if (tx_ring->tx_status) {
2659 dma_free_coherent(&adapter->pdev->dev,
2660 sizeof(u32),
2661 tx_ring->tx_status,
2662 tx_ring->tx_status_pa);
2663
2664 tx_ring->tx_status = NULL;
2665 }
2666 /* Free the memory for the tcb structures */
2667 kfree(tx_ring->tcb_ring);
2668 }
2669
2670 /* nic_send_packet - NIC specific send handler for version B silicon.
2671 * @adapter: pointer to our adapter
2672 * @tcb: pointer to struct tcb
2673 */
2674 static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
2675 {
2676 u32 i;
2677 struct tx_desc desc[24]; /* 24 x 16 byte */
2678 u32 frag = 0;
2679 u32 thiscopy, remainder;
2680 struct sk_buff *skb = tcb->skb;
2681 u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
2682 struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
2683 unsigned long flags;
2684 struct phy_device *phydev = adapter->phydev;
2685 dma_addr_t dma_addr;
2686 struct tx_ring *tx_ring = &adapter->tx_ring;
2687
2688 /* Part of the optimizations of this send routine restrict us to
2689 * sending 24 fragments at a pass. In practice we should never see
2690 * more than 5 fragments.
2691 *
2692 * NOTE: The older version of this function (below) can handle any
2693 * number of fragments. If needed, we can call this function,
2694 * although it is less efficient.
2695 */
2696
2697 /* nr_frags should be no more than 18. */
2698 BUILD_BUG_ON(MAX_SKB_FRAGS + 1 > 23);
2699
2700 memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
2701
2702 for (i = 0; i < nr_frags; i++) {
2703 /* If there is something in this element, lets get a
2704 * descriptor from the ring and get the necessary data
2705 */
2706 if (i == 0) {
2707 /* If the fragments are smaller than a standard MTU,
2708 * then map them to a single descriptor in the Tx
2709 * Desc ring. However, if they're larger, as is
2710 * possible with support for jumbo packets, then
2711 * split them each across 2 descriptors.
2712 *
2713 * This will work until we determine why the hardware
2714 * doesn't seem to like large fragments.
2715 */
2716 if (skb_headlen(skb) <= 1514) {
2717 /* Low 16bits are length, high is vlan and
2718 * unused currently so zero
2719 */
2720 desc[frag].len_vlan = skb_headlen(skb);
2721 dma_addr = dma_map_single(&adapter->pdev->dev,
2722 skb->data,
2723 skb_headlen(skb),
2724 DMA_TO_DEVICE);
2725 desc[frag].addr_lo = lower_32_bits(dma_addr);
2726 desc[frag].addr_hi = upper_32_bits(dma_addr);
2727 frag++;
2728 } else {
2729 desc[frag].len_vlan = skb_headlen(skb) / 2;
2730 dma_addr = dma_map_single(&adapter->pdev->dev,
2731 skb->data,
2732 (skb_headlen(skb) / 2),
2733 DMA_TO_DEVICE);
2734 desc[frag].addr_lo = lower_32_bits(dma_addr);
2735 desc[frag].addr_hi = upper_32_bits(dma_addr);
2736 frag++;
2737
2738 desc[frag].len_vlan = skb_headlen(skb) / 2;
2739 dma_addr = dma_map_single(&adapter->pdev->dev,
2740 skb->data +
2741 (skb_headlen(skb) / 2),
2742 (skb_headlen(skb) / 2),
2743 DMA_TO_DEVICE);
2744 desc[frag].addr_lo = lower_32_bits(dma_addr);
2745 desc[frag].addr_hi = upper_32_bits(dma_addr);
2746 frag++;
2747 }
2748 } else {
2749 desc[frag].len_vlan = frags[i - 1].size;
2750 dma_addr = skb_frag_dma_map(&adapter->pdev->dev,
2751 &frags[i - 1],
2752 0,
2753 frags[i - 1].size,
2754 DMA_TO_DEVICE);
2755 desc[frag].addr_lo = lower_32_bits(dma_addr);
2756 desc[frag].addr_hi = upper_32_bits(dma_addr);
2757 frag++;
2758 }
2759 }
2760
2761 if (phydev && phydev->speed == SPEED_1000) {
2762 if (++tx_ring->since_irq == PARM_TX_NUM_BUFS_DEF) {
2763 /* Last element & Interrupt flag */
2764 desc[frag - 1].flags =
2765 TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
2766 tx_ring->since_irq = 0;
2767 } else { /* Last element */
2768 desc[frag - 1].flags = TXDESC_FLAG_LASTPKT;
2769 }
2770 } else
2771 desc[frag - 1].flags =
2772 TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
2773
2774 desc[0].flags |= TXDESC_FLAG_FIRSTPKT;
2775
2776 tcb->index_start = tx_ring->send_idx;
2777 tcb->stale = 0;
2778
2779 spin_lock_irqsave(&adapter->send_hw_lock, flags);
2780
2781 thiscopy = NUM_DESC_PER_RING_TX - INDEX10(tx_ring->send_idx);
2782
2783 if (thiscopy >= frag) {
2784 remainder = 0;
2785 thiscopy = frag;
2786 } else {
2787 remainder = frag - thiscopy;
2788 }
2789
2790 memcpy(tx_ring->tx_desc_ring + INDEX10(tx_ring->send_idx),
2791 desc,
2792 sizeof(struct tx_desc) * thiscopy);
2793
2794 add_10bit(&tx_ring->send_idx, thiscopy);
2795
2796 if (INDEX10(tx_ring->send_idx) == 0 ||
2797 INDEX10(tx_ring->send_idx) == NUM_DESC_PER_RING_TX) {
2798 tx_ring->send_idx &= ~ET_DMA10_MASK;
2799 tx_ring->send_idx ^= ET_DMA10_WRAP;
2800 }
2801
2802 if (remainder) {
2803 memcpy(tx_ring->tx_desc_ring,
2804 desc + thiscopy,
2805 sizeof(struct tx_desc) * remainder);
2806
2807 add_10bit(&tx_ring->send_idx, remainder);
2808 }
2809
2810 if (INDEX10(tx_ring->send_idx) == 0) {
2811 if (tx_ring->send_idx)
2812 tcb->index = NUM_DESC_PER_RING_TX - 1;
2813 else
2814 tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
2815 } else
2816 tcb->index = tx_ring->send_idx - 1;
2817
2818 spin_lock(&adapter->tcb_send_qlock);
2819
2820 if (tx_ring->send_tail)
2821 tx_ring->send_tail->next = tcb;
2822 else
2823 tx_ring->send_head = tcb;
2824
2825 tx_ring->send_tail = tcb;
2826
2827 WARN_ON(tcb->next != NULL);
2828
2829 tx_ring->used++;
2830
2831 spin_unlock(&adapter->tcb_send_qlock);
2832
2833 /* Write the new write pointer back to the device. */
2834 writel(tx_ring->send_idx, &adapter->regs->txdma.service_request);
2835
2836 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
2837 * timer to wake us up if this packet isn't followed by N more.
2838 */
2839 if (phydev && phydev->speed == SPEED_1000) {
2840 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2841 &adapter->regs->global.watchdog_timer);
2842 }
2843 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
2844
2845 return 0;
2846 }
2847
2848 /* send_packet - Do the work to send a packet
2849 *
2850 * Assumption: Send spinlock has been acquired
2851 */
2852 static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
2853 {
2854 int status;
2855 struct tcb *tcb;
2856 unsigned long flags;
2857 struct tx_ring *tx_ring = &adapter->tx_ring;
2858
2859 /* All packets must have at least a MAC address and a protocol type */
2860 if (skb->len < ETH_HLEN)
2861 return -EIO;
2862
2863 /* Get a TCB for this packet */
2864 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
2865
2866 tcb = tx_ring->tcb_qhead;
2867
2868 if (tcb == NULL) {
2869 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2870 return -ENOMEM;
2871 }
2872
2873 tx_ring->tcb_qhead = tcb->next;
2874
2875 if (tx_ring->tcb_qhead == NULL)
2876 tx_ring->tcb_qtail = NULL;
2877
2878 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2879
2880 tcb->skb = skb;
2881 tcb->next = NULL;
2882
2883 /* Call the NIC specific send handler. */
2884 status = nic_send_packet(adapter, tcb);
2885
2886 if (status != 0) {
2887 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
2888
2889 if (tx_ring->tcb_qtail)
2890 tx_ring->tcb_qtail->next = tcb;
2891 else
2892 /* Apparently ready Q is empty. */
2893 tx_ring->tcb_qhead = tcb;
2894
2895 tx_ring->tcb_qtail = tcb;
2896 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2897 return status;
2898 }
2899 WARN_ON(tx_ring->used > NUM_TCB);
2900 return 0;
2901 }
2902
2903 /* free_send_packet - Recycle a struct tcb
2904 * @adapter: pointer to our adapter
2905 * @tcb: pointer to struct tcb
2906 *
2907 * Complete the packet if necessary
2908 * Assumption - Send spinlock has been acquired
2909 */
2910 static inline void free_send_packet(struct et131x_adapter *adapter,
2911 struct tcb *tcb)
2912 {
2913 unsigned long flags;
2914 struct tx_desc *desc = NULL;
2915 struct net_device_stats *stats = &adapter->netdev->stats;
2916 struct tx_ring *tx_ring = &adapter->tx_ring;
2917 u64 dma_addr;
2918
2919 if (tcb->skb) {
2920 stats->tx_bytes += tcb->skb->len;
2921
2922 /* Iterate through the TX descriptors on the ring
2923 * corresponding to this packet and umap the fragments
2924 * they point to
2925 */
2926 do {
2927 desc = tx_ring->tx_desc_ring +
2928 INDEX10(tcb->index_start);
2929
2930 dma_addr = desc->addr_lo;
2931 dma_addr |= (u64)desc->addr_hi << 32;
2932
2933 dma_unmap_single(&adapter->pdev->dev,
2934 dma_addr,
2935 desc->len_vlan, DMA_TO_DEVICE);
2936
2937 add_10bit(&tcb->index_start, 1);
2938 if (INDEX10(tcb->index_start) >=
2939 NUM_DESC_PER_RING_TX) {
2940 tcb->index_start &= ~ET_DMA10_MASK;
2941 tcb->index_start ^= ET_DMA10_WRAP;
2942 }
2943 } while (desc != tx_ring->tx_desc_ring + INDEX10(tcb->index));
2944
2945 dev_kfree_skb_any(tcb->skb);
2946 }
2947
2948 memset(tcb, 0, sizeof(struct tcb));
2949
2950 /* Add the TCB to the Ready Q */
2951 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
2952
2953 stats->tx_packets++;
2954
2955 if (tx_ring->tcb_qtail)
2956 tx_ring->tcb_qtail->next = tcb;
2957 else
2958 /* Apparently ready Q is empty. */
2959 tx_ring->tcb_qhead = tcb;
2960
2961 tx_ring->tcb_qtail = tcb;
2962
2963 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2964 WARN_ON(tx_ring->used < 0);
2965 }
2966
2967 /* et131x_free_busy_send_packets - Free and complete the stopped active sends
2968 *
2969 * Assumption - Send spinlock has been acquired
2970 */
2971 static void et131x_free_busy_send_packets(struct et131x_adapter *adapter)
2972 {
2973 struct tcb *tcb;
2974 unsigned long flags;
2975 u32 freed = 0;
2976 struct tx_ring *tx_ring = &adapter->tx_ring;
2977
2978 /* Any packets being sent? Check the first TCB on the send list */
2979 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
2980
2981 tcb = tx_ring->send_head;
2982
2983 while (tcb != NULL && freed < NUM_TCB) {
2984 struct tcb *next = tcb->next;
2985
2986 tx_ring->send_head = next;
2987
2988 if (next == NULL)
2989 tx_ring->send_tail = NULL;
2990
2991 tx_ring->used--;
2992
2993 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
2994
2995 freed++;
2996 free_send_packet(adapter, tcb);
2997
2998 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
2999
3000 tcb = tx_ring->send_head;
3001 }
3002
3003 WARN_ON(freed == NUM_TCB);
3004
3005 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3006
3007 tx_ring->used = 0;
3008 }
3009
3010 /* et131x_handle_send_pkts - Interrupt handler for sending processing
3011 *
3012 * Re-claim the send resources, complete sends and get more to send from
3013 * the send wait queue.
3014 *
3015 * Assumption - Send spinlock has been acquired
3016 */
3017 static void et131x_handle_send_pkts(struct et131x_adapter *adapter)
3018 {
3019 unsigned long flags;
3020 u32 serviced;
3021 struct tcb *tcb;
3022 u32 index;
3023 struct tx_ring *tx_ring = &adapter->tx_ring;
3024
3025 serviced = readl(&adapter->regs->txdma.new_service_complete);
3026 index = INDEX10(serviced);
3027
3028 /* Has the ring wrapped? Process any descriptors that do not have
3029 * the same "wrap" indicator as the current completion indicator
3030 */
3031 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3032
3033 tcb = tx_ring->send_head;
3034
3035 while (tcb &&
3036 ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
3037 index < INDEX10(tcb->index)) {
3038 tx_ring->used--;
3039 tx_ring->send_head = tcb->next;
3040 if (tcb->next == NULL)
3041 tx_ring->send_tail = NULL;
3042
3043 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3044 free_send_packet(adapter, tcb);
3045 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3046
3047 /* Goto the next packet */
3048 tcb = tx_ring->send_head;
3049 }
3050 while (tcb &&
3051 !((serviced ^ tcb->index) & ET_DMA10_WRAP)
3052 && index > (tcb->index & ET_DMA10_MASK)) {
3053 tx_ring->used--;
3054 tx_ring->send_head = tcb->next;
3055 if (tcb->next == NULL)
3056 tx_ring->send_tail = NULL;
3057
3058 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3059 free_send_packet(adapter, tcb);
3060 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3061
3062 /* Goto the next packet */
3063 tcb = tx_ring->send_head;
3064 }
3065
3066 /* Wake up the queue when we hit a low-water mark */
3067 if (tx_ring->used <= NUM_TCB / 3)
3068 netif_wake_queue(adapter->netdev);
3069
3070 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3071 }
3072
3073 static int et131x_get_settings(struct net_device *netdev,
3074 struct ethtool_cmd *cmd)
3075 {
3076 struct et131x_adapter *adapter = netdev_priv(netdev);
3077
3078 return phy_ethtool_gset(adapter->phydev, cmd);
3079 }
3080
3081 static int et131x_set_settings(struct net_device *netdev,
3082 struct ethtool_cmd *cmd)
3083 {
3084 struct et131x_adapter *adapter = netdev_priv(netdev);
3085
3086 return phy_ethtool_sset(adapter->phydev, cmd);
3087 }
3088
3089 static int et131x_get_regs_len(struct net_device *netdev)
3090 {
3091 #define ET131X_REGS_LEN 256
3092 return ET131X_REGS_LEN * sizeof(u32);
3093 }
3094
3095 static void et131x_get_regs(struct net_device *netdev,
3096 struct ethtool_regs *regs, void *regs_data)
3097 {
3098 struct et131x_adapter *adapter = netdev_priv(netdev);
3099 struct address_map __iomem *aregs = adapter->regs;
3100 u32 *regs_buff = regs_data;
3101 u32 num = 0;
3102 u16 tmp;
3103
3104 memset(regs_data, 0, et131x_get_regs_len(netdev));
3105
3106 regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
3107 adapter->pdev->device;
3108
3109 /* PHY regs */
3110 et131x_mii_read(adapter, MII_BMCR, &tmp);
3111 regs_buff[num++] = tmp;
3112 et131x_mii_read(adapter, MII_BMSR, &tmp);
3113 regs_buff[num++] = tmp;
3114 et131x_mii_read(adapter, MII_PHYSID1, &tmp);
3115 regs_buff[num++] = tmp;
3116 et131x_mii_read(adapter, MII_PHYSID2, &tmp);
3117 regs_buff[num++] = tmp;
3118 et131x_mii_read(adapter, MII_ADVERTISE, &tmp);
3119 regs_buff[num++] = tmp;
3120 et131x_mii_read(adapter, MII_LPA, &tmp);
3121 regs_buff[num++] = tmp;
3122 et131x_mii_read(adapter, MII_EXPANSION, &tmp);
3123 regs_buff[num++] = tmp;
3124 /* Autoneg next page transmit reg */
3125 et131x_mii_read(adapter, 0x07, &tmp);
3126 regs_buff[num++] = tmp;
3127 /* Link partner next page reg */
3128 et131x_mii_read(adapter, 0x08, &tmp);
3129 regs_buff[num++] = tmp;
3130 et131x_mii_read(adapter, MII_CTRL1000, &tmp);
3131 regs_buff[num++] = tmp;
3132 et131x_mii_read(adapter, MII_STAT1000, &tmp);
3133 regs_buff[num++] = tmp;
3134 et131x_mii_read(adapter, 0x0b, &tmp);
3135 regs_buff[num++] = tmp;
3136 et131x_mii_read(adapter, 0x0c, &tmp);
3137 regs_buff[num++] = tmp;
3138 et131x_mii_read(adapter, MII_MMD_CTRL, &tmp);
3139 regs_buff[num++] = tmp;
3140 et131x_mii_read(adapter, MII_MMD_DATA, &tmp);
3141 regs_buff[num++] = tmp;
3142 et131x_mii_read(adapter, MII_ESTATUS, &tmp);
3143 regs_buff[num++] = tmp;
3144
3145 et131x_mii_read(adapter, PHY_INDEX_REG, &tmp);
3146 regs_buff[num++] = tmp;
3147 et131x_mii_read(adapter, PHY_DATA_REG, &tmp);
3148 regs_buff[num++] = tmp;
3149 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, &tmp);
3150 regs_buff[num++] = tmp;
3151 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL, &tmp);
3152 regs_buff[num++] = tmp;
3153 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL + 1, &tmp);
3154 regs_buff[num++] = tmp;
3155
3156 et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL, &tmp);
3157 regs_buff[num++] = tmp;
3158 et131x_mii_read(adapter, PHY_CONFIG, &tmp);
3159 regs_buff[num++] = tmp;
3160 et131x_mii_read(adapter, PHY_PHY_CONTROL, &tmp);
3161 regs_buff[num++] = tmp;
3162 et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &tmp);
3163 regs_buff[num++] = tmp;
3164 et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &tmp);
3165 regs_buff[num++] = tmp;
3166 et131x_mii_read(adapter, PHY_PHY_STATUS, &tmp);
3167 regs_buff[num++] = tmp;
3168 et131x_mii_read(adapter, PHY_LED_1, &tmp);
3169 regs_buff[num++] = tmp;
3170 et131x_mii_read(adapter, PHY_LED_2, &tmp);
3171 regs_buff[num++] = tmp;
3172
3173 /* Global regs */
3174 regs_buff[num++] = readl(&aregs->global.txq_start_addr);
3175 regs_buff[num++] = readl(&aregs->global.txq_end_addr);
3176 regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
3177 regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
3178 regs_buff[num++] = readl(&aregs->global.pm_csr);
3179 regs_buff[num++] = adapter->stats.interrupt_status;
3180 regs_buff[num++] = readl(&aregs->global.int_mask);
3181 regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
3182 regs_buff[num++] = readl(&aregs->global.int_status_alias);
3183 regs_buff[num++] = readl(&aregs->global.sw_reset);
3184 regs_buff[num++] = readl(&aregs->global.slv_timer);
3185 regs_buff[num++] = readl(&aregs->global.msi_config);
3186 regs_buff[num++] = readl(&aregs->global.loopback);
3187 regs_buff[num++] = readl(&aregs->global.watchdog_timer);
3188
3189 /* TXDMA regs */
3190 regs_buff[num++] = readl(&aregs->txdma.csr);
3191 regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
3192 regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
3193 regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
3194 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
3195 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
3196 regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
3197 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
3198 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
3199 regs_buff[num++] = readl(&aregs->txdma.service_request);
3200 regs_buff[num++] = readl(&aregs->txdma.service_complete);
3201 regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
3202 regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
3203 regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
3204 regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
3205 regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
3206 regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
3207 regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
3208 regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
3209 regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
3210 regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
3211 regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
3212 regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
3213 regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
3214 regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
3215 regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
3216
3217 /* RXDMA regs */
3218 regs_buff[num++] = readl(&aregs->rxdma.csr);
3219 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
3220 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
3221 regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
3222 regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
3223 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
3224 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
3225 regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
3226 regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
3227 regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
3228 regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
3229 regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
3230 regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
3231 regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
3232 regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
3233 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
3234 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
3235 regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
3236 regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
3237 regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
3238 regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
3239 regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
3240 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
3241 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
3242 regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
3243 regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
3244 regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
3245 regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
3246 regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
3247 }
3248
3249 static void et131x_get_drvinfo(struct net_device *netdev,
3250 struct ethtool_drvinfo *info)
3251 {
3252 struct et131x_adapter *adapter = netdev_priv(netdev);
3253
3254 strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
3255 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3256 strlcpy(info->bus_info, pci_name(adapter->pdev),
3257 sizeof(info->bus_info));
3258 }
3259
3260 static struct ethtool_ops et131x_ethtool_ops = {
3261 .get_settings = et131x_get_settings,
3262 .set_settings = et131x_set_settings,
3263 .get_drvinfo = et131x_get_drvinfo,
3264 .get_regs_len = et131x_get_regs_len,
3265 .get_regs = et131x_get_regs,
3266 .get_link = ethtool_op_get_link,
3267 };
3268
3269 /* et131x_hwaddr_init - set up the MAC Address on the ET1310 */
3270 static void et131x_hwaddr_init(struct et131x_adapter *adapter)
3271 {
3272 /* If have our default mac from init and no mac address from
3273 * EEPROM then we need to generate the last octet and set it on the
3274 * device
3275 */
3276 if (is_zero_ether_addr(adapter->rom_addr)) {
3277 /* We need to randomly generate the last octet so we
3278 * decrease our chances of setting the mac address to
3279 * same as another one of our cards in the system
3280 */
3281 get_random_bytes(&adapter->addr[5], 1);
3282 /* We have the default value in the register we are
3283 * working with so we need to copy the current
3284 * address into the permanent address
3285 */
3286 memcpy(adapter->rom_addr,
3287 adapter->addr, ETH_ALEN);
3288 } else {
3289 /* We do not have an override address, so set the
3290 * current address to the permanent address and add
3291 * it to the device
3292 */
3293 memcpy(adapter->addr,
3294 adapter->rom_addr, ETH_ALEN);
3295 }
3296 }
3297
3298 /* et131x_pci_init - initial PCI setup
3299 *
3300 * Perform the initial setup of PCI registers and if possible initialise
3301 * the MAC address. At this point the I/O registers have yet to be mapped
3302 */
3303 static int et131x_pci_init(struct et131x_adapter *adapter,
3304 struct pci_dev *pdev)
3305 {
3306 u16 max_payload;
3307 int i, rc;
3308
3309 rc = et131x_init_eeprom(adapter);
3310 if (rc < 0)
3311 goto out;
3312
3313 if (!pci_is_pcie(pdev)) {
3314 dev_err(&pdev->dev, "Missing PCIe capabilities\n");
3315 goto err_out;
3316 }
3317
3318 /* Let's set up the PORT LOGIC Register. */
3319
3320 /* Program the Ack/Nak latency and replay timers */
3321 max_payload = pdev->pcie_mpss;
3322
3323 if (max_payload < 2) {
3324 static const u16 acknak[2] = { 0x76, 0xD0 };
3325 static const u16 replay[2] = { 0x1E0, 0x2ED };
3326
3327 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
3328 acknak[max_payload])) {
3329 dev_err(&pdev->dev,
3330 "Could not write PCI config space for ACK/NAK\n");
3331 goto err_out;
3332 }
3333 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
3334 replay[max_payload])) {
3335 dev_err(&pdev->dev,
3336 "Could not write PCI config space for Replay Timer\n");
3337 goto err_out;
3338 }
3339 }
3340
3341 /* l0s and l1 latency timers. We are using default values.
3342 * Representing 001 for L0s and 010 for L1
3343 */
3344 if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
3345 dev_err(&pdev->dev,
3346 "Could not write PCI config space for Latency Timers\n");
3347 goto err_out;
3348 }
3349
3350 /* Change the max read size to 2k */
3351 if (pcie_set_readrq(pdev, 2048)) {
3352 dev_err(&pdev->dev,
3353 "Couldn't change PCI config space for Max read size\n");
3354 goto err_out;
3355 }
3356
3357 /* Get MAC address from config space if an eeprom exists, otherwise
3358 * the MAC address there will not be valid
3359 */
3360 if (!adapter->has_eeprom) {
3361 et131x_hwaddr_init(adapter);
3362 return 0;
3363 }
3364
3365 for (i = 0; i < ETH_ALEN; i++) {
3366 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
3367 adapter->rom_addr + i)) {
3368 dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
3369 goto err_out;
3370 }
3371 }
3372 ether_addr_copy(adapter->addr, adapter->rom_addr);
3373 out:
3374 return rc;
3375 err_out:
3376 rc = -EIO;
3377 goto out;
3378 }
3379
3380 /* et131x_error_timer_handler
3381 * @data: timer-specific variable; here a pointer to our adapter structure
3382 *
3383 * The routine called when the error timer expires, to track the number of
3384 * recurring errors.
3385 */
3386 static void et131x_error_timer_handler(unsigned long data)
3387 {
3388 struct et131x_adapter *adapter = (struct et131x_adapter *) data;
3389 struct phy_device *phydev = adapter->phydev;
3390
3391 if (et1310_in_phy_coma(adapter)) {
3392 /* Bring the device immediately out of coma, to
3393 * prevent it from sleeping indefinitely, this
3394 * mechanism could be improved!
3395 */
3396 et1310_disable_phy_coma(adapter);
3397 adapter->boot_coma = 20;
3398 } else {
3399 et1310_update_macstat_host_counters(adapter);
3400 }
3401
3402 if (!phydev->link && adapter->boot_coma < 11)
3403 adapter->boot_coma++;
3404
3405 if (adapter->boot_coma == 10) {
3406 if (!phydev->link) {
3407 if (!et1310_in_phy_coma(adapter)) {
3408 /* NOTE - This was originally a 'sync with
3409 * interrupt'. How to do that under Linux?
3410 */
3411 et131x_enable_interrupts(adapter);
3412 et1310_enable_phy_coma(adapter);
3413 }
3414 }
3415 }
3416
3417 /* This is a periodic timer, so reschedule */
3418 mod_timer(&adapter->error_timer, jiffies + TX_ERROR_PERIOD * HZ / 1000);
3419 }
3420
3421 /* et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx */
3422 static void et131x_adapter_memory_free(struct et131x_adapter *adapter)
3423 {
3424 et131x_tx_dma_memory_free(adapter);
3425 et131x_rx_dma_memory_free(adapter);
3426 }
3427
3428 /* et131x_adapter_memory_alloc
3429 * Allocate all the memory blocks for send, receive and others.
3430 */
3431 static int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
3432 {
3433 int status;
3434
3435 /* Allocate memory for the Tx Ring */
3436 status = et131x_tx_dma_memory_alloc(adapter);
3437 if (status) {
3438 dev_err(&adapter->pdev->dev,
3439 "et131x_tx_dma_memory_alloc FAILED\n");
3440 et131x_tx_dma_memory_free(adapter);
3441 return status;
3442 }
3443 /* Receive buffer memory allocation */
3444 status = et131x_rx_dma_memory_alloc(adapter);
3445 if (status) {
3446 dev_err(&adapter->pdev->dev,
3447 "et131x_rx_dma_memory_alloc FAILED\n");
3448 et131x_adapter_memory_free(adapter);
3449 return status;
3450 }
3451
3452 /* Init receive data structures */
3453 status = et131x_init_recv(adapter);
3454 if (status) {
3455 dev_err(&adapter->pdev->dev, "et131x_init_recv FAILED\n");
3456 et131x_adapter_memory_free(adapter);
3457 }
3458 return status;
3459 }
3460
3461 static void et131x_adjust_link(struct net_device *netdev)
3462 {
3463 struct et131x_adapter *adapter = netdev_priv(netdev);
3464 struct phy_device *phydev = adapter->phydev;
3465
3466 if (!phydev)
3467 return;
3468 if (phydev->link == adapter->link)
3469 return;
3470
3471 /* Check to see if we are in coma mode and if
3472 * so, disable it because we will not be able
3473 * to read PHY values until we are out.
3474 */
3475 if (et1310_in_phy_coma(adapter))
3476 et1310_disable_phy_coma(adapter);
3477
3478 adapter->link = phydev->link;
3479 phy_print_status(phydev);
3480
3481 if (phydev->link) {
3482 adapter->boot_coma = 20;
3483 if (phydev->speed == SPEED_10) {
3484 u16 register18;
3485
3486 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3487 &register18);
3488 et131x_mii_write(adapter, phydev->addr,
3489 PHY_MPHY_CONTROL_REG, register18 | 0x4);
3490 et131x_mii_write(adapter, phydev->addr, PHY_INDEX_REG,
3491 register18 | 0x8402);
3492 et131x_mii_write(adapter, phydev->addr, PHY_DATA_REG,
3493 register18 | 511);
3494 et131x_mii_write(adapter, phydev->addr,
3495 PHY_MPHY_CONTROL_REG, register18);
3496 }
3497
3498 et1310_config_flow_control(adapter);
3499
3500 if (phydev->speed == SPEED_1000 &&
3501 adapter->registry_jumbo_packet > 2048) {
3502 u16 reg;
3503
3504 et131x_mii_read(adapter, PHY_CONFIG, &reg);
3505 reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH;
3506 reg |= ET_PHY_CONFIG_FIFO_DEPTH_32;
3507 et131x_mii_write(adapter, phydev->addr, PHY_CONFIG,
3508 reg);
3509 }
3510
3511 et131x_set_rx_dma_timer(adapter);
3512 et1310_config_mac_regs2(adapter);
3513 } else {
3514 adapter->boot_coma = 0;
3515
3516 if (phydev->speed == SPEED_10) {
3517 u16 register18;
3518
3519 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3520 &register18);
3521 et131x_mii_write(adapter, phydev->addr,
3522 PHY_MPHY_CONTROL_REG, register18 | 0x4);
3523 et131x_mii_write(adapter, phydev->addr,
3524 PHY_INDEX_REG, register18 | 0x8402);
3525 et131x_mii_write(adapter, phydev->addr,
3526 PHY_DATA_REG, register18 | 511);
3527 et131x_mii_write(adapter, phydev->addr,
3528 PHY_MPHY_CONTROL_REG, register18);
3529 }
3530
3531 /* Free the packets being actively sent & stopped */
3532 et131x_free_busy_send_packets(adapter);
3533
3534 /* Re-initialize the send structures */
3535 et131x_init_send(adapter);
3536
3537 /* Bring the device back to the state it was during
3538 * init prior to autonegotiation being complete. This
3539 * way, when we get the auto-neg complete interrupt,
3540 * we can complete init by calling config_mac_regs2.
3541 */
3542 et131x_soft_reset(adapter);
3543
3544 /* Setup ET1310 as per the documentation */
3545 et131x_adapter_setup(adapter);
3546
3547 /* perform reset of tx/rx */
3548 et131x_disable_txrx(netdev);
3549 et131x_enable_txrx(netdev);
3550 }
3551 }
3552
3553 static int et131x_mii_probe(struct net_device *netdev)
3554 {
3555 struct et131x_adapter *adapter = netdev_priv(netdev);
3556 struct phy_device *phydev = NULL;
3557
3558 phydev = phy_find_first(adapter->mii_bus);
3559 if (!phydev) {
3560 dev_err(&adapter->pdev->dev, "no PHY found\n");
3561 return -ENODEV;
3562 }
3563
3564 phydev = phy_connect(netdev, dev_name(&phydev->dev),
3565 &et131x_adjust_link, PHY_INTERFACE_MODE_MII);
3566
3567 if (IS_ERR(phydev)) {
3568 dev_err(&adapter->pdev->dev, "Could not attach to PHY\n");
3569 return PTR_ERR(phydev);
3570 }
3571
3572 phydev->supported &= (SUPPORTED_10baseT_Half |
3573 SUPPORTED_10baseT_Full |
3574 SUPPORTED_100baseT_Half |
3575 SUPPORTED_100baseT_Full |
3576 SUPPORTED_Autoneg |
3577 SUPPORTED_MII |
3578 SUPPORTED_TP);
3579
3580 if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
3581 phydev->supported |= SUPPORTED_1000baseT_Half |
3582 SUPPORTED_1000baseT_Full;
3583
3584 phydev->advertising = phydev->supported;
3585 phydev->autoneg = AUTONEG_ENABLE;
3586 adapter->phydev = phydev;
3587
3588 dev_info(&adapter->pdev->dev,
3589 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3590 phydev->drv->name, dev_name(&phydev->dev));
3591
3592 return 0;
3593 }
3594
3595 /* et131x_adapter_init
3596 *
3597 * Initialize the data structures for the et131x_adapter object and link
3598 * them together with the platform provided device structures.
3599 */
3600 static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
3601 struct pci_dev *pdev)
3602 {
3603 static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
3604
3605 struct et131x_adapter *adapter;
3606
3607 /* Allocate private adapter struct and copy in relevant information */
3608 adapter = netdev_priv(netdev);
3609 adapter->pdev = pci_dev_get(pdev);
3610 adapter->netdev = netdev;
3611
3612 /* Initialize spinlocks here */
3613 spin_lock_init(&adapter->tcb_send_qlock);
3614 spin_lock_init(&adapter->tcb_ready_qlock);
3615 spin_lock_init(&adapter->send_hw_lock);
3616 spin_lock_init(&adapter->rcv_lock);
3617
3618 adapter->registry_jumbo_packet = 1514; /* 1514-9216 */
3619
3620 /* Set the MAC address to a default */
3621 ether_addr_copy(adapter->addr, default_mac);
3622
3623 return adapter;
3624 }
3625
3626 /* et131x_pci_remove
3627 *
3628 * Registered in the pci_driver structure, this function is called when the
3629 * PCI subsystem detects that a PCI device which matches the information
3630 * contained in the pci_device_id table has been removed.
3631 */
3632 static void et131x_pci_remove(struct pci_dev *pdev)
3633 {
3634 struct net_device *netdev = pci_get_drvdata(pdev);
3635 struct et131x_adapter *adapter = netdev_priv(netdev);
3636
3637 unregister_netdev(netdev);
3638 netif_napi_del(&adapter->napi);
3639 phy_disconnect(adapter->phydev);
3640 mdiobus_unregister(adapter->mii_bus);
3641 kfree(adapter->mii_bus->irq);
3642 mdiobus_free(adapter->mii_bus);
3643
3644 et131x_adapter_memory_free(adapter);
3645 iounmap(adapter->regs);
3646 pci_dev_put(pdev);
3647
3648 free_netdev(netdev);
3649 pci_release_regions(pdev);
3650 pci_disable_device(pdev);
3651 }
3652
3653 /* et131x_up - Bring up a device for use. */
3654 static void et131x_up(struct net_device *netdev)
3655 {
3656 struct et131x_adapter *adapter = netdev_priv(netdev);
3657
3658 et131x_enable_txrx(netdev);
3659 phy_start(adapter->phydev);
3660 }
3661
3662 /* et131x_down - Bring down the device */
3663 static void et131x_down(struct net_device *netdev)
3664 {
3665 struct et131x_adapter *adapter = netdev_priv(netdev);
3666
3667 /* Save the timestamp for the TX watchdog, prevent a timeout */
3668 netdev->trans_start = jiffies;
3669
3670 phy_stop(adapter->phydev);
3671 et131x_disable_txrx(netdev);
3672 }
3673
3674 #ifdef CONFIG_PM_SLEEP
3675 static int et131x_suspend(struct device *dev)
3676 {
3677 struct pci_dev *pdev = to_pci_dev(dev);
3678 struct net_device *netdev = pci_get_drvdata(pdev);
3679
3680 if (netif_running(netdev)) {
3681 netif_device_detach(netdev);
3682 et131x_down(netdev);
3683 pci_save_state(pdev);
3684 }
3685
3686 return 0;
3687 }
3688
3689 static int et131x_resume(struct device *dev)
3690 {
3691 struct pci_dev *pdev = to_pci_dev(dev);
3692 struct net_device *netdev = pci_get_drvdata(pdev);
3693
3694 if (netif_running(netdev)) {
3695 pci_restore_state(pdev);
3696 et131x_up(netdev);
3697 netif_device_attach(netdev);
3698 }
3699
3700 return 0;
3701 }
3702
3703 static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
3704 #define ET131X_PM_OPS (&et131x_pm_ops)
3705 #else
3706 #define ET131X_PM_OPS NULL
3707 #endif
3708
3709 /* et131x_isr - The Interrupt Service Routine for the driver.
3710 * @irq: the IRQ on which the interrupt was received.
3711 * @dev_id: device-specific info (here a pointer to a net_device struct)
3712 *
3713 * Returns a value indicating if the interrupt was handled.
3714 */
3715 static irqreturn_t et131x_isr(int irq, void *dev_id)
3716 {
3717 bool handled = true;
3718 bool enable_interrupts = true;
3719 struct net_device *netdev = (struct net_device *)dev_id;
3720 struct et131x_adapter *adapter = netdev_priv(netdev);
3721 struct address_map __iomem *iomem = adapter->regs;
3722 struct rx_ring *rx_ring = &adapter->rx_ring;
3723 struct tx_ring *tx_ring = &adapter->tx_ring;
3724 u32 status;
3725
3726 if (!netif_device_present(netdev)) {
3727 handled = false;
3728 enable_interrupts = false;
3729 goto out;
3730 }
3731
3732 /* If the adapter is in low power state, then it should not
3733 * recognize any interrupt
3734 */
3735
3736 /* Disable Device Interrupts */
3737 et131x_disable_interrupts(adapter);
3738
3739 /* Get a copy of the value in the interrupt status register
3740 * so we can process the interrupting section
3741 */
3742 status = readl(&adapter->regs->global.int_status);
3743
3744 if (adapter->flowcontrol == FLOW_TXONLY ||
3745 adapter->flowcontrol == FLOW_BOTH) {
3746 status &= ~INT_MASK_ENABLE;
3747 } else {
3748 status &= ~INT_MASK_ENABLE_NO_FLOW;
3749 }
3750
3751 /* Make sure this is our interrupt */
3752 if (!status) {
3753 handled = false;
3754 et131x_enable_interrupts(adapter);
3755 goto out;
3756 }
3757
3758 /* This is our interrupt, so process accordingly */
3759 if (status & ET_INTR_WATCHDOG) {
3760 struct tcb *tcb = tx_ring->send_head;
3761
3762 if (tcb)
3763 if (++tcb->stale > 1)
3764 status |= ET_INTR_TXDMA_ISR;
3765
3766 if (rx_ring->unfinished_receives)
3767 status |= ET_INTR_RXDMA_XFR_DONE;
3768 else if (tcb == NULL)
3769 writel(0, &adapter->regs->global.watchdog_timer);
3770
3771 status &= ~ET_INTR_WATCHDOG;
3772 }
3773
3774 if (status & (ET_INTR_RXDMA_XFR_DONE | ET_INTR_TXDMA_ISR)) {
3775 enable_interrupts = false;
3776 napi_schedule(&adapter->napi);
3777 }
3778
3779 status &= ~(ET_INTR_TXDMA_ISR | ET_INTR_RXDMA_XFR_DONE);
3780
3781 if (!status)
3782 goto out;
3783
3784 /* Handle the TXDMA Error interrupt */
3785 if (status & ET_INTR_TXDMA_ERR) {
3786 /* Following read also clears the register (COR) */
3787 u32 txdma_err = readl(&iomem->txdma.tx_dma_error);
3788
3789 dev_warn(&adapter->pdev->dev,
3790 "TXDMA_ERR interrupt, error = %d\n",
3791 txdma_err);
3792 }
3793
3794 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
3795 if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
3796 /* This indicates the number of unused buffers in RXDMA free
3797 * buffer ring 0 is <= the limit you programmed. Free buffer
3798 * resources need to be returned. Free buffers are consumed as
3799 * packets are passed from the network to the host. The host
3800 * becomes aware of the packets from the contents of the packet
3801 * status ring. This ring is queried when the packet done
3802 * interrupt occurs. Packets are then passed to the OS. When
3803 * the OS is done with the packets the resources can be
3804 * returned to the ET1310 for re-use. This interrupt is one
3805 * method of returning resources.
3806 */
3807
3808 /* If the user has flow control on, then we will
3809 * send a pause packet, otherwise just exit
3810 */
3811 if (adapter->flowcontrol == FLOW_TXONLY ||
3812 adapter->flowcontrol == FLOW_BOTH) {
3813 u32 pm_csr;
3814
3815 /* Tell the device to send a pause packet via the back
3816 * pressure register (bp req and bp xon/xoff)
3817 */
3818 pm_csr = readl(&iomem->global.pm_csr);
3819 if (!et1310_in_phy_coma(adapter))
3820 writel(3, &iomem->txmac.bp_ctrl);
3821 }
3822 }
3823
3824 /* Handle Packet Status Ring Low Interrupt */
3825 if (status & ET_INTR_RXDMA_STAT_LOW) {
3826 /* Same idea as with the two Free Buffer Rings. Packets going
3827 * from the network to the host each consume a free buffer
3828 * resource and a packet status resource. These resources are
3829 * passed to the OS. When the OS is done with the resources,
3830 * they need to be returned to the ET1310. This is one method
3831 * of returning the resources.
3832 */
3833 }
3834
3835 /* Handle RXDMA Error Interrupt */
3836 if (status & ET_INTR_RXDMA_ERR) {
3837 /* The rxdma_error interrupt is sent when a time-out on a
3838 * request issued by the JAGCore has occurred or a completion is
3839 * returned with an un-successful status. In both cases the
3840 * request is considered complete. The JAGCore will
3841 * automatically re-try the request in question. Normally
3842 * information on events like these are sent to the host using
3843 * the "Advanced Error Reporting" capability. This interrupt is
3844 * another way of getting similar information. The only thing
3845 * required is to clear the interrupt by reading the ISR in the
3846 * global resources. The JAGCore will do a re-try on the
3847 * request. Normally you should never see this interrupt. If
3848 * you start to see this interrupt occurring frequently then
3849 * something bad has occurred. A reset might be the thing to do.
3850 */
3851 /* TRAP();*/
3852
3853 dev_warn(&adapter->pdev->dev,
3854 "RxDMA_ERR interrupt, error %x\n",
3855 readl(&iomem->txmac.tx_test));
3856 }
3857
3858 /* Handle the Wake on LAN Event */
3859 if (status & ET_INTR_WOL) {
3860 /* This is a secondary interrupt for wake on LAN. The driver
3861 * should never see this, if it does, something serious is
3862 * wrong. We will TRAP the message when we are in DBG mode,
3863 * otherwise we will ignore it.
3864 */
3865 dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
3866 }
3867
3868 /* Let's move on to the TxMac */
3869 if (status & ET_INTR_TXMAC) {
3870 u32 err = readl(&iomem->txmac.err);
3871
3872 /* When any of the errors occur and TXMAC generates an
3873 * interrupt to report these errors, it usually means that
3874 * TXMAC has detected an error in the data stream retrieved
3875 * from the on-chip Tx Q. All of these errors are catastrophic
3876 * and TXMAC won't be able to recover data when these errors
3877 * occur. In a nutshell, the whole Tx path will have to be reset
3878 * and re-configured afterwards.
3879 */
3880 dev_warn(&adapter->pdev->dev,
3881 "TXMAC interrupt, error 0x%08x\n",
3882 err);
3883
3884 /* If we are debugging, we want to see this error, otherwise we
3885 * just want the device to be reset and continue
3886 */
3887 }
3888
3889 /* Handle RXMAC Interrupt */
3890 if (status & ET_INTR_RXMAC) {
3891 /* These interrupts are catastrophic to the device, what we need
3892 * to do is disable the interrupts and set the flag to cause us
3893 * to reset so we can solve this issue.
3894 */
3895 /* MP_SET_FLAG( adapter, FMP_ADAPTER_HARDWARE_ERROR); */
3896
3897 dev_warn(&adapter->pdev->dev,
3898 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
3899 readl(&iomem->rxmac.err_reg));
3900
3901 dev_warn(&adapter->pdev->dev,
3902 "Enable 0x%08x, Diag 0x%08x\n",
3903 readl(&iomem->rxmac.ctrl),
3904 readl(&iomem->rxmac.rxq_diag));
3905
3906 /* If we are debugging, we want to see this error, otherwise we
3907 * just want the device to be reset and continue
3908 */
3909 }
3910
3911 /* Handle MAC_STAT Interrupt */
3912 if (status & ET_INTR_MAC_STAT) {
3913 /* This means at least one of the un-masked counters in the
3914 * MAC_STAT block has rolled over. Use this to maintain the top,
3915 * software managed bits of the counter(s).
3916 */
3917 et1310_handle_macstat_interrupt(adapter);
3918 }
3919
3920 /* Handle SLV Timeout Interrupt */
3921 if (status & ET_INTR_SLV_TIMEOUT) {
3922 /* This means a timeout has occurred on a read or write request
3923 * to one of the JAGCore registers. The Global Resources block
3924 * has terminated the request and on a read request, returned a
3925 * "fake" value. The most likely reasons are: Bad Address or the
3926 * addressed module is in a power-down state and can't respond.
3927 */
3928 }
3929
3930 out:
3931 if (enable_interrupts)
3932 et131x_enable_interrupts(adapter);
3933
3934 return IRQ_RETVAL(handled);
3935 }
3936
3937 static int et131x_poll(struct napi_struct *napi, int budget)
3938 {
3939 struct et131x_adapter *adapter =
3940 container_of(napi, struct et131x_adapter, napi);
3941 int work_done = et131x_handle_recv_pkts(adapter, budget);
3942
3943 et131x_handle_send_pkts(adapter);
3944
3945 if (work_done < budget) {
3946 napi_complete(&adapter->napi);
3947 et131x_enable_interrupts(adapter);
3948 }
3949
3950 return work_done;
3951 }
3952
3953 /* et131x_stats - Return the current device statistics */
3954 static struct net_device_stats *et131x_stats(struct net_device *netdev)
3955 {
3956 struct et131x_adapter *adapter = netdev_priv(netdev);
3957 struct net_device_stats *stats = &adapter->netdev->stats;
3958 struct ce_stats *devstat = &adapter->stats;
3959
3960 stats->rx_errors = devstat->rx_length_errs +
3961 devstat->rx_align_errs +
3962 devstat->rx_crc_errs +
3963 devstat->rx_code_violations +
3964 devstat->rx_other_errs;
3965 stats->tx_errors = devstat->tx_max_pkt_errs;
3966 stats->multicast = devstat->multicast_pkts_rcvd;
3967 stats->collisions = devstat->tx_collisions;
3968
3969 stats->rx_length_errors = devstat->rx_length_errs;
3970 stats->rx_over_errors = devstat->rx_overflows;
3971 stats->rx_crc_errors = devstat->rx_crc_errs;
3972 stats->rx_dropped = devstat->rcvd_pkts_dropped;
3973
3974 /* NOTE: Not used, can't find analogous statistics */
3975 /* stats->rx_frame_errors = devstat->; */
3976 /* stats->rx_fifo_errors = devstat->; */
3977 /* stats->rx_missed_errors = devstat->; */
3978
3979 /* stats->tx_aborted_errors = devstat->; */
3980 /* stats->tx_carrier_errors = devstat->; */
3981 /* stats->tx_fifo_errors = devstat->; */
3982 /* stats->tx_heartbeat_errors = devstat->; */
3983 /* stats->tx_window_errors = devstat->; */
3984 return stats;
3985 }
3986
3987 /* et131x_open - Open the device for use. */
3988 static int et131x_open(struct net_device *netdev)
3989 {
3990 struct et131x_adapter *adapter = netdev_priv(netdev);
3991 struct pci_dev *pdev = adapter->pdev;
3992 unsigned int irq = pdev->irq;
3993 int result;
3994
3995 /* Start the timer to track NIC errors */
3996 init_timer(&adapter->error_timer);
3997 adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
3998 adapter->error_timer.function = et131x_error_timer_handler;
3999 adapter->error_timer.data = (unsigned long)adapter;
4000 add_timer(&adapter->error_timer);
4001
4002 result = request_irq(irq, et131x_isr,
4003 IRQF_SHARED, netdev->name, netdev);
4004 if (result) {
4005 dev_err(&pdev->dev, "could not register IRQ %d\n", irq);
4006 return result;
4007 }
4008
4009 adapter->flags |= FMP_ADAPTER_INTERRUPT_IN_USE;
4010
4011 napi_enable(&adapter->napi);
4012
4013 et131x_up(netdev);
4014
4015 return result;
4016 }
4017
4018 /* et131x_close - Close the device */
4019 static int et131x_close(struct net_device *netdev)
4020 {
4021 struct et131x_adapter *adapter = netdev_priv(netdev);
4022
4023 et131x_down(netdev);
4024 napi_disable(&adapter->napi);
4025
4026 adapter->flags &= ~FMP_ADAPTER_INTERRUPT_IN_USE;
4027 free_irq(adapter->pdev->irq, netdev);
4028
4029 /* Stop the error timer */
4030 return del_timer_sync(&adapter->error_timer);
4031 }
4032
4033 /* et131x_ioctl - The I/O Control handler for the driver
4034 * @netdev: device on which the control request is being made
4035 * @reqbuf: a pointer to the IOCTL request buffer
4036 * @cmd: the IOCTL command code
4037 */
4038 static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf,
4039 int cmd)
4040 {
4041 struct et131x_adapter *adapter = netdev_priv(netdev);
4042
4043 if (!adapter->phydev)
4044 return -EINVAL;
4045
4046 return phy_mii_ioctl(adapter->phydev, reqbuf, cmd);
4047 }
4048
4049 /* et131x_set_packet_filter - Configures the Rx Packet filtering on the device
4050 * @adapter: pointer to our private adapter structure
4051 *
4052 * FIXME: lot of dups with MAC code
4053 */
4054 static int et131x_set_packet_filter(struct et131x_adapter *adapter)
4055 {
4056 int filter = adapter->packet_filter;
4057 u32 ctrl;
4058 u32 pf_ctrl;
4059
4060 ctrl = readl(&adapter->regs->rxmac.ctrl);
4061 pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
4062
4063 /* Default to disabled packet filtering. Enable it in the individual
4064 * case statements that require the device to filter something
4065 */
4066 ctrl |= 0x04;
4067
4068 /* Set us to be in promiscuous mode so we receive everything, this
4069 * is also true when we get a packet filter of 0
4070 */
4071 if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
4072 pf_ctrl &= ~7; /* Clear filter bits */
4073 else {
4074 /* Set us up with Multicast packet filtering. Three cases are
4075 * possible - (1) we have a multi-cast list, (2) we receive ALL
4076 * multicast entries or (3) we receive none.
4077 */
4078 if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
4079 pf_ctrl &= ~2; /* Multicast filter bit */
4080 else {
4081 et1310_setup_device_for_multicast(adapter);
4082 pf_ctrl |= 2;
4083 ctrl &= ~0x04;
4084 }
4085
4086 /* Set us up with Unicast packet filtering */
4087 if (filter & ET131X_PACKET_TYPE_DIRECTED) {
4088 et1310_setup_device_for_unicast(adapter);
4089 pf_ctrl |= 4;
4090 ctrl &= ~0x04;
4091 }
4092
4093 /* Set us up with Broadcast packet filtering */
4094 if (filter & ET131X_PACKET_TYPE_BROADCAST) {
4095 pf_ctrl |= 1; /* Broadcast filter bit */
4096 ctrl &= ~0x04;
4097 } else
4098 pf_ctrl &= ~1;
4099
4100 /* Setup the receive mac configuration registers - Packet
4101 * Filter control + the enable / disable for packet filter
4102 * in the control reg.
4103 */
4104 writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
4105 writel(ctrl, &adapter->regs->rxmac.ctrl);
4106 }
4107 return 0;
4108 }
4109
4110 /* et131x_multicast - The handler to configure multicasting on the interface */
4111 static void et131x_multicast(struct net_device *netdev)
4112 {
4113 struct et131x_adapter *adapter = netdev_priv(netdev);
4114 int packet_filter;
4115 struct netdev_hw_addr *ha;
4116 int i;
4117
4118 /* Before we modify the platform-independent filter flags, store them
4119 * locally. This allows us to determine if anything's changed and if
4120 * we even need to bother the hardware
4121 */
4122 packet_filter = adapter->packet_filter;
4123
4124 /* Clear the 'multicast' flag locally; because we only have a single
4125 * flag to check multicast, and multiple multicast addresses can be
4126 * set, this is the easiest way to determine if more than one
4127 * multicast address is being set.
4128 */
4129 packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4130
4131 /* Check the net_device flags and set the device independent flags
4132 * accordingly
4133 */
4134
4135 if (netdev->flags & IFF_PROMISC)
4136 adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
4137 else
4138 adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
4139
4140 if (netdev->flags & IFF_ALLMULTI)
4141 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4142
4143 if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST)
4144 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4145
4146 if (netdev_mc_count(netdev) < 1) {
4147 adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
4148 adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4149 } else
4150 adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST;
4151
4152 /* Set values in the private adapter struct */
4153 i = 0;
4154 netdev_for_each_mc_addr(ha, netdev) {
4155 if (i == NIC_MAX_MCAST_LIST)
4156 break;
4157 memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN);
4158 }
4159 adapter->multicast_addr_count = i;
4160
4161 /* Are the new flags different from the previous ones? If not, then no
4162 * action is required
4163 *
4164 * NOTE - This block will always update the multicast_list with the
4165 * hardware, even if the addresses aren't the same.
4166 */
4167 if (packet_filter != adapter->packet_filter)
4168 et131x_set_packet_filter(adapter);
4169 }
4170
4171 /* et131x_tx - The handler to tx a packet on the device */
4172 static netdev_tx_t et131x_tx(struct sk_buff *skb, struct net_device *netdev)
4173 {
4174 struct et131x_adapter *adapter = netdev_priv(netdev);
4175 struct tx_ring *tx_ring = &adapter->tx_ring;
4176
4177 /* stop the queue if it's getting full */
4178 if (tx_ring->used >= NUM_TCB - 1 && !netif_queue_stopped(netdev))
4179 netif_stop_queue(netdev);
4180
4181 /* Save the timestamp for the TX timeout watchdog */
4182 netdev->trans_start = jiffies;
4183
4184 /* TCB is not available */
4185 if (tx_ring->used >= NUM_TCB)
4186 goto drop_err;
4187
4188 if ((adapter->flags & FMP_ADAPTER_FAIL_SEND_MASK) ||
4189 !netif_carrier_ok(netdev))
4190 goto drop_err;
4191
4192 if (send_packet(skb, adapter))
4193 goto drop_err;
4194
4195 return NETDEV_TX_OK;
4196
4197 drop_err:
4198 dev_kfree_skb_any(skb);
4199 skb = NULL;
4200 adapter->netdev->stats.tx_dropped++;
4201 return NETDEV_TX_OK;
4202 }
4203
4204 /* et131x_tx_timeout - Timeout handler
4205 *
4206 * The handler called when a Tx request times out. The timeout period is
4207 * specified by the 'tx_timeo" element in the net_device structure (see
4208 * et131x_alloc_device() to see how this value is set).
4209 */
4210 static void et131x_tx_timeout(struct net_device *netdev)
4211 {
4212 struct et131x_adapter *adapter = netdev_priv(netdev);
4213 struct tx_ring *tx_ring = &adapter->tx_ring;
4214 struct tcb *tcb;
4215 unsigned long flags;
4216
4217 /* If the device is closed, ignore the timeout */
4218 if (~(adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE))
4219 return;
4220
4221 /* Any nonrecoverable hardware error?
4222 * Checks adapter->flags for any failure in phy reading
4223 */
4224 if (adapter->flags & FMP_ADAPTER_NON_RECOVER_ERROR)
4225 return;
4226
4227 /* Hardware failure? */
4228 if (adapter->flags & FMP_ADAPTER_HARDWARE_ERROR) {
4229 dev_err(&adapter->pdev->dev, "hardware error - reset\n");
4230 return;
4231 }
4232
4233 /* Is send stuck? */
4234 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
4235
4236 tcb = tx_ring->send_head;
4237
4238 if (tcb != NULL) {
4239 tcb->count++;
4240
4241 if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
4242 spin_unlock_irqrestore(&adapter->tcb_send_qlock,
4243 flags);
4244
4245 dev_warn(&adapter->pdev->dev,
4246 "Send stuck - reset. tcb->WrIndex %x\n",
4247 tcb->index);
4248
4249 adapter->netdev->stats.tx_errors++;
4250
4251 /* perform reset of tx/rx */
4252 et131x_disable_txrx(netdev);
4253 et131x_enable_txrx(netdev);
4254 return;
4255 }
4256 }
4257
4258 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
4259 }
4260
4261 /* et131x_change_mtu - The handler called to change the MTU for the device */
4262 static int et131x_change_mtu(struct net_device *netdev, int new_mtu)
4263 {
4264 int result = 0;
4265 struct et131x_adapter *adapter = netdev_priv(netdev);
4266
4267 /* Make sure the requested MTU is valid */
4268 if (new_mtu < 64 || new_mtu > 9216)
4269 return -EINVAL;
4270
4271 et131x_disable_txrx(netdev);
4272
4273 /* Set the new MTU */
4274 netdev->mtu = new_mtu;
4275
4276 /* Free Rx DMA memory */
4277 et131x_adapter_memory_free(adapter);
4278
4279 /* Set the config parameter for Jumbo Packet support */
4280 adapter->registry_jumbo_packet = new_mtu + 14;
4281 et131x_soft_reset(adapter);
4282
4283 /* Alloc and init Rx DMA memory */
4284 result = et131x_adapter_memory_alloc(adapter);
4285 if (result != 0) {
4286 dev_warn(&adapter->pdev->dev,
4287 "Change MTU failed; couldn't re-alloc DMA memory\n");
4288 return result;
4289 }
4290
4291 et131x_init_send(adapter);
4292
4293 et131x_hwaddr_init(adapter);
4294 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4295
4296 /* Init the device with the new settings */
4297 et131x_adapter_setup(adapter);
4298
4299 et131x_enable_txrx(netdev);
4300
4301 return result;
4302 }
4303
4304 static const struct net_device_ops et131x_netdev_ops = {
4305 .ndo_open = et131x_open,
4306 .ndo_stop = et131x_close,
4307 .ndo_start_xmit = et131x_tx,
4308 .ndo_set_rx_mode = et131x_multicast,
4309 .ndo_tx_timeout = et131x_tx_timeout,
4310 .ndo_change_mtu = et131x_change_mtu,
4311 .ndo_set_mac_address = eth_mac_addr,
4312 .ndo_validate_addr = eth_validate_addr,
4313 .ndo_get_stats = et131x_stats,
4314 .ndo_do_ioctl = et131x_ioctl,
4315 };
4316
4317 /* et131x_pci_setup - Perform device initialization
4318 * @pdev: a pointer to the device's pci_dev structure
4319 * @ent: this device's entry in the pci_device_id table
4320 *
4321 * Registered in the pci_driver structure, this function is called when the
4322 * PCI subsystem finds a new PCI device which matches the information
4323 * contained in the pci_device_id table. This routine is the equivalent to
4324 * a device insertion routine.
4325 */
4326 static int et131x_pci_setup(struct pci_dev *pdev,
4327 const struct pci_device_id *ent)
4328 {
4329 struct net_device *netdev;
4330 struct et131x_adapter *adapter;
4331 int rc;
4332 int ii;
4333
4334 rc = pci_enable_device(pdev);
4335 if (rc < 0) {
4336 dev_err(&pdev->dev, "pci_enable_device() failed\n");
4337 goto out;
4338 }
4339
4340 /* Perform some basic PCI checks */
4341 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4342 dev_err(&pdev->dev, "Can't find PCI device's base address\n");
4343 rc = -ENODEV;
4344 goto err_disable;
4345 }
4346
4347 rc = pci_request_regions(pdev, DRIVER_NAME);
4348 if (rc < 0) {
4349 dev_err(&pdev->dev, "Can't get PCI resources\n");
4350 goto err_disable;
4351 }
4352
4353 pci_set_master(pdev);
4354
4355 /* Check the DMA addressing support of this device */
4356 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
4357 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
4358 dev_err(&pdev->dev, "No usable DMA addressing method\n");
4359 rc = -EIO;
4360 goto err_release_res;
4361 }
4362
4363 /* Allocate netdev and private adapter structs */
4364 netdev = alloc_etherdev(sizeof(struct et131x_adapter));
4365 if (!netdev) {
4366 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
4367 rc = -ENOMEM;
4368 goto err_release_res;
4369 }
4370
4371 netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
4372 netdev->netdev_ops = &et131x_netdev_ops;
4373
4374 SET_NETDEV_DEV(netdev, &pdev->dev);
4375 netdev->ethtool_ops = &et131x_ethtool_ops;
4376
4377 adapter = et131x_adapter_init(netdev, pdev);
4378
4379 rc = et131x_pci_init(adapter, pdev);
4380 if (rc < 0)
4381 goto err_free_dev;
4382
4383 /* Map the bus-relative registers to system virtual memory */
4384 adapter->regs = pci_ioremap_bar(pdev, 0);
4385 if (!adapter->regs) {
4386 dev_err(&pdev->dev, "Cannot map device registers\n");
4387 rc = -ENOMEM;
4388 goto err_free_dev;
4389 }
4390
4391 /* If Phy COMA mode was enabled when we went down, disable it here. */
4392 writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
4393
4394 /* Issue a global reset to the et1310 */
4395 et131x_soft_reset(adapter);
4396
4397 /* Disable all interrupts (paranoid) */
4398 et131x_disable_interrupts(adapter);
4399
4400 /* Allocate DMA memory */
4401 rc = et131x_adapter_memory_alloc(adapter);
4402 if (rc < 0) {
4403 dev_err(&pdev->dev, "Could not alloc adapter memory (DMA)\n");
4404 goto err_iounmap;
4405 }
4406
4407 /* Init send data structures */
4408 et131x_init_send(adapter);
4409
4410 netif_napi_add(netdev, &adapter->napi, et131x_poll, 64);
4411
4412 /* Copy address into the net_device struct */
4413 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4414
4415 rc = -ENOMEM;
4416
4417 /* Setup the mii_bus struct */
4418 adapter->mii_bus = mdiobus_alloc();
4419 if (!adapter->mii_bus) {
4420 dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n");
4421 goto err_mem_free;
4422 }
4423
4424 adapter->mii_bus->name = "et131x_eth_mii";
4425 snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
4426 (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
4427 adapter->mii_bus->priv = netdev;
4428 adapter->mii_bus->read = et131x_mdio_read;
4429 adapter->mii_bus->write = et131x_mdio_write;
4430 adapter->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int),
4431 GFP_KERNEL);
4432 if (!adapter->mii_bus->irq)
4433 goto err_mdio_free;
4434
4435 for (ii = 0; ii < PHY_MAX_ADDR; ii++)
4436 adapter->mii_bus->irq[ii] = PHY_POLL;
4437
4438 rc = mdiobus_register(adapter->mii_bus);
4439 if (rc < 0) {
4440 dev_err(&pdev->dev, "failed to register MII bus\n");
4441 goto err_mdio_free_irq;
4442 }
4443
4444 rc = et131x_mii_probe(netdev);
4445 if (rc < 0) {
4446 dev_err(&pdev->dev, "failed to probe MII bus\n");
4447 goto err_mdio_unregister;
4448 }
4449
4450 /* Setup et1310 as per the documentation */
4451 et131x_adapter_setup(adapter);
4452
4453 /* Init variable for counting how long we do not have link status */
4454 adapter->boot_coma = 0;
4455 et1310_disable_phy_coma(adapter);
4456
4457 /* We can enable interrupts now
4458 *
4459 * NOTE - Because registration of interrupt handler is done in the
4460 * device's open(), defer enabling device interrupts to that
4461 * point
4462 */
4463
4464 /* Register the net_device struct with the Linux network layer */
4465 rc = register_netdev(netdev);
4466 if (rc < 0) {
4467 dev_err(&pdev->dev, "register_netdev() failed\n");
4468 goto err_phy_disconnect;
4469 }
4470
4471 /* Register the net_device struct with the PCI subsystem. Save a copy
4472 * of the PCI config space for this device now that the device has
4473 * been initialized, just in case it needs to be quickly restored.
4474 */
4475 pci_set_drvdata(pdev, netdev);
4476 out:
4477 return rc;
4478
4479 err_phy_disconnect:
4480 phy_disconnect(adapter->phydev);
4481 err_mdio_unregister:
4482 mdiobus_unregister(adapter->mii_bus);
4483 err_mdio_free_irq:
4484 kfree(adapter->mii_bus->irq);
4485 err_mdio_free:
4486 mdiobus_free(adapter->mii_bus);
4487 err_mem_free:
4488 et131x_adapter_memory_free(adapter);
4489 err_iounmap:
4490 iounmap(adapter->regs);
4491 err_free_dev:
4492 pci_dev_put(pdev);
4493 free_netdev(netdev);
4494 err_release_res:
4495 pci_release_regions(pdev);
4496 err_disable:
4497 pci_disable_device(pdev);
4498 goto out;
4499 }
4500
4501 static const struct pci_device_id et131x_pci_table[] = {
4502 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL},
4503 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL},
4504 {0,}
4505 };
4506 MODULE_DEVICE_TABLE(pci, et131x_pci_table);
4507
4508 static struct pci_driver et131x_driver = {
4509 .name = DRIVER_NAME,
4510 .id_table = et131x_pci_table,
4511 .probe = et131x_pci_setup,
4512 .remove = et131x_pci_remove,
4513 .driver.pm = ET131X_PM_OPS,
4514 };
4515
4516 module_pci_driver(et131x_driver);
Linux kernel - Deliverables
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