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[deliverable/linux.git] / drivers / staging / et131x / et131x.c
1 /* Agere Systems Inc.
2 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
3 *
4 * Copyright © 2005 Agere Systems Inc.
5 * All rights reserved.
6 * http://www.agere.com
7 *
8 * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
9 *
10 *------------------------------------------------------------------------------
11 *
12 * SOFTWARE LICENSE
13 *
14 * This software is provided subject to the following terms and conditions,
15 * which you should read carefully before using the software. Using this
16 * software indicates your acceptance of these terms and conditions. If you do
17 * not agree with these terms and conditions, do not use the software.
18 *
19 * Copyright © 2005 Agere Systems Inc.
20 * All rights reserved.
21 *
22 * Redistribution and use in source or binary forms, with or without
23 * modifications, are permitted provided that the following conditions are met:
24 *
25 * . Redistributions of source code must retain the above copyright notice, this
26 * list of conditions and the following Disclaimer as comments in the code as
27 * well as in the documentation and/or other materials provided with the
28 * distribution.
29 *
30 * . Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following Disclaimer in the documentation
32 * and/or other materials provided with the distribution.
33 *
34 * . Neither the name of Agere Systems Inc. nor the names of the contributors
35 * may be used to endorse or promote products derived from this software
36 * without specific prior written permission.
37 *
38 * Disclaimer
39 *
40 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
41 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
42 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
43 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
44 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
47 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
48 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
50 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
51 * DAMAGE.
52 */
53
54 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
55
56 #include <linux/pci.h>
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/kernel.h>
60
61 #include <linux/sched.h>
62 #include <linux/ptrace.h>
63 #include <linux/slab.h>
64 #include <linux/ctype.h>
65 #include <linux/string.h>
66 #include <linux/timer.h>
67 #include <linux/interrupt.h>
68 #include <linux/in.h>
69 #include <linux/delay.h>
70 #include <linux/bitops.h>
71 #include <linux/io.h>
72
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/if_arp.h>
77 #include <linux/ioport.h>
78 #include <linux/crc32.h>
79 #include <linux/random.h>
80 #include <linux/phy.h>
81
82 #include "et131x.h"
83
84 MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
85 MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
86 MODULE_LICENSE("Dual BSD/GPL");
87 MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems");
88
89 /* EEPROM defines */
90 #define MAX_NUM_REGISTER_POLLS 1000
91 #define MAX_NUM_WRITE_RETRIES 2
92
93 /* MAC defines */
94 #define COUNTER_WRAP_16_BIT 0x10000
95 #define COUNTER_WRAP_12_BIT 0x1000
96
97 /* PCI defines */
98 #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
99 #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
100
101 /* ISR defines */
102 /* For interrupts, normal running is:
103 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
104 * watchdog_interrupt & txdma_xfer_done
105 *
106 * In both cases, when flow control is enabled for either Tx or bi-direction,
107 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
108 * buffer rings are running low.
109 */
110 #define INT_MASK_DISABLE 0xffffffff
111
112 /* NOTE: Masking out MAC_STAT Interrupt for now...
113 * #define INT_MASK_ENABLE 0xfff6bf17
114 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
115 */
116 #define INT_MASK_ENABLE 0xfffebf17
117 #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
118
119 /* General defines */
120 /* Packet and header sizes */
121 #define NIC_MIN_PACKET_SIZE 60
122
123 /* Multicast list size */
124 #define NIC_MAX_MCAST_LIST 128
125
126 /* Supported Filters */
127 #define ET131X_PACKET_TYPE_DIRECTED 0x0001
128 #define ET131X_PACKET_TYPE_MULTICAST 0x0002
129 #define ET131X_PACKET_TYPE_BROADCAST 0x0004
130 #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
131 #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
132
133 /* Tx Timeout */
134 #define ET131X_TX_TIMEOUT (1 * HZ)
135 #define NIC_SEND_HANG_THRESHOLD 0
136
137 /* MP_TCB flags */
138 #define FMP_DEST_MULTI 0x00000001
139 #define FMP_DEST_BROAD 0x00000002
140
141 /* MP_ADAPTER flags */
142 #define FMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
143
144 /* MP_SHARED flags */
145 #define FMP_ADAPTER_LOWER_POWER 0x00200000
146
147 #define FMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
148 #define FMP_ADAPTER_HARDWARE_ERROR 0x04000000
149
150 #define FMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
151
152 /* Some offsets in PCI config space that are actually used. */
153 #define ET1310_PCI_MAC_ADDRESS 0xA4
154 #define ET1310_PCI_EEPROM_STATUS 0xB2
155 #define ET1310_PCI_ACK_NACK 0xC0
156 #define ET1310_PCI_REPLAY 0xC2
157 #define ET1310_PCI_L0L1LATENCY 0xCF
158
159 /* PCI Product IDs */
160 #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
161 #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
162
163 /* Define order of magnitude converter */
164 #define NANO_IN_A_MICRO 1000
165
166 #define PARM_RX_NUM_BUFS_DEF 4
167 #define PARM_RX_TIME_INT_DEF 10
168 #define PARM_RX_MEM_END_DEF 0x2bc
169 #define PARM_TX_TIME_INT_DEF 40
170 #define PARM_TX_NUM_BUFS_DEF 4
171 #define PARM_DMA_CACHE_DEF 0
172
173 /* RX defines */
174 #define FBR_CHUNKS 32
175 #define MAX_DESC_PER_RING_RX 1024
176
177 /* number of RFDs - default and min */
178 #define RFD_LOW_WATER_MARK 40
179 #define NIC_DEFAULT_NUM_RFD 1024
180 #define NUM_FBRS 2
181
182 #define MAX_PACKETS_HANDLED 256
183
184 #define ALCATEL_MULTICAST_PKT 0x01000000
185 #define ALCATEL_BROADCAST_PKT 0x02000000
186
187 /* typedefs for Free Buffer Descriptors */
188 struct fbr_desc {
189 u32 addr_lo;
190 u32 addr_hi;
191 u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
192 };
193
194 /* Packet Status Ring Descriptors
195 *
196 * Word 0:
197 *
198 * top 16 bits are from the Alcatel Status Word as enumerated in
199 * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
200 *
201 * 0: hp hash pass
202 * 1: ipa IP checksum assist
203 * 2: ipp IP checksum pass
204 * 3: tcpa TCP checksum assist
205 * 4: tcpp TCP checksum pass
206 * 5: wol WOL Event
207 * 6: rxmac_error RXMAC Error Indicator
208 * 7: drop Drop packet
209 * 8: ft Frame Truncated
210 * 9: jp Jumbo Packet
211 * 10: vp VLAN Packet
212 * 11-15: unused
213 * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
214 * 17: asw_RX_DV_event short receive event detected
215 * 18: asw_false_carrier_event bad carrier since last good packet
216 * 19: asw_code_err one or more nibbles signalled as errors
217 * 20: asw_CRC_err CRC error
218 * 21: asw_len_chk_err frame length field incorrect
219 * 22: asw_too_long frame length > 1518 bytes
220 * 23: asw_OK valid CRC + no code error
221 * 24: asw_multicast has a multicast address
222 * 25: asw_broadcast has a broadcast address
223 * 26: asw_dribble_nibble spurious bits after EOP
224 * 27: asw_control_frame is a control frame
225 * 28: asw_pause_frame is a pause frame
226 * 29: asw_unsupported_op unsupported OP code
227 * 30: asw_VLAN_tag VLAN tag detected
228 * 31: asw_long_evt Rx long event
229 *
230 * Word 1:
231 * 0-15: length length in bytes
232 * 16-25: bi Buffer Index
233 * 26-27: ri Ring Index
234 * 28-31: reserved
235 */
236
237 struct pkt_stat_desc {
238 u32 word0;
239 u32 word1;
240 };
241
242 /* Typedefs for the RX DMA status word */
243
244 /* rx status word 0 holds part of the status bits of the Rx DMA engine
245 * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
246 * which contains the Free Buffer ring 0 and 1 available offset.
247 *
248 * bit 0-9 FBR1 offset
249 * bit 10 Wrap flag for FBR1
250 * bit 16-25 FBR0 offset
251 * bit 26 Wrap flag for FBR0
252 */
253
254 /* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
255 * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
256 * which contains the Packet Status Ring available offset.
257 *
258 * bit 0-15 reserved
259 * bit 16-27 PSRoffset
260 * bit 28 PSRwrap
261 * bit 29-31 unused
262 */
263
264 /* struct rx_status_block is a structure representing the status of the Rx
265 * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
266 */
267 struct rx_status_block {
268 u32 word0;
269 u32 word1;
270 };
271
272 /* Structure for look-up table holding free buffer ring pointers, addresses
273 * and state.
274 */
275 struct fbr_lookup {
276 void *virt[MAX_DESC_PER_RING_RX];
277 u32 bus_high[MAX_DESC_PER_RING_RX];
278 u32 bus_low[MAX_DESC_PER_RING_RX];
279 void *ring_virtaddr;
280 dma_addr_t ring_physaddr;
281 void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
282 dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
283 u32 local_full;
284 u32 num_entries;
285 dma_addr_t buffsize;
286 };
287
288 /* struct rx_ring is the structure representing the adaptor's local
289 * reference(s) to the rings
290 */
291 struct rx_ring {
292 struct fbr_lookup *fbr[NUM_FBRS];
293 void *ps_ring_virtaddr;
294 dma_addr_t ps_ring_physaddr;
295 u32 local_psr_full;
296 u32 psr_num_entries;
297
298 struct rx_status_block *rx_status_block;
299 dma_addr_t rx_status_bus;
300
301 /* RECV */
302 struct list_head recv_list;
303 u32 num_ready_recv;
304
305 u32 num_rfd;
306
307 bool unfinished_receives;
308 };
309
310 /* TX defines */
311 /* word 2 of the control bits in the Tx Descriptor ring for the ET-1310
312 *
313 * 0-15: length of packet
314 * 16-27: VLAN tag
315 * 28: VLAN CFI
316 * 29-31: VLAN priority
317 *
318 * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
319 *
320 * 0: last packet in the sequence
321 * 1: first packet in the sequence
322 * 2: interrupt the processor when this pkt sent
323 * 3: Control word - no packet data
324 * 4: Issue half-duplex backpressure : XON/XOFF
325 * 5: send pause frame
326 * 6: Tx frame has error
327 * 7: append CRC
328 * 8: MAC override
329 * 9: pad packet
330 * 10: Packet is a Huge packet
331 * 11: append VLAN tag
332 * 12: IP checksum assist
333 * 13: TCP checksum assist
334 * 14: UDP checksum assist
335 */
336
337 #define TXDESC_FLAG_LASTPKT 0x0001
338 #define TXDESC_FLAG_FIRSTPKT 0x0002
339 #define TXDESC_FLAG_INTPROC 0x0004
340
341 /* struct tx_desc represents each descriptor on the ring */
342 struct tx_desc {
343 u32 addr_hi;
344 u32 addr_lo;
345 u32 len_vlan; /* control words how to xmit the */
346 u32 flags; /* data (detailed above) */
347 };
348
349 /* The status of the Tx DMA engine it sits in free memory, and is pointed to
350 * by 0x101c / 0x1020. This is a DMA10 type
351 */
352
353 /* TCB (Transmit Control Block: Host Side) */
354 struct tcb {
355 struct tcb *next; /* Next entry in ring */
356 u32 flags; /* Our flags for the packet */
357 u32 count; /* Used to spot stuck/lost packets */
358 u32 stale; /* Used to spot stuck/lost packets */
359 struct sk_buff *skb; /* Network skb we are tied to */
360 u32 index; /* Ring indexes */
361 u32 index_start;
362 };
363
364 /* Structure representing our local reference(s) to the ring */
365 struct tx_ring {
366 /* TCB (Transmit Control Block) memory and lists */
367 struct tcb *tcb_ring;
368
369 /* List of TCBs that are ready to be used */
370 struct tcb *tcb_qhead;
371 struct tcb *tcb_qtail;
372
373 /* list of TCBs that are currently being sent. NOTE that access to all
374 * three of these (including used) are controlled via the
375 * TCBSendQLock. This lock should be secured prior to incementing /
376 * decrementing used, or any queue manipulation on send_head /
377 * tail
378 */
379 struct tcb *send_head;
380 struct tcb *send_tail;
381 int used;
382
383 /* The actual descriptor ring */
384 struct tx_desc *tx_desc_ring;
385 dma_addr_t tx_desc_ring_pa;
386
387 /* send_idx indicates where we last wrote to in the descriptor ring. */
388 u32 send_idx;
389
390 /* The location of the write-back status block */
391 u32 *tx_status;
392 dma_addr_t tx_status_pa;
393
394 /* Packets since the last IRQ: used for interrupt coalescing */
395 int since_irq;
396 };
397
398 /* Do not change these values: if changed, then change also in respective
399 * TXdma and Rxdma engines
400 */
401 #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
402 #define NUM_TCB 64
403
404 /* These values are all superseded by registry entries to facilitate tuning.
405 * Once the desired performance has been achieved, the optimal registry values
406 * should be re-populated to these #defines:
407 */
408 #define TX_ERROR_PERIOD 1000
409
410 #define LO_MARK_PERCENT_FOR_PSR 15
411 #define LO_MARK_PERCENT_FOR_RX 15
412
413 /* RFD (Receive Frame Descriptor) */
414 struct rfd {
415 struct list_head list_node;
416 struct sk_buff *skb;
417 u32 len; /* total size of receive frame */
418 u16 bufferindex;
419 u8 ringindex;
420 };
421
422 /* Flow Control */
423 #define FLOW_BOTH 0
424 #define FLOW_TXONLY 1
425 #define FLOW_RXONLY 2
426 #define FLOW_NONE 3
427
428 /* Struct to define some device statistics */
429 struct ce_stats {
430 /* MIB II variables
431 *
432 * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
433 * MUST have 32, then we'll need another way to perform atomic
434 * operations
435 */
436 u32 unicast_pkts_rcvd;
437 atomic_t unicast_pkts_xmtd;
438 u32 multicast_pkts_rcvd;
439 atomic_t multicast_pkts_xmtd;
440 u32 broadcast_pkts_rcvd;
441 atomic_t broadcast_pkts_xmtd;
442 u32 rcvd_pkts_dropped;
443
444 /* Tx Statistics. */
445 u32 tx_underflows;
446
447 u32 tx_collisions;
448 u32 tx_excessive_collisions;
449 u32 tx_first_collisions;
450 u32 tx_late_collisions;
451 u32 tx_max_pkt_errs;
452 u32 tx_deferred;
453
454 /* Rx Statistics. */
455 u32 rx_overflows;
456
457 u32 rx_length_errs;
458 u32 rx_align_errs;
459 u32 rx_crc_errs;
460 u32 rx_code_violations;
461 u32 rx_other_errs;
462
463 u32 synchronous_iterations;
464 u32 interrupt_status;
465 };
466
467 /* The private adapter structure */
468 struct et131x_adapter {
469 struct net_device *netdev;
470 struct pci_dev *pdev;
471 struct mii_bus *mii_bus;
472 struct phy_device *phydev;
473 struct napi_struct napi;
474
475 /* Flags that indicate current state of the adapter */
476 u32 flags;
477
478 /* local link state, to determine if a state change has occurred */
479 int link;
480
481 /* Configuration */
482 u8 rom_addr[ETH_ALEN];
483 u8 addr[ETH_ALEN];
484 bool has_eeprom;
485 u8 eeprom_data[2];
486
487 /* Spinlocks */
488 spinlock_t tcb_send_qlock;
489 spinlock_t tcb_ready_qlock;
490 spinlock_t send_hw_lock;
491
492 spinlock_t rcv_lock;
493 spinlock_t fbr_lock;
494
495 /* Packet Filter and look ahead size */
496 u32 packet_filter;
497
498 /* multicast list */
499 u32 multicast_addr_count;
500 u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
501
502 /* Pointer to the device's PCI register space */
503 struct address_map __iomem *regs;
504
505 /* Registry parameters */
506 u8 wanted_flow; /* Flow we want for 802.3x flow control */
507 u32 registry_jumbo_packet; /* Max supported ethernet packet size */
508
509 /* Derived from the registry: */
510 u8 flowcontrol; /* flow control validated by the far-end */
511
512 /* Minimize init-time */
513 struct timer_list error_timer;
514
515 /* variable putting the phy into coma mode when boot up with no cable
516 * plugged in after 5 seconds
517 */
518 u8 boot_coma;
519
520 /* Next two used to save power information at power down. This
521 * information will be used during power up to set up parts of Power
522 * Management in JAGCore
523 */
524 u16 pdown_speed;
525 u8 pdown_duplex;
526
527 /* Tx Memory Variables */
528 struct tx_ring tx_ring;
529
530 /* Rx Memory Variables */
531 struct rx_ring rx_ring;
532
533 /* Stats */
534 struct ce_stats stats;
535 };
536
537 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
538 {
539 u32 reg;
540 int i;
541
542 /* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
543 * bits 7,1:0 both equal to 1, at least once after reset.
544 * Subsequent operations need only to check that bits 1:0 are equal
545 * to 1 prior to starting a single byte read/write
546 */
547
548 for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
549 /* Read registers grouped in DWORD1 */
550 if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, &reg))
551 return -EIO;
552
553 /* I2C idle and Phy Queue Avail both true */
554 if ((reg & 0x3000) == 0x3000) {
555 if (status)
556 *status = reg;
557 return reg & 0xFF;
558 }
559 }
560 return -ETIMEDOUT;
561 }
562
563 /* eeprom_write - Write a byte to the ET1310's EEPROM
564 * @adapter: pointer to our private adapter structure
565 * @addr: the address to write
566 * @data: the value to write
567 *
568 * Returns 1 for a successful write.
569 */
570 static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
571 {
572 struct pci_dev *pdev = adapter->pdev;
573 int index = 0;
574 int retries;
575 int err = 0;
576 int writeok = 0;
577 u32 status;
578 u32 val = 0;
579
580 /* For an EEPROM, an I2C single byte write is defined as a START
581 * condition followed by the device address, EEPROM address, one byte
582 * of data and a STOP condition. The STOP condition will trigger the
583 * EEPROM's internally timed write cycle to the nonvolatile memory.
584 * All inputs are disabled during this write cycle and the EEPROM will
585 * not respond to any access until the internal write is complete.
586 */
587
588 err = eeprom_wait_ready(pdev, NULL);
589 if (err < 0)
590 return err;
591
592 /* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
593 * and bits 1:0 both =0. Bit 5 should be set according to the
594 * type of EEPROM being accessed (1=two byte addressing, 0=one
595 * byte addressing).
596 */
597 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
598 LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
599 return -EIO;
600
601 /* Prepare EEPROM address for Step 3 */
602
603 for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
604 /* Write the address to the LBCIF Address Register */
605 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
606 break;
607 /* Write the data to the LBCIF Data Register (the I2C write
608 * will begin).
609 */
610 if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
611 break;
612 /* Monitor bit 1:0 of the LBCIF Status Register. When bits
613 * 1:0 are both equal to 1, the I2C write has completed and the
614 * internal write cycle of the EEPROM is about to start.
615 * (bits 1:0 = 01 is a legal state while waiting from both
616 * equal to 1, but bits 1:0 = 10 is invalid and implies that
617 * something is broken).
618 */
619 err = eeprom_wait_ready(pdev, &status);
620 if (err < 0)
621 return 0;
622
623 /* Check bit 3 of the LBCIF Status Register. If equal to 1,
624 * an error has occurred.Don't break here if we are revision
625 * 1, this is so we do a blind write for load bug.
626 */
627 if ((status & LBCIF_STATUS_GENERAL_ERROR)
628 && adapter->pdev->revision == 0)
629 break;
630
631 /* Check bit 2 of the LBCIF Status Register. If equal to 1 an
632 * ACK error has occurred on the address phase of the write.
633 * This could be due to an actual hardware failure or the
634 * EEPROM may still be in its internal write cycle from a
635 * previous write. This write operation was ignored and must be
636 *repeated later.
637 */
638 if (status & LBCIF_STATUS_ACK_ERROR) {
639 /* This could be due to an actual hardware failure
640 * or the EEPROM may still be in its internal write
641 * cycle from a previous write. This write operation
642 * was ignored and must be repeated later.
643 */
644 udelay(10);
645 continue;
646 }
647
648 writeok = 1;
649 break;
650 }
651
652 /* Set bit 6 of the LBCIF Control Register = 0.
653 */
654 udelay(10);
655
656 while (1) {
657 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
658 LBCIF_CONTROL_LBCIF_ENABLE))
659 writeok = 0;
660
661 /* Do read until internal ACK_ERROR goes away meaning write
662 * completed
663 */
664 do {
665 pci_write_config_dword(pdev,
666 LBCIF_ADDRESS_REGISTER,
667 addr);
668 do {
669 pci_read_config_dword(pdev,
670 LBCIF_DATA_REGISTER, &val);
671 } while ((val & 0x00010000) == 0);
672 } while (val & 0x00040000);
673
674 if ((val & 0xFF00) != 0xC000 || index == 10000)
675 break;
676 index++;
677 }
678 return writeok ? 0 : -EIO;
679 }
680
681 /* eeprom_read - Read a byte from the ET1310's EEPROM
682 * @adapter: pointer to our private adapter structure
683 * @addr: the address from which to read
684 * @pdata: a pointer to a byte in which to store the value of the read
685 * @eeprom_id: the ID of the EEPROM
686 * @addrmode: how the EEPROM is to be accessed
687 *
688 * Returns 1 for a successful read
689 */
690 static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
691 {
692 struct pci_dev *pdev = adapter->pdev;
693 int err;
694 u32 status;
695
696 /* A single byte read is similar to the single byte write, with the
697 * exception of the data flow:
698 */
699
700 err = eeprom_wait_ready(pdev, NULL);
701 if (err < 0)
702 return err;
703 /* Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
704 * and bits 1:0 both =0. Bit 5 should be set according to the type
705 * of EEPROM being accessed (1=two byte addressing, 0=one byte
706 * addressing).
707 */
708 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
709 LBCIF_CONTROL_LBCIF_ENABLE))
710 return -EIO;
711 /* Write the address to the LBCIF Address Register (I2C read will
712 * begin).
713 */
714 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
715 return -EIO;
716 /* Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
717 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
718 * has occurred).
719 */
720 err = eeprom_wait_ready(pdev, &status);
721 if (err < 0)
722 return err;
723 /* Regardless of error status, read data byte from LBCIF Data
724 * Register.
725 */
726 *pdata = err;
727 /* Check bit 2 of the LBCIF Status Register. If = 1,
728 * then an error has occurred.
729 */
730 return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
731 }
732
733 static int et131x_init_eeprom(struct et131x_adapter *adapter)
734 {
735 struct pci_dev *pdev = adapter->pdev;
736 u8 eestatus;
737
738 /* We first need to check the EEPROM Status code located at offset
739 * 0xB2 of config space
740 */
741 pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus);
742
743 /* THIS IS A WORKAROUND:
744 * I need to call this function twice to get my card in a
745 * LG M1 Express Dual running. I tried also a msleep before this
746 * function, because I thought there could be some time conditions
747 * but it didn't work. Call the whole function twice also work.
748 */
749 if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
750 dev_err(&pdev->dev,
751 "Could not read PCI config space for EEPROM Status\n");
752 return -EIO;
753 }
754
755 /* Determine if the error(s) we care about are present. If they are
756 * present we need to fail.
757 */
758 if (eestatus & 0x4C) {
759 int write_failed = 0;
760
761 if (pdev->revision == 0x01) {
762 int i;
763 static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
764
765 /* Re-write the first 4 bytes if we have an eeprom
766 * present and the revision id is 1, this fixes the
767 * corruption seen with 1310 B Silicon
768 */
769 for (i = 0; i < 3; i++)
770 if (eeprom_write(adapter, i, eedata[i]) < 0)
771 write_failed = 1;
772 }
773 if (pdev->revision != 0x01 || write_failed) {
774 dev_err(&pdev->dev,
775 "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
776
777 /* This error could mean that there was an error
778 * reading the eeprom or that the eeprom doesn't exist.
779 * We will treat each case the same and not try to
780 * gather additional information that normally would
781 * come from the eeprom, like MAC Address
782 */
783 adapter->has_eeprom = 0;
784 return -EIO;
785 }
786 }
787 adapter->has_eeprom = 1;
788
789 /* Read the EEPROM for information regarding LED behavior. Refer to
790 * ET1310_phy.c, et131x_xcvr_init(), for its use.
791 */
792 eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
793 eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
794
795 if (adapter->eeprom_data[0] != 0xcd)
796 /* Disable all optional features */
797 adapter->eeprom_data[1] = 0x00;
798
799 return 0;
800 }
801
802 /* et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
803 * @adapter: pointer to our adapter structure
804 */
805 static void et131x_rx_dma_enable(struct et131x_adapter *adapter)
806 {
807 /* Setup the receive dma configuration register for normal operation */
808 u32 csr = ET_RXDMA_CSR_FBR1_ENABLE;
809 struct rx_ring *rx_ring = &adapter->rx_ring;
810
811 if (rx_ring->fbr[1]->buffsize == 4096)
812 csr |= ET_RXDMA_CSR_FBR1_SIZE_LO;
813 else if (rx_ring->fbr[1]->buffsize == 8192)
814 csr |= ET_RXDMA_CSR_FBR1_SIZE_HI;
815 else if (rx_ring->fbr[1]->buffsize == 16384)
816 csr |= ET_RXDMA_CSR_FBR1_SIZE_LO | ET_RXDMA_CSR_FBR1_SIZE_HI;
817
818 csr |= ET_RXDMA_CSR_FBR0_ENABLE;
819 if (rx_ring->fbr[0]->buffsize == 256)
820 csr |= ET_RXDMA_CSR_FBR0_SIZE_LO;
821 else if (rx_ring->fbr[0]->buffsize == 512)
822 csr |= ET_RXDMA_CSR_FBR0_SIZE_HI;
823 else if (rx_ring->fbr[0]->buffsize == 1024)
824 csr |= ET_RXDMA_CSR_FBR0_SIZE_LO | ET_RXDMA_CSR_FBR0_SIZE_HI;
825 writel(csr, &adapter->regs->rxdma.csr);
826
827 csr = readl(&adapter->regs->rxdma.csr);
828 if (csr & ET_RXDMA_CSR_HALT_STATUS) {
829 udelay(5);
830 csr = readl(&adapter->regs->rxdma.csr);
831 if (csr & ET_RXDMA_CSR_HALT_STATUS) {
832 dev_err(&adapter->pdev->dev,
833 "RX Dma failed to exit halt state. CSR 0x%08x\n",
834 csr);
835 }
836 }
837 }
838
839 /* et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
840 * @adapter: pointer to our adapter structure
841 */
842 static void et131x_rx_dma_disable(struct et131x_adapter *adapter)
843 {
844 u32 csr;
845 /* Setup the receive dma configuration register */
846 writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE,
847 &adapter->regs->rxdma.csr);
848 csr = readl(&adapter->regs->rxdma.csr);
849 if (!(csr & ET_RXDMA_CSR_HALT_STATUS)) {
850 udelay(5);
851 csr = readl(&adapter->regs->rxdma.csr);
852 if (!(csr & ET_RXDMA_CSR_HALT_STATUS))
853 dev_err(&adapter->pdev->dev,
854 "RX Dma failed to enter halt state. CSR 0x%08x\n",
855 csr);
856 }
857 }
858
859 /* et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
860 * @adapter: pointer to our adapter structure
861 *
862 * Mainly used after a return to the D0 (full-power) state from a lower state.
863 */
864 static void et131x_tx_dma_enable(struct et131x_adapter *adapter)
865 {
866 /* Setup the transmit dma configuration register for normal
867 * operation
868 */
869 writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
870 &adapter->regs->txdma.csr);
871 }
872
873 static inline void add_10bit(u32 *v, int n)
874 {
875 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
876 }
877
878 static inline void add_12bit(u32 *v, int n)
879 {
880 *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
881 }
882
883 /* et1310_config_mac_regs1 - Initialize the first part of MAC regs
884 * @adapter: pointer to our adapter structure
885 */
886 static void et1310_config_mac_regs1(struct et131x_adapter *adapter)
887 {
888 struct mac_regs __iomem *macregs = &adapter->regs->mac;
889 u32 station1;
890 u32 station2;
891 u32 ipg;
892
893 /* First we need to reset everything. Write to MAC configuration
894 * register 1 to perform reset.
895 */
896 writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
897 ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
898 ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC,
899 &macregs->cfg1);
900
901 /* Next lets configure the MAC Inter-packet gap register */
902 ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
903 ipg |= 0x50 << 8; /* ifg enforce 0x50 */
904 writel(ipg, &macregs->ipg);
905
906 /* Next lets configure the MAC Half Duplex register */
907 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
908 writel(0x00A1F037, &macregs->hfdp);
909
910 /* Next lets configure the MAC Interface Control register */
911 writel(0, &macregs->if_ctrl);
912
913 /* Let's move on to setting up the mii management configuration */
914 writel(ET_MAC_MIIMGMT_CLK_RST, &macregs->mii_mgmt_cfg);
915
916 /* Next lets configure the MAC Station Address register. These
917 * values are read from the EEPROM during initialization and stored
918 * in the adapter structure. We write what is stored in the adapter
919 * structure to the MAC Station Address registers high and low. This
920 * station address is used for generating and checking pause control
921 * packets.
922 */
923 station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
924 (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
925 station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
926 (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
927 (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
928 adapter->addr[2];
929 writel(station1, &macregs->station_addr_1);
930 writel(station2, &macregs->station_addr_2);
931
932 /* Max ethernet packet in bytes that will be passed by the mac without
933 * being truncated. Allow the MAC to pass 4 more than our max packet
934 * size. This is 4 for the Ethernet CRC.
935 *
936 * Packets larger than (registry_jumbo_packet) that do not contain a
937 * VLAN ID will be dropped by the Rx function.
938 */
939 writel(adapter->registry_jumbo_packet + 4, &macregs->max_fm_len);
940
941 /* clear out MAC config reset */
942 writel(0, &macregs->cfg1);
943 }
944
945 /* et1310_config_mac_regs2 - Initialize the second part of MAC regs
946 * @adapter: pointer to our adapter structure
947 */
948 static void et1310_config_mac_regs2(struct et131x_adapter *adapter)
949 {
950 int32_t delay = 0;
951 struct mac_regs __iomem *mac = &adapter->regs->mac;
952 struct phy_device *phydev = adapter->phydev;
953 u32 cfg1;
954 u32 cfg2;
955 u32 ifctrl;
956 u32 ctl;
957
958 ctl = readl(&adapter->regs->txmac.ctl);
959 cfg1 = readl(&mac->cfg1);
960 cfg2 = readl(&mac->cfg2);
961 ifctrl = readl(&mac->if_ctrl);
962
963 /* Set up the if mode bits */
964 cfg2 &= ~ET_MAC_CFG2_IFMODE_MASK;
965 if (phydev->speed == SPEED_1000) {
966 cfg2 |= ET_MAC_CFG2_IFMODE_1000;
967 /* Phy mode bit */
968 ifctrl &= ~ET_MAC_IFCTRL_PHYMODE;
969 } else {
970 cfg2 |= ET_MAC_CFG2_IFMODE_100;
971 ifctrl |= ET_MAC_IFCTRL_PHYMODE;
972 }
973
974 /* We need to enable Rx/Tx */
975 cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE |
976 ET_MAC_CFG1_TX_FLOW;
977 /* Initialize loop back to off */
978 cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW);
979 if (adapter->flowcontrol == FLOW_RXONLY ||
980 adapter->flowcontrol == FLOW_BOTH)
981 cfg1 |= ET_MAC_CFG1_RX_FLOW;
982 writel(cfg1, &mac->cfg1);
983
984 /* Now we need to initialize the MAC Configuration 2 register */
985 /* preamble 7, check length, huge frame off, pad crc, crc enable
986 * full duplex off
987 */
988 cfg2 |= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT;
989 cfg2 |= ET_MAC_CFG2_IFMODE_LEN_CHECK;
990 cfg2 |= ET_MAC_CFG2_IFMODE_PAD_CRC;
991 cfg2 |= ET_MAC_CFG2_IFMODE_CRC_ENABLE;
992 cfg2 &= ~ET_MAC_CFG2_IFMODE_HUGE_FRAME;
993 cfg2 &= ~ET_MAC_CFG2_IFMODE_FULL_DPLX;
994
995 /* Turn on duplex if needed */
996 if (phydev->duplex == DUPLEX_FULL)
997 cfg2 |= ET_MAC_CFG2_IFMODE_FULL_DPLX;
998
999 ifctrl &= ~ET_MAC_IFCTRL_GHDMODE;
1000 if (phydev->duplex == DUPLEX_HALF)
1001 ifctrl |= ET_MAC_IFCTRL_GHDMODE;
1002
1003 writel(ifctrl, &mac->if_ctrl);
1004 writel(cfg2, &mac->cfg2);
1005
1006 do {
1007 udelay(10);
1008 delay++;
1009 cfg1 = readl(&mac->cfg1);
1010 } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100);
1011
1012 if (delay == 100) {
1013 dev_warn(&adapter->pdev->dev,
1014 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
1015 cfg1);
1016 }
1017
1018 /* Enable txmac */
1019 ctl |= ET_TX_CTRL_TXMAC_ENABLE | ET_TX_CTRL_FC_DISABLE;
1020 writel(ctl, &adapter->regs->txmac.ctl);
1021
1022 /* Ready to start the RXDMA/TXDMA engine */
1023 if (adapter->flags & FMP_ADAPTER_LOWER_POWER) {
1024 et131x_rx_dma_enable(adapter);
1025 et131x_tx_dma_enable(adapter);
1026 }
1027 }
1028
1029 /* et1310_in_phy_coma - check if the device is in phy coma
1030 * @adapter: pointer to our adapter structure
1031 *
1032 * Returns 0 if the device is not in phy coma, 1 if it is in phy coma
1033 */
1034 static int et1310_in_phy_coma(struct et131x_adapter *adapter)
1035 {
1036 u32 pmcsr = readl(&adapter->regs->global.pm_csr);
1037
1038 return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
1039 }
1040
1041 static void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
1042 {
1043 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1044 u32 hash1 = 0;
1045 u32 hash2 = 0;
1046 u32 hash3 = 0;
1047 u32 hash4 = 0;
1048 u32 pm_csr;
1049
1050 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
1051 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
1052 * specified) then we should pass NO multi-cast addresses to the
1053 * driver.
1054 */
1055 if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) {
1056 int i;
1057
1058 /* Loop through our multicast array and set up the device */
1059 for (i = 0; i < adapter->multicast_addr_count; i++) {
1060 u32 result;
1061
1062 result = ether_crc(6, adapter->multicast_list[i]);
1063
1064 result = (result & 0x3F800000) >> 23;
1065
1066 if (result < 32) {
1067 hash1 |= (1 << result);
1068 } else if ((31 < result) && (result < 64)) {
1069 result -= 32;
1070 hash2 |= (1 << result);
1071 } else if ((63 < result) && (result < 96)) {
1072 result -= 64;
1073 hash3 |= (1 << result);
1074 } else {
1075 result -= 96;
1076 hash4 |= (1 << result);
1077 }
1078 }
1079 }
1080
1081 /* Write out the new hash to the device */
1082 pm_csr = readl(&adapter->regs->global.pm_csr);
1083 if (!et1310_in_phy_coma(adapter)) {
1084 writel(hash1, &rxmac->multi_hash1);
1085 writel(hash2, &rxmac->multi_hash2);
1086 writel(hash3, &rxmac->multi_hash3);
1087 writel(hash4, &rxmac->multi_hash4);
1088 }
1089 }
1090
1091 static void et1310_setup_device_for_unicast(struct et131x_adapter *adapter)
1092 {
1093 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1094 u32 uni_pf1;
1095 u32 uni_pf2;
1096 u32 uni_pf3;
1097 u32 pm_csr;
1098
1099 /* Set up unicast packet filter reg 3 to be the first two octets of
1100 * the MAC address for both address
1101 *
1102 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
1103 * MAC address for second address
1104 *
1105 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
1106 * MAC address for first address
1107 */
1108 uni_pf3 = (adapter->addr[0] << ET_RX_UNI_PF_ADDR2_1_SHIFT) |
1109 (adapter->addr[1] << ET_RX_UNI_PF_ADDR2_2_SHIFT) |
1110 (adapter->addr[0] << ET_RX_UNI_PF_ADDR1_1_SHIFT) |
1111 adapter->addr[1];
1112
1113 uni_pf2 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR2_3_SHIFT) |
1114 (adapter->addr[3] << ET_RX_UNI_PF_ADDR2_4_SHIFT) |
1115 (adapter->addr[4] << ET_RX_UNI_PF_ADDR2_5_SHIFT) |
1116 adapter->addr[5];
1117
1118 uni_pf1 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR1_3_SHIFT) |
1119 (adapter->addr[3] << ET_RX_UNI_PF_ADDR1_4_SHIFT) |
1120 (adapter->addr[4] << ET_RX_UNI_PF_ADDR1_5_SHIFT) |
1121 adapter->addr[5];
1122
1123 pm_csr = readl(&adapter->regs->global.pm_csr);
1124 if (!et1310_in_phy_coma(adapter)) {
1125 writel(uni_pf1, &rxmac->uni_pf_addr1);
1126 writel(uni_pf2, &rxmac->uni_pf_addr2);
1127 writel(uni_pf3, &rxmac->uni_pf_addr3);
1128 }
1129 }
1130
1131 static void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
1132 {
1133 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1134 struct phy_device *phydev = adapter->phydev;
1135 u32 sa_lo;
1136 u32 sa_hi = 0;
1137 u32 pf_ctrl = 0;
1138 u32 __iomem *wolw;
1139
1140 /* Disable the MAC while it is being configured (also disable WOL) */
1141 writel(0x8, &rxmac->ctrl);
1142
1143 /* Initialize WOL to disabled. */
1144 writel(0, &rxmac->crc0);
1145 writel(0, &rxmac->crc12);
1146 writel(0, &rxmac->crc34);
1147
1148 /* We need to set the WOL mask0 - mask4 next. We initialize it to
1149 * its default Values of 0x00000000 because there are not WOL masks
1150 * as of this time.
1151 */
1152 for (wolw = &rxmac->mask0_word0; wolw <= &rxmac->mask4_word3; wolw++)
1153 writel(0, wolw);
1154
1155 /* Lets setup the WOL Source Address */
1156 sa_lo = (adapter->addr[2] << ET_RX_WOL_LO_SA3_SHIFT) |
1157 (adapter->addr[3] << ET_RX_WOL_LO_SA4_SHIFT) |
1158 (adapter->addr[4] << ET_RX_WOL_LO_SA5_SHIFT) |
1159 adapter->addr[5];
1160 writel(sa_lo, &rxmac->sa_lo);
1161
1162 sa_hi = (u32) (adapter->addr[0] << ET_RX_WOL_HI_SA1_SHIFT) |
1163 adapter->addr[1];
1164 writel(sa_hi, &rxmac->sa_hi);
1165
1166 /* Disable all Packet Filtering */
1167 writel(0, &rxmac->pf_ctrl);
1168
1169 /* Let's initialize the Unicast Packet filtering address */
1170 if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
1171 et1310_setup_device_for_unicast(adapter);
1172 pf_ctrl |= ET_RX_PFCTRL_UNICST_FILTER_ENABLE;
1173 } else {
1174 writel(0, &rxmac->uni_pf_addr1);
1175 writel(0, &rxmac->uni_pf_addr2);
1176 writel(0, &rxmac->uni_pf_addr3);
1177 }
1178
1179 /* Let's initialize the Multicast hash */
1180 if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
1181 pf_ctrl |= ET_RX_PFCTRL_MLTCST_FILTER_ENABLE;
1182 et1310_setup_device_for_multicast(adapter);
1183 }
1184
1185 /* Runt packet filtering. Didn't work in version A silicon. */
1186 pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT;
1187 pf_ctrl |= ET_RX_PFCTRL_FRAG_FILTER_ENABLE;
1188
1189 if (adapter->registry_jumbo_packet > 8192)
1190 /* In order to transmit jumbo packets greater than 8k, the
1191 * FIFO between RxMAC and RxDMA needs to be reduced in size
1192 * to (16k - Jumbo packet size). In order to implement this,
1193 * we must use "cut through" mode in the RxMAC, which chops
1194 * packets down into segments which are (max_size * 16). In
1195 * this case we selected 256 bytes, since this is the size of
1196 * the PCI-Express TLP's that the 1310 uses.
1197 *
1198 * seg_en on, fc_en off, size 0x10
1199 */
1200 writel(0x41, &rxmac->mcif_ctrl_max_seg);
1201 else
1202 writel(0, &rxmac->mcif_ctrl_max_seg);
1203
1204 /* Initialize the MCIF water marks */
1205 writel(0, &rxmac->mcif_water_mark);
1206
1207 /* Initialize the MIF control */
1208 writel(0, &rxmac->mif_ctrl);
1209
1210 /* Initialize the Space Available Register */
1211 writel(0, &rxmac->space_avail);
1212
1213 /* Initialize the the mif_ctrl register
1214 * bit 3: Receive code error. One or more nibbles were signaled as
1215 * errors during the reception of the packet. Clear this
1216 * bit in Gigabit, set it in 100Mbit. This was derived
1217 * experimentally at UNH.
1218 * bit 4: Receive CRC error. The packet's CRC did not match the
1219 * internally generated CRC.
1220 * bit 5: Receive length check error. Indicates that frame length
1221 * field value in the packet does not match the actual data
1222 * byte length and is not a type field.
1223 * bit 16: Receive frame truncated.
1224 * bit 17: Drop packet enable
1225 */
1226 if (phydev && phydev->speed == SPEED_100)
1227 writel(0x30038, &rxmac->mif_ctrl);
1228 else
1229 writel(0x30030, &rxmac->mif_ctrl);
1230
1231 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
1232 * filter is always enabled since it is where the runt packets are
1233 * supposed to be dropped. For version A silicon, runt packet
1234 * dropping doesn't work, so it is disabled in the pf_ctrl register,
1235 * but we still leave the packet filter on.
1236 */
1237 writel(pf_ctrl, &rxmac->pf_ctrl);
1238 writel(ET_RX_CTRL_RXMAC_ENABLE | ET_RX_CTRL_WOL_DISABLE, &rxmac->ctrl);
1239 }
1240
1241 static void et1310_config_txmac_regs(struct et131x_adapter *adapter)
1242 {
1243 struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
1244
1245 /* We need to update the Control Frame Parameters
1246 * cfpt - control frame pause timer set to 64 (0x40)
1247 * cfep - control frame extended pause timer set to 0x0
1248 */
1249 if (adapter->flowcontrol == FLOW_NONE)
1250 writel(0, &txmac->cf_param);
1251 else
1252 writel(0x40, &txmac->cf_param);
1253 }
1254
1255 static void et1310_config_macstat_regs(struct et131x_adapter *adapter)
1256 {
1257 struct macstat_regs __iomem *macstat = &adapter->regs->macstat;
1258 u32 __iomem *reg;
1259
1260 /* initialize all the macstat registers to zero on the device */
1261 for (reg = &macstat->txrx_0_64_byte_frames;
1262 reg <= &macstat->carry_reg2; reg++)
1263 writel(0, reg);
1264
1265 /* Unmask any counters that we want to track the overflow of.
1266 * Initially this will be all counters. It may become clear later
1267 * that we do not need to track all counters.
1268 */
1269 writel(0xFFFFBE32, &macstat->carry_reg1_mask);
1270 writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
1271 }
1272
1273 /* et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
1274 * @adapter: pointer to our private adapter structure
1275 * @addr: the address of the transceiver
1276 * @reg: the register to read
1277 * @value: pointer to a 16-bit value in which the value will be stored
1278 */
1279 static int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
1280 u8 reg, u16 *value)
1281 {
1282 struct mac_regs __iomem *mac = &adapter->regs->mac;
1283 int status = 0;
1284 u32 delay = 0;
1285 u32 mii_addr;
1286 u32 mii_cmd;
1287 u32 mii_indicator;
1288
1289 /* Save a local copy of the registers we are dealing with so we can
1290 * set them back
1291 */
1292 mii_addr = readl(&mac->mii_mgmt_addr);
1293 mii_cmd = readl(&mac->mii_mgmt_cmd);
1294
1295 /* Stop the current operation */
1296 writel(0, &mac->mii_mgmt_cmd);
1297
1298 /* Set up the register we need to read from on the correct PHY */
1299 writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1300
1301 writel(0x1, &mac->mii_mgmt_cmd);
1302
1303 do {
1304 udelay(50);
1305 delay++;
1306 mii_indicator = readl(&mac->mii_mgmt_indicator);
1307 } while ((mii_indicator & ET_MAC_MGMT_WAIT) && delay < 50);
1308
1309 /* If we hit the max delay, we could not read the register */
1310 if (delay == 50) {
1311 dev_warn(&adapter->pdev->dev,
1312 "reg 0x%08x could not be read\n", reg);
1313 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1314 mii_indicator);
1315
1316 status = -EIO;
1317 goto out;
1318 }
1319
1320 /* If we hit here we were able to read the register and we need to
1321 * return the value to the caller
1322 */
1323 *value = readl(&mac->mii_mgmt_stat) & ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK;
1324
1325 out:
1326 /* Stop the read operation */
1327 writel(0, &mac->mii_mgmt_cmd);
1328
1329 /* set the registers we touched back to the state at which we entered
1330 * this function
1331 */
1332 writel(mii_addr, &mac->mii_mgmt_addr);
1333 writel(mii_cmd, &mac->mii_mgmt_cmd);
1334
1335 return status;
1336 }
1337
1338 static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
1339 {
1340 struct phy_device *phydev = adapter->phydev;
1341
1342 if (!phydev)
1343 return -EIO;
1344
1345 return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
1346 }
1347
1348 /* et131x_mii_write - Write to a PHY reg through the MII interface of the MAC
1349 * @adapter: pointer to our private adapter structure
1350 * @reg: the register to read
1351 * @value: 16-bit value to write
1352 */
1353 static int et131x_mii_write(struct et131x_adapter *adapter, u8 addr, u8 reg,
1354 u16 value)
1355 {
1356 struct mac_regs __iomem *mac = &adapter->regs->mac;
1357 int status = 0;
1358 u32 delay = 0;
1359 u32 mii_addr;
1360 u32 mii_cmd;
1361 u32 mii_indicator;
1362
1363 /* Save a local copy of the registers we are dealing with so we can
1364 * set them back
1365 */
1366 mii_addr = readl(&mac->mii_mgmt_addr);
1367 mii_cmd = readl(&mac->mii_mgmt_cmd);
1368
1369 /* Stop the current operation */
1370 writel(0, &mac->mii_mgmt_cmd);
1371
1372 /* Set up the register we need to write to on the correct PHY */
1373 writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1374
1375 /* Add the value to write to the registers to the mac */
1376 writel(value, &mac->mii_mgmt_ctrl);
1377
1378 do {
1379 udelay(50);
1380 delay++;
1381 mii_indicator = readl(&mac->mii_mgmt_indicator);
1382 } while ((mii_indicator & ET_MAC_MGMT_BUSY) && delay < 100);
1383
1384 /* If we hit the max delay, we could not write the register */
1385 if (delay == 100) {
1386 u16 tmp;
1387
1388 dev_warn(&adapter->pdev->dev,
1389 "reg 0x%08x could not be written", reg);
1390 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1391 mii_indicator);
1392 dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
1393 readl(&mac->mii_mgmt_cmd));
1394
1395 et131x_mii_read(adapter, reg, &tmp);
1396
1397 status = -EIO;
1398 }
1399 /* Stop the write operation */
1400 writel(0, &mac->mii_mgmt_cmd);
1401
1402 /* set the registers we touched back to the state at which we entered
1403 * this function
1404 */
1405 writel(mii_addr, &mac->mii_mgmt_addr);
1406 writel(mii_cmd, &mac->mii_mgmt_cmd);
1407
1408 return status;
1409 }
1410
1411 static void et1310_phy_read_mii_bit(struct et131x_adapter *adapter,
1412 u16 regnum,
1413 u16 bitnum,
1414 u8 *value)
1415 {
1416 u16 reg;
1417 u16 mask = 1 << bitnum;
1418
1419 /* Read the requested register */
1420 et131x_mii_read(adapter, regnum, &reg);
1421
1422 *value = (reg & mask) >> bitnum;
1423 }
1424
1425 static void et1310_config_flow_control(struct et131x_adapter *adapter)
1426 {
1427 struct phy_device *phydev = adapter->phydev;
1428
1429 if (phydev->duplex == DUPLEX_HALF) {
1430 adapter->flowcontrol = FLOW_NONE;
1431 } else {
1432 char remote_pause, remote_async_pause;
1433
1434 et1310_phy_read_mii_bit(adapter, 5, 10, &remote_pause);
1435 et1310_phy_read_mii_bit(adapter, 5, 11, &remote_async_pause);
1436
1437 if (remote_pause && remote_async_pause) {
1438 adapter->flowcontrol = adapter->wanted_flow;
1439 } else if (remote_pause && !remote_async_pause) {
1440 if (adapter->wanted_flow == FLOW_BOTH)
1441 adapter->flowcontrol = FLOW_BOTH;
1442 else
1443 adapter->flowcontrol = FLOW_NONE;
1444 } else if (!remote_pause && !remote_async_pause) {
1445 adapter->flowcontrol = FLOW_NONE;
1446 } else {
1447 if (adapter->wanted_flow == FLOW_BOTH)
1448 adapter->flowcontrol = FLOW_RXONLY;
1449 else
1450 adapter->flowcontrol = FLOW_NONE;
1451 }
1452 }
1453 }
1454
1455 /* et1310_update_macstat_host_counters - Update local copy of the statistics */
1456 static void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
1457 {
1458 struct ce_stats *stats = &adapter->stats;
1459 struct macstat_regs __iomem *macstat =
1460 &adapter->regs->macstat;
1461
1462 stats->tx_collisions += readl(&macstat->tx_total_collisions);
1463 stats->tx_first_collisions += readl(&macstat->tx_single_collisions);
1464 stats->tx_deferred += readl(&macstat->tx_deferred);
1465 stats->tx_excessive_collisions +=
1466 readl(&macstat->tx_multiple_collisions);
1467 stats->tx_late_collisions += readl(&macstat->tx_late_collisions);
1468 stats->tx_underflows += readl(&macstat->tx_undersize_frames);
1469 stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames);
1470
1471 stats->rx_align_errs += readl(&macstat->rx_align_errs);
1472 stats->rx_crc_errs += readl(&macstat->rx_code_errs);
1473 stats->rcvd_pkts_dropped += readl(&macstat->rx_drops);
1474 stats->rx_overflows += readl(&macstat->rx_oversize_packets);
1475 stats->rx_code_violations += readl(&macstat->rx_fcs_errs);
1476 stats->rx_length_errs += readl(&macstat->rx_frame_len_errs);
1477 stats->rx_other_errs += readl(&macstat->rx_fragment_packets);
1478 }
1479
1480 /* et1310_handle_macstat_interrupt
1481 *
1482 * One of the MACSTAT counters has wrapped. Update the local copy of
1483 * the statistics held in the adapter structure, checking the "wrap"
1484 * bit for each counter.
1485 */
1486 static void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter)
1487 {
1488 u32 carry_reg1;
1489 u32 carry_reg2;
1490
1491 /* Read the interrupt bits from the register(s). These are Clear On
1492 * Write.
1493 */
1494 carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);
1495 carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);
1496
1497 writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
1498 writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
1499
1500 /* We need to do update the host copy of all the MAC_STAT counters.
1501 * For each counter, check it's overflow bit. If the overflow bit is
1502 * set, then increment the host version of the count by one complete
1503 * revolution of the counter. This routine is called when the counter
1504 * block indicates that one of the counters has wrapped.
1505 */
1506 if (carry_reg1 & (1 << 14))
1507 adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT;
1508 if (carry_reg1 & (1 << 8))
1509 adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT;
1510 if (carry_reg1 & (1 << 7))
1511 adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT;
1512 if (carry_reg1 & (1 << 2))
1513 adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT;
1514 if (carry_reg1 & (1 << 6))
1515 adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT;
1516 if (carry_reg1 & (1 << 3))
1517 adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT;
1518 if (carry_reg1 & (1 << 0))
1519 adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT;
1520 if (carry_reg2 & (1 << 16))
1521 adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT;
1522 if (carry_reg2 & (1 << 15))
1523 adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT;
1524 if (carry_reg2 & (1 << 6))
1525 adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT;
1526 if (carry_reg2 & (1 << 8))
1527 adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT;
1528 if (carry_reg2 & (1 << 5))
1529 adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT;
1530 if (carry_reg2 & (1 << 4))
1531 adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT;
1532 if (carry_reg2 & (1 << 2))
1533 adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT;
1534 }
1535
1536 static int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
1537 {
1538 struct net_device *netdev = bus->priv;
1539 struct et131x_adapter *adapter = netdev_priv(netdev);
1540 u16 value;
1541 int ret;
1542
1543 ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
1544
1545 if (ret < 0)
1546 return ret;
1547 else
1548 return value;
1549 }
1550
1551 static int et131x_mdio_write(struct mii_bus *bus, int phy_addr,
1552 int reg, u16 value)
1553 {
1554 struct net_device *netdev = bus->priv;
1555 struct et131x_adapter *adapter = netdev_priv(netdev);
1556
1557 return et131x_mii_write(adapter, phy_addr, reg, value);
1558 }
1559
1560 /* et1310_phy_power_switch - PHY power control
1561 * @adapter: device to control
1562 * @down: true for off/false for back on
1563 *
1564 * one hundred, ten, one thousand megs
1565 * How would you like to have your LAN accessed
1566 * Can't you see that this code processed
1567 * Phy power, phy power..
1568 */
1569 static void et1310_phy_power_switch(struct et131x_adapter *adapter, bool down)
1570 {
1571 u16 data;
1572 struct phy_device *phydev = adapter->phydev;
1573
1574 et131x_mii_read(adapter, MII_BMCR, &data);
1575 data &= ~BMCR_PDOWN;
1576 if (down)
1577 data |= BMCR_PDOWN;
1578 et131x_mii_write(adapter, phydev->addr, MII_BMCR, data);
1579 }
1580
1581 /* et131x_xcvr_init - Init the phy if we are setting it into force mode */
1582 static void et131x_xcvr_init(struct et131x_adapter *adapter)
1583 {
1584 u16 lcr2;
1585 struct phy_device *phydev = adapter->phydev;
1586
1587 /* Set the LED behavior such that LED 1 indicates speed (off =
1588 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
1589 * link and activity (on for link, blink off for activity).
1590 *
1591 * NOTE: Some customizations have been added here for specific
1592 * vendors; The LED behavior is now determined by vendor data in the
1593 * EEPROM. However, the above description is the default.
1594 */
1595 if ((adapter->eeprom_data[1] & 0x4) == 0) {
1596 et131x_mii_read(adapter, PHY_LED_2, &lcr2);
1597
1598 lcr2 &= (ET_LED2_LED_100TX | ET_LED2_LED_1000T);
1599 lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
1600
1601 if ((adapter->eeprom_data[1] & 0x8) == 0)
1602 lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
1603 else
1604 lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
1605
1606 et131x_mii_write(adapter, phydev->addr, PHY_LED_2, lcr2);
1607 }
1608 }
1609
1610 /* et131x_configure_global_regs - configure JAGCore global regs
1611 *
1612 * Used to configure the global registers on the JAGCore
1613 */
1614 static void et131x_configure_global_regs(struct et131x_adapter *adapter)
1615 {
1616 struct global_regs __iomem *regs = &adapter->regs->global;
1617
1618 writel(0, &regs->rxq_start_addr);
1619 writel(INTERNAL_MEM_SIZE - 1, &regs->txq_end_addr);
1620
1621 if (adapter->registry_jumbo_packet < 2048) {
1622 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
1623 * block of RAM that the driver can split between Tx
1624 * and Rx as it desires. Our default is to split it
1625 * 50/50:
1626 */
1627 writel(PARM_RX_MEM_END_DEF, &regs->rxq_end_addr);
1628 writel(PARM_RX_MEM_END_DEF + 1, &regs->txq_start_addr);
1629 } else if (adapter->registry_jumbo_packet < 8192) {
1630 /* For jumbo packets > 2k but < 8k, split 50-50. */
1631 writel(INTERNAL_MEM_RX_OFFSET, &regs->rxq_end_addr);
1632 writel(INTERNAL_MEM_RX_OFFSET + 1, &regs->txq_start_addr);
1633 } else {
1634 /* 9216 is the only packet size greater than 8k that
1635 * is available. The Tx buffer has to be big enough
1636 * for one whole packet on the Tx side. We'll make
1637 * the Tx 9408, and give the rest to Rx
1638 */
1639 writel(0x01b3, &regs->rxq_end_addr);
1640 writel(0x01b4, &regs->txq_start_addr);
1641 }
1642
1643 /* Initialize the loopback register. Disable all loopbacks. */
1644 writel(0, &regs->loopback);
1645
1646 /* MSI Register */
1647 writel(0, &regs->msi_config);
1648
1649 /* By default, disable the watchdog timer. It will be enabled when
1650 * a packet is queued.
1651 */
1652 writel(0, &regs->watchdog_timer);
1653 }
1654
1655 /* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence */
1656 static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
1657 {
1658 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
1659 struct rx_ring *rx_local = &adapter->rx_ring;
1660 struct fbr_desc *fbr_entry;
1661 u32 entry;
1662 u32 psr_num_des;
1663 unsigned long flags;
1664 u8 id;
1665
1666 /* Halt RXDMA to perform the reconfigure. */
1667 et131x_rx_dma_disable(adapter);
1668
1669 /* Load the completion writeback physical address */
1670 writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi);
1671 writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo);
1672
1673 memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
1674
1675 /* Set the address and parameters of the packet status ring into the
1676 * 1310's registers
1677 */
1678 writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi);
1679 writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo);
1680 writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des);
1681 writel(0, &rx_dma->psr_full_offset);
1682
1683 psr_num_des = readl(&rx_dma->psr_num_des) & ET_RXDMA_PSR_NUM_DES_MASK;
1684 writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
1685 &rx_dma->psr_min_des);
1686
1687 spin_lock_irqsave(&adapter->rcv_lock, flags);
1688
1689 /* These local variables track the PSR in the adapter structure */
1690 rx_local->local_psr_full = 0;
1691
1692 for (id = 0; id < NUM_FBRS; id++) {
1693 u32 __iomem *num_des;
1694 u32 __iomem *full_offset;
1695 u32 __iomem *min_des;
1696 u32 __iomem *base_hi;
1697 u32 __iomem *base_lo;
1698 struct fbr_lookup *fbr = rx_local->fbr[id];
1699
1700 if (id == 0) {
1701 num_des = &rx_dma->fbr0_num_des;
1702 full_offset = &rx_dma->fbr0_full_offset;
1703 min_des = &rx_dma->fbr0_min_des;
1704 base_hi = &rx_dma->fbr0_base_hi;
1705 base_lo = &rx_dma->fbr0_base_lo;
1706 } else {
1707 num_des = &rx_dma->fbr1_num_des;
1708 full_offset = &rx_dma->fbr1_full_offset;
1709 min_des = &rx_dma->fbr1_min_des;
1710 base_hi = &rx_dma->fbr1_base_hi;
1711 base_lo = &rx_dma->fbr1_base_lo;
1712 }
1713
1714 /* Now's the best time to initialize FBR contents */
1715 fbr_entry = fbr->ring_virtaddr;
1716 for (entry = 0; entry < fbr->num_entries; entry++) {
1717 fbr_entry->addr_hi = fbr->bus_high[entry];
1718 fbr_entry->addr_lo = fbr->bus_low[entry];
1719 fbr_entry->word2 = entry;
1720 fbr_entry++;
1721 }
1722
1723 /* Set the address and parameters of Free buffer ring 1 and 0
1724 * into the 1310's registers
1725 */
1726 writel(upper_32_bits(fbr->ring_physaddr), base_hi);
1727 writel(lower_32_bits(fbr->ring_physaddr), base_lo);
1728 writel(fbr->num_entries - 1, num_des);
1729 writel(ET_DMA10_WRAP, full_offset);
1730
1731 /* This variable tracks the free buffer ring 1 full position,
1732 * so it has to match the above.
1733 */
1734 fbr->local_full = ET_DMA10_WRAP;
1735 writel(((fbr->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
1736 min_des);
1737 }
1738
1739 /* Program the number of packets we will receive before generating an
1740 * interrupt.
1741 * For version B silicon, this value gets updated once autoneg is
1742 *complete.
1743 */
1744 writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
1745
1746 /* The "time_done" is not working correctly to coalesce interrupts
1747 * after a given time period, but rather is giving us an interrupt
1748 * regardless of whether we have received packets.
1749 * This value gets updated once autoneg is complete.
1750 */
1751 writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
1752
1753 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
1754 }
1755
1756 /* et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
1757 *
1758 * Configure the transmit engine with the ring buffers we have created
1759 * and prepare it for use.
1760 */
1761 static void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
1762 {
1763 struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
1764 struct tx_ring *tx_ring = &adapter->tx_ring;
1765
1766 /* Load the hardware with the start of the transmit descriptor ring. */
1767 writel(upper_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_hi);
1768 writel(lower_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_lo);
1769
1770 /* Initialise the transmit DMA engine */
1771 writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
1772
1773 /* Load the completion writeback physical address */
1774 writel(upper_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_hi);
1775 writel(lower_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_lo);
1776
1777 *tx_ring->tx_status = 0;
1778
1779 writel(0, &txdma->service_request);
1780 tx_ring->send_idx = 0;
1781 }
1782
1783 /* et131x_adapter_setup - Set the adapter up as per cassini+ documentation */
1784 static void et131x_adapter_setup(struct et131x_adapter *adapter)
1785 {
1786 /* Configure the JAGCore */
1787 et131x_configure_global_regs(adapter);
1788
1789 et1310_config_mac_regs1(adapter);
1790
1791 /* Configure the MMC registers */
1792 /* All we need to do is initialize the Memory Control Register */
1793 writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
1794
1795 et1310_config_rxmac_regs(adapter);
1796 et1310_config_txmac_regs(adapter);
1797
1798 et131x_config_rx_dma_regs(adapter);
1799 et131x_config_tx_dma_regs(adapter);
1800
1801 et1310_config_macstat_regs(adapter);
1802
1803 et1310_phy_power_switch(adapter, 0);
1804 et131x_xcvr_init(adapter);
1805 }
1806
1807 /* et131x_soft_reset - Issue soft reset to the hardware, complete for ET1310 */
1808 static void et131x_soft_reset(struct et131x_adapter *adapter)
1809 {
1810 u32 reg;
1811
1812 /* Disable MAC Core */
1813 reg = ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
1814 ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
1815 ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
1816 writel(reg, &adapter->regs->mac.cfg1);
1817
1818 reg = ET_RESET_ALL;
1819 writel(reg, &adapter->regs->global.sw_reset);
1820
1821 reg = ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
1822 ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
1823 writel(reg, &adapter->regs->mac.cfg1);
1824 writel(0, &adapter->regs->mac.cfg1);
1825 }
1826
1827 /* et131x_enable_interrupts - enable interrupt
1828 *
1829 * Enable the appropriate interrupts on the ET131x according to our
1830 * configuration
1831 */
1832 static void et131x_enable_interrupts(struct et131x_adapter *adapter)
1833 {
1834 u32 mask;
1835
1836 /* Enable all global interrupts */
1837 if (adapter->flowcontrol == FLOW_TXONLY ||
1838 adapter->flowcontrol == FLOW_BOTH)
1839 mask = INT_MASK_ENABLE;
1840 else
1841 mask = INT_MASK_ENABLE_NO_FLOW;
1842
1843 writel(mask, &adapter->regs->global.int_mask);
1844 }
1845
1846 /* et131x_disable_interrupts - interrupt disable
1847 *
1848 * Block all interrupts from the et131x device at the device itself
1849 */
1850 static void et131x_disable_interrupts(struct et131x_adapter *adapter)
1851 {
1852 /* Disable all global interrupts */
1853 writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
1854 }
1855
1856 /* et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310 */
1857 static void et131x_tx_dma_disable(struct et131x_adapter *adapter)
1858 {
1859 /* Setup the transmit dma configuration register */
1860 writel(ET_TXDMA_CSR_HALT | ET_TXDMA_SNGL_EPKT,
1861 &adapter->regs->txdma.csr);
1862 }
1863
1864 /* et131x_enable_txrx - Enable tx/rx queues */
1865 static void et131x_enable_txrx(struct net_device *netdev)
1866 {
1867 struct et131x_adapter *adapter = netdev_priv(netdev);
1868
1869 /* Enable the Tx and Rx DMA engines (if not already enabled) */
1870 et131x_rx_dma_enable(adapter);
1871 et131x_tx_dma_enable(adapter);
1872
1873 /* Enable device interrupts */
1874 if (adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE)
1875 et131x_enable_interrupts(adapter);
1876
1877 /* We're ready to move some data, so start the queue */
1878 netif_start_queue(netdev);
1879 }
1880
1881 /* et131x_disable_txrx - Disable tx/rx queues */
1882 static void et131x_disable_txrx(struct net_device *netdev)
1883 {
1884 struct et131x_adapter *adapter = netdev_priv(netdev);
1885
1886 /* First thing is to stop the queue */
1887 netif_stop_queue(netdev);
1888
1889 /* Stop the Tx and Rx DMA engines */
1890 et131x_rx_dma_disable(adapter);
1891 et131x_tx_dma_disable(adapter);
1892
1893 /* Disable device interrupts */
1894 et131x_disable_interrupts(adapter);
1895 }
1896
1897 /* et131x_init_send - Initialize send data structures */
1898 static void et131x_init_send(struct et131x_adapter *adapter)
1899 {
1900 u32 ct;
1901 struct tx_ring *tx_ring = &adapter->tx_ring;
1902 struct tcb *tcb = tx_ring->tcb_ring;
1903
1904 tx_ring->tcb_qhead = tcb;
1905
1906 memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
1907
1908 /* Go through and set up each TCB */
1909 for (ct = 0; ct++ < NUM_TCB; tcb++)
1910 /* Set the link pointer in HW TCB to the next TCB in the
1911 * chain
1912 */
1913 tcb->next = tcb + 1;
1914
1915 /* Set the tail pointer */
1916 tcb--;
1917 tx_ring->tcb_qtail = tcb;
1918 tcb->next = NULL;
1919 /* Curr send queue should now be empty */
1920 tx_ring->send_head = NULL;
1921 tx_ring->send_tail = NULL;
1922 }
1923
1924 /* et1310_enable_phy_coma - called when network cable is unplugged
1925 *
1926 * driver receive an phy status change interrupt while in D0 and check that
1927 * phy_status is down.
1928 *
1929 * -- gate off JAGCore;
1930 * -- set gigE PHY in Coma mode
1931 * -- wake on phy_interrupt; Perform software reset JAGCore,
1932 * re-initialize jagcore and gigE PHY
1933 *
1934 * Add D0-ASPM-PhyLinkDown Support:
1935 * -- while in D0, when there is a phy_interrupt indicating phy link
1936 * down status, call the MPSetPhyComa routine to enter this active
1937 * state power saving mode
1938 * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
1939 * indicating linkup status, call the MPDisablePhyComa routine to
1940 * restore JAGCore and gigE PHY
1941 */
1942 static void et1310_enable_phy_coma(struct et131x_adapter *adapter)
1943 {
1944 unsigned long flags;
1945 u32 pmcsr;
1946
1947 pmcsr = readl(&adapter->regs->global.pm_csr);
1948
1949 /* Save the GbE PHY speed and duplex modes. Need to restore this
1950 * when cable is plugged back in
1951 */
1952
1953 /* Stop sending packets. */
1954 spin_lock_irqsave(&adapter->send_hw_lock, flags);
1955 adapter->flags |= FMP_ADAPTER_LOWER_POWER;
1956 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
1957
1958 /* Wait for outstanding Receive packets */
1959
1960 et131x_disable_txrx(adapter->netdev);
1961
1962 /* Gate off JAGCore 3 clock domains */
1963 pmcsr &= ~ET_PMCSR_INIT;
1964 writel(pmcsr, &adapter->regs->global.pm_csr);
1965
1966 /* Program gigE PHY in to Coma mode */
1967 pmcsr |= ET_PM_PHY_SW_COMA;
1968 writel(pmcsr, &adapter->regs->global.pm_csr);
1969 }
1970
1971 /* et1310_disable_phy_coma - Disable the Phy Coma Mode */
1972 static void et1310_disable_phy_coma(struct et131x_adapter *adapter)
1973 {
1974 u32 pmcsr;
1975
1976 pmcsr = readl(&adapter->regs->global.pm_csr);
1977
1978 /* Disable phy_sw_coma register and re-enable JAGCore clocks */
1979 pmcsr |= ET_PMCSR_INIT;
1980 pmcsr &= ~ET_PM_PHY_SW_COMA;
1981 writel(pmcsr, &adapter->regs->global.pm_csr);
1982
1983 /* Restore the GbE PHY speed and duplex modes;
1984 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
1985 */
1986
1987 /* Re-initialize the send structures */
1988 et131x_init_send(adapter);
1989
1990 /* Bring the device back to the state it was during init prior to
1991 * autonegotiation being complete. This way, when we get the auto-neg
1992 * complete interrupt, we can complete init by calling ConfigMacREGS2.
1993 */
1994 et131x_soft_reset(adapter);
1995
1996 /* setup et1310 as per the documentation ?? */
1997 et131x_adapter_setup(adapter);
1998
1999 /* Allow Tx to restart */
2000 adapter->flags &= ~FMP_ADAPTER_LOWER_POWER;
2001
2002 et131x_enable_txrx(adapter->netdev);
2003 }
2004
2005 static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
2006 {
2007 u32 tmp_free_buff_ring = *free_buff_ring;
2008
2009 tmp_free_buff_ring++;
2010 /* This works for all cases where limit < 1024. The 1023 case
2011 * works because 1023++ is 1024 which means the if condition is not
2012 * taken but the carry of the bit into the wrap bit toggles the wrap
2013 * value correctly
2014 */
2015 if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) {
2016 tmp_free_buff_ring &= ~ET_DMA10_MASK;
2017 tmp_free_buff_ring ^= ET_DMA10_WRAP;
2018 }
2019 /* For the 1023 case */
2020 tmp_free_buff_ring &= (ET_DMA10_MASK | ET_DMA10_WRAP);
2021 *free_buff_ring = tmp_free_buff_ring;
2022 return tmp_free_buff_ring;
2023 }
2024
2025 /* et131x_rx_dma_memory_alloc
2026 *
2027 * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
2028 * and the Packet Status Ring.
2029 */
2030 static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
2031 {
2032 u8 id;
2033 u32 i, j;
2034 u32 bufsize;
2035 u32 pktstat_ringsize;
2036 u32 fbr_chunksize;
2037 struct rx_ring *rx_ring = &adapter->rx_ring;
2038 struct fbr_lookup *fbr;
2039
2040 /* Alloc memory for the lookup table */
2041 rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2042 if (rx_ring->fbr[0] == NULL)
2043 return -ENOMEM;
2044 rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2045 if (rx_ring->fbr[1] == NULL)
2046 return -ENOMEM;
2047
2048 /* The first thing we will do is configure the sizes of the buffer
2049 * rings. These will change based on jumbo packet support. Larger
2050 * jumbo packets increases the size of each entry in FBR0, and the
2051 * number of entries in FBR0, while at the same time decreasing the
2052 * number of entries in FBR1.
2053 *
2054 * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
2055 * entries are huge in order to accommodate a "jumbo" frame, then it
2056 * will have less entries. Conversely, FBR1 will now be relied upon
2057 * to carry more "normal" frames, thus it's entry size also increases
2058 * and the number of entries goes up too (since it now carries
2059 * "small" + "regular" packets.
2060 *
2061 * In this scheme, we try to maintain 512 entries between the two
2062 * rings. Also, FBR1 remains a constant size - when it's size doubles
2063 * the number of entries halves. FBR0 increases in size, however.
2064 */
2065
2066 if (adapter->registry_jumbo_packet < 2048) {
2067 rx_ring->fbr[0]->buffsize = 256;
2068 rx_ring->fbr[0]->num_entries = 512;
2069 rx_ring->fbr[1]->buffsize = 2048;
2070 rx_ring->fbr[1]->num_entries = 512;
2071 } else if (adapter->registry_jumbo_packet < 4096) {
2072 rx_ring->fbr[0]->buffsize = 512;
2073 rx_ring->fbr[0]->num_entries = 1024;
2074 rx_ring->fbr[1]->buffsize = 4096;
2075 rx_ring->fbr[1]->num_entries = 512;
2076 } else {
2077 rx_ring->fbr[0]->buffsize = 1024;
2078 rx_ring->fbr[0]->num_entries = 768;
2079 rx_ring->fbr[1]->buffsize = 16384;
2080 rx_ring->fbr[1]->num_entries = 128;
2081 }
2082
2083 rx_ring->psr_num_entries = rx_ring->fbr[0]->num_entries +
2084 rx_ring->fbr[1]->num_entries;
2085
2086 for (id = 0; id < NUM_FBRS; id++) {
2087 fbr = rx_ring->fbr[id];
2088 /* Allocate an area of memory for Free Buffer Ring */
2089 bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
2090 fbr->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2091 bufsize,
2092 &fbr->ring_physaddr,
2093 GFP_KERNEL);
2094 if (!fbr->ring_virtaddr) {
2095 dev_err(&adapter->pdev->dev,
2096 "Cannot alloc memory for Free Buffer Ring %d\n", id);
2097 return -ENOMEM;
2098 }
2099 }
2100
2101 for (id = 0; id < NUM_FBRS; id++) {
2102 fbr = rx_ring->fbr[id];
2103 fbr_chunksize = (FBR_CHUNKS * fbr->buffsize);
2104
2105 for (i = 0; i < fbr->num_entries / FBR_CHUNKS; i++) {
2106 dma_addr_t fbr_tmp_physaddr;
2107
2108 fbr->mem_virtaddrs[i] = dma_alloc_coherent(
2109 &adapter->pdev->dev, fbr_chunksize,
2110 &fbr->mem_physaddrs[i],
2111 GFP_KERNEL);
2112
2113 if (!fbr->mem_virtaddrs[i]) {
2114 dev_err(&adapter->pdev->dev,
2115 "Could not alloc memory\n");
2116 return -ENOMEM;
2117 }
2118
2119 /* See NOTE in "Save Physical Address" comment above */
2120 fbr_tmp_physaddr = fbr->mem_physaddrs[i];
2121
2122 for (j = 0; j < FBR_CHUNKS; j++) {
2123 u32 index = (i * FBR_CHUNKS) + j;
2124
2125 /* Save the Virtual address of this index for
2126 * quick access later
2127 */
2128 fbr->virt[index] = (u8 *)fbr->mem_virtaddrs[i] +
2129 (j * fbr->buffsize);
2130
2131 /* now store the physical address in the
2132 * descriptor so the device can access it
2133 */
2134 fbr->bus_high[index] =
2135 upper_32_bits(fbr_tmp_physaddr);
2136 fbr->bus_low[index] =
2137 lower_32_bits(fbr_tmp_physaddr);
2138
2139 fbr_tmp_physaddr += fbr->buffsize;
2140 }
2141 }
2142 }
2143
2144 /* Allocate an area of memory for FIFO of Packet Status ring entries */
2145 pktstat_ringsize =
2146 sizeof(struct pkt_stat_desc) * rx_ring->psr_num_entries;
2147
2148 rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2149 pktstat_ringsize,
2150 &rx_ring->ps_ring_physaddr,
2151 GFP_KERNEL);
2152
2153 if (!rx_ring->ps_ring_virtaddr) {
2154 dev_err(&adapter->pdev->dev,
2155 "Cannot alloc memory for Packet Status Ring\n");
2156 return -ENOMEM;
2157 }
2158
2159 /* NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
2160 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2161 * are ever returned, make sure the high part is retrieved here before
2162 * storing the adjusted address.
2163 */
2164
2165 /* Allocate an area of memory for writeback of status information */
2166 rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev,
2167 sizeof(struct rx_status_block),
2168 &rx_ring->rx_status_bus,
2169 GFP_KERNEL);
2170 if (!rx_ring->rx_status_block) {
2171 dev_err(&adapter->pdev->dev,
2172 "Cannot alloc memory for Status Block\n");
2173 return -ENOMEM;
2174 }
2175 rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
2176
2177 /* The RFDs are going to be put on lists later on, so initialize the
2178 * lists now.
2179 */
2180 INIT_LIST_HEAD(&rx_ring->recv_list);
2181 return 0;
2182 }
2183
2184 /* et131x_rx_dma_memory_free - Free all memory allocated within this module */
2185 static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
2186 {
2187 u8 id;
2188 u32 index;
2189 u32 bufsize;
2190 u32 pktstat_ringsize;
2191 struct rfd *rfd;
2192 struct rx_ring *rx_ring = &adapter->rx_ring;
2193 struct fbr_lookup *fbr;
2194
2195 /* Free RFDs and associated packet descriptors */
2196 WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd);
2197
2198 while (!list_empty(&rx_ring->recv_list)) {
2199 rfd = list_entry(rx_ring->recv_list.next,
2200 struct rfd, list_node);
2201
2202 list_del(&rfd->list_node);
2203 rfd->skb = NULL;
2204 kfree(rfd);
2205 }
2206
2207 /* Free Free Buffer Rings */
2208 for (id = 0; id < NUM_FBRS; id++) {
2209 fbr = rx_ring->fbr[id];
2210
2211 if (!fbr || !fbr->ring_virtaddr)
2212 continue;
2213
2214 /* First the packet memory */
2215 for (index = 0;
2216 index < fbr->num_entries / FBR_CHUNKS;
2217 index++) {
2218 if (fbr->mem_virtaddrs[index]) {
2219 bufsize = fbr->buffsize * FBR_CHUNKS;
2220
2221 dma_free_coherent(&adapter->pdev->dev,
2222 bufsize,
2223 fbr->mem_virtaddrs[index],
2224 fbr->mem_physaddrs[index]);
2225
2226 fbr->mem_virtaddrs[index] = NULL;
2227 }
2228 }
2229
2230 bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
2231
2232 dma_free_coherent(&adapter->pdev->dev,
2233 bufsize,
2234 fbr->ring_virtaddr,
2235 fbr->ring_physaddr);
2236
2237 fbr->ring_virtaddr = NULL;
2238 }
2239
2240 /* Free Packet Status Ring */
2241 if (rx_ring->ps_ring_virtaddr) {
2242 pktstat_ringsize = sizeof(struct pkt_stat_desc) *
2243 rx_ring->psr_num_entries;
2244
2245 dma_free_coherent(&adapter->pdev->dev, pktstat_ringsize,
2246 rx_ring->ps_ring_virtaddr,
2247 rx_ring->ps_ring_physaddr);
2248
2249 rx_ring->ps_ring_virtaddr = NULL;
2250 }
2251
2252 /* Free area of memory for the writeback of status information */
2253 if (rx_ring->rx_status_block) {
2254 dma_free_coherent(&adapter->pdev->dev,
2255 sizeof(struct rx_status_block),
2256 rx_ring->rx_status_block, rx_ring->rx_status_bus);
2257 rx_ring->rx_status_block = NULL;
2258 }
2259
2260 /* Free the FBR Lookup Table */
2261 kfree(rx_ring->fbr[0]);
2262 kfree(rx_ring->fbr[1]);
2263
2264 /* Reset Counters */
2265 rx_ring->num_ready_recv = 0;
2266 }
2267
2268 /* et131x_init_recv - Initialize receive data structures */
2269 static int et131x_init_recv(struct et131x_adapter *adapter)
2270 {
2271 struct rfd *rfd;
2272 u32 rfdct;
2273 struct rx_ring *rx_ring = &adapter->rx_ring;
2274
2275 /* Setup each RFD */
2276 for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) {
2277 rfd = kzalloc(sizeof(struct rfd), GFP_ATOMIC | GFP_DMA);
2278 if (!rfd)
2279 return -ENOMEM;
2280
2281 rfd->skb = NULL;
2282
2283 /* Add this RFD to the recv_list */
2284 list_add_tail(&rfd->list_node, &rx_ring->recv_list);
2285
2286 /* Increment the available RFD's */
2287 rx_ring->num_ready_recv++;
2288 }
2289
2290 return 0;
2291 }
2292
2293 /* et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate */
2294 static void et131x_set_rx_dma_timer(struct et131x_adapter *adapter)
2295 {
2296 struct phy_device *phydev = adapter->phydev;
2297
2298 /* For version B silicon, we do not use the RxDMA timer for 10 and 100
2299 * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
2300 */
2301 if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) {
2302 writel(0, &adapter->regs->rxdma.max_pkt_time);
2303 writel(1, &adapter->regs->rxdma.num_pkt_done);
2304 }
2305 }
2306
2307 /* NICReturnRFD - Recycle a RFD and put it back onto the receive list
2308 * @adapter: pointer to our adapter
2309 * @rfd: pointer to the RFD
2310 */
2311 static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
2312 {
2313 struct rx_ring *rx_local = &adapter->rx_ring;
2314 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
2315 u16 buff_index = rfd->bufferindex;
2316 u8 ring_index = rfd->ringindex;
2317 unsigned long flags;
2318 struct fbr_lookup *fbr = rx_local->fbr[ring_index];
2319
2320 /* We don't use any of the OOB data besides status. Otherwise, we
2321 * need to clean up OOB data
2322 */
2323 if (buff_index < fbr->num_entries) {
2324 u32 free_buff_ring;
2325 u32 __iomem *offset;
2326 struct fbr_desc *next;
2327
2328 spin_lock_irqsave(&adapter->fbr_lock, flags);
2329
2330 if (ring_index == 0)
2331 offset = &rx_dma->fbr0_full_offset;
2332 else
2333 offset = &rx_dma->fbr1_full_offset;
2334
2335 next = (struct fbr_desc *)(fbr->ring_virtaddr) +
2336 INDEX10(fbr->local_full);
2337
2338 /* Handle the Free Buffer Ring advancement here. Write
2339 * the PA / Buffer Index for the returned buffer into
2340 * the oldest (next to be freed)FBR entry
2341 */
2342 next->addr_hi = fbr->bus_high[buff_index];
2343 next->addr_lo = fbr->bus_low[buff_index];
2344 next->word2 = buff_index;
2345
2346 free_buff_ring = bump_free_buff_ring(&fbr->local_full,
2347 fbr->num_entries - 1);
2348 writel(free_buff_ring, offset);
2349
2350 spin_unlock_irqrestore(&adapter->fbr_lock, flags);
2351 } else {
2352 dev_err(&adapter->pdev->dev,
2353 "%s illegal Buffer Index returned\n", __func__);
2354 }
2355
2356 /* The processing on this RFD is done, so put it back on the tail of
2357 * our list
2358 */
2359 spin_lock_irqsave(&adapter->rcv_lock, flags);
2360 list_add_tail(&rfd->list_node, &rx_local->recv_list);
2361 rx_local->num_ready_recv++;
2362 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2363
2364 WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd);
2365 }
2366
2367 /* nic_rx_pkts - Checks the hardware for available packets
2368 *
2369 * Returns rfd, a pointer to our MPRFD.
2370 *
2371 * Checks the hardware for available packets, using completion ring
2372 * If packets are available, it gets an RFD from the recv_list, attaches
2373 * the packet to it, puts the RFD in the RecvPendList, and also returns
2374 * the pointer to the RFD.
2375 */
2376 static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
2377 {
2378 struct rx_ring *rx_local = &adapter->rx_ring;
2379 struct rx_status_block *status;
2380 struct pkt_stat_desc *psr;
2381 struct rfd *rfd;
2382 u32 i;
2383 u8 *buf;
2384 unsigned long flags;
2385 struct list_head *element;
2386 u8 ring_index;
2387 u16 buff_index;
2388 u32 len;
2389 u32 word0;
2390 u32 word1;
2391 struct sk_buff *skb;
2392 struct fbr_lookup *fbr;
2393
2394 /* RX Status block is written by the DMA engine prior to every
2395 * interrupt. It contains the next to be used entry in the Packet
2396 * Status Ring, and also the two Free Buffer rings.
2397 */
2398 status = rx_local->rx_status_block;
2399 word1 = status->word1 >> 16; /* Get the useful bits */
2400
2401 /* Check the PSR and wrap bits do not match */
2402 if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
2403 return NULL; /* Looks like this ring is not updated yet */
2404
2405 /* The packet status ring indicates that data is available. */
2406 psr = (struct pkt_stat_desc *) (rx_local->ps_ring_virtaddr) +
2407 (rx_local->local_psr_full & 0xFFF);
2408
2409 /* Grab any information that is required once the PSR is advanced,
2410 * since we can no longer rely on the memory being accurate
2411 */
2412 len = psr->word1 & 0xFFFF;
2413 ring_index = (psr->word1 >> 26) & 0x03;
2414 fbr = rx_local->fbr[ring_index];
2415 buff_index = (psr->word1 >> 16) & 0x3FF;
2416 word0 = psr->word0;
2417
2418 /* Indicate that we have used this PSR entry. */
2419 /* FIXME wrap 12 */
2420 add_12bit(&rx_local->local_psr_full, 1);
2421 if (
2422 (rx_local->local_psr_full & 0xFFF) > rx_local->psr_num_entries - 1) {
2423 /* Clear psr full and toggle the wrap bit */
2424 rx_local->local_psr_full &= ~0xFFF;
2425 rx_local->local_psr_full ^= 0x1000;
2426 }
2427
2428 writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset);
2429
2430 if (ring_index > 1 || buff_index > fbr->num_entries - 1) {
2431 /* Illegal buffer or ring index cannot be used by S/W*/
2432 dev_err(&adapter->pdev->dev,
2433 "NICRxPkts PSR Entry %d indicates length of %d and/or bad bi(%d)\n",
2434 rx_local->local_psr_full & 0xFFF, len, buff_index);
2435 return NULL;
2436 }
2437
2438 /* Get and fill the RFD. */
2439 spin_lock_irqsave(&adapter->rcv_lock, flags);
2440
2441 element = rx_local->recv_list.next;
2442 rfd = list_entry(element, struct rfd, list_node);
2443
2444 if (!rfd) {
2445 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2446 return NULL;
2447 }
2448
2449 list_del(&rfd->list_node);
2450 rx_local->num_ready_recv--;
2451
2452 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2453
2454 rfd->bufferindex = buff_index;
2455 rfd->ringindex = ring_index;
2456
2457 /* In V1 silicon, there is a bug which screws up filtering of runt
2458 * packets. Therefore runt packet filtering is disabled in the MAC and
2459 * the packets are dropped here. They are also counted here.
2460 */
2461 if (len < (NIC_MIN_PACKET_SIZE + 4)) {
2462 adapter->stats.rx_other_errs++;
2463 len = 0;
2464 }
2465
2466 if (len == 0) {
2467 rfd->len = 0;
2468 goto out;
2469 }
2470
2471 /* Determine if this is a multicast packet coming in */
2472 if ((word0 & ALCATEL_MULTICAST_PKT) &&
2473 !(word0 & ALCATEL_BROADCAST_PKT)) {
2474 /* Promiscuous mode and Multicast mode are not mutually
2475 * exclusive as was first thought. I guess Promiscuous is just
2476 * considered a super-set of the other filters. Generally filter
2477 * is 0x2b when in promiscuous mode.
2478 */
2479 if ((adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST)
2480 && !(adapter->packet_filter & ET131X_PACKET_TYPE_PROMISCUOUS)
2481 && !(adapter->packet_filter &
2482 ET131X_PACKET_TYPE_ALL_MULTICAST)) {
2483 buf = fbr->virt[buff_index];
2484
2485 /* Loop through our list to see if the destination
2486 * address of this packet matches one in our list.
2487 */
2488 for (i = 0; i < adapter->multicast_addr_count; i++) {
2489 if (buf[0] == adapter->multicast_list[i][0]
2490 && buf[1] == adapter->multicast_list[i][1]
2491 && buf[2] == adapter->multicast_list[i][2]
2492 && buf[3] == adapter->multicast_list[i][3]
2493 && buf[4] == adapter->multicast_list[i][4]
2494 && buf[5] == adapter->multicast_list[i][5]) {
2495 break;
2496 }
2497 }
2498
2499 /* If our index is equal to the number of Multicast
2500 * address we have, then this means we did not find this
2501 * packet's matching address in our list. Set the len to
2502 * zero, so we free our RFD when we return from this
2503 * function.
2504 */
2505 if (i == adapter->multicast_addr_count)
2506 len = 0;
2507 }
2508
2509 if (len > 0)
2510 adapter->stats.multicast_pkts_rcvd++;
2511 } else if (word0 & ALCATEL_BROADCAST_PKT) {
2512 adapter->stats.broadcast_pkts_rcvd++;
2513 } else {
2514 /* Not sure what this counter measures in promiscuous mode.
2515 * Perhaps we should check the MAC address to see if it is
2516 * directed to us in promiscuous mode.
2517 */
2518 adapter->stats.unicast_pkts_rcvd++;
2519 }
2520
2521 if (!len) {
2522 rfd->len = 0;
2523 goto out;
2524 }
2525
2526 rfd->len = len;
2527
2528 skb = dev_alloc_skb(rfd->len + 2);
2529 if (!skb) {
2530 dev_err(&adapter->pdev->dev, "Couldn't alloc an SKB for Rx\n");
2531 return NULL;
2532 }
2533
2534 adapter->netdev->stats.rx_bytes += rfd->len;
2535
2536 memcpy(skb_put(skb, rfd->len), fbr->virt[buff_index], rfd->len);
2537
2538 skb->protocol = eth_type_trans(skb, adapter->netdev);
2539 skb->ip_summed = CHECKSUM_NONE;
2540 netif_receive_skb(skb);
2541
2542 out:
2543 nic_return_rfd(adapter, rfd);
2544 return rfd;
2545 }
2546
2547 /* et131x_handle_recv_pkts - Interrupt handler for receive processing
2548 *
2549 * Assumption, Rcv spinlock has been acquired.
2550 */
2551 static int et131x_handle_recv_pkts(struct et131x_adapter *adapter, int budget)
2552 {
2553 struct rfd *rfd = NULL;
2554 int count = 0;
2555 int limit = budget;
2556 bool done = true;
2557 struct rx_ring *rx_ring = &adapter->rx_ring;
2558
2559 if (budget > MAX_PACKETS_HANDLED)
2560 limit = MAX_PACKETS_HANDLED;
2561
2562 /* Process up to available RFD's */
2563 while (count < limit) {
2564 if (list_empty(&rx_ring->recv_list)) {
2565 WARN_ON(rx_ring->num_ready_recv != 0);
2566 done = false;
2567 break;
2568 }
2569
2570 rfd = nic_rx_pkts(adapter);
2571
2572 if (rfd == NULL)
2573 break;
2574
2575 /* Do not receive any packets until a filter has been set.
2576 * Do not receive any packets until we have link.
2577 * If length is zero, return the RFD in order to advance the
2578 * Free buffer ring.
2579 */
2580 if (!adapter->packet_filter ||
2581 !netif_carrier_ok(adapter->netdev) ||
2582 rfd->len == 0)
2583 continue;
2584
2585 /* Increment the number of packets we received */
2586 adapter->netdev->stats.rx_packets++;
2587
2588 /* Set the status on the packet, either resources or success */
2589 if (rx_ring->num_ready_recv < RFD_LOW_WATER_MARK)
2590 dev_warn(&adapter->pdev->dev, "RFD's are running out\n");
2591
2592 count++;
2593 }
2594
2595 if (count == limit || !done) {
2596 rx_ring->unfinished_receives = true;
2597 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2598 &adapter->regs->global.watchdog_timer);
2599 } else
2600 /* Watchdog timer will disable itself if appropriate. */
2601 rx_ring->unfinished_receives = false;
2602
2603 return count;
2604 }
2605
2606 /* et131x_tx_dma_memory_alloc
2607 *
2608 * Allocates memory that will be visible both to the device and to the CPU.
2609 * The OS will pass us packets, pointers to which we will insert in the Tx
2610 * Descriptor queue. The device will read this queue to find the packets in
2611 * memory. The device will update the "status" in memory each time it xmits a
2612 * packet.
2613 */
2614 static int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
2615 {
2616 int desc_size = 0;
2617 struct tx_ring *tx_ring = &adapter->tx_ring;
2618
2619 /* Allocate memory for the TCB's (Transmit Control Block) */
2620 tx_ring->tcb_ring = kcalloc(NUM_TCB, sizeof(struct tcb),
2621 GFP_ATOMIC | GFP_DMA);
2622 if (!tx_ring->tcb_ring)
2623 return -ENOMEM;
2624
2625 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
2626 tx_ring->tx_desc_ring = dma_alloc_coherent(&adapter->pdev->dev,
2627 desc_size,
2628 &tx_ring->tx_desc_ring_pa,
2629 GFP_KERNEL);
2630 if (!tx_ring->tx_desc_ring) {
2631 dev_err(&adapter->pdev->dev,
2632 "Cannot alloc memory for Tx Ring\n");
2633 return -ENOMEM;
2634 }
2635
2636 /* Save physical address
2637 *
2638 * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
2639 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2640 * are ever returned, make sure the high part is retrieved here before
2641 * storing the adjusted address.
2642 */
2643 /* Allocate memory for the Tx status block */
2644 tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev,
2645 sizeof(u32),
2646 &tx_ring->tx_status_pa,
2647 GFP_KERNEL);
2648 if (!tx_ring->tx_status_pa) {
2649 dev_err(&adapter->pdev->dev,
2650 "Cannot alloc memory for Tx status block\n");
2651 return -ENOMEM;
2652 }
2653 return 0;
2654 }
2655
2656 /* et131x_tx_dma_memory_free - Free all memory allocated within this module */
2657 static void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
2658 {
2659 int desc_size = 0;
2660 struct tx_ring *tx_ring = &adapter->tx_ring;
2661
2662 if (tx_ring->tx_desc_ring) {
2663 /* Free memory relating to Tx rings here */
2664 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
2665 dma_free_coherent(&adapter->pdev->dev,
2666 desc_size,
2667 tx_ring->tx_desc_ring,
2668 tx_ring->tx_desc_ring_pa);
2669 tx_ring->tx_desc_ring = NULL;
2670 }
2671
2672 /* Free memory for the Tx status block */
2673 if (tx_ring->tx_status) {
2674 dma_free_coherent(&adapter->pdev->dev,
2675 sizeof(u32),
2676 tx_ring->tx_status,
2677 tx_ring->tx_status_pa);
2678
2679 tx_ring->tx_status = NULL;
2680 }
2681 /* Free the memory for the tcb structures */
2682 kfree(tx_ring->tcb_ring);
2683 }
2684
2685 /* nic_send_packet - NIC specific send handler for version B silicon.
2686 * @adapter: pointer to our adapter
2687 * @tcb: pointer to struct tcb
2688 */
2689 static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
2690 {
2691 u32 i;
2692 struct tx_desc desc[24]; /* 24 x 16 byte */
2693 u32 frag = 0;
2694 u32 thiscopy, remainder;
2695 struct sk_buff *skb = tcb->skb;
2696 u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
2697 struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
2698 unsigned long flags;
2699 struct phy_device *phydev = adapter->phydev;
2700 dma_addr_t dma_addr;
2701 struct tx_ring *tx_ring = &adapter->tx_ring;
2702
2703 /* Part of the optimizations of this send routine restrict us to
2704 * sending 24 fragments at a pass. In practice we should never see
2705 * more than 5 fragments.
2706 *
2707 * NOTE: The older version of this function (below) can handle any
2708 * number of fragments. If needed, we can call this function,
2709 * although it is less efficient.
2710 */
2711
2712 /* nr_frags should be no more than 18. */
2713 BUILD_BUG_ON(MAX_SKB_FRAGS + 1 > 23);
2714
2715 memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
2716
2717 for (i = 0; i < nr_frags; i++) {
2718 /* If there is something in this element, lets get a
2719 * descriptor from the ring and get the necessary data
2720 */
2721 if (i == 0) {
2722 /* If the fragments are smaller than a standard MTU,
2723 * then map them to a single descriptor in the Tx
2724 * Desc ring. However, if they're larger, as is
2725 * possible with support for jumbo packets, then
2726 * split them each across 2 descriptors.
2727 *
2728 * This will work until we determine why the hardware
2729 * doesn't seem to like large fragments.
2730 */
2731 if (skb_headlen(skb) <= 1514) {
2732 /* Low 16bits are length, high is vlan and
2733 * unused currently so zero
2734 */
2735 desc[frag].len_vlan = skb_headlen(skb);
2736 dma_addr = dma_map_single(&adapter->pdev->dev,
2737 skb->data,
2738 skb_headlen(skb),
2739 DMA_TO_DEVICE);
2740 desc[frag].addr_lo = lower_32_bits(dma_addr);
2741 desc[frag].addr_hi = upper_32_bits(dma_addr);
2742 frag++;
2743 } else {
2744 desc[frag].len_vlan = skb_headlen(skb) / 2;
2745 dma_addr = dma_map_single(&adapter->pdev->dev,
2746 skb->data,
2747 (skb_headlen(skb) / 2),
2748 DMA_TO_DEVICE);
2749 desc[frag].addr_lo = lower_32_bits(dma_addr);
2750 desc[frag].addr_hi = upper_32_bits(dma_addr);
2751 frag++;
2752
2753 desc[frag].len_vlan = skb_headlen(skb) / 2;
2754 dma_addr = dma_map_single(&adapter->pdev->dev,
2755 skb->data +
2756 (skb_headlen(skb) / 2),
2757 (skb_headlen(skb) / 2),
2758 DMA_TO_DEVICE);
2759 desc[frag].addr_lo = lower_32_bits(dma_addr);
2760 desc[frag].addr_hi = upper_32_bits(dma_addr);
2761 frag++;
2762 }
2763 } else {
2764 desc[frag].len_vlan = frags[i - 1].size;
2765 dma_addr = skb_frag_dma_map(&adapter->pdev->dev,
2766 &frags[i - 1],
2767 0,
2768 frags[i - 1].size,
2769 DMA_TO_DEVICE);
2770 desc[frag].addr_lo = lower_32_bits(dma_addr);
2771 desc[frag].addr_hi = upper_32_bits(dma_addr);
2772 frag++;
2773 }
2774 }
2775
2776 if (phydev && phydev->speed == SPEED_1000) {
2777 if (++tx_ring->since_irq == PARM_TX_NUM_BUFS_DEF) {
2778 /* Last element & Interrupt flag */
2779 desc[frag - 1].flags =
2780 TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
2781 tx_ring->since_irq = 0;
2782 } else { /* Last element */
2783 desc[frag - 1].flags = TXDESC_FLAG_LASTPKT;
2784 }
2785 } else
2786 desc[frag - 1].flags =
2787 TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
2788
2789 desc[0].flags |= TXDESC_FLAG_FIRSTPKT;
2790
2791 tcb->index_start = tx_ring->send_idx;
2792 tcb->stale = 0;
2793
2794 spin_lock_irqsave(&adapter->send_hw_lock, flags);
2795
2796 thiscopy = NUM_DESC_PER_RING_TX - INDEX10(tx_ring->send_idx);
2797
2798 if (thiscopy >= frag) {
2799 remainder = 0;
2800 thiscopy = frag;
2801 } else {
2802 remainder = frag - thiscopy;
2803 }
2804
2805 memcpy(tx_ring->tx_desc_ring + INDEX10(tx_ring->send_idx),
2806 desc,
2807 sizeof(struct tx_desc) * thiscopy);
2808
2809 add_10bit(&tx_ring->send_idx, thiscopy);
2810
2811 if (INDEX10(tx_ring->send_idx) == 0 ||
2812 INDEX10(tx_ring->send_idx) == NUM_DESC_PER_RING_TX) {
2813 tx_ring->send_idx &= ~ET_DMA10_MASK;
2814 tx_ring->send_idx ^= ET_DMA10_WRAP;
2815 }
2816
2817 if (remainder) {
2818 memcpy(tx_ring->tx_desc_ring,
2819 desc + thiscopy,
2820 sizeof(struct tx_desc) * remainder);
2821
2822 add_10bit(&tx_ring->send_idx, remainder);
2823 }
2824
2825 if (INDEX10(tx_ring->send_idx) == 0) {
2826 if (tx_ring->send_idx)
2827 tcb->index = NUM_DESC_PER_RING_TX - 1;
2828 else
2829 tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
2830 } else
2831 tcb->index = tx_ring->send_idx - 1;
2832
2833 spin_lock(&adapter->tcb_send_qlock);
2834
2835 if (tx_ring->send_tail)
2836 tx_ring->send_tail->next = tcb;
2837 else
2838 tx_ring->send_head = tcb;
2839
2840 tx_ring->send_tail = tcb;
2841
2842 WARN_ON(tcb->next != NULL);
2843
2844 tx_ring->used++;
2845
2846 spin_unlock(&adapter->tcb_send_qlock);
2847
2848 /* Write the new write pointer back to the device. */
2849 writel(tx_ring->send_idx, &adapter->regs->txdma.service_request);
2850
2851 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
2852 * timer to wake us up if this packet isn't followed by N more.
2853 */
2854 if (phydev && phydev->speed == SPEED_1000) {
2855 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2856 &adapter->regs->global.watchdog_timer);
2857 }
2858 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
2859
2860 return 0;
2861 }
2862
2863 /* send_packet - Do the work to send a packet
2864 *
2865 * Assumption: Send spinlock has been acquired
2866 */
2867 static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
2868 {
2869 int status;
2870 struct tcb *tcb;
2871 u16 *shbufva;
2872 unsigned long flags;
2873 struct tx_ring *tx_ring = &adapter->tx_ring;
2874
2875 /* All packets must have at least a MAC address and a protocol type */
2876 if (skb->len < ETH_HLEN)
2877 return -EIO;
2878
2879 /* Get a TCB for this packet */
2880 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
2881
2882 tcb = tx_ring->tcb_qhead;
2883
2884 if (tcb == NULL) {
2885 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2886 return -ENOMEM;
2887 }
2888
2889 tx_ring->tcb_qhead = tcb->next;
2890
2891 if (tx_ring->tcb_qhead == NULL)
2892 tx_ring->tcb_qtail = NULL;
2893
2894 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2895
2896 tcb->skb = skb;
2897
2898 if (skb->data != NULL && skb_headlen(skb) >= 6) {
2899 shbufva = (u16 *) skb->data;
2900
2901 if ((shbufva[0] == 0xffff) &&
2902 (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff))
2903 tcb->flags |= FMP_DEST_BROAD;
2904 else if ((shbufva[0] & 0x3) == 0x0001)
2905 tcb->flags |= FMP_DEST_MULTI;
2906 }
2907
2908 tcb->next = NULL;
2909
2910 /* Call the NIC specific send handler. */
2911 status = nic_send_packet(adapter, tcb);
2912
2913 if (status != 0) {
2914 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
2915
2916 if (tx_ring->tcb_qtail)
2917 tx_ring->tcb_qtail->next = tcb;
2918 else
2919 /* Apparently ready Q is empty. */
2920 tx_ring->tcb_qhead = tcb;
2921
2922 tx_ring->tcb_qtail = tcb;
2923 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2924 return status;
2925 }
2926 WARN_ON(tx_ring->used > NUM_TCB);
2927 return 0;
2928 }
2929
2930 /* et131x_send_packets - This function is called by the OS to send packets */
2931 static int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
2932 {
2933 int status = 0;
2934 struct et131x_adapter *adapter = netdev_priv(netdev);
2935 struct tx_ring *tx_ring = &adapter->tx_ring;
2936
2937 /* Send these packets
2938 *
2939 * NOTE: The Linux Tx entry point is only given one packet at a time
2940 * to Tx, so the PacketCount and it's array used makes no sense here
2941 */
2942
2943 /* TCB is not available */
2944 if (tx_ring->used >= NUM_TCB) {
2945 /* NOTE: If there's an error on send, no need to queue the
2946 * packet under Linux; if we just send an error up to the
2947 * netif layer, it will resend the skb to us.
2948 */
2949 status = -ENOMEM;
2950 } else {
2951 /* We need to see if the link is up; if it's not, make the
2952 * netif layer think we're good and drop the packet
2953 */
2954 if ((adapter->flags & FMP_ADAPTER_FAIL_SEND_MASK) ||
2955 !netif_carrier_ok(netdev)) {
2956 dev_kfree_skb_any(skb);
2957 skb = NULL;
2958
2959 adapter->netdev->stats.tx_dropped++;
2960 } else {
2961 status = send_packet(skb, adapter);
2962 if (status != 0 && status != -ENOMEM) {
2963 /* On any other error, make netif think we're
2964 * OK and drop the packet
2965 */
2966 dev_kfree_skb_any(skb);
2967 skb = NULL;
2968 adapter->netdev->stats.tx_dropped++;
2969 }
2970 }
2971 }
2972 return status;
2973 }
2974
2975 /* free_send_packet - Recycle a struct tcb
2976 * @adapter: pointer to our adapter
2977 * @tcb: pointer to struct tcb
2978 *
2979 * Complete the packet if necessary
2980 * Assumption - Send spinlock has been acquired
2981 */
2982 static inline void free_send_packet(struct et131x_adapter *adapter,
2983 struct tcb *tcb)
2984 {
2985 unsigned long flags;
2986 struct tx_desc *desc = NULL;
2987 struct net_device_stats *stats = &adapter->netdev->stats;
2988 struct tx_ring *tx_ring = &adapter->tx_ring;
2989 u64 dma_addr;
2990
2991 if (tcb->flags & FMP_DEST_BROAD)
2992 atomic_inc(&adapter->stats.broadcast_pkts_xmtd);
2993 else if (tcb->flags & FMP_DEST_MULTI)
2994 atomic_inc(&adapter->stats.multicast_pkts_xmtd);
2995 else
2996 atomic_inc(&adapter->stats.unicast_pkts_xmtd);
2997
2998 if (tcb->skb) {
2999 stats->tx_bytes += tcb->skb->len;
3000
3001 /* Iterate through the TX descriptors on the ring
3002 * corresponding to this packet and umap the fragments
3003 * they point to
3004 */
3005 do {
3006 desc = tx_ring->tx_desc_ring +
3007 INDEX10(tcb->index_start);
3008
3009 dma_addr = desc->addr_lo;
3010 dma_addr |= (u64)desc->addr_hi << 32;
3011
3012 dma_unmap_single(&adapter->pdev->dev,
3013 dma_addr,
3014 desc->len_vlan, DMA_TO_DEVICE);
3015
3016 add_10bit(&tcb->index_start, 1);
3017 if (INDEX10(tcb->index_start) >=
3018 NUM_DESC_PER_RING_TX) {
3019 tcb->index_start &= ~ET_DMA10_MASK;
3020 tcb->index_start ^= ET_DMA10_WRAP;
3021 }
3022 } while (desc != tx_ring->tx_desc_ring + INDEX10(tcb->index));
3023
3024 dev_kfree_skb_any(tcb->skb);
3025 }
3026
3027 memset(tcb, 0, sizeof(struct tcb));
3028
3029 /* Add the TCB to the Ready Q */
3030 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3031
3032 stats->tx_packets++;
3033
3034 if (tx_ring->tcb_qtail)
3035 tx_ring->tcb_qtail->next = tcb;
3036 else
3037 /* Apparently ready Q is empty. */
3038 tx_ring->tcb_qhead = tcb;
3039
3040 tx_ring->tcb_qtail = tcb;
3041
3042 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3043 WARN_ON(tx_ring->used < 0);
3044 }
3045
3046 /* et131x_free_busy_send_packets - Free and complete the stopped active sends
3047 *
3048 * Assumption - Send spinlock has been acquired
3049 */
3050 static void et131x_free_busy_send_packets(struct et131x_adapter *adapter)
3051 {
3052 struct tcb *tcb;
3053 unsigned long flags;
3054 u32 freed = 0;
3055 struct tx_ring *tx_ring = &adapter->tx_ring;
3056
3057 /* Any packets being sent? Check the first TCB on the send list */
3058 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3059
3060 tcb = tx_ring->send_head;
3061
3062 while (tcb != NULL && freed < NUM_TCB) {
3063 struct tcb *next = tcb->next;
3064
3065 tx_ring->send_head = next;
3066
3067 if (next == NULL)
3068 tx_ring->send_tail = NULL;
3069
3070 tx_ring->used--;
3071
3072 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3073
3074 freed++;
3075 free_send_packet(adapter, tcb);
3076
3077 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3078
3079 tcb = tx_ring->send_head;
3080 }
3081
3082 WARN_ON(freed == NUM_TCB);
3083
3084 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3085
3086 tx_ring->used = 0;
3087 }
3088
3089 /* et131x_handle_send_pkts - Interrupt handler for sending processing
3090 *
3091 * Re-claim the send resources, complete sends and get more to send from
3092 * the send wait queue.
3093 *
3094 * Assumption - Send spinlock has been acquired
3095 */
3096 static void et131x_handle_send_pkts(struct et131x_adapter *adapter)
3097 {
3098 unsigned long flags;
3099 u32 serviced;
3100 struct tcb *tcb;
3101 u32 index;
3102 struct tx_ring *tx_ring = &adapter->tx_ring;
3103
3104 serviced = readl(&adapter->regs->txdma.new_service_complete);
3105 index = INDEX10(serviced);
3106
3107 /* Has the ring wrapped? Process any descriptors that do not have
3108 * the same "wrap" indicator as the current completion indicator
3109 */
3110 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3111
3112 tcb = tx_ring->send_head;
3113
3114 while (tcb &&
3115 ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
3116 index < INDEX10(tcb->index)) {
3117 tx_ring->used--;
3118 tx_ring->send_head = tcb->next;
3119 if (tcb->next == NULL)
3120 tx_ring->send_tail = NULL;
3121
3122 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3123 free_send_packet(adapter, tcb);
3124 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3125
3126 /* Goto the next packet */
3127 tcb = tx_ring->send_head;
3128 }
3129 while (tcb &&
3130 !((serviced ^ tcb->index) & ET_DMA10_WRAP)
3131 && index > (tcb->index & ET_DMA10_MASK)) {
3132 tx_ring->used--;
3133 tx_ring->send_head = tcb->next;
3134 if (tcb->next == NULL)
3135 tx_ring->send_tail = NULL;
3136
3137 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3138 free_send_packet(adapter, tcb);
3139 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3140
3141 /* Goto the next packet */
3142 tcb = tx_ring->send_head;
3143 }
3144
3145 /* Wake up the queue when we hit a low-water mark */
3146 if (tx_ring->used <= NUM_TCB / 3)
3147 netif_wake_queue(adapter->netdev);
3148
3149 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3150 }
3151
3152 static int et131x_get_settings(struct net_device *netdev,
3153 struct ethtool_cmd *cmd)
3154 {
3155 struct et131x_adapter *adapter = netdev_priv(netdev);
3156
3157 return phy_ethtool_gset(adapter->phydev, cmd);
3158 }
3159
3160 static int et131x_set_settings(struct net_device *netdev,
3161 struct ethtool_cmd *cmd)
3162 {
3163 struct et131x_adapter *adapter = netdev_priv(netdev);
3164
3165 return phy_ethtool_sset(adapter->phydev, cmd);
3166 }
3167
3168 static int et131x_get_regs_len(struct net_device *netdev)
3169 {
3170 #define ET131X_REGS_LEN 256
3171 return ET131X_REGS_LEN * sizeof(u32);
3172 }
3173
3174 static void et131x_get_regs(struct net_device *netdev,
3175 struct ethtool_regs *regs, void *regs_data)
3176 {
3177 struct et131x_adapter *adapter = netdev_priv(netdev);
3178 struct address_map __iomem *aregs = adapter->regs;
3179 u32 *regs_buff = regs_data;
3180 u32 num = 0;
3181 u16 tmp;
3182
3183 memset(regs_data, 0, et131x_get_regs_len(netdev));
3184
3185 regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
3186 adapter->pdev->device;
3187
3188 /* PHY regs */
3189 et131x_mii_read(adapter, MII_BMCR, &tmp);
3190 regs_buff[num++] = tmp;
3191 et131x_mii_read(adapter, MII_BMSR, &tmp);
3192 regs_buff[num++] = tmp;
3193 et131x_mii_read(adapter, MII_PHYSID1, &tmp);
3194 regs_buff[num++] = tmp;
3195 et131x_mii_read(adapter, MII_PHYSID2, &tmp);
3196 regs_buff[num++] = tmp;
3197 et131x_mii_read(adapter, MII_ADVERTISE, &tmp);
3198 regs_buff[num++] = tmp;
3199 et131x_mii_read(adapter, MII_LPA, &tmp);
3200 regs_buff[num++] = tmp;
3201 et131x_mii_read(adapter, MII_EXPANSION, &tmp);
3202 regs_buff[num++] = tmp;
3203 /* Autoneg next page transmit reg */
3204 et131x_mii_read(adapter, 0x07, &tmp);
3205 regs_buff[num++] = tmp;
3206 /* Link partner next page reg */
3207 et131x_mii_read(adapter, 0x08, &tmp);
3208 regs_buff[num++] = tmp;
3209 et131x_mii_read(adapter, MII_CTRL1000, &tmp);
3210 regs_buff[num++] = tmp;
3211 et131x_mii_read(adapter, MII_STAT1000, &tmp);
3212 regs_buff[num++] = tmp;
3213 et131x_mii_read(adapter, 0x0b, &tmp);
3214 regs_buff[num++] = tmp;
3215 et131x_mii_read(adapter, 0x0c, &tmp);
3216 regs_buff[num++] = tmp;
3217 et131x_mii_read(adapter, MII_MMD_CTRL, &tmp);
3218 regs_buff[num++] = tmp;
3219 et131x_mii_read(adapter, MII_MMD_DATA, &tmp);
3220 regs_buff[num++] = tmp;
3221 et131x_mii_read(adapter, MII_ESTATUS, &tmp);
3222 regs_buff[num++] = tmp;
3223
3224 et131x_mii_read(adapter, PHY_INDEX_REG, &tmp);
3225 regs_buff[num++] = tmp;
3226 et131x_mii_read(adapter, PHY_DATA_REG, &tmp);
3227 regs_buff[num++] = tmp;
3228 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, &tmp);
3229 regs_buff[num++] = tmp;
3230 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL, &tmp);
3231 regs_buff[num++] = tmp;
3232 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL + 1, &tmp);
3233 regs_buff[num++] = tmp;
3234
3235 et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL, &tmp);
3236 regs_buff[num++] = tmp;
3237 et131x_mii_read(adapter, PHY_CONFIG, &tmp);
3238 regs_buff[num++] = tmp;
3239 et131x_mii_read(adapter, PHY_PHY_CONTROL, &tmp);
3240 regs_buff[num++] = tmp;
3241 et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &tmp);
3242 regs_buff[num++] = tmp;
3243 et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &tmp);
3244 regs_buff[num++] = tmp;
3245 et131x_mii_read(adapter, PHY_PHY_STATUS, &tmp);
3246 regs_buff[num++] = tmp;
3247 et131x_mii_read(adapter, PHY_LED_1, &tmp);
3248 regs_buff[num++] = tmp;
3249 et131x_mii_read(adapter, PHY_LED_2, &tmp);
3250 regs_buff[num++] = tmp;
3251
3252 /* Global regs */
3253 regs_buff[num++] = readl(&aregs->global.txq_start_addr);
3254 regs_buff[num++] = readl(&aregs->global.txq_end_addr);
3255 regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
3256 regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
3257 regs_buff[num++] = readl(&aregs->global.pm_csr);
3258 regs_buff[num++] = adapter->stats.interrupt_status;
3259 regs_buff[num++] = readl(&aregs->global.int_mask);
3260 regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
3261 regs_buff[num++] = readl(&aregs->global.int_status_alias);
3262 regs_buff[num++] = readl(&aregs->global.sw_reset);
3263 regs_buff[num++] = readl(&aregs->global.slv_timer);
3264 regs_buff[num++] = readl(&aregs->global.msi_config);
3265 regs_buff[num++] = readl(&aregs->global.loopback);
3266 regs_buff[num++] = readl(&aregs->global.watchdog_timer);
3267
3268 /* TXDMA regs */
3269 regs_buff[num++] = readl(&aregs->txdma.csr);
3270 regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
3271 regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
3272 regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
3273 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
3274 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
3275 regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
3276 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
3277 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
3278 regs_buff[num++] = readl(&aregs->txdma.service_request);
3279 regs_buff[num++] = readl(&aregs->txdma.service_complete);
3280 regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
3281 regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
3282 regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
3283 regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
3284 regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
3285 regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
3286 regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
3287 regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
3288 regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
3289 regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
3290 regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
3291 regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
3292 regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
3293 regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
3294 regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
3295
3296 /* RXDMA regs */
3297 regs_buff[num++] = readl(&aregs->rxdma.csr);
3298 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
3299 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
3300 regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
3301 regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
3302 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
3303 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
3304 regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
3305 regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
3306 regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
3307 regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
3308 regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
3309 regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
3310 regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
3311 regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
3312 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
3313 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
3314 regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
3315 regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
3316 regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
3317 regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
3318 regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
3319 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
3320 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
3321 regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
3322 regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
3323 regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
3324 regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
3325 regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
3326 }
3327
3328 static void et131x_get_drvinfo(struct net_device *netdev,
3329 struct ethtool_drvinfo *info)
3330 {
3331 struct et131x_adapter *adapter = netdev_priv(netdev);
3332
3333 strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
3334 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3335 strlcpy(info->bus_info, pci_name(adapter->pdev),
3336 sizeof(info->bus_info));
3337 }
3338
3339 static struct ethtool_ops et131x_ethtool_ops = {
3340 .get_settings = et131x_get_settings,
3341 .set_settings = et131x_set_settings,
3342 .get_drvinfo = et131x_get_drvinfo,
3343 .get_regs_len = et131x_get_regs_len,
3344 .get_regs = et131x_get_regs,
3345 .get_link = ethtool_op_get_link,
3346 };
3347
3348 /* et131x_hwaddr_init - set up the MAC Address on the ET1310 */
3349 static void et131x_hwaddr_init(struct et131x_adapter *adapter)
3350 {
3351 /* If have our default mac from init and no mac address from
3352 * EEPROM then we need to generate the last octet and set it on the
3353 * device
3354 */
3355 if (is_zero_ether_addr(adapter->rom_addr)) {
3356 /* We need to randomly generate the last octet so we
3357 * decrease our chances of setting the mac address to
3358 * same as another one of our cards in the system
3359 */
3360 get_random_bytes(&adapter->addr[5], 1);
3361 /* We have the default value in the register we are
3362 * working with so we need to copy the current
3363 * address into the permanent address
3364 */
3365 memcpy(adapter->rom_addr,
3366 adapter->addr, ETH_ALEN);
3367 } else {
3368 /* We do not have an override address, so set the
3369 * current address to the permanent address and add
3370 * it to the device
3371 */
3372 memcpy(adapter->addr,
3373 adapter->rom_addr, ETH_ALEN);
3374 }
3375 }
3376
3377 /* et131x_pci_init - initial PCI setup
3378 *
3379 * Perform the initial setup of PCI registers and if possible initialise
3380 * the MAC address. At this point the I/O registers have yet to be mapped
3381 */
3382 static int et131x_pci_init(struct et131x_adapter *adapter,
3383 struct pci_dev *pdev)
3384 {
3385 u16 max_payload;
3386 int i, rc;
3387
3388 rc = et131x_init_eeprom(adapter);
3389 if (rc < 0)
3390 goto out;
3391
3392 if (!pci_is_pcie(pdev)) {
3393 dev_err(&pdev->dev, "Missing PCIe capabilities\n");
3394 goto err_out;
3395 }
3396
3397 /* Let's set up the PORT LOGIC Register. */
3398
3399 /* Program the Ack/Nak latency and replay timers */
3400 max_payload = pdev->pcie_mpss;
3401
3402 if (max_payload < 2) {
3403 static const u16 acknak[2] = { 0x76, 0xD0 };
3404 static const u16 replay[2] = { 0x1E0, 0x2ED };
3405
3406 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
3407 acknak[max_payload])) {
3408 dev_err(&pdev->dev,
3409 "Could not write PCI config space for ACK/NAK\n");
3410 goto err_out;
3411 }
3412 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
3413 replay[max_payload])) {
3414 dev_err(&pdev->dev,
3415 "Could not write PCI config space for Replay Timer\n");
3416 goto err_out;
3417 }
3418 }
3419
3420 /* l0s and l1 latency timers. We are using default values.
3421 * Representing 001 for L0s and 010 for L1
3422 */
3423 if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
3424 dev_err(&pdev->dev,
3425 "Could not write PCI config space for Latency Timers\n");
3426 goto err_out;
3427 }
3428
3429 /* Change the max read size to 2k */
3430 if (pcie_set_readrq(pdev, 2048)) {
3431 dev_err(&pdev->dev,
3432 "Couldn't change PCI config space for Max read size\n");
3433 goto err_out;
3434 }
3435
3436 /* Get MAC address from config space if an eeprom exists, otherwise
3437 * the MAC address there will not be valid
3438 */
3439 if (!adapter->has_eeprom) {
3440 et131x_hwaddr_init(adapter);
3441 return 0;
3442 }
3443
3444 for (i = 0; i < ETH_ALEN; i++) {
3445 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
3446 adapter->rom_addr + i)) {
3447 dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
3448 goto err_out;
3449 }
3450 }
3451 ether_addr_copy(adapter->addr, adapter->rom_addr);
3452 out:
3453 return rc;
3454 err_out:
3455 rc = -EIO;
3456 goto out;
3457 }
3458
3459 /* et131x_error_timer_handler
3460 * @data: timer-specific variable; here a pointer to our adapter structure
3461 *
3462 * The routine called when the error timer expires, to track the number of
3463 * recurring errors.
3464 */
3465 static void et131x_error_timer_handler(unsigned long data)
3466 {
3467 struct et131x_adapter *adapter = (struct et131x_adapter *) data;
3468 struct phy_device *phydev = adapter->phydev;
3469
3470 if (et1310_in_phy_coma(adapter)) {
3471 /* Bring the device immediately out of coma, to
3472 * prevent it from sleeping indefinitely, this
3473 * mechanism could be improved!
3474 */
3475 et1310_disable_phy_coma(adapter);
3476 adapter->boot_coma = 20;
3477 } else {
3478 et1310_update_macstat_host_counters(adapter);
3479 }
3480
3481 if (!phydev->link && adapter->boot_coma < 11)
3482 adapter->boot_coma++;
3483
3484 if (adapter->boot_coma == 10) {
3485 if (!phydev->link) {
3486 if (!et1310_in_phy_coma(adapter)) {
3487 /* NOTE - This was originally a 'sync with
3488 * interrupt'. How to do that under Linux?
3489 */
3490 et131x_enable_interrupts(adapter);
3491 et1310_enable_phy_coma(adapter);
3492 }
3493 }
3494 }
3495
3496 /* This is a periodic timer, so reschedule */
3497 mod_timer(&adapter->error_timer, jiffies + TX_ERROR_PERIOD * HZ / 1000);
3498 }
3499
3500 /* et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx */
3501 static void et131x_adapter_memory_free(struct et131x_adapter *adapter)
3502 {
3503 et131x_tx_dma_memory_free(adapter);
3504 et131x_rx_dma_memory_free(adapter);
3505 }
3506
3507 /* et131x_adapter_memory_alloc
3508 * Allocate all the memory blocks for send, receive and others.
3509 */
3510 static int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
3511 {
3512 int status;
3513
3514 /* Allocate memory for the Tx Ring */
3515 status = et131x_tx_dma_memory_alloc(adapter);
3516 if (status) {
3517 dev_err(&adapter->pdev->dev,
3518 "et131x_tx_dma_memory_alloc FAILED\n");
3519 et131x_tx_dma_memory_free(adapter);
3520 return status;
3521 }
3522 /* Receive buffer memory allocation */
3523 status = et131x_rx_dma_memory_alloc(adapter);
3524 if (status) {
3525 dev_err(&adapter->pdev->dev,
3526 "et131x_rx_dma_memory_alloc FAILED\n");
3527 et131x_adapter_memory_free(adapter);
3528 return status;
3529 }
3530
3531 /* Init receive data structures */
3532 status = et131x_init_recv(adapter);
3533 if (status) {
3534 dev_err(&adapter->pdev->dev, "et131x_init_recv FAILED\n");
3535 et131x_adapter_memory_free(adapter);
3536 }
3537 return status;
3538 }
3539
3540 static void et131x_adjust_link(struct net_device *netdev)
3541 {
3542 struct et131x_adapter *adapter = netdev_priv(netdev);
3543 struct phy_device *phydev = adapter->phydev;
3544
3545 if (!phydev)
3546 return;
3547 if (phydev->link == adapter->link)
3548 return;
3549
3550 /* Check to see if we are in coma mode and if
3551 * so, disable it because we will not be able
3552 * to read PHY values until we are out.
3553 */
3554 if (et1310_in_phy_coma(adapter))
3555 et1310_disable_phy_coma(adapter);
3556
3557 adapter->link = phydev->link;
3558 phy_print_status(phydev);
3559
3560 if (phydev->link) {
3561 adapter->boot_coma = 20;
3562 if (phydev->speed == SPEED_10) {
3563 u16 register18;
3564
3565 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3566 &register18);
3567 et131x_mii_write(adapter, phydev->addr,
3568 PHY_MPHY_CONTROL_REG, register18 | 0x4);
3569 et131x_mii_write(adapter, phydev->addr, PHY_INDEX_REG,
3570 register18 | 0x8402);
3571 et131x_mii_write(adapter, phydev->addr, PHY_DATA_REG,
3572 register18 | 511);
3573 et131x_mii_write(adapter, phydev->addr,
3574 PHY_MPHY_CONTROL_REG, register18);
3575 }
3576
3577 et1310_config_flow_control(adapter);
3578
3579 if (phydev->speed == SPEED_1000 &&
3580 adapter->registry_jumbo_packet > 2048) {
3581 u16 reg;
3582
3583 et131x_mii_read(adapter, PHY_CONFIG, &reg);
3584 reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH;
3585 reg |= ET_PHY_CONFIG_FIFO_DEPTH_32;
3586 et131x_mii_write(adapter, phydev->addr, PHY_CONFIG,
3587 reg);
3588 }
3589
3590 et131x_set_rx_dma_timer(adapter);
3591 et1310_config_mac_regs2(adapter);
3592 } else {
3593 adapter->boot_coma = 0;
3594
3595 if (phydev->speed == SPEED_10) {
3596 u16 register18;
3597
3598 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3599 &register18);
3600 et131x_mii_write(adapter, phydev->addr,
3601 PHY_MPHY_CONTROL_REG, register18 | 0x4);
3602 et131x_mii_write(adapter, phydev->addr,
3603 PHY_INDEX_REG, register18 | 0x8402);
3604 et131x_mii_write(adapter, phydev->addr,
3605 PHY_DATA_REG, register18 | 511);
3606 et131x_mii_write(adapter, phydev->addr,
3607 PHY_MPHY_CONTROL_REG, register18);
3608 }
3609
3610 /* Free the packets being actively sent & stopped */
3611 et131x_free_busy_send_packets(adapter);
3612
3613 /* Re-initialize the send structures */
3614 et131x_init_send(adapter);
3615
3616 /* Bring the device back to the state it was during
3617 * init prior to autonegotiation being complete. This
3618 * way, when we get the auto-neg complete interrupt,
3619 * we can complete init by calling config_mac_regs2.
3620 */
3621 et131x_soft_reset(adapter);
3622
3623 /* Setup ET1310 as per the documentation */
3624 et131x_adapter_setup(adapter);
3625
3626 /* perform reset of tx/rx */
3627 et131x_disable_txrx(netdev);
3628 et131x_enable_txrx(netdev);
3629 }
3630 }
3631
3632 static int et131x_mii_probe(struct net_device *netdev)
3633 {
3634 struct et131x_adapter *adapter = netdev_priv(netdev);
3635 struct phy_device *phydev = NULL;
3636
3637 phydev = phy_find_first(adapter->mii_bus);
3638 if (!phydev) {
3639 dev_err(&adapter->pdev->dev, "no PHY found\n");
3640 return -ENODEV;
3641 }
3642
3643 phydev = phy_connect(netdev, dev_name(&phydev->dev),
3644 &et131x_adjust_link, PHY_INTERFACE_MODE_MII);
3645
3646 if (IS_ERR(phydev)) {
3647 dev_err(&adapter->pdev->dev, "Could not attach to PHY\n");
3648 return PTR_ERR(phydev);
3649 }
3650
3651 phydev->supported &= (SUPPORTED_10baseT_Half
3652 | SUPPORTED_10baseT_Full
3653 | SUPPORTED_100baseT_Half
3654 | SUPPORTED_100baseT_Full
3655 | SUPPORTED_Autoneg
3656 | SUPPORTED_MII
3657 | SUPPORTED_TP);
3658
3659 if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
3660 phydev->supported |= SUPPORTED_1000baseT_Full;
3661
3662 phydev->advertising = phydev->supported;
3663 adapter->phydev = phydev;
3664
3665 dev_info(&adapter->pdev->dev,
3666 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3667 phydev->drv->name, dev_name(&phydev->dev));
3668
3669 return 0;
3670 }
3671
3672 /* et131x_adapter_init
3673 *
3674 * Initialize the data structures for the et131x_adapter object and link
3675 * them together with the platform provided device structures.
3676 */
3677 static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
3678 struct pci_dev *pdev)
3679 {
3680 static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
3681
3682 struct et131x_adapter *adapter;
3683
3684 /* Allocate private adapter struct and copy in relevant information */
3685 adapter = netdev_priv(netdev);
3686 adapter->pdev = pci_dev_get(pdev);
3687 adapter->netdev = netdev;
3688
3689 /* Initialize spinlocks here */
3690 spin_lock_init(&adapter->tcb_send_qlock);
3691 spin_lock_init(&adapter->tcb_ready_qlock);
3692 spin_lock_init(&adapter->send_hw_lock);
3693 spin_lock_init(&adapter->rcv_lock);
3694 spin_lock_init(&adapter->fbr_lock);
3695
3696 adapter->registry_jumbo_packet = 1514; /* 1514-9216 */
3697
3698 /* Set the MAC address to a default */
3699 ether_addr_copy(adapter->addr, default_mac);
3700
3701 return adapter;
3702 }
3703
3704 /* et131x_pci_remove
3705 *
3706 * Registered in the pci_driver structure, this function is called when the
3707 * PCI subsystem detects that a PCI device which matches the information
3708 * contained in the pci_device_id table has been removed.
3709 */
3710 static void et131x_pci_remove(struct pci_dev *pdev)
3711 {
3712 struct net_device *netdev = pci_get_drvdata(pdev);
3713 struct et131x_adapter *adapter = netdev_priv(netdev);
3714
3715 unregister_netdev(netdev);
3716 netif_napi_del(&adapter->napi);
3717 phy_disconnect(adapter->phydev);
3718 mdiobus_unregister(adapter->mii_bus);
3719 kfree(adapter->mii_bus->irq);
3720 mdiobus_free(adapter->mii_bus);
3721
3722 et131x_adapter_memory_free(adapter);
3723 iounmap(adapter->regs);
3724 pci_dev_put(pdev);
3725
3726 free_netdev(netdev);
3727 pci_release_regions(pdev);
3728 pci_disable_device(pdev);
3729 }
3730
3731 /* et131x_up - Bring up a device for use. */
3732 static void et131x_up(struct net_device *netdev)
3733 {
3734 struct et131x_adapter *adapter = netdev_priv(netdev);
3735
3736 et131x_enable_txrx(netdev);
3737 phy_start(adapter->phydev);
3738 }
3739
3740 /* et131x_down - Bring down the device */
3741 static void et131x_down(struct net_device *netdev)
3742 {
3743 struct et131x_adapter *adapter = netdev_priv(netdev);
3744
3745 /* Save the timestamp for the TX watchdog, prevent a timeout */
3746 netdev->trans_start = jiffies;
3747
3748 phy_stop(adapter->phydev);
3749 et131x_disable_txrx(netdev);
3750 }
3751
3752 #ifdef CONFIG_PM_SLEEP
3753 static int et131x_suspend(struct device *dev)
3754 {
3755 struct pci_dev *pdev = to_pci_dev(dev);
3756 struct net_device *netdev = pci_get_drvdata(pdev);
3757
3758 if (netif_running(netdev)) {
3759 netif_device_detach(netdev);
3760 et131x_down(netdev);
3761 pci_save_state(pdev);
3762 }
3763
3764 return 0;
3765 }
3766
3767 static int et131x_resume(struct device *dev)
3768 {
3769 struct pci_dev *pdev = to_pci_dev(dev);
3770 struct net_device *netdev = pci_get_drvdata(pdev);
3771
3772 if (netif_running(netdev)) {
3773 pci_restore_state(pdev);
3774 et131x_up(netdev);
3775 netif_device_attach(netdev);
3776 }
3777
3778 return 0;
3779 }
3780
3781 static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
3782 #define ET131X_PM_OPS (&et131x_pm_ops)
3783 #else
3784 #define ET131X_PM_OPS NULL
3785 #endif
3786
3787 /* et131x_isr - The Interrupt Service Routine for the driver.
3788 * @irq: the IRQ on which the interrupt was received.
3789 * @dev_id: device-specific info (here a pointer to a net_device struct)
3790 *
3791 * Returns a value indicating if the interrupt was handled.
3792 */
3793 static irqreturn_t et131x_isr(int irq, void *dev_id)
3794 {
3795 bool handled = true;
3796 bool enable_interrupts = true;
3797 struct net_device *netdev = (struct net_device *)dev_id;
3798 struct et131x_adapter *adapter = netdev_priv(netdev);
3799 struct address_map __iomem *iomem = adapter->regs;
3800 struct rx_ring *rx_ring = &adapter->rx_ring;
3801 struct tx_ring *tx_ring = &adapter->tx_ring;
3802 u32 status;
3803
3804 if (!netif_device_present(netdev)) {
3805 handled = false;
3806 enable_interrupts = false;
3807 goto out;
3808 }
3809
3810 /* If the adapter is in low power state, then it should not
3811 * recognize any interrupt
3812 */
3813
3814 /* Disable Device Interrupts */
3815 et131x_disable_interrupts(adapter);
3816
3817 /* Get a copy of the value in the interrupt status register
3818 * so we can process the interrupting section
3819 */
3820 status = readl(&adapter->regs->global.int_status);
3821
3822 if (adapter->flowcontrol == FLOW_TXONLY ||
3823 adapter->flowcontrol == FLOW_BOTH) {
3824 status &= ~INT_MASK_ENABLE;
3825 } else {
3826 status &= ~INT_MASK_ENABLE_NO_FLOW;
3827 }
3828
3829 /* Make sure this is our interrupt */
3830 if (!status) {
3831 handled = false;
3832 et131x_enable_interrupts(adapter);
3833 goto out;
3834 }
3835
3836 /* This is our interrupt, so process accordingly */
3837 if (status & ET_INTR_WATCHDOG) {
3838 struct tcb *tcb = tx_ring->send_head;
3839
3840 if (tcb)
3841 if (++tcb->stale > 1)
3842 status |= ET_INTR_TXDMA_ISR;
3843
3844 if (rx_ring->unfinished_receives)
3845 status |= ET_INTR_RXDMA_XFR_DONE;
3846 else if (tcb == NULL)
3847 writel(0, &adapter->regs->global.watchdog_timer);
3848
3849 status &= ~ET_INTR_WATCHDOG;
3850 }
3851
3852 if (status & (ET_INTR_RXDMA_XFR_DONE | ET_INTR_TXDMA_ISR)) {
3853 enable_interrupts = false;
3854 napi_schedule(&adapter->napi);
3855 }
3856
3857 status &= ~(ET_INTR_TXDMA_ISR | ET_INTR_RXDMA_XFR_DONE);
3858
3859 if (!status)
3860 goto out;
3861
3862 /* Handle the TXDMA Error interrupt */
3863 if (status & ET_INTR_TXDMA_ERR) {
3864 /* Following read also clears the register (COR) */
3865 u32 txdma_err = readl(&iomem->txdma.tx_dma_error);
3866
3867 dev_warn(&adapter->pdev->dev,
3868 "TXDMA_ERR interrupt, error = %d\n",
3869 txdma_err);
3870 }
3871
3872 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
3873 if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
3874 /* This indicates the number of unused buffers in RXDMA free
3875 * buffer ring 0 is <= the limit you programmed. Free buffer
3876 * resources need to be returned. Free buffers are consumed as
3877 * packets are passed from the network to the host. The host
3878 * becomes aware of the packets from the contents of the packet
3879 * status ring. This ring is queried when the packet done
3880 * interrupt occurs. Packets are then passed to the OS. When
3881 * the OS is done with the packets the resources can be
3882 * returned to the ET1310 for re-use. This interrupt is one
3883 * method of returning resources.
3884 */
3885
3886 /* If the user has flow control on, then we will
3887 * send a pause packet, otherwise just exit
3888 */
3889 if (adapter->flowcontrol == FLOW_TXONLY ||
3890 adapter->flowcontrol == FLOW_BOTH) {
3891 u32 pm_csr;
3892
3893 /* Tell the device to send a pause packet via the back
3894 * pressure register (bp req and bp xon/xoff)
3895 */
3896 pm_csr = readl(&iomem->global.pm_csr);
3897 if (!et1310_in_phy_coma(adapter))
3898 writel(3, &iomem->txmac.bp_ctrl);
3899 }
3900 }
3901
3902 /* Handle Packet Status Ring Low Interrupt */
3903 if (status & ET_INTR_RXDMA_STAT_LOW) {
3904 /* Same idea as with the two Free Buffer Rings. Packets going
3905 * from the network to the host each consume a free buffer
3906 * resource and a packet status resource. These resources are
3907 * passed to the OS. When the OS is done with the resources,
3908 * they need to be returned to the ET1310. This is one method
3909 * of returning the resources.
3910 */
3911 }
3912
3913 /* Handle RXDMA Error Interrupt */
3914 if (status & ET_INTR_RXDMA_ERR) {
3915 /* The rxdma_error interrupt is sent when a time-out on a
3916 * request issued by the JAGCore has occurred or a completion is
3917 * returned with an un-successful status. In both cases the
3918 * request is considered complete. The JAGCore will
3919 * automatically re-try the request in question. Normally
3920 * information on events like these are sent to the host using
3921 * the "Advanced Error Reporting" capability. This interrupt is
3922 * another way of getting similar information. The only thing
3923 * required is to clear the interrupt by reading the ISR in the
3924 * global resources. The JAGCore will do a re-try on the
3925 * request. Normally you should never see this interrupt. If
3926 * you start to see this interrupt occurring frequently then
3927 * something bad has occurred. A reset might be the thing to do.
3928 */
3929 /* TRAP();*/
3930
3931 dev_warn(&adapter->pdev->dev,
3932 "RxDMA_ERR interrupt, error %x\n",
3933 readl(&iomem->txmac.tx_test));
3934 }
3935
3936 /* Handle the Wake on LAN Event */
3937 if (status & ET_INTR_WOL) {
3938 /* This is a secondary interrupt for wake on LAN. The driver
3939 * should never see this, if it does, something serious is
3940 * wrong. We will TRAP the message when we are in DBG mode,
3941 * otherwise we will ignore it.
3942 */
3943 dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
3944 }
3945
3946 /* Let's move on to the TxMac */
3947 if (status & ET_INTR_TXMAC) {
3948 u32 err = readl(&iomem->txmac.err);
3949
3950 /* When any of the errors occur and TXMAC generates an
3951 * interrupt to report these errors, it usually means that
3952 * TXMAC has detected an error in the data stream retrieved
3953 * from the on-chip Tx Q. All of these errors are catastrophic
3954 * and TXMAC won't be able to recover data when these errors
3955 * occur. In a nutshell, the whole Tx path will have to be reset
3956 * and re-configured afterwards.
3957 */
3958 dev_warn(&adapter->pdev->dev,
3959 "TXMAC interrupt, error 0x%08x\n",
3960 err);
3961
3962 /* If we are debugging, we want to see this error, otherwise we
3963 * just want the device to be reset and continue
3964 */
3965 }
3966
3967 /* Handle RXMAC Interrupt */
3968 if (status & ET_INTR_RXMAC) {
3969 /* These interrupts are catastrophic to the device, what we need
3970 * to do is disable the interrupts and set the flag to cause us
3971 * to reset so we can solve this issue.
3972 */
3973 /* MP_SET_FLAG( adapter, FMP_ADAPTER_HARDWARE_ERROR); */
3974
3975 dev_warn(&adapter->pdev->dev,
3976 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
3977 readl(&iomem->rxmac.err_reg));
3978
3979 dev_warn(&adapter->pdev->dev,
3980 "Enable 0x%08x, Diag 0x%08x\n",
3981 readl(&iomem->rxmac.ctrl),
3982 readl(&iomem->rxmac.rxq_diag));
3983
3984 /* If we are debugging, we want to see this error, otherwise we
3985 * just want the device to be reset and continue
3986 */
3987 }
3988
3989 /* Handle MAC_STAT Interrupt */
3990 if (status & ET_INTR_MAC_STAT) {
3991 /* This means at least one of the un-masked counters in the
3992 * MAC_STAT block has rolled over. Use this to maintain the top,
3993 * software managed bits of the counter(s).
3994 */
3995 et1310_handle_macstat_interrupt(adapter);
3996 }
3997
3998 /* Handle SLV Timeout Interrupt */
3999 if (status & ET_INTR_SLV_TIMEOUT) {
4000 /* This means a timeout has occurred on a read or write request
4001 * to one of the JAGCore registers. The Global Resources block
4002 * has terminated the request and on a read request, returned a
4003 * "fake" value. The most likely reasons are: Bad Address or the
4004 * addressed module is in a power-down state and can't respond.
4005 */
4006 }
4007
4008 out:
4009 if (enable_interrupts)
4010 et131x_enable_interrupts(adapter);
4011
4012 return IRQ_RETVAL(handled);
4013 }
4014
4015 static int et131x_poll(struct napi_struct *napi, int budget)
4016 {
4017 struct et131x_adapter *adapter =
4018 container_of(napi, struct et131x_adapter, napi);
4019 int work_done = et131x_handle_recv_pkts(adapter, budget);
4020
4021 et131x_handle_send_pkts(adapter);
4022
4023 if (work_done < budget) {
4024 napi_complete(&adapter->napi);
4025 et131x_enable_interrupts(adapter);
4026 }
4027
4028 return work_done;
4029 }
4030
4031 /* et131x_stats - Return the current device statistics */
4032 static struct net_device_stats *et131x_stats(struct net_device *netdev)
4033 {
4034 struct et131x_adapter *adapter = netdev_priv(netdev);
4035 struct net_device_stats *stats = &adapter->netdev->stats;
4036 struct ce_stats *devstat = &adapter->stats;
4037
4038 stats->rx_errors = devstat->rx_length_errs +
4039 devstat->rx_align_errs +
4040 devstat->rx_crc_errs +
4041 devstat->rx_code_violations +
4042 devstat->rx_other_errs;
4043 stats->tx_errors = devstat->tx_max_pkt_errs;
4044 stats->multicast = devstat->multicast_pkts_rcvd;
4045 stats->collisions = devstat->tx_collisions;
4046
4047 stats->rx_length_errors = devstat->rx_length_errs;
4048 stats->rx_over_errors = devstat->rx_overflows;
4049 stats->rx_crc_errors = devstat->rx_crc_errs;
4050
4051 /* NOTE: These stats don't have corresponding values in CE_STATS,
4052 * so we're going to have to update these directly from within the
4053 * TX/RX code
4054 */
4055 /* stats->rx_bytes = 20; devstat->; */
4056 /* stats->tx_bytes = 20; devstat->; */
4057 /* stats->rx_dropped = devstat->; */
4058 /* stats->tx_dropped = devstat->; */
4059
4060 /* NOTE: Not used, can't find analogous statistics */
4061 /* stats->rx_frame_errors = devstat->; */
4062 /* stats->rx_fifo_errors = devstat->; */
4063 /* stats->rx_missed_errors = devstat->; */
4064
4065 /* stats->tx_aborted_errors = devstat->; */
4066 /* stats->tx_carrier_errors = devstat->; */
4067 /* stats->tx_fifo_errors = devstat->; */
4068 /* stats->tx_heartbeat_errors = devstat->; */
4069 /* stats->tx_window_errors = devstat->; */
4070 return stats;
4071 }
4072
4073 /* et131x_open - Open the device for use. */
4074 static int et131x_open(struct net_device *netdev)
4075 {
4076 struct et131x_adapter *adapter = netdev_priv(netdev);
4077 struct pci_dev *pdev = adapter->pdev;
4078 unsigned int irq = pdev->irq;
4079 int result;
4080
4081 /* Start the timer to track NIC errors */
4082 init_timer(&adapter->error_timer);
4083 adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
4084 adapter->error_timer.function = et131x_error_timer_handler;
4085 adapter->error_timer.data = (unsigned long)adapter;
4086 add_timer(&adapter->error_timer);
4087
4088 result = request_irq(irq, et131x_isr,
4089 IRQF_SHARED, netdev->name, netdev);
4090 if (result) {
4091 dev_err(&pdev->dev, "could not register IRQ %d\n", irq);
4092 return result;
4093 }
4094
4095 adapter->flags |= FMP_ADAPTER_INTERRUPT_IN_USE;
4096
4097 napi_enable(&adapter->napi);
4098
4099 et131x_up(netdev);
4100
4101 return result;
4102 }
4103
4104 /* et131x_close - Close the device */
4105 static int et131x_close(struct net_device *netdev)
4106 {
4107 struct et131x_adapter *adapter = netdev_priv(netdev);
4108
4109 et131x_down(netdev);
4110 napi_disable(&adapter->napi);
4111
4112 adapter->flags &= ~FMP_ADAPTER_INTERRUPT_IN_USE;
4113 free_irq(adapter->pdev->irq, netdev);
4114
4115 /* Stop the error timer */
4116 return del_timer_sync(&adapter->error_timer);
4117 }
4118
4119 /* et131x_ioctl - The I/O Control handler for the driver
4120 * @netdev: device on which the control request is being made
4121 * @reqbuf: a pointer to the IOCTL request buffer
4122 * @cmd: the IOCTL command code
4123 */
4124 static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf,
4125 int cmd)
4126 {
4127 struct et131x_adapter *adapter = netdev_priv(netdev);
4128
4129 if (!adapter->phydev)
4130 return -EINVAL;
4131
4132 return phy_mii_ioctl(adapter->phydev, reqbuf, cmd);
4133 }
4134
4135 /* et131x_set_packet_filter - Configures the Rx Packet filtering on the device
4136 * @adapter: pointer to our private adapter structure
4137 *
4138 * FIXME: lot of dups with MAC code
4139 */
4140 static int et131x_set_packet_filter(struct et131x_adapter *adapter)
4141 {
4142 int filter = adapter->packet_filter;
4143 u32 ctrl;
4144 u32 pf_ctrl;
4145
4146 ctrl = readl(&adapter->regs->rxmac.ctrl);
4147 pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
4148
4149 /* Default to disabled packet filtering. Enable it in the individual
4150 * case statements that require the device to filter something
4151 */
4152 ctrl |= 0x04;
4153
4154 /* Set us to be in promiscuous mode so we receive everything, this
4155 * is also true when we get a packet filter of 0
4156 */
4157 if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
4158 pf_ctrl &= ~7; /* Clear filter bits */
4159 else {
4160 /* Set us up with Multicast packet filtering. Three cases are
4161 * possible - (1) we have a multi-cast list, (2) we receive ALL
4162 * multicast entries or (3) we receive none.
4163 */
4164 if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
4165 pf_ctrl &= ~2; /* Multicast filter bit */
4166 else {
4167 et1310_setup_device_for_multicast(adapter);
4168 pf_ctrl |= 2;
4169 ctrl &= ~0x04;
4170 }
4171
4172 /* Set us up with Unicast packet filtering */
4173 if (filter & ET131X_PACKET_TYPE_DIRECTED) {
4174 et1310_setup_device_for_unicast(adapter);
4175 pf_ctrl |= 4;
4176 ctrl &= ~0x04;
4177 }
4178
4179 /* Set us up with Broadcast packet filtering */
4180 if (filter & ET131X_PACKET_TYPE_BROADCAST) {
4181 pf_ctrl |= 1; /* Broadcast filter bit */
4182 ctrl &= ~0x04;
4183 } else
4184 pf_ctrl &= ~1;
4185
4186 /* Setup the receive mac configuration registers - Packet
4187 * Filter control + the enable / disable for packet filter
4188 * in the control reg.
4189 */
4190 writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
4191 writel(ctrl, &adapter->regs->rxmac.ctrl);
4192 }
4193 return 0;
4194 }
4195
4196 /* et131x_multicast - The handler to configure multicasting on the interface */
4197 static void et131x_multicast(struct net_device *netdev)
4198 {
4199 struct et131x_adapter *adapter = netdev_priv(netdev);
4200 int packet_filter;
4201 struct netdev_hw_addr *ha;
4202 int i;
4203
4204 /* Before we modify the platform-independent filter flags, store them
4205 * locally. This allows us to determine if anything's changed and if
4206 * we even need to bother the hardware
4207 */
4208 packet_filter = adapter->packet_filter;
4209
4210 /* Clear the 'multicast' flag locally; because we only have a single
4211 * flag to check multicast, and multiple multicast addresses can be
4212 * set, this is the easiest way to determine if more than one
4213 * multicast address is being set.
4214 */
4215 packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4216
4217 /* Check the net_device flags and set the device independent flags
4218 * accordingly
4219 */
4220
4221 if (netdev->flags & IFF_PROMISC)
4222 adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
4223 else
4224 adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
4225
4226 if (netdev->flags & IFF_ALLMULTI)
4227 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4228
4229 if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST)
4230 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4231
4232 if (netdev_mc_count(netdev) < 1) {
4233 adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
4234 adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4235 } else
4236 adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST;
4237
4238 /* Set values in the private adapter struct */
4239 i = 0;
4240 netdev_for_each_mc_addr(ha, netdev) {
4241 if (i == NIC_MAX_MCAST_LIST)
4242 break;
4243 memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN);
4244 }
4245 adapter->multicast_addr_count = i;
4246
4247 /* Are the new flags different from the previous ones? If not, then no
4248 * action is required
4249 *
4250 * NOTE - This block will always update the multicast_list with the
4251 * hardware, even if the addresses aren't the same.
4252 */
4253 if (packet_filter != adapter->packet_filter)
4254 et131x_set_packet_filter(adapter);
4255 }
4256
4257 /* et131x_tx - The handler to tx a packet on the device */
4258 static netdev_tx_t et131x_tx(struct sk_buff *skb, struct net_device *netdev)
4259 {
4260 int status = 0;
4261 struct et131x_adapter *adapter = netdev_priv(netdev);
4262 struct tx_ring *tx_ring = &adapter->tx_ring;
4263
4264 /* stop the queue if it's getting full */
4265 if (tx_ring->used >= NUM_TCB - 1 && !netif_queue_stopped(netdev))
4266 netif_stop_queue(netdev);
4267
4268 /* Save the timestamp for the TX timeout watchdog */
4269 netdev->trans_start = jiffies;
4270
4271 /* Call the device-specific data Tx routine */
4272 status = et131x_send_packets(skb, netdev);
4273
4274 /* Check status and manage the netif queue if necessary */
4275 if (status != 0) {
4276 if (status == -ENOMEM)
4277 status = NETDEV_TX_BUSY;
4278 else
4279 status = NETDEV_TX_OK;
4280 }
4281 return status;
4282 }
4283
4284 /* et131x_tx_timeout - Timeout handler
4285 *
4286 * The handler called when a Tx request times out. The timeout period is
4287 * specified by the 'tx_timeo" element in the net_device structure (see
4288 * et131x_alloc_device() to see how this value is set).
4289 */
4290 static void et131x_tx_timeout(struct net_device *netdev)
4291 {
4292 struct et131x_adapter *adapter = netdev_priv(netdev);
4293 struct tx_ring *tx_ring = &adapter->tx_ring;
4294 struct tcb *tcb;
4295 unsigned long flags;
4296
4297 /* If the device is closed, ignore the timeout */
4298 if (~(adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE))
4299 return;
4300
4301 /* Any nonrecoverable hardware error?
4302 * Checks adapter->flags for any failure in phy reading
4303 */
4304 if (adapter->flags & FMP_ADAPTER_NON_RECOVER_ERROR)
4305 return;
4306
4307 /* Hardware failure? */
4308 if (adapter->flags & FMP_ADAPTER_HARDWARE_ERROR) {
4309 dev_err(&adapter->pdev->dev, "hardware error - reset\n");
4310 return;
4311 }
4312
4313 /* Is send stuck? */
4314 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
4315
4316 tcb = tx_ring->send_head;
4317
4318 if (tcb != NULL) {
4319 tcb->count++;
4320
4321 if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
4322 spin_unlock_irqrestore(&adapter->tcb_send_qlock,
4323 flags);
4324
4325 dev_warn(&adapter->pdev->dev,
4326 "Send stuck - reset. tcb->WrIndex %x, flags 0x%08x\n",
4327 tcb->index,
4328 tcb->flags);
4329
4330 adapter->netdev->stats.tx_errors++;
4331
4332 /* perform reset of tx/rx */
4333 et131x_disable_txrx(netdev);
4334 et131x_enable_txrx(netdev);
4335 return;
4336 }
4337 }
4338
4339 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
4340 }
4341
4342 /* et131x_change_mtu - The handler called to change the MTU for the device */
4343 static int et131x_change_mtu(struct net_device *netdev, int new_mtu)
4344 {
4345 int result = 0;
4346 struct et131x_adapter *adapter = netdev_priv(netdev);
4347
4348 /* Make sure the requested MTU is valid */
4349 if (new_mtu < 64 || new_mtu > 9216)
4350 return -EINVAL;
4351
4352 et131x_disable_txrx(netdev);
4353
4354 /* Set the new MTU */
4355 netdev->mtu = new_mtu;
4356
4357 /* Free Rx DMA memory */
4358 et131x_adapter_memory_free(adapter);
4359
4360 /* Set the config parameter for Jumbo Packet support */
4361 adapter->registry_jumbo_packet = new_mtu + 14;
4362 et131x_soft_reset(adapter);
4363
4364 /* Alloc and init Rx DMA memory */
4365 result = et131x_adapter_memory_alloc(adapter);
4366 if (result != 0) {
4367 dev_warn(&adapter->pdev->dev,
4368 "Change MTU failed; couldn't re-alloc DMA memory\n");
4369 return result;
4370 }
4371
4372 et131x_init_send(adapter);
4373
4374 et131x_hwaddr_init(adapter);
4375 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4376
4377 /* Init the device with the new settings */
4378 et131x_adapter_setup(adapter);
4379
4380 et131x_enable_txrx(netdev);
4381
4382 return result;
4383 }
4384
4385 static const struct net_device_ops et131x_netdev_ops = {
4386 .ndo_open = et131x_open,
4387 .ndo_stop = et131x_close,
4388 .ndo_start_xmit = et131x_tx,
4389 .ndo_set_rx_mode = et131x_multicast,
4390 .ndo_tx_timeout = et131x_tx_timeout,
4391 .ndo_change_mtu = et131x_change_mtu,
4392 .ndo_set_mac_address = eth_mac_addr,
4393 .ndo_validate_addr = eth_validate_addr,
4394 .ndo_get_stats = et131x_stats,
4395 .ndo_do_ioctl = et131x_ioctl,
4396 };
4397
4398 /* et131x_pci_setup - Perform device initialization
4399 * @pdev: a pointer to the device's pci_dev structure
4400 * @ent: this device's entry in the pci_device_id table
4401 *
4402 * Registered in the pci_driver structure, this function is called when the
4403 * PCI subsystem finds a new PCI device which matches the information
4404 * contained in the pci_device_id table. This routine is the equivalent to
4405 * a device insertion routine.
4406 */
4407 static int et131x_pci_setup(struct pci_dev *pdev,
4408 const struct pci_device_id *ent)
4409 {
4410 struct net_device *netdev;
4411 struct et131x_adapter *adapter;
4412 int rc;
4413 int ii;
4414
4415 rc = pci_enable_device(pdev);
4416 if (rc < 0) {
4417 dev_err(&pdev->dev, "pci_enable_device() failed\n");
4418 goto out;
4419 }
4420
4421 /* Perform some basic PCI checks */
4422 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4423 dev_err(&pdev->dev, "Can't find PCI device's base address\n");
4424 rc = -ENODEV;
4425 goto err_disable;
4426 }
4427
4428 rc = pci_request_regions(pdev, DRIVER_NAME);
4429 if (rc < 0) {
4430 dev_err(&pdev->dev, "Can't get PCI resources\n");
4431 goto err_disable;
4432 }
4433
4434 pci_set_master(pdev);
4435
4436 /* Check the DMA addressing support of this device */
4437 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
4438 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
4439 dev_err(&pdev->dev, "No usable DMA addressing method\n");
4440 rc = -EIO;
4441 goto err_release_res;
4442 }
4443
4444 /* Allocate netdev and private adapter structs */
4445 netdev = alloc_etherdev(sizeof(struct et131x_adapter));
4446 if (!netdev) {
4447 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
4448 rc = -ENOMEM;
4449 goto err_release_res;
4450 }
4451
4452 netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
4453 netdev->netdev_ops = &et131x_netdev_ops;
4454
4455 SET_NETDEV_DEV(netdev, &pdev->dev);
4456 netdev->ethtool_ops = &et131x_ethtool_ops;
4457
4458 adapter = et131x_adapter_init(netdev, pdev);
4459
4460 rc = et131x_pci_init(adapter, pdev);
4461 if (rc < 0)
4462 goto err_free_dev;
4463
4464 /* Map the bus-relative registers to system virtual memory */
4465 adapter->regs = pci_ioremap_bar(pdev, 0);
4466 if (!adapter->regs) {
4467 dev_err(&pdev->dev, "Cannot map device registers\n");
4468 rc = -ENOMEM;
4469 goto err_free_dev;
4470 }
4471
4472 /* If Phy COMA mode was enabled when we went down, disable it here. */
4473 writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
4474
4475 /* Issue a global reset to the et1310 */
4476 et131x_soft_reset(adapter);
4477
4478 /* Disable all interrupts (paranoid) */
4479 et131x_disable_interrupts(adapter);
4480
4481 /* Allocate DMA memory */
4482 rc = et131x_adapter_memory_alloc(adapter);
4483 if (rc < 0) {
4484 dev_err(&pdev->dev, "Could not alloc adapter memory (DMA)\n");
4485 goto err_iounmap;
4486 }
4487
4488 /* Init send data structures */
4489 et131x_init_send(adapter);
4490
4491 netif_napi_add(netdev, &adapter->napi, et131x_poll, 64);
4492
4493 /* Copy address into the net_device struct */
4494 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4495
4496 rc = -ENOMEM;
4497
4498 /* Setup the mii_bus struct */
4499 adapter->mii_bus = mdiobus_alloc();
4500 if (!adapter->mii_bus) {
4501 dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n");
4502 goto err_mem_free;
4503 }
4504
4505 adapter->mii_bus->name = "et131x_eth_mii";
4506 snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
4507 (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
4508 adapter->mii_bus->priv = netdev;
4509 adapter->mii_bus->read = et131x_mdio_read;
4510 adapter->mii_bus->write = et131x_mdio_write;
4511 adapter->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int),
4512 GFP_KERNEL);
4513 if (!adapter->mii_bus->irq)
4514 goto err_mdio_free;
4515
4516 for (ii = 0; ii < PHY_MAX_ADDR; ii++)
4517 adapter->mii_bus->irq[ii] = PHY_POLL;
4518
4519 rc = mdiobus_register(adapter->mii_bus);
4520 if (rc < 0) {
4521 dev_err(&pdev->dev, "failed to register MII bus\n");
4522 goto err_mdio_free_irq;
4523 }
4524
4525 rc = et131x_mii_probe(netdev);
4526 if (rc < 0) {
4527 dev_err(&pdev->dev, "failed to probe MII bus\n");
4528 goto err_mdio_unregister;
4529 }
4530
4531 /* Setup et1310 as per the documentation */
4532 et131x_adapter_setup(adapter);
4533
4534 /* Init variable for counting how long we do not have link status */
4535 adapter->boot_coma = 0;
4536 et1310_disable_phy_coma(adapter);
4537
4538 /* We can enable interrupts now
4539 *
4540 * NOTE - Because registration of interrupt handler is done in the
4541 * device's open(), defer enabling device interrupts to that
4542 * point
4543 */
4544
4545 /* Register the net_device struct with the Linux network layer */
4546 rc = register_netdev(netdev);
4547 if (rc < 0) {
4548 dev_err(&pdev->dev, "register_netdev() failed\n");
4549 goto err_phy_disconnect;
4550 }
4551
4552 /* Register the net_device struct with the PCI subsystem. Save a copy
4553 * of the PCI config space for this device now that the device has
4554 * been initialized, just in case it needs to be quickly restored.
4555 */
4556 pci_set_drvdata(pdev, netdev);
4557 out:
4558 return rc;
4559
4560 err_phy_disconnect:
4561 phy_disconnect(adapter->phydev);
4562 err_mdio_unregister:
4563 mdiobus_unregister(adapter->mii_bus);
4564 err_mdio_free_irq:
4565 kfree(adapter->mii_bus->irq);
4566 err_mdio_free:
4567 mdiobus_free(adapter->mii_bus);
4568 err_mem_free:
4569 et131x_adapter_memory_free(adapter);
4570 err_iounmap:
4571 iounmap(adapter->regs);
4572 err_free_dev:
4573 pci_dev_put(pdev);
4574 free_netdev(netdev);
4575 err_release_res:
4576 pci_release_regions(pdev);
4577 err_disable:
4578 pci_disable_device(pdev);
4579 goto out;
4580 }
4581
4582 static const struct pci_device_id et131x_pci_table[] = {
4583 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL},
4584 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL},
4585 {0,}
4586 };
4587 MODULE_DEVICE_TABLE(pci, et131x_pci_table);
4588
4589 static struct pci_driver et131x_driver = {
4590 .name = DRIVER_NAME,
4591 .id_table = et131x_pci_table,
4592 .probe = et131x_pci_setup,
4593 .remove = et131x_pci_remove,
4594 .driver.pm = ET131X_PM_OPS,
4595 };
4596
4597 module_pci_driver(et131x_driver);
Linux kernel - Deliverables
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