2 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 * Copyright © 2005 Agere Systems Inc.
8 * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
10 *------------------------------------------------------------------------------
14 * This software is provided subject to the following terms and conditions,
15 * which you should read carefully before using the software. Using this
16 * software indicates your acceptance of these terms and conditions. If you do
17 * not agree with these terms and conditions, do not use the software.
19 * Copyright © 2005 Agere Systems Inc.
20 * All rights reserved.
22 * Redistribution and use in source or binary forms, with or without
23 * modifications, are permitted provided that the following conditions are met:
25 * . Redistributions of source code must retain the above copyright notice, this
26 * list of conditions and the following Disclaimer as comments in the code as
27 * well as in the documentation and/or other materials provided with the
30 * . Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following Disclaimer in the documentation
32 * and/or other materials provided with the distribution.
34 * . Neither the name of Agere Systems Inc. nor the names of the contributors
35 * may be used to endorse or promote products derived from this software
36 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
41 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
42 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
43 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
44 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
47 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
48 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
50 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56 #include <linux/pci.h>
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/kernel.h>
61 #include <linux/sched.h>
62 #include <linux/ptrace.h>
63 #include <linux/slab.h>
64 #include <linux/ctype.h>
65 #include <linux/string.h>
66 #include <linux/timer.h>
67 #include <linux/interrupt.h>
69 #include <linux/delay.h>
70 #include <linux/bitops.h>
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/if_arp.h>
77 #include <linux/ioport.h>
78 #include <linux/crc32.h>
79 #include <linux/random.h>
80 #include <linux/phy.h>
84 MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
85 MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
86 MODULE_LICENSE("Dual BSD/GPL");
87 MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems");
90 #define MAX_NUM_REGISTER_POLLS 1000
91 #define MAX_NUM_WRITE_RETRIES 2
94 #define COUNTER_WRAP_16_BIT 0x10000
95 #define COUNTER_WRAP_12_BIT 0x1000
98 #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
99 #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
102 /* For interrupts, normal running is:
103 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
104 * watchdog_interrupt & txdma_xfer_done
106 * In both cases, when flow control is enabled for either Tx or bi-direction,
107 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
108 * buffer rings are running low.
110 #define INT_MASK_DISABLE 0xffffffff
112 /* NOTE: Masking out MAC_STAT Interrupt for now...
113 * #define INT_MASK_ENABLE 0xfff6bf17
114 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
116 #define INT_MASK_ENABLE 0xfffebf17
117 #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
119 /* General defines */
120 /* Packet and header sizes */
121 #define NIC_MIN_PACKET_SIZE 60
123 /* Multicast list size */
124 #define NIC_MAX_MCAST_LIST 128
126 /* Supported Filters */
127 #define ET131X_PACKET_TYPE_DIRECTED 0x0001
128 #define ET131X_PACKET_TYPE_MULTICAST 0x0002
129 #define ET131X_PACKET_TYPE_BROADCAST 0x0004
130 #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
131 #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
134 #define ET131X_TX_TIMEOUT (1 * HZ)
135 #define NIC_SEND_HANG_THRESHOLD 0
137 /* MP_ADAPTER flags */
138 #define FMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
140 /* MP_SHARED flags */
141 #define FMP_ADAPTER_LOWER_POWER 0x00200000
143 #define FMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
144 #define FMP_ADAPTER_HARDWARE_ERROR 0x04000000
146 #define FMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
148 /* Some offsets in PCI config space that are actually used. */
149 #define ET1310_PCI_MAC_ADDRESS 0xA4
150 #define ET1310_PCI_EEPROM_STATUS 0xB2
151 #define ET1310_PCI_ACK_NACK 0xC0
152 #define ET1310_PCI_REPLAY 0xC2
153 #define ET1310_PCI_L0L1LATENCY 0xCF
155 /* PCI Product IDs */
156 #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
157 #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
159 /* Define order of magnitude converter */
160 #define NANO_IN_A_MICRO 1000
162 #define PARM_RX_NUM_BUFS_DEF 4
163 #define PARM_RX_TIME_INT_DEF 10
164 #define PARM_RX_MEM_END_DEF 0x2bc
165 #define PARM_TX_TIME_INT_DEF 40
166 #define PARM_TX_NUM_BUFS_DEF 4
167 #define PARM_DMA_CACHE_DEF 0
170 #define FBR_CHUNKS 32
171 #define MAX_DESC_PER_RING_RX 1024
173 /* number of RFDs - default and min */
174 #define RFD_LOW_WATER_MARK 40
175 #define NIC_DEFAULT_NUM_RFD 1024
178 #define MAX_PACKETS_HANDLED 256
180 #define ALCATEL_MULTICAST_PKT 0x01000000
181 #define ALCATEL_BROADCAST_PKT 0x02000000
183 /* typedefs for Free Buffer Descriptors */
187 u32 word2
; /* Bits 10-31 reserved, 0-9 descriptor */
190 /* Packet Status Ring Descriptors
194 * top 16 bits are from the Alcatel Status Word as enumerated in
195 * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
198 * 1: ipa IP checksum assist
199 * 2: ipp IP checksum pass
200 * 3: tcpa TCP checksum assist
201 * 4: tcpp TCP checksum pass
203 * 6: rxmac_error RXMAC Error Indicator
204 * 7: drop Drop packet
205 * 8: ft Frame Truncated
209 * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
210 * 17: asw_RX_DV_event short receive event detected
211 * 18: asw_false_carrier_event bad carrier since last good packet
212 * 19: asw_code_err one or more nibbles signalled as errors
213 * 20: asw_CRC_err CRC error
214 * 21: asw_len_chk_err frame length field incorrect
215 * 22: asw_too_long frame length > 1518 bytes
216 * 23: asw_OK valid CRC + no code error
217 * 24: asw_multicast has a multicast address
218 * 25: asw_broadcast has a broadcast address
219 * 26: asw_dribble_nibble spurious bits after EOP
220 * 27: asw_control_frame is a control frame
221 * 28: asw_pause_frame is a pause frame
222 * 29: asw_unsupported_op unsupported OP code
223 * 30: asw_VLAN_tag VLAN tag detected
224 * 31: asw_long_evt Rx long event
227 * 0-15: length length in bytes
228 * 16-25: bi Buffer Index
229 * 26-27: ri Ring Index
232 struct pkt_stat_desc
{
237 /* Typedefs for the RX DMA status word */
239 /* rx status word 0 holds part of the status bits of the Rx DMA engine
240 * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
241 * which contains the Free Buffer ring 0 and 1 available offset.
243 * bit 0-9 FBR1 offset
244 * bit 10 Wrap flag for FBR1
245 * bit 16-25 FBR0 offset
246 * bit 26 Wrap flag for FBR0
249 /* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
250 * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
251 * which contains the Packet Status Ring available offset.
254 * bit 16-27 PSRoffset
259 /* struct rx_status_block is a structure representing the status of the Rx
260 * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
262 struct rx_status_block
{
267 /* Structure for look-up table holding free buffer ring pointers, addresses
271 void *virt
[MAX_DESC_PER_RING_RX
];
272 u32 bus_high
[MAX_DESC_PER_RING_RX
];
273 u32 bus_low
[MAX_DESC_PER_RING_RX
];
275 dma_addr_t ring_physaddr
;
276 void *mem_virtaddrs
[MAX_DESC_PER_RING_RX
/ FBR_CHUNKS
];
277 dma_addr_t mem_physaddrs
[MAX_DESC_PER_RING_RX
/ FBR_CHUNKS
];
283 /* struct rx_ring is the structure representing the adaptor's local
284 * reference(s) to the rings
287 struct fbr_lookup
*fbr
[NUM_FBRS
];
288 void *ps_ring_virtaddr
;
289 dma_addr_t ps_ring_physaddr
;
293 struct rx_status_block
*rx_status_block
;
294 dma_addr_t rx_status_bus
;
297 struct list_head recv_list
;
302 bool unfinished_receives
;
306 /* word 2 of the control bits in the Tx Descriptor ring for the ET-1310
308 * 0-15: length of packet
311 * 29-31: VLAN priority
313 * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
315 * 0: last packet in the sequence
316 * 1: first packet in the sequence
317 * 2: interrupt the processor when this pkt sent
318 * 3: Control word - no packet data
319 * 4: Issue half-duplex backpressure : XON/XOFF
320 * 5: send pause frame
321 * 6: Tx frame has error
325 * 10: Packet is a Huge packet
326 * 11: append VLAN tag
327 * 12: IP checksum assist
328 * 13: TCP checksum assist
329 * 14: UDP checksum assist
331 #define TXDESC_FLAG_LASTPKT 0x0001
332 #define TXDESC_FLAG_FIRSTPKT 0x0002
333 #define TXDESC_FLAG_INTPROC 0x0004
335 /* struct tx_desc represents each descriptor on the ring */
339 u32 len_vlan
; /* control words how to xmit the */
340 u32 flags
; /* data (detailed above) */
343 /* The status of the Tx DMA engine it sits in free memory, and is pointed to
344 * by 0x101c / 0x1020. This is a DMA10 type
347 /* TCB (Transmit Control Block: Host Side) */
349 struct tcb
*next
; /* Next entry in ring */
350 u32 count
; /* Used to spot stuck/lost packets */
351 u32 stale
; /* Used to spot stuck/lost packets */
352 struct sk_buff
*skb
; /* Network skb we are tied to */
353 u32 index
; /* Ring indexes */
357 /* Structure representing our local reference(s) to the ring */
359 /* TCB (Transmit Control Block) memory and lists */
360 struct tcb
*tcb_ring
;
362 /* List of TCBs that are ready to be used */
363 struct tcb
*tcb_qhead
;
364 struct tcb
*tcb_qtail
;
366 /* list of TCBs that are currently being sent. NOTE that access to all
367 * three of these (including used) are controlled via the
368 * TCBSendQLock. This lock should be secured prior to incementing /
369 * decrementing used, or any queue manipulation on send_head /
372 struct tcb
*send_head
;
373 struct tcb
*send_tail
;
376 /* The actual descriptor ring */
377 struct tx_desc
*tx_desc_ring
;
378 dma_addr_t tx_desc_ring_pa
;
380 /* send_idx indicates where we last wrote to in the descriptor ring. */
383 /* The location of the write-back status block */
385 dma_addr_t tx_status_pa
;
387 /* Packets since the last IRQ: used for interrupt coalescing */
391 /* Do not change these values: if changed, then change also in respective
392 * TXdma and Rxdma engines
394 #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
397 /* These values are all superseded by registry entries to facilitate tuning.
398 * Once the desired performance has been achieved, the optimal registry values
399 * should be re-populated to these #defines:
401 #define TX_ERROR_PERIOD 1000
403 #define LO_MARK_PERCENT_FOR_PSR 15
404 #define LO_MARK_PERCENT_FOR_RX 15
406 /* RFD (Receive Frame Descriptor) */
408 struct list_head list_node
;
410 u32 len
; /* total size of receive frame */
417 #define FLOW_TXONLY 1
418 #define FLOW_RXONLY 2
421 /* Struct to define some device statistics */
425 * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
426 * MUST have 32, then we'll need another way to perform atomic
429 u32 multicast_pkts_rcvd
;
430 u32 rcvd_pkts_dropped
;
435 u32 tx_excessive_collisions
;
436 u32 tx_first_collisions
;
437 u32 tx_late_collisions
;
446 u32 rx_code_violations
;
449 u32 interrupt_status
;
452 /* The private adapter structure */
453 struct et131x_adapter
{
454 struct net_device
*netdev
;
455 struct pci_dev
*pdev
;
456 struct mii_bus
*mii_bus
;
457 struct phy_device
*phydev
;
458 struct napi_struct napi
;
460 /* Flags that indicate current state of the adapter */
463 /* local link state, to determine if a state change has occurred */
467 u8 rom_addr
[ETH_ALEN
];
472 spinlock_t tcb_send_qlock
; /* protects the tx_ring send tcb list */
473 spinlock_t tcb_ready_qlock
; /* protects the tx_ring ready tcb list */
474 spinlock_t rcv_lock
; /* protects the rx_ring receive list */
476 /* Packet Filter and look ahead size */
480 u32 multicast_addr_count
;
481 u8 multicast_list
[NIC_MAX_MCAST_LIST
][ETH_ALEN
];
483 /* Pointer to the device's PCI register space */
484 struct address_map __iomem
*regs
;
486 /* Registry parameters */
487 u8 wanted_flow
; /* Flow we want for 802.3x flow control */
488 u32 registry_jumbo_packet
; /* Max supported ethernet packet size */
490 /* Derived from the registry: */
491 u8 flowcontrol
; /* flow control validated by the far-end */
493 /* Minimize init-time */
494 struct timer_list error_timer
;
496 /* variable putting the phy into coma mode when boot up with no cable
497 * plugged in after 5 seconds
501 /* Tx Memory Variables */
502 struct tx_ring tx_ring
;
504 /* Rx Memory Variables */
505 struct rx_ring rx_ring
;
508 struct ce_stats stats
;
511 static int eeprom_wait_ready(struct pci_dev
*pdev
, u32
*status
)
516 /* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
517 * bits 7,1:0 both equal to 1, at least once after reset.
518 * Subsequent operations need only to check that bits 1:0 are equal
519 * to 1 prior to starting a single byte read/write
521 for (i
= 0; i
< MAX_NUM_REGISTER_POLLS
; i
++) {
522 /* Read registers grouped in DWORD1 */
523 if (pci_read_config_dword(pdev
, LBCIF_DWORD1_GROUP
, ®
))
526 /* I2C idle and Phy Queue Avail both true */
527 if ((reg
& 0x3000) == 0x3000) {
536 /* eeprom_write - Write a byte to the ET1310's EEPROM
537 * @adapter: pointer to our private adapter structure
538 * @addr: the address to write
539 * @data: the value to write
541 * Returns 1 for a successful write.
543 static int eeprom_write(struct et131x_adapter
*adapter
, u32 addr
, u8 data
)
545 struct pci_dev
*pdev
= adapter
->pdev
;
553 /* For an EEPROM, an I2C single byte write is defined as a START
554 * condition followed by the device address, EEPROM address, one byte
555 * of data and a STOP condition. The STOP condition will trigger the
556 * EEPROM's internally timed write cycle to the nonvolatile memory.
557 * All inputs are disabled during this write cycle and the EEPROM will
558 * not respond to any access until the internal write is complete.
560 err
= eeprom_wait_ready(pdev
, NULL
);
564 /* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
565 * and bits 1:0 both =0. Bit 5 should be set according to the
566 * type of EEPROM being accessed (1=two byte addressing, 0=one
569 if (pci_write_config_byte(pdev
, LBCIF_CONTROL_REGISTER
,
570 LBCIF_CONTROL_LBCIF_ENABLE
|
571 LBCIF_CONTROL_I2C_WRITE
))
574 /* Prepare EEPROM address for Step 3 */
575 for (retries
= 0; retries
< MAX_NUM_WRITE_RETRIES
; retries
++) {
576 /* Write the address to the LBCIF Address Register */
577 if (pci_write_config_dword(pdev
, LBCIF_ADDRESS_REGISTER
, addr
))
579 /* Write the data to the LBCIF Data Register (the I2C write
582 if (pci_write_config_byte(pdev
, LBCIF_DATA_REGISTER
, data
))
584 /* Monitor bit 1:0 of the LBCIF Status Register. When bits
585 * 1:0 are both equal to 1, the I2C write has completed and the
586 * internal write cycle of the EEPROM is about to start.
587 * (bits 1:0 = 01 is a legal state while waiting from both
588 * equal to 1, but bits 1:0 = 10 is invalid and implies that
589 * something is broken).
591 err
= eeprom_wait_ready(pdev
, &status
);
595 /* Check bit 3 of the LBCIF Status Register. If equal to 1,
596 * an error has occurred.Don't break here if we are revision
597 * 1, this is so we do a blind write for load bug.
599 if ((status
& LBCIF_STATUS_GENERAL_ERROR
) &&
600 adapter
->pdev
->revision
== 0)
603 /* Check bit 2 of the LBCIF Status Register. If equal to 1 an
604 * ACK error has occurred on the address phase of the write.
605 * This could be due to an actual hardware failure or the
606 * EEPROM may still be in its internal write cycle from a
607 * previous write. This write operation was ignored and must be
610 if (status
& LBCIF_STATUS_ACK_ERROR
) {
611 /* This could be due to an actual hardware failure
612 * or the EEPROM may still be in its internal write
613 * cycle from a previous write. This write operation
614 * was ignored and must be repeated later.
624 /* Set bit 6 of the LBCIF Control Register = 0.
629 if (pci_write_config_byte(pdev
, LBCIF_CONTROL_REGISTER
,
630 LBCIF_CONTROL_LBCIF_ENABLE
))
633 /* Do read until internal ACK_ERROR goes away meaning write
637 pci_write_config_dword(pdev
,
638 LBCIF_ADDRESS_REGISTER
,
641 pci_read_config_dword(pdev
,
644 } while ((val
& 0x00010000) == 0);
645 } while (val
& 0x00040000);
647 if ((val
& 0xFF00) != 0xC000 || index
== 10000)
651 return writeok
? 0 : -EIO
;
654 /* eeprom_read - Read a byte from the ET1310's EEPROM
655 * @adapter: pointer to our private adapter structure
656 * @addr: the address from which to read
657 * @pdata: a pointer to a byte in which to store the value of the read
658 * @eeprom_id: the ID of the EEPROM
659 * @addrmode: how the EEPROM is to be accessed
661 * Returns 1 for a successful read
663 static int eeprom_read(struct et131x_adapter
*adapter
, u32 addr
, u8
*pdata
)
665 struct pci_dev
*pdev
= adapter
->pdev
;
669 /* A single byte read is similar to the single byte write, with the
670 * exception of the data flow:
672 err
= eeprom_wait_ready(pdev
, NULL
);
675 /* Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
676 * and bits 1:0 both =0. Bit 5 should be set according to the type
677 * of EEPROM being accessed (1=two byte addressing, 0=one byte
680 if (pci_write_config_byte(pdev
, LBCIF_CONTROL_REGISTER
,
681 LBCIF_CONTROL_LBCIF_ENABLE
))
683 /* Write the address to the LBCIF Address Register (I2C read will
686 if (pci_write_config_dword(pdev
, LBCIF_ADDRESS_REGISTER
, addr
))
688 /* Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
689 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
692 err
= eeprom_wait_ready(pdev
, &status
);
695 /* Regardless of error status, read data byte from LBCIF Data
699 /* Check bit 2 of the LBCIF Status Register. If = 1,
700 * then an error has occurred.
702 return (status
& LBCIF_STATUS_ACK_ERROR
) ? -EIO
: 0;
705 static int et131x_init_eeprom(struct et131x_adapter
*adapter
)
707 struct pci_dev
*pdev
= adapter
->pdev
;
710 /* We first need to check the EEPROM Status code located at offset
711 * 0xB2 of config space
713 pci_read_config_byte(pdev
, ET1310_PCI_EEPROM_STATUS
, &eestatus
);
715 /* THIS IS A WORKAROUND:
716 * I need to call this function twice to get my card in a
717 * LG M1 Express Dual running. I tried also a msleep before this
718 * function, because I thought there could be some time conditions
719 * but it didn't work. Call the whole function twice also work.
721 if (pci_read_config_byte(pdev
, ET1310_PCI_EEPROM_STATUS
, &eestatus
)) {
723 "Could not read PCI config space for EEPROM Status\n");
727 /* Determine if the error(s) we care about are present. If they are
728 * present we need to fail.
730 if (eestatus
& 0x4C) {
731 int write_failed
= 0;
733 if (pdev
->revision
== 0x01) {
735 static const u8 eedata
[4] = { 0xFE, 0x13, 0x10, 0xFF };
737 /* Re-write the first 4 bytes if we have an eeprom
738 * present and the revision id is 1, this fixes the
739 * corruption seen with 1310 B Silicon
741 for (i
= 0; i
< 3; i
++)
742 if (eeprom_write(adapter
, i
, eedata
[i
]) < 0)
745 if (pdev
->revision
!= 0x01 || write_failed
) {
747 "Fatal EEPROM Status Error - 0x%04x\n",
750 /* This error could mean that there was an error
751 * reading the eeprom or that the eeprom doesn't exist.
752 * We will treat each case the same and not try to
753 * gather additional information that normally would
754 * come from the eeprom, like MAC Address
756 adapter
->has_eeprom
= 0;
760 adapter
->has_eeprom
= 1;
762 /* Read the EEPROM for information regarding LED behavior. Refer to
763 * ET1310_phy.c, et131x_xcvr_init(), for its use.
765 eeprom_read(adapter
, 0x70, &adapter
->eeprom_data
[0]);
766 eeprom_read(adapter
, 0x71, &adapter
->eeprom_data
[1]);
768 if (adapter
->eeprom_data
[0] != 0xcd)
769 /* Disable all optional features */
770 adapter
->eeprom_data
[1] = 0x00;
775 /* et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
776 * @adapter: pointer to our adapter structure
778 static void et131x_rx_dma_enable(struct et131x_adapter
*adapter
)
780 /* Setup the receive dma configuration register for normal operation */
781 u32 csr
= ET_RXDMA_CSR_FBR1_ENABLE
;
782 struct rx_ring
*rx_ring
= &adapter
->rx_ring
;
784 if (rx_ring
->fbr
[1]->buffsize
== 4096)
785 csr
|= ET_RXDMA_CSR_FBR1_SIZE_LO
;
786 else if (rx_ring
->fbr
[1]->buffsize
== 8192)
787 csr
|= ET_RXDMA_CSR_FBR1_SIZE_HI
;
788 else if (rx_ring
->fbr
[1]->buffsize
== 16384)
789 csr
|= ET_RXDMA_CSR_FBR1_SIZE_LO
| ET_RXDMA_CSR_FBR1_SIZE_HI
;
791 csr
|= ET_RXDMA_CSR_FBR0_ENABLE
;
792 if (rx_ring
->fbr
[0]->buffsize
== 256)
793 csr
|= ET_RXDMA_CSR_FBR0_SIZE_LO
;
794 else if (rx_ring
->fbr
[0]->buffsize
== 512)
795 csr
|= ET_RXDMA_CSR_FBR0_SIZE_HI
;
796 else if (rx_ring
->fbr
[0]->buffsize
== 1024)
797 csr
|= ET_RXDMA_CSR_FBR0_SIZE_LO
| ET_RXDMA_CSR_FBR0_SIZE_HI
;
798 writel(csr
, &adapter
->regs
->rxdma
.csr
);
800 csr
= readl(&adapter
->regs
->rxdma
.csr
);
801 if (csr
& ET_RXDMA_CSR_HALT_STATUS
) {
803 csr
= readl(&adapter
->regs
->rxdma
.csr
);
804 if (csr
& ET_RXDMA_CSR_HALT_STATUS
) {
805 dev_err(&adapter
->pdev
->dev
,
806 "RX Dma failed to exit halt state. CSR 0x%08x\n",
812 /* et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
813 * @adapter: pointer to our adapter structure
815 static void et131x_rx_dma_disable(struct et131x_adapter
*adapter
)
818 /* Setup the receive dma configuration register */
819 writel(ET_RXDMA_CSR_HALT
| ET_RXDMA_CSR_FBR1_ENABLE
,
820 &adapter
->regs
->rxdma
.csr
);
821 csr
= readl(&adapter
->regs
->rxdma
.csr
);
822 if (!(csr
& ET_RXDMA_CSR_HALT_STATUS
)) {
824 csr
= readl(&adapter
->regs
->rxdma
.csr
);
825 if (!(csr
& ET_RXDMA_CSR_HALT_STATUS
))
826 dev_err(&adapter
->pdev
->dev
,
827 "RX Dma failed to enter halt state. CSR 0x%08x\n",
832 /* et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
833 * @adapter: pointer to our adapter structure
835 * Mainly used after a return to the D0 (full-power) state from a lower state.
837 static void et131x_tx_dma_enable(struct et131x_adapter
*adapter
)
839 /* Setup the transmit dma configuration register for normal
842 writel(ET_TXDMA_SNGL_EPKT
| (PARM_DMA_CACHE_DEF
<< ET_TXDMA_CACHE_SHIFT
),
843 &adapter
->regs
->txdma
.csr
);
846 static inline void add_10bit(u32
*v
, int n
)
848 *v
= INDEX10(*v
+ n
) | (*v
& ET_DMA10_WRAP
);
851 static inline void add_12bit(u32
*v
, int n
)
853 *v
= INDEX12(*v
+ n
) | (*v
& ET_DMA12_WRAP
);
856 /* et1310_config_mac_regs1 - Initialize the first part of MAC regs
857 * @adapter: pointer to our adapter structure
859 static void et1310_config_mac_regs1(struct et131x_adapter
*adapter
)
861 struct mac_regs __iomem
*macregs
= &adapter
->regs
->mac
;
866 /* First we need to reset everything. Write to MAC configuration
867 * register 1 to perform reset.
869 writel(ET_MAC_CFG1_SOFT_RESET
| ET_MAC_CFG1_SIM_RESET
|
870 ET_MAC_CFG1_RESET_RXMC
| ET_MAC_CFG1_RESET_TXMC
|
871 ET_MAC_CFG1_RESET_RXFUNC
| ET_MAC_CFG1_RESET_TXFUNC
,
874 /* Next lets configure the MAC Inter-packet gap register */
875 ipg
= 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
876 ipg
|= 0x50 << 8; /* ifg enforce 0x50 */
877 writel(ipg
, ¯egs
->ipg
);
879 /* Next lets configure the MAC Half Duplex register */
880 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
881 writel(0x00A1F037, ¯egs
->hfdp
);
883 /* Next lets configure the MAC Interface Control register */
884 writel(0, ¯egs
->if_ctrl
);
886 /* Let's move on to setting up the mii management configuration */
887 writel(ET_MAC_MIIMGMT_CLK_RST
, ¯egs
->mii_mgmt_cfg
);
889 /* Next lets configure the MAC Station Address register. These
890 * values are read from the EEPROM during initialization and stored
891 * in the adapter structure. We write what is stored in the adapter
892 * structure to the MAC Station Address registers high and low. This
893 * station address is used for generating and checking pause control
896 station2
= (adapter
->addr
[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT
) |
897 (adapter
->addr
[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT
);
898 station1
= (adapter
->addr
[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT
) |
899 (adapter
->addr
[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT
) |
900 (adapter
->addr
[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT
) |
902 writel(station1
, ¯egs
->station_addr_1
);
903 writel(station2
, ¯egs
->station_addr_2
);
905 /* Max ethernet packet in bytes that will be passed by the mac without
906 * being truncated. Allow the MAC to pass 4 more than our max packet
907 * size. This is 4 for the Ethernet CRC.
909 * Packets larger than (registry_jumbo_packet) that do not contain a
910 * VLAN ID will be dropped by the Rx function.
912 writel(adapter
->registry_jumbo_packet
+ 4, ¯egs
->max_fm_len
);
914 /* clear out MAC config reset */
915 writel(0, ¯egs
->cfg1
);
918 /* et1310_config_mac_regs2 - Initialize the second part of MAC regs
919 * @adapter: pointer to our adapter structure
921 static void et1310_config_mac_regs2(struct et131x_adapter
*adapter
)
924 struct mac_regs __iomem
*mac
= &adapter
->regs
->mac
;
925 struct phy_device
*phydev
= adapter
->phydev
;
931 ctl
= readl(&adapter
->regs
->txmac
.ctl
);
932 cfg1
= readl(&mac
->cfg1
);
933 cfg2
= readl(&mac
->cfg2
);
934 ifctrl
= readl(&mac
->if_ctrl
);
936 /* Set up the if mode bits */
937 cfg2
&= ~ET_MAC_CFG2_IFMODE_MASK
;
938 if (phydev
->speed
== SPEED_1000
) {
939 cfg2
|= ET_MAC_CFG2_IFMODE_1000
;
941 ifctrl
&= ~ET_MAC_IFCTRL_PHYMODE
;
943 cfg2
|= ET_MAC_CFG2_IFMODE_100
;
944 ifctrl
|= ET_MAC_IFCTRL_PHYMODE
;
947 /* We need to enable Rx/Tx */
948 cfg1
|= ET_MAC_CFG1_RX_ENABLE
| ET_MAC_CFG1_TX_ENABLE
|
950 /* Initialize loop back to off */
951 cfg1
&= ~(ET_MAC_CFG1_LOOPBACK
| ET_MAC_CFG1_RX_FLOW
);
952 if (adapter
->flowcontrol
== FLOW_RXONLY
||
953 adapter
->flowcontrol
== FLOW_BOTH
)
954 cfg1
|= ET_MAC_CFG1_RX_FLOW
;
955 writel(cfg1
, &mac
->cfg1
);
957 /* Now we need to initialize the MAC Configuration 2 register */
958 /* preamble 7, check length, huge frame off, pad crc, crc enable
961 cfg2
|= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT
;
962 cfg2
|= ET_MAC_CFG2_IFMODE_LEN_CHECK
;
963 cfg2
|= ET_MAC_CFG2_IFMODE_PAD_CRC
;
964 cfg2
|= ET_MAC_CFG2_IFMODE_CRC_ENABLE
;
965 cfg2
&= ~ET_MAC_CFG2_IFMODE_HUGE_FRAME
;
966 cfg2
&= ~ET_MAC_CFG2_IFMODE_FULL_DPLX
;
968 /* Turn on duplex if needed */
969 if (phydev
->duplex
== DUPLEX_FULL
)
970 cfg2
|= ET_MAC_CFG2_IFMODE_FULL_DPLX
;
972 ifctrl
&= ~ET_MAC_IFCTRL_GHDMODE
;
973 if (phydev
->duplex
== DUPLEX_HALF
)
974 ifctrl
|= ET_MAC_IFCTRL_GHDMODE
;
976 writel(ifctrl
, &mac
->if_ctrl
);
977 writel(cfg2
, &mac
->cfg2
);
982 cfg1
= readl(&mac
->cfg1
);
983 } while ((cfg1
& ET_MAC_CFG1_WAIT
) != ET_MAC_CFG1_WAIT
&& delay
< 100);
986 dev_warn(&adapter
->pdev
->dev
,
987 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
992 ctl
|= ET_TX_CTRL_TXMAC_ENABLE
| ET_TX_CTRL_FC_DISABLE
;
993 writel(ctl
, &adapter
->regs
->txmac
.ctl
);
995 /* Ready to start the RXDMA/TXDMA engine */
996 if (adapter
->flags
& FMP_ADAPTER_LOWER_POWER
) {
997 et131x_rx_dma_enable(adapter
);
998 et131x_tx_dma_enable(adapter
);
1002 /* et1310_in_phy_coma - check if the device is in phy coma
1003 * @adapter: pointer to our adapter structure
1005 * Returns 0 if the device is not in phy coma, 1 if it is in phy coma
1007 static int et1310_in_phy_coma(struct et131x_adapter
*adapter
)
1009 u32 pmcsr
= readl(&adapter
->regs
->global
.pm_csr
);
1011 return ET_PM_PHY_SW_COMA
& pmcsr
? 1 : 0;
1014 static void et1310_setup_device_for_multicast(struct et131x_adapter
*adapter
)
1016 struct rxmac_regs __iomem
*rxmac
= &adapter
->regs
->rxmac
;
1023 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
1024 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
1025 * specified) then we should pass NO multi-cast addresses to the
1028 if (adapter
->packet_filter
& ET131X_PACKET_TYPE_MULTICAST
) {
1031 /* Loop through our multicast array and set up the device */
1032 for (i
= 0; i
< adapter
->multicast_addr_count
; i
++) {
1035 result
= ether_crc(6, adapter
->multicast_list
[i
]);
1037 result
= (result
& 0x3F800000) >> 23;
1040 hash1
|= (1 << result
);
1041 } else if ((31 < result
) && (result
< 64)) {
1043 hash2
|= (1 << result
);
1044 } else if ((63 < result
) && (result
< 96)) {
1046 hash3
|= (1 << result
);
1049 hash4
|= (1 << result
);
1054 /* Write out the new hash to the device */
1055 pm_csr
= readl(&adapter
->regs
->global
.pm_csr
);
1056 if (!et1310_in_phy_coma(adapter
)) {
1057 writel(hash1
, &rxmac
->multi_hash1
);
1058 writel(hash2
, &rxmac
->multi_hash2
);
1059 writel(hash3
, &rxmac
->multi_hash3
);
1060 writel(hash4
, &rxmac
->multi_hash4
);
1064 static void et1310_setup_device_for_unicast(struct et131x_adapter
*adapter
)
1066 struct rxmac_regs __iomem
*rxmac
= &adapter
->regs
->rxmac
;
1072 /* Set up unicast packet filter reg 3 to be the first two octets of
1073 * the MAC address for both address
1075 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
1076 * MAC address for second address
1078 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
1079 * MAC address for first address
1081 uni_pf3
= (adapter
->addr
[0] << ET_RX_UNI_PF_ADDR2_1_SHIFT
) |
1082 (adapter
->addr
[1] << ET_RX_UNI_PF_ADDR2_2_SHIFT
) |
1083 (adapter
->addr
[0] << ET_RX_UNI_PF_ADDR1_1_SHIFT
) |
1086 uni_pf2
= (adapter
->addr
[2] << ET_RX_UNI_PF_ADDR2_3_SHIFT
) |
1087 (adapter
->addr
[3] << ET_RX_UNI_PF_ADDR2_4_SHIFT
) |
1088 (adapter
->addr
[4] << ET_RX_UNI_PF_ADDR2_5_SHIFT
) |
1091 uni_pf1
= (adapter
->addr
[2] << ET_RX_UNI_PF_ADDR1_3_SHIFT
) |
1092 (adapter
->addr
[3] << ET_RX_UNI_PF_ADDR1_4_SHIFT
) |
1093 (adapter
->addr
[4] << ET_RX_UNI_PF_ADDR1_5_SHIFT
) |
1096 pm_csr
= readl(&adapter
->regs
->global
.pm_csr
);
1097 if (!et1310_in_phy_coma(adapter
)) {
1098 writel(uni_pf1
, &rxmac
->uni_pf_addr1
);
1099 writel(uni_pf2
, &rxmac
->uni_pf_addr2
);
1100 writel(uni_pf3
, &rxmac
->uni_pf_addr3
);
1104 static void et1310_config_rxmac_regs(struct et131x_adapter
*adapter
)
1106 struct rxmac_regs __iomem
*rxmac
= &adapter
->regs
->rxmac
;
1107 struct phy_device
*phydev
= adapter
->phydev
;
1113 /* Disable the MAC while it is being configured (also disable WOL) */
1114 writel(0x8, &rxmac
->ctrl
);
1116 /* Initialize WOL to disabled. */
1117 writel(0, &rxmac
->crc0
);
1118 writel(0, &rxmac
->crc12
);
1119 writel(0, &rxmac
->crc34
);
1121 /* We need to set the WOL mask0 - mask4 next. We initialize it to
1122 * its default Values of 0x00000000 because there are not WOL masks
1125 for (wolw
= &rxmac
->mask0_word0
; wolw
<= &rxmac
->mask4_word3
; wolw
++)
1128 /* Lets setup the WOL Source Address */
1129 sa_lo
= (adapter
->addr
[2] << ET_RX_WOL_LO_SA3_SHIFT
) |
1130 (adapter
->addr
[3] << ET_RX_WOL_LO_SA4_SHIFT
) |
1131 (adapter
->addr
[4] << ET_RX_WOL_LO_SA5_SHIFT
) |
1133 writel(sa_lo
, &rxmac
->sa_lo
);
1135 sa_hi
= (u32
)(adapter
->addr
[0] << ET_RX_WOL_HI_SA1_SHIFT
) |
1137 writel(sa_hi
, &rxmac
->sa_hi
);
1139 /* Disable all Packet Filtering */
1140 writel(0, &rxmac
->pf_ctrl
);
1142 /* Let's initialize the Unicast Packet filtering address */
1143 if (adapter
->packet_filter
& ET131X_PACKET_TYPE_DIRECTED
) {
1144 et1310_setup_device_for_unicast(adapter
);
1145 pf_ctrl
|= ET_RX_PFCTRL_UNICST_FILTER_ENABLE
;
1147 writel(0, &rxmac
->uni_pf_addr1
);
1148 writel(0, &rxmac
->uni_pf_addr2
);
1149 writel(0, &rxmac
->uni_pf_addr3
);
1152 /* Let's initialize the Multicast hash */
1153 if (!(adapter
->packet_filter
& ET131X_PACKET_TYPE_ALL_MULTICAST
)) {
1154 pf_ctrl
|= ET_RX_PFCTRL_MLTCST_FILTER_ENABLE
;
1155 et1310_setup_device_for_multicast(adapter
);
1158 /* Runt packet filtering. Didn't work in version A silicon. */
1159 pf_ctrl
|= (NIC_MIN_PACKET_SIZE
+ 4) << ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT
;
1160 pf_ctrl
|= ET_RX_PFCTRL_FRAG_FILTER_ENABLE
;
1162 if (adapter
->registry_jumbo_packet
> 8192)
1163 /* In order to transmit jumbo packets greater than 8k, the
1164 * FIFO between RxMAC and RxDMA needs to be reduced in size
1165 * to (16k - Jumbo packet size). In order to implement this,
1166 * we must use "cut through" mode in the RxMAC, which chops
1167 * packets down into segments which are (max_size * 16). In
1168 * this case we selected 256 bytes, since this is the size of
1169 * the PCI-Express TLP's that the 1310 uses.
1171 * seg_en on, fc_en off, size 0x10
1173 writel(0x41, &rxmac
->mcif_ctrl_max_seg
);
1175 writel(0, &rxmac
->mcif_ctrl_max_seg
);
1177 /* Initialize the MCIF water marks */
1178 writel(0, &rxmac
->mcif_water_mark
);
1180 /* Initialize the MIF control */
1181 writel(0, &rxmac
->mif_ctrl
);
1183 /* Initialize the Space Available Register */
1184 writel(0, &rxmac
->space_avail
);
1186 /* Initialize the the mif_ctrl register
1187 * bit 3: Receive code error. One or more nibbles were signaled as
1188 * errors during the reception of the packet. Clear this
1189 * bit in Gigabit, set it in 100Mbit. This was derived
1190 * experimentally at UNH.
1191 * bit 4: Receive CRC error. The packet's CRC did not match the
1192 * internally generated CRC.
1193 * bit 5: Receive length check error. Indicates that frame length
1194 * field value in the packet does not match the actual data
1195 * byte length and is not a type field.
1196 * bit 16: Receive frame truncated.
1197 * bit 17: Drop packet enable
1199 if (phydev
&& phydev
->speed
== SPEED_100
)
1200 writel(0x30038, &rxmac
->mif_ctrl
);
1202 writel(0x30030, &rxmac
->mif_ctrl
);
1204 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
1205 * filter is always enabled since it is where the runt packets are
1206 * supposed to be dropped. For version A silicon, runt packet
1207 * dropping doesn't work, so it is disabled in the pf_ctrl register,
1208 * but we still leave the packet filter on.
1210 writel(pf_ctrl
, &rxmac
->pf_ctrl
);
1211 writel(ET_RX_CTRL_RXMAC_ENABLE
| ET_RX_CTRL_WOL_DISABLE
, &rxmac
->ctrl
);
1214 static void et1310_config_txmac_regs(struct et131x_adapter
*adapter
)
1216 struct txmac_regs __iomem
*txmac
= &adapter
->regs
->txmac
;
1218 /* We need to update the Control Frame Parameters
1219 * cfpt - control frame pause timer set to 64 (0x40)
1220 * cfep - control frame extended pause timer set to 0x0
1222 if (adapter
->flowcontrol
== FLOW_NONE
)
1223 writel(0, &txmac
->cf_param
);
1225 writel(0x40, &txmac
->cf_param
);
1228 static void et1310_config_macstat_regs(struct et131x_adapter
*adapter
)
1230 struct macstat_regs __iomem
*macstat
= &adapter
->regs
->macstat
;
1233 /* initialize all the macstat registers to zero on the device */
1234 for (reg
= &macstat
->txrx_0_64_byte_frames
;
1235 reg
<= &macstat
->carry_reg2
; reg
++)
1238 /* Unmask any counters that we want to track the overflow of.
1239 * Initially this will be all counters. It may become clear later
1240 * that we do not need to track all counters.
1242 writel(0xFFFFBE32, &macstat
->carry_reg1_mask
);
1243 writel(0xFFFE7E8B, &macstat
->carry_reg2_mask
);
1246 /* et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
1247 * @adapter: pointer to our private adapter structure
1248 * @addr: the address of the transceiver
1249 * @reg: the register to read
1250 * @value: pointer to a 16-bit value in which the value will be stored
1252 static int et131x_phy_mii_read(struct et131x_adapter
*adapter
, u8 addr
,
1255 struct mac_regs __iomem
*mac
= &adapter
->regs
->mac
;
1262 /* Save a local copy of the registers we are dealing with so we can
1265 mii_addr
= readl(&mac
->mii_mgmt_addr
);
1266 mii_cmd
= readl(&mac
->mii_mgmt_cmd
);
1268 /* Stop the current operation */
1269 writel(0, &mac
->mii_mgmt_cmd
);
1271 /* Set up the register we need to read from on the correct PHY */
1272 writel(ET_MAC_MII_ADDR(addr
, reg
), &mac
->mii_mgmt_addr
);
1274 writel(0x1, &mac
->mii_mgmt_cmd
);
1279 mii_indicator
= readl(&mac
->mii_mgmt_indicator
);
1280 } while ((mii_indicator
& ET_MAC_MGMT_WAIT
) && delay
< 50);
1282 /* If we hit the max delay, we could not read the register */
1284 dev_warn(&adapter
->pdev
->dev
,
1285 "reg 0x%08x could not be read\n", reg
);
1286 dev_warn(&adapter
->pdev
->dev
, "status is 0x%08x\n",
1293 /* If we hit here we were able to read the register and we need to
1294 * return the value to the caller
1296 *value
= readl(&mac
->mii_mgmt_stat
) & ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK
;
1299 /* Stop the read operation */
1300 writel(0, &mac
->mii_mgmt_cmd
);
1302 /* set the registers we touched back to the state at which we entered
1305 writel(mii_addr
, &mac
->mii_mgmt_addr
);
1306 writel(mii_cmd
, &mac
->mii_mgmt_cmd
);
1311 static int et131x_mii_read(struct et131x_adapter
*adapter
, u8 reg
, u16
*value
)
1313 struct phy_device
*phydev
= adapter
->phydev
;
1318 return et131x_phy_mii_read(adapter
, phydev
->addr
, reg
, value
);
1321 /* et131x_mii_write - Write to a PHY reg through the MII interface of the MAC
1322 * @adapter: pointer to our private adapter structure
1323 * @reg: the register to read
1324 * @value: 16-bit value to write
1326 static int et131x_mii_write(struct et131x_adapter
*adapter
, u8 addr
, u8 reg
,
1329 struct mac_regs __iomem
*mac
= &adapter
->regs
->mac
;
1336 /* Save a local copy of the registers we are dealing with so we can
1339 mii_addr
= readl(&mac
->mii_mgmt_addr
);
1340 mii_cmd
= readl(&mac
->mii_mgmt_cmd
);
1342 /* Stop the current operation */
1343 writel(0, &mac
->mii_mgmt_cmd
);
1345 /* Set up the register we need to write to on the correct PHY */
1346 writel(ET_MAC_MII_ADDR(addr
, reg
), &mac
->mii_mgmt_addr
);
1348 /* Add the value to write to the registers to the mac */
1349 writel(value
, &mac
->mii_mgmt_ctrl
);
1354 mii_indicator
= readl(&mac
->mii_mgmt_indicator
);
1355 } while ((mii_indicator
& ET_MAC_MGMT_BUSY
) && delay
< 100);
1357 /* If we hit the max delay, we could not write the register */
1361 dev_warn(&adapter
->pdev
->dev
,
1362 "reg 0x%08x could not be written", reg
);
1363 dev_warn(&adapter
->pdev
->dev
, "status is 0x%08x\n",
1365 dev_warn(&adapter
->pdev
->dev
, "command is 0x%08x\n",
1366 readl(&mac
->mii_mgmt_cmd
));
1368 et131x_mii_read(adapter
, reg
, &tmp
);
1372 /* Stop the write operation */
1373 writel(0, &mac
->mii_mgmt_cmd
);
1375 /* set the registers we touched back to the state at which we entered
1378 writel(mii_addr
, &mac
->mii_mgmt_addr
);
1379 writel(mii_cmd
, &mac
->mii_mgmt_cmd
);
1384 static void et1310_phy_read_mii_bit(struct et131x_adapter
*adapter
,
1390 u16 mask
= 1 << bitnum
;
1392 /* Read the requested register */
1393 et131x_mii_read(adapter
, regnum
, ®
);
1395 *value
= (reg
& mask
) >> bitnum
;
1398 static void et1310_config_flow_control(struct et131x_adapter
*adapter
)
1400 struct phy_device
*phydev
= adapter
->phydev
;
1402 if (phydev
->duplex
== DUPLEX_HALF
) {
1403 adapter
->flowcontrol
= FLOW_NONE
;
1405 char remote_pause
, remote_async_pause
;
1407 et1310_phy_read_mii_bit(adapter
, 5, 10, &remote_pause
);
1408 et1310_phy_read_mii_bit(adapter
, 5, 11, &remote_async_pause
);
1410 if (remote_pause
&& remote_async_pause
) {
1411 adapter
->flowcontrol
= adapter
->wanted_flow
;
1412 } else if (remote_pause
&& !remote_async_pause
) {
1413 if (adapter
->wanted_flow
== FLOW_BOTH
)
1414 adapter
->flowcontrol
= FLOW_BOTH
;
1416 adapter
->flowcontrol
= FLOW_NONE
;
1417 } else if (!remote_pause
&& !remote_async_pause
) {
1418 adapter
->flowcontrol
= FLOW_NONE
;
1420 if (adapter
->wanted_flow
== FLOW_BOTH
)
1421 adapter
->flowcontrol
= FLOW_RXONLY
;
1423 adapter
->flowcontrol
= FLOW_NONE
;
1428 /* et1310_update_macstat_host_counters - Update local copy of the statistics */
1429 static void et1310_update_macstat_host_counters(struct et131x_adapter
*adapter
)
1431 struct ce_stats
*stats
= &adapter
->stats
;
1432 struct macstat_regs __iomem
*macstat
=
1433 &adapter
->regs
->macstat
;
1435 stats
->tx_collisions
+= readl(&macstat
->tx_total_collisions
);
1436 stats
->tx_first_collisions
+= readl(&macstat
->tx_single_collisions
);
1437 stats
->tx_deferred
+= readl(&macstat
->tx_deferred
);
1438 stats
->tx_excessive_collisions
+=
1439 readl(&macstat
->tx_multiple_collisions
);
1440 stats
->tx_late_collisions
+= readl(&macstat
->tx_late_collisions
);
1441 stats
->tx_underflows
+= readl(&macstat
->tx_undersize_frames
);
1442 stats
->tx_max_pkt_errs
+= readl(&macstat
->tx_oversize_frames
);
1444 stats
->rx_align_errs
+= readl(&macstat
->rx_align_errs
);
1445 stats
->rx_crc_errs
+= readl(&macstat
->rx_code_errs
);
1446 stats
->rcvd_pkts_dropped
+= readl(&macstat
->rx_drops
);
1447 stats
->rx_overflows
+= readl(&macstat
->rx_oversize_packets
);
1448 stats
->rx_code_violations
+= readl(&macstat
->rx_fcs_errs
);
1449 stats
->rx_length_errs
+= readl(&macstat
->rx_frame_len_errs
);
1450 stats
->rx_other_errs
+= readl(&macstat
->rx_fragment_packets
);
1453 /* et1310_handle_macstat_interrupt
1455 * One of the MACSTAT counters has wrapped. Update the local copy of
1456 * the statistics held in the adapter structure, checking the "wrap"
1457 * bit for each counter.
1459 static void et1310_handle_macstat_interrupt(struct et131x_adapter
*adapter
)
1464 /* Read the interrupt bits from the register(s). These are Clear On
1467 carry_reg1
= readl(&adapter
->regs
->macstat
.carry_reg1
);
1468 carry_reg2
= readl(&adapter
->regs
->macstat
.carry_reg2
);
1470 writel(carry_reg1
, &adapter
->regs
->macstat
.carry_reg1
);
1471 writel(carry_reg2
, &adapter
->regs
->macstat
.carry_reg2
);
1473 /* We need to do update the host copy of all the MAC_STAT counters.
1474 * For each counter, check it's overflow bit. If the overflow bit is
1475 * set, then increment the host version of the count by one complete
1476 * revolution of the counter. This routine is called when the counter
1477 * block indicates that one of the counters has wrapped.
1479 if (carry_reg1
& (1 << 14))
1480 adapter
->stats
.rx_code_violations
+= COUNTER_WRAP_16_BIT
;
1481 if (carry_reg1
& (1 << 8))
1482 adapter
->stats
.rx_align_errs
+= COUNTER_WRAP_12_BIT
;
1483 if (carry_reg1
& (1 << 7))
1484 adapter
->stats
.rx_length_errs
+= COUNTER_WRAP_16_BIT
;
1485 if (carry_reg1
& (1 << 2))
1486 adapter
->stats
.rx_other_errs
+= COUNTER_WRAP_16_BIT
;
1487 if (carry_reg1
& (1 << 6))
1488 adapter
->stats
.rx_crc_errs
+= COUNTER_WRAP_16_BIT
;
1489 if (carry_reg1
& (1 << 3))
1490 adapter
->stats
.rx_overflows
+= COUNTER_WRAP_16_BIT
;
1491 if (carry_reg1
& (1 << 0))
1492 adapter
->stats
.rcvd_pkts_dropped
+= COUNTER_WRAP_16_BIT
;
1493 if (carry_reg2
& (1 << 16))
1494 adapter
->stats
.tx_max_pkt_errs
+= COUNTER_WRAP_12_BIT
;
1495 if (carry_reg2
& (1 << 15))
1496 adapter
->stats
.tx_underflows
+= COUNTER_WRAP_12_BIT
;
1497 if (carry_reg2
& (1 << 6))
1498 adapter
->stats
.tx_first_collisions
+= COUNTER_WRAP_12_BIT
;
1499 if (carry_reg2
& (1 << 8))
1500 adapter
->stats
.tx_deferred
+= COUNTER_WRAP_12_BIT
;
1501 if (carry_reg2
& (1 << 5))
1502 adapter
->stats
.tx_excessive_collisions
+= COUNTER_WRAP_12_BIT
;
1503 if (carry_reg2
& (1 << 4))
1504 adapter
->stats
.tx_late_collisions
+= COUNTER_WRAP_12_BIT
;
1505 if (carry_reg2
& (1 << 2))
1506 adapter
->stats
.tx_collisions
+= COUNTER_WRAP_12_BIT
;
1509 static int et131x_mdio_read(struct mii_bus
*bus
, int phy_addr
, int reg
)
1511 struct net_device
*netdev
= bus
->priv
;
1512 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
1516 ret
= et131x_phy_mii_read(adapter
, phy_addr
, reg
, &value
);
1524 static int et131x_mdio_write(struct mii_bus
*bus
, int phy_addr
,
1527 struct net_device
*netdev
= bus
->priv
;
1528 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
1530 return et131x_mii_write(adapter
, phy_addr
, reg
, value
);
1533 /* et1310_phy_power_switch - PHY power control
1534 * @adapter: device to control
1535 * @down: true for off/false for back on
1537 * one hundred, ten, one thousand megs
1538 * How would you like to have your LAN accessed
1539 * Can't you see that this code processed
1540 * Phy power, phy power..
1542 static void et1310_phy_power_switch(struct et131x_adapter
*adapter
, bool down
)
1545 struct phy_device
*phydev
= adapter
->phydev
;
1547 et131x_mii_read(adapter
, MII_BMCR
, &data
);
1548 data
&= ~BMCR_PDOWN
;
1551 et131x_mii_write(adapter
, phydev
->addr
, MII_BMCR
, data
);
1554 /* et131x_xcvr_init - Init the phy if we are setting it into force mode */
1555 static void et131x_xcvr_init(struct et131x_adapter
*adapter
)
1558 struct phy_device
*phydev
= adapter
->phydev
;
1560 /* Set the LED behavior such that LED 1 indicates speed (off =
1561 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
1562 * link and activity (on for link, blink off for activity).
1564 * NOTE: Some customizations have been added here for specific
1565 * vendors; The LED behavior is now determined by vendor data in the
1566 * EEPROM. However, the above description is the default.
1568 if ((adapter
->eeprom_data
[1] & 0x4) == 0) {
1569 et131x_mii_read(adapter
, PHY_LED_2
, &lcr2
);
1571 lcr2
&= (ET_LED2_LED_100TX
| ET_LED2_LED_1000T
);
1572 lcr2
|= (LED_VAL_LINKON_ACTIVE
<< LED_LINK_SHIFT
);
1574 if ((adapter
->eeprom_data
[1] & 0x8) == 0)
1575 lcr2
|= (LED_VAL_1000BT_100BTX
<< LED_TXRX_SHIFT
);
1577 lcr2
|= (LED_VAL_LINKON
<< LED_TXRX_SHIFT
);
1579 et131x_mii_write(adapter
, phydev
->addr
, PHY_LED_2
, lcr2
);
1583 /* et131x_configure_global_regs - configure JAGCore global regs
1585 * Used to configure the global registers on the JAGCore
1587 static void et131x_configure_global_regs(struct et131x_adapter
*adapter
)
1589 struct global_regs __iomem
*regs
= &adapter
->regs
->global
;
1591 writel(0, ®s
->rxq_start_addr
);
1592 writel(INTERNAL_MEM_SIZE
- 1, ®s
->txq_end_addr
);
1594 if (adapter
->registry_jumbo_packet
< 2048) {
1595 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
1596 * block of RAM that the driver can split between Tx
1597 * and Rx as it desires. Our default is to split it
1600 writel(PARM_RX_MEM_END_DEF
, ®s
->rxq_end_addr
);
1601 writel(PARM_RX_MEM_END_DEF
+ 1, ®s
->txq_start_addr
);
1602 } else if (adapter
->registry_jumbo_packet
< 8192) {
1603 /* For jumbo packets > 2k but < 8k, split 50-50. */
1604 writel(INTERNAL_MEM_RX_OFFSET
, ®s
->rxq_end_addr
);
1605 writel(INTERNAL_MEM_RX_OFFSET
+ 1, ®s
->txq_start_addr
);
1607 /* 9216 is the only packet size greater than 8k that
1608 * is available. The Tx buffer has to be big enough
1609 * for one whole packet on the Tx side. We'll make
1610 * the Tx 9408, and give the rest to Rx
1612 writel(0x01b3, ®s
->rxq_end_addr
);
1613 writel(0x01b4, ®s
->txq_start_addr
);
1616 /* Initialize the loopback register. Disable all loopbacks. */
1617 writel(0, ®s
->loopback
);
1620 writel(0, ®s
->msi_config
);
1622 /* By default, disable the watchdog timer. It will be enabled when
1623 * a packet is queued.
1625 writel(0, ®s
->watchdog_timer
);
1628 /* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence */
1629 static void et131x_config_rx_dma_regs(struct et131x_adapter
*adapter
)
1631 struct rxdma_regs __iomem
*rx_dma
= &adapter
->regs
->rxdma
;
1632 struct rx_ring
*rx_local
= &adapter
->rx_ring
;
1633 struct fbr_desc
*fbr_entry
;
1636 unsigned long flags
;
1639 /* Halt RXDMA to perform the reconfigure. */
1640 et131x_rx_dma_disable(adapter
);
1642 /* Load the completion writeback physical address */
1643 writel(upper_32_bits(rx_local
->rx_status_bus
), &rx_dma
->dma_wb_base_hi
);
1644 writel(lower_32_bits(rx_local
->rx_status_bus
), &rx_dma
->dma_wb_base_lo
);
1646 memset(rx_local
->rx_status_block
, 0, sizeof(struct rx_status_block
));
1648 /* Set the address and parameters of the packet status ring into the
1651 writel(upper_32_bits(rx_local
->ps_ring_physaddr
), &rx_dma
->psr_base_hi
);
1652 writel(lower_32_bits(rx_local
->ps_ring_physaddr
), &rx_dma
->psr_base_lo
);
1653 writel(rx_local
->psr_entries
- 1, &rx_dma
->psr_num_des
);
1654 writel(0, &rx_dma
->psr_full_offset
);
1656 psr_num_des
= readl(&rx_dma
->psr_num_des
) & ET_RXDMA_PSR_NUM_DES_MASK
;
1657 writel((psr_num_des
* LO_MARK_PERCENT_FOR_PSR
) / 100,
1658 &rx_dma
->psr_min_des
);
1660 spin_lock_irqsave(&adapter
->rcv_lock
, flags
);
1662 /* These local variables track the PSR in the adapter structure */
1663 rx_local
->local_psr_full
= 0;
1665 for (id
= 0; id
< NUM_FBRS
; id
++) {
1666 u32 __iomem
*num_des
;
1667 u32 __iomem
*full_offset
;
1668 u32 __iomem
*min_des
;
1669 u32 __iomem
*base_hi
;
1670 u32 __iomem
*base_lo
;
1671 struct fbr_lookup
*fbr
= rx_local
->fbr
[id
];
1674 num_des
= &rx_dma
->fbr0_num_des
;
1675 full_offset
= &rx_dma
->fbr0_full_offset
;
1676 min_des
= &rx_dma
->fbr0_min_des
;
1677 base_hi
= &rx_dma
->fbr0_base_hi
;
1678 base_lo
= &rx_dma
->fbr0_base_lo
;
1680 num_des
= &rx_dma
->fbr1_num_des
;
1681 full_offset
= &rx_dma
->fbr1_full_offset
;
1682 min_des
= &rx_dma
->fbr1_min_des
;
1683 base_hi
= &rx_dma
->fbr1_base_hi
;
1684 base_lo
= &rx_dma
->fbr1_base_lo
;
1687 /* Now's the best time to initialize FBR contents */
1688 fbr_entry
= fbr
->ring_virtaddr
;
1689 for (entry
= 0; entry
< fbr
->num_entries
; entry
++) {
1690 fbr_entry
->addr_hi
= fbr
->bus_high
[entry
];
1691 fbr_entry
->addr_lo
= fbr
->bus_low
[entry
];
1692 fbr_entry
->word2
= entry
;
1696 /* Set the address and parameters of Free buffer ring 1 and 0
1697 * into the 1310's registers
1699 writel(upper_32_bits(fbr
->ring_physaddr
), base_hi
);
1700 writel(lower_32_bits(fbr
->ring_physaddr
), base_lo
);
1701 writel(fbr
->num_entries
- 1, num_des
);
1702 writel(ET_DMA10_WRAP
, full_offset
);
1704 /* This variable tracks the free buffer ring 1 full position,
1705 * so it has to match the above.
1707 fbr
->local_full
= ET_DMA10_WRAP
;
1708 writel(((fbr
->num_entries
* LO_MARK_PERCENT_FOR_RX
) / 100) - 1,
1712 /* Program the number of packets we will receive before generating an
1714 * For version B silicon, this value gets updated once autoneg is
1717 writel(PARM_RX_NUM_BUFS_DEF
, &rx_dma
->num_pkt_done
);
1719 /* The "time_done" is not working correctly to coalesce interrupts
1720 * after a given time period, but rather is giving us an interrupt
1721 * regardless of whether we have received packets.
1722 * This value gets updated once autoneg is complete.
1724 writel(PARM_RX_TIME_INT_DEF
, &rx_dma
->max_pkt_time
);
1726 spin_unlock_irqrestore(&adapter
->rcv_lock
, flags
);
1729 /* et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
1731 * Configure the transmit engine with the ring buffers we have created
1732 * and prepare it for use.
1734 static void et131x_config_tx_dma_regs(struct et131x_adapter
*adapter
)
1736 struct txdma_regs __iomem
*txdma
= &adapter
->regs
->txdma
;
1737 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
1739 /* Load the hardware with the start of the transmit descriptor ring. */
1740 writel(upper_32_bits(tx_ring
->tx_desc_ring_pa
), &txdma
->pr_base_hi
);
1741 writel(lower_32_bits(tx_ring
->tx_desc_ring_pa
), &txdma
->pr_base_lo
);
1743 /* Initialise the transmit DMA engine */
1744 writel(NUM_DESC_PER_RING_TX
- 1, &txdma
->pr_num_des
);
1746 /* Load the completion writeback physical address */
1747 writel(upper_32_bits(tx_ring
->tx_status_pa
), &txdma
->dma_wb_base_hi
);
1748 writel(lower_32_bits(tx_ring
->tx_status_pa
), &txdma
->dma_wb_base_lo
);
1750 *tx_ring
->tx_status
= 0;
1752 writel(0, &txdma
->service_request
);
1753 tx_ring
->send_idx
= 0;
1756 /* et131x_adapter_setup - Set the adapter up as per cassini+ documentation */
1757 static void et131x_adapter_setup(struct et131x_adapter
*adapter
)
1759 /* Configure the JAGCore */
1760 et131x_configure_global_regs(adapter
);
1762 et1310_config_mac_regs1(adapter
);
1764 /* Configure the MMC registers */
1765 /* All we need to do is initialize the Memory Control Register */
1766 writel(ET_MMC_ENABLE
, &adapter
->regs
->mmc
.mmc_ctrl
);
1768 et1310_config_rxmac_regs(adapter
);
1769 et1310_config_txmac_regs(adapter
);
1771 et131x_config_rx_dma_regs(adapter
);
1772 et131x_config_tx_dma_regs(adapter
);
1774 et1310_config_macstat_regs(adapter
);
1776 et1310_phy_power_switch(adapter
, 0);
1777 et131x_xcvr_init(adapter
);
1780 /* et131x_soft_reset - Issue soft reset to the hardware, complete for ET1310 */
1781 static void et131x_soft_reset(struct et131x_adapter
*adapter
)
1785 /* Disable MAC Core */
1786 reg
= ET_MAC_CFG1_SOFT_RESET
| ET_MAC_CFG1_SIM_RESET
|
1787 ET_MAC_CFG1_RESET_RXMC
| ET_MAC_CFG1_RESET_TXMC
|
1788 ET_MAC_CFG1_RESET_RXFUNC
| ET_MAC_CFG1_RESET_TXFUNC
;
1789 writel(reg
, &adapter
->regs
->mac
.cfg1
);
1792 writel(reg
, &adapter
->regs
->global
.sw_reset
);
1794 reg
= ET_MAC_CFG1_RESET_RXMC
| ET_MAC_CFG1_RESET_TXMC
|
1795 ET_MAC_CFG1_RESET_RXFUNC
| ET_MAC_CFG1_RESET_TXFUNC
;
1796 writel(reg
, &adapter
->regs
->mac
.cfg1
);
1797 writel(0, &adapter
->regs
->mac
.cfg1
);
1800 /* et131x_enable_interrupts - enable interrupt
1802 * Enable the appropriate interrupts on the ET131x according to our
1805 static void et131x_enable_interrupts(struct et131x_adapter
*adapter
)
1809 /* Enable all global interrupts */
1810 if (adapter
->flowcontrol
== FLOW_TXONLY
||
1811 adapter
->flowcontrol
== FLOW_BOTH
)
1812 mask
= INT_MASK_ENABLE
;
1814 mask
= INT_MASK_ENABLE_NO_FLOW
;
1816 writel(mask
, &adapter
->regs
->global
.int_mask
);
1819 /* et131x_disable_interrupts - interrupt disable
1821 * Block all interrupts from the et131x device at the device itself
1823 static void et131x_disable_interrupts(struct et131x_adapter
*adapter
)
1825 /* Disable all global interrupts */
1826 writel(INT_MASK_DISABLE
, &adapter
->regs
->global
.int_mask
);
1829 /* et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310 */
1830 static void et131x_tx_dma_disable(struct et131x_adapter
*adapter
)
1832 /* Setup the transmit dma configuration register */
1833 writel(ET_TXDMA_CSR_HALT
| ET_TXDMA_SNGL_EPKT
,
1834 &adapter
->regs
->txdma
.csr
);
1837 /* et131x_enable_txrx - Enable tx/rx queues */
1838 static void et131x_enable_txrx(struct net_device
*netdev
)
1840 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
1842 /* Enable the Tx and Rx DMA engines (if not already enabled) */
1843 et131x_rx_dma_enable(adapter
);
1844 et131x_tx_dma_enable(adapter
);
1846 /* Enable device interrupts */
1847 if (adapter
->flags
& FMP_ADAPTER_INTERRUPT_IN_USE
)
1848 et131x_enable_interrupts(adapter
);
1850 /* We're ready to move some data, so start the queue */
1851 netif_start_queue(netdev
);
1854 /* et131x_disable_txrx - Disable tx/rx queues */
1855 static void et131x_disable_txrx(struct net_device
*netdev
)
1857 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
1859 /* First thing is to stop the queue */
1860 netif_stop_queue(netdev
);
1862 /* Stop the Tx and Rx DMA engines */
1863 et131x_rx_dma_disable(adapter
);
1864 et131x_tx_dma_disable(adapter
);
1866 /* Disable device interrupts */
1867 et131x_disable_interrupts(adapter
);
1870 /* et131x_init_send - Initialize send data structures */
1871 static void et131x_init_send(struct et131x_adapter
*adapter
)
1874 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
1875 struct tcb
*tcb
= tx_ring
->tcb_ring
;
1877 tx_ring
->tcb_qhead
= tcb
;
1879 memset(tcb
, 0, sizeof(struct tcb
) * NUM_TCB
);
1881 /* Go through and set up each TCB */
1882 for (ct
= 0; ct
++ < NUM_TCB
; tcb
++)
1883 /* Set the link pointer in HW TCB to the next TCB in the
1886 tcb
->next
= tcb
+ 1;
1888 /* Set the tail pointer */
1890 tx_ring
->tcb_qtail
= tcb
;
1892 /* Curr send queue should now be empty */
1893 tx_ring
->send_head
= NULL
;
1894 tx_ring
->send_tail
= NULL
;
1897 /* et1310_enable_phy_coma - called when network cable is unplugged
1899 * driver receive an phy status change interrupt while in D0 and check that
1900 * phy_status is down.
1902 * -- gate off JAGCore;
1903 * -- set gigE PHY in Coma mode
1904 * -- wake on phy_interrupt; Perform software reset JAGCore,
1905 * re-initialize jagcore and gigE PHY
1907 * Add D0-ASPM-PhyLinkDown Support:
1908 * -- while in D0, when there is a phy_interrupt indicating phy link
1909 * down status, call the MPSetPhyComa routine to enter this active
1910 * state power saving mode
1911 * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
1912 * indicating linkup status, call the MPDisablePhyComa routine to
1913 * restore JAGCore and gigE PHY
1915 static void et1310_enable_phy_coma(struct et131x_adapter
*adapter
)
1917 u32 pmcsr
= readl(&adapter
->regs
->global
.pm_csr
);
1919 /* Save the GbE PHY speed and duplex modes. Need to restore this
1920 * when cable is plugged back in
1923 /* Stop sending packets. */
1924 adapter
->flags
|= FMP_ADAPTER_LOWER_POWER
;
1926 /* Wait for outstanding Receive packets */
1927 et131x_disable_txrx(adapter
->netdev
);
1929 /* Gate off JAGCore 3 clock domains */
1930 pmcsr
&= ~ET_PMCSR_INIT
;
1931 writel(pmcsr
, &adapter
->regs
->global
.pm_csr
);
1933 /* Program gigE PHY in to Coma mode */
1934 pmcsr
|= ET_PM_PHY_SW_COMA
;
1935 writel(pmcsr
, &adapter
->regs
->global
.pm_csr
);
1938 /* et1310_disable_phy_coma - Disable the Phy Coma Mode */
1939 static void et1310_disable_phy_coma(struct et131x_adapter
*adapter
)
1943 pmcsr
= readl(&adapter
->regs
->global
.pm_csr
);
1945 /* Disable phy_sw_coma register and re-enable JAGCore clocks */
1946 pmcsr
|= ET_PMCSR_INIT
;
1947 pmcsr
&= ~ET_PM_PHY_SW_COMA
;
1948 writel(pmcsr
, &adapter
->regs
->global
.pm_csr
);
1950 /* Restore the GbE PHY speed and duplex modes;
1951 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
1954 /* Re-initialize the send structures */
1955 et131x_init_send(adapter
);
1957 /* Bring the device back to the state it was during init prior to
1958 * autonegotiation being complete. This way, when we get the auto-neg
1959 * complete interrupt, we can complete init by calling ConfigMacREGS2.
1961 et131x_soft_reset(adapter
);
1963 /* setup et1310 as per the documentation ?? */
1964 et131x_adapter_setup(adapter
);
1966 /* Allow Tx to restart */
1967 adapter
->flags
&= ~FMP_ADAPTER_LOWER_POWER
;
1969 et131x_enable_txrx(adapter
->netdev
);
1972 static inline u32
bump_free_buff_ring(u32
*free_buff_ring
, u32 limit
)
1974 u32 tmp_free_buff_ring
= *free_buff_ring
;
1976 tmp_free_buff_ring
++;
1977 /* This works for all cases where limit < 1024. The 1023 case
1978 * works because 1023++ is 1024 which means the if condition is not
1979 * taken but the carry of the bit into the wrap bit toggles the wrap
1982 if ((tmp_free_buff_ring
& ET_DMA10_MASK
) > limit
) {
1983 tmp_free_buff_ring
&= ~ET_DMA10_MASK
;
1984 tmp_free_buff_ring
^= ET_DMA10_WRAP
;
1986 /* For the 1023 case */
1987 tmp_free_buff_ring
&= (ET_DMA10_MASK
| ET_DMA10_WRAP
);
1988 *free_buff_ring
= tmp_free_buff_ring
;
1989 return tmp_free_buff_ring
;
1992 /* et131x_rx_dma_memory_alloc
1994 * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
1995 * and the Packet Status Ring.
1997 static int et131x_rx_dma_memory_alloc(struct et131x_adapter
*adapter
)
2004 struct rx_ring
*rx_ring
= &adapter
->rx_ring
;
2005 struct fbr_lookup
*fbr
;
2007 /* Alloc memory for the lookup table */
2008 rx_ring
->fbr
[0] = kmalloc(sizeof(*fbr
), GFP_KERNEL
);
2009 if (rx_ring
->fbr
[0] == NULL
)
2011 rx_ring
->fbr
[1] = kmalloc(sizeof(*fbr
), GFP_KERNEL
);
2012 if (rx_ring
->fbr
[1] == NULL
)
2015 /* The first thing we will do is configure the sizes of the buffer
2016 * rings. These will change based on jumbo packet support. Larger
2017 * jumbo packets increases the size of each entry in FBR0, and the
2018 * number of entries in FBR0, while at the same time decreasing the
2019 * number of entries in FBR1.
2021 * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
2022 * entries are huge in order to accommodate a "jumbo" frame, then it
2023 * will have less entries. Conversely, FBR1 will now be relied upon
2024 * to carry more "normal" frames, thus it's entry size also increases
2025 * and the number of entries goes up too (since it now carries
2026 * "small" + "regular" packets.
2028 * In this scheme, we try to maintain 512 entries between the two
2029 * rings. Also, FBR1 remains a constant size - when it's size doubles
2030 * the number of entries halves. FBR0 increases in size, however.
2032 if (adapter
->registry_jumbo_packet
< 2048) {
2033 rx_ring
->fbr
[0]->buffsize
= 256;
2034 rx_ring
->fbr
[0]->num_entries
= 512;
2035 rx_ring
->fbr
[1]->buffsize
= 2048;
2036 rx_ring
->fbr
[1]->num_entries
= 512;
2037 } else if (adapter
->registry_jumbo_packet
< 4096) {
2038 rx_ring
->fbr
[0]->buffsize
= 512;
2039 rx_ring
->fbr
[0]->num_entries
= 1024;
2040 rx_ring
->fbr
[1]->buffsize
= 4096;
2041 rx_ring
->fbr
[1]->num_entries
= 512;
2043 rx_ring
->fbr
[0]->buffsize
= 1024;
2044 rx_ring
->fbr
[0]->num_entries
= 768;
2045 rx_ring
->fbr
[1]->buffsize
= 16384;
2046 rx_ring
->fbr
[1]->num_entries
= 128;
2049 rx_ring
->psr_entries
= rx_ring
->fbr
[0]->num_entries
+
2050 rx_ring
->fbr
[1]->num_entries
;
2052 for (id
= 0; id
< NUM_FBRS
; id
++) {
2053 fbr
= rx_ring
->fbr
[id
];
2054 /* Allocate an area of memory for Free Buffer Ring */
2055 bufsize
= sizeof(struct fbr_desc
) * fbr
->num_entries
;
2056 fbr
->ring_virtaddr
= dma_alloc_coherent(&adapter
->pdev
->dev
,
2058 &fbr
->ring_physaddr
,
2060 if (!fbr
->ring_virtaddr
) {
2061 dev_err(&adapter
->pdev
->dev
,
2062 "Cannot alloc memory for Free Buffer Ring %d\n",
2068 for (id
= 0; id
< NUM_FBRS
; id
++) {
2069 fbr
= rx_ring
->fbr
[id
];
2070 fbr_chunksize
= (FBR_CHUNKS
* fbr
->buffsize
);
2072 for (i
= 0; i
< fbr
->num_entries
/ FBR_CHUNKS
; i
++) {
2073 dma_addr_t fbr_physaddr
;
2075 fbr
->mem_virtaddrs
[i
] = dma_alloc_coherent(
2076 &adapter
->pdev
->dev
, fbr_chunksize
,
2077 &fbr
->mem_physaddrs
[i
],
2080 if (!fbr
->mem_virtaddrs
[i
]) {
2081 dev_err(&adapter
->pdev
->dev
,
2082 "Could not alloc memory\n");
2086 /* See NOTE in "Save Physical Address" comment above */
2087 fbr_physaddr
= fbr
->mem_physaddrs
[i
];
2089 for (j
= 0; j
< FBR_CHUNKS
; j
++) {
2090 u32 k
= (i
* FBR_CHUNKS
) + j
;
2092 /* Save the Virtual address of this index for
2093 * quick access later
2095 fbr
->virt
[k
] = (u8
*)fbr
->mem_virtaddrs
[i
] +
2096 (j
* fbr
->buffsize
);
2098 /* now store the physical address in the
2099 * descriptor so the device can access it
2101 fbr
->bus_high
[k
] = upper_32_bits(fbr_physaddr
);
2102 fbr
->bus_low
[k
] = lower_32_bits(fbr_physaddr
);
2103 fbr_physaddr
+= fbr
->buffsize
;
2108 /* Allocate an area of memory for FIFO of Packet Status ring entries */
2109 psr_size
= sizeof(struct pkt_stat_desc
) * rx_ring
->psr_entries
;
2111 rx_ring
->ps_ring_virtaddr
= dma_alloc_coherent(&adapter
->pdev
->dev
,
2113 &rx_ring
->ps_ring_physaddr
,
2116 if (!rx_ring
->ps_ring_virtaddr
) {
2117 dev_err(&adapter
->pdev
->dev
,
2118 "Cannot alloc memory for Packet Status Ring\n");
2122 /* NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
2123 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2124 * are ever returned, make sure the high part is retrieved here before
2125 * storing the adjusted address.
2128 /* Allocate an area of memory for writeback of status information */
2129 rx_ring
->rx_status_block
= dma_alloc_coherent(&adapter
->pdev
->dev
,
2130 sizeof(struct rx_status_block
),
2131 &rx_ring
->rx_status_bus
,
2133 if (!rx_ring
->rx_status_block
) {
2134 dev_err(&adapter
->pdev
->dev
,
2135 "Cannot alloc memory for Status Block\n");
2138 rx_ring
->num_rfd
= NIC_DEFAULT_NUM_RFD
;
2140 /* The RFDs are going to be put on lists later on, so initialize the
2143 INIT_LIST_HEAD(&rx_ring
->recv_list
);
2147 /* et131x_rx_dma_memory_free - Free all memory allocated within this module */
2148 static void et131x_rx_dma_memory_free(struct et131x_adapter
*adapter
)
2155 struct rx_ring
*rx_ring
= &adapter
->rx_ring
;
2156 struct fbr_lookup
*fbr
;
2158 /* Free RFDs and associated packet descriptors */
2159 WARN_ON(rx_ring
->num_ready_recv
!= rx_ring
->num_rfd
);
2161 while (!list_empty(&rx_ring
->recv_list
)) {
2162 rfd
= list_entry(rx_ring
->recv_list
.next
,
2163 struct rfd
, list_node
);
2165 list_del(&rfd
->list_node
);
2170 /* Free Free Buffer Rings */
2171 for (id
= 0; id
< NUM_FBRS
; id
++) {
2172 fbr
= rx_ring
->fbr
[id
];
2174 if (!fbr
|| !fbr
->ring_virtaddr
)
2177 /* First the packet memory */
2178 for (ii
= 0; ii
< fbr
->num_entries
/ FBR_CHUNKS
; ii
++) {
2179 if (fbr
->mem_virtaddrs
[ii
]) {
2180 bufsize
= fbr
->buffsize
* FBR_CHUNKS
;
2182 dma_free_coherent(&adapter
->pdev
->dev
,
2184 fbr
->mem_virtaddrs
[ii
],
2185 fbr
->mem_physaddrs
[ii
]);
2187 fbr
->mem_virtaddrs
[ii
] = NULL
;
2191 bufsize
= sizeof(struct fbr_desc
) * fbr
->num_entries
;
2193 dma_free_coherent(&adapter
->pdev
->dev
,
2196 fbr
->ring_physaddr
);
2198 fbr
->ring_virtaddr
= NULL
;
2201 /* Free Packet Status Ring */
2202 if (rx_ring
->ps_ring_virtaddr
) {
2203 psr_size
= sizeof(struct pkt_stat_desc
) * rx_ring
->psr_entries
;
2205 dma_free_coherent(&adapter
->pdev
->dev
, psr_size
,
2206 rx_ring
->ps_ring_virtaddr
,
2207 rx_ring
->ps_ring_physaddr
);
2209 rx_ring
->ps_ring_virtaddr
= NULL
;
2212 /* Free area of memory for the writeback of status information */
2213 if (rx_ring
->rx_status_block
) {
2214 dma_free_coherent(&adapter
->pdev
->dev
,
2215 sizeof(struct rx_status_block
),
2216 rx_ring
->rx_status_block
,
2217 rx_ring
->rx_status_bus
);
2218 rx_ring
->rx_status_block
= NULL
;
2221 /* Free the FBR Lookup Table */
2222 kfree(rx_ring
->fbr
[0]);
2223 kfree(rx_ring
->fbr
[1]);
2225 /* Reset Counters */
2226 rx_ring
->num_ready_recv
= 0;
2229 /* et131x_init_recv - Initialize receive data structures */
2230 static int et131x_init_recv(struct et131x_adapter
*adapter
)
2234 struct rx_ring
*rx_ring
= &adapter
->rx_ring
;
2236 /* Setup each RFD */
2237 for (rfdct
= 0; rfdct
< rx_ring
->num_rfd
; rfdct
++) {
2238 rfd
= kzalloc(sizeof(*rfd
), GFP_ATOMIC
| GFP_DMA
);
2244 /* Add this RFD to the recv_list */
2245 list_add_tail(&rfd
->list_node
, &rx_ring
->recv_list
);
2247 /* Increment the available RFD's */
2248 rx_ring
->num_ready_recv
++;
2254 /* et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate */
2255 static void et131x_set_rx_dma_timer(struct et131x_adapter
*adapter
)
2257 struct phy_device
*phydev
= adapter
->phydev
;
2259 /* For version B silicon, we do not use the RxDMA timer for 10 and 100
2260 * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
2262 if ((phydev
->speed
== SPEED_100
) || (phydev
->speed
== SPEED_10
)) {
2263 writel(0, &adapter
->regs
->rxdma
.max_pkt_time
);
2264 writel(1, &adapter
->regs
->rxdma
.num_pkt_done
);
2268 /* NICReturnRFD - Recycle a RFD and put it back onto the receive list
2269 * @adapter: pointer to our adapter
2270 * @rfd: pointer to the RFD
2272 static void nic_return_rfd(struct et131x_adapter
*adapter
, struct rfd
*rfd
)
2274 struct rx_ring
*rx_local
= &adapter
->rx_ring
;
2275 struct rxdma_regs __iomem
*rx_dma
= &adapter
->regs
->rxdma
;
2276 u16 buff_index
= rfd
->bufferindex
;
2277 u8 ring_index
= rfd
->ringindex
;
2278 unsigned long flags
;
2279 struct fbr_lookup
*fbr
= rx_local
->fbr
[ring_index
];
2281 /* We don't use any of the OOB data besides status. Otherwise, we
2282 * need to clean up OOB data
2284 if (buff_index
< fbr
->num_entries
) {
2286 u32 __iomem
*offset
;
2287 struct fbr_desc
*next
;
2289 if (ring_index
== 0)
2290 offset
= &rx_dma
->fbr0_full_offset
;
2292 offset
= &rx_dma
->fbr1_full_offset
;
2294 next
= (struct fbr_desc
*)(fbr
->ring_virtaddr
) +
2295 INDEX10(fbr
->local_full
);
2297 /* Handle the Free Buffer Ring advancement here. Write
2298 * the PA / Buffer Index for the returned buffer into
2299 * the oldest (next to be freed)FBR entry
2301 next
->addr_hi
= fbr
->bus_high
[buff_index
];
2302 next
->addr_lo
= fbr
->bus_low
[buff_index
];
2303 next
->word2
= buff_index
;
2305 free_buff_ring
= bump_free_buff_ring(&fbr
->local_full
,
2306 fbr
->num_entries
- 1);
2307 writel(free_buff_ring
, offset
);
2309 dev_err(&adapter
->pdev
->dev
,
2310 "%s illegal Buffer Index returned\n", __func__
);
2313 /* The processing on this RFD is done, so put it back on the tail of
2316 spin_lock_irqsave(&adapter
->rcv_lock
, flags
);
2317 list_add_tail(&rfd
->list_node
, &rx_local
->recv_list
);
2318 rx_local
->num_ready_recv
++;
2319 spin_unlock_irqrestore(&adapter
->rcv_lock
, flags
);
2321 WARN_ON(rx_local
->num_ready_recv
> rx_local
->num_rfd
);
2324 /* nic_rx_pkts - Checks the hardware for available packets
2326 * Returns rfd, a pointer to our MPRFD.
2328 * Checks the hardware for available packets, using completion ring
2329 * If packets are available, it gets an RFD from the recv_list, attaches
2330 * the packet to it, puts the RFD in the RecvPendList, and also returns
2331 * the pointer to the RFD.
2333 static struct rfd
*nic_rx_pkts(struct et131x_adapter
*adapter
)
2335 struct rx_ring
*rx_local
= &adapter
->rx_ring
;
2336 struct rx_status_block
*status
;
2337 struct pkt_stat_desc
*psr
;
2339 unsigned long flags
;
2340 struct list_head
*element
;
2346 struct sk_buff
*skb
;
2347 struct fbr_lookup
*fbr
;
2349 /* RX Status block is written by the DMA engine prior to every
2350 * interrupt. It contains the next to be used entry in the Packet
2351 * Status Ring, and also the two Free Buffer rings.
2353 status
= rx_local
->rx_status_block
;
2354 word1
= status
->word1
>> 16; /* Get the useful bits */
2356 /* Check the PSR and wrap bits do not match */
2357 if ((word1
& 0x1FFF) == (rx_local
->local_psr_full
& 0x1FFF))
2358 return NULL
; /* Looks like this ring is not updated yet */
2360 /* The packet status ring indicates that data is available. */
2361 psr
= (struct pkt_stat_desc
*)(rx_local
->ps_ring_virtaddr
) +
2362 (rx_local
->local_psr_full
& 0xFFF);
2364 /* Grab any information that is required once the PSR is advanced,
2365 * since we can no longer rely on the memory being accurate
2367 len
= psr
->word1
& 0xFFFF;
2368 ring_index
= (psr
->word1
>> 26) & 0x03;
2369 fbr
= rx_local
->fbr
[ring_index
];
2370 buff_index
= (psr
->word1
>> 16) & 0x3FF;
2373 /* Indicate that we have used this PSR entry. */
2375 add_12bit(&rx_local
->local_psr_full
, 1);
2376 if ((rx_local
->local_psr_full
& 0xFFF) > rx_local
->psr_entries
- 1) {
2377 /* Clear psr full and toggle the wrap bit */
2378 rx_local
->local_psr_full
&= ~0xFFF;
2379 rx_local
->local_psr_full
^= 0x1000;
2382 writel(rx_local
->local_psr_full
, &adapter
->regs
->rxdma
.psr_full_offset
);
2384 if (ring_index
> 1 || buff_index
> fbr
->num_entries
- 1) {
2385 /* Illegal buffer or ring index cannot be used by S/W*/
2386 dev_err(&adapter
->pdev
->dev
,
2387 "NICRxPkts PSR Entry %d indicates length of %d and/or bad bi(%d)\n",
2388 rx_local
->local_psr_full
& 0xFFF, len
, buff_index
);
2392 /* Get and fill the RFD. */
2393 spin_lock_irqsave(&adapter
->rcv_lock
, flags
);
2395 element
= rx_local
->recv_list
.next
;
2396 rfd
= list_entry(element
, struct rfd
, list_node
);
2399 spin_unlock_irqrestore(&adapter
->rcv_lock
, flags
);
2403 list_del(&rfd
->list_node
);
2404 rx_local
->num_ready_recv
--;
2406 spin_unlock_irqrestore(&adapter
->rcv_lock
, flags
);
2408 rfd
->bufferindex
= buff_index
;
2409 rfd
->ringindex
= ring_index
;
2411 /* In V1 silicon, there is a bug which screws up filtering of runt
2412 * packets. Therefore runt packet filtering is disabled in the MAC and
2413 * the packets are dropped here. They are also counted here.
2415 if (len
< (NIC_MIN_PACKET_SIZE
+ 4)) {
2416 adapter
->stats
.rx_other_errs
++;
2421 if ((word0
& ALCATEL_MULTICAST_PKT
) && !(word0
& ALCATEL_BROADCAST_PKT
))
2422 adapter
->stats
.multicast_pkts_rcvd
++;
2426 skb
= dev_alloc_skb(rfd
->len
+ 2);
2428 dev_err(&adapter
->pdev
->dev
, "Couldn't alloc an SKB for Rx\n");
2432 adapter
->netdev
->stats
.rx_bytes
+= rfd
->len
;
2434 memcpy(skb_put(skb
, rfd
->len
), fbr
->virt
[buff_index
], rfd
->len
);
2436 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
2437 skb
->ip_summed
= CHECKSUM_NONE
;
2438 netif_receive_skb(skb
);
2441 nic_return_rfd(adapter
, rfd
);
2445 /* et131x_handle_recv_pkts - Interrupt handler for receive processing
2447 * Assumption, Rcv spinlock has been acquired.
2449 static int et131x_handle_recv_pkts(struct et131x_adapter
*adapter
, int budget
)
2451 struct rfd
*rfd
= NULL
;
2455 struct rx_ring
*rx_ring
= &adapter
->rx_ring
;
2457 if (budget
> MAX_PACKETS_HANDLED
)
2458 limit
= MAX_PACKETS_HANDLED
;
2460 /* Process up to available RFD's */
2461 while (count
< limit
) {
2462 if (list_empty(&rx_ring
->recv_list
)) {
2463 WARN_ON(rx_ring
->num_ready_recv
!= 0);
2468 rfd
= nic_rx_pkts(adapter
);
2473 /* Do not receive any packets until a filter has been set.
2474 * Do not receive any packets until we have link.
2475 * If length is zero, return the RFD in order to advance the
2478 if (!adapter
->packet_filter
||
2479 !netif_carrier_ok(adapter
->netdev
) ||
2483 /* Increment the number of packets we received */
2484 adapter
->netdev
->stats
.rx_packets
++;
2486 /* Set the status on the packet, either resources or success */
2487 if (rx_ring
->num_ready_recv
< RFD_LOW_WATER_MARK
)
2488 dev_warn(&adapter
->pdev
->dev
, "RFD's are running out\n");
2493 if (count
== limit
|| !done
) {
2494 rx_ring
->unfinished_receives
= true;
2495 writel(PARM_TX_TIME_INT_DEF
* NANO_IN_A_MICRO
,
2496 &adapter
->regs
->global
.watchdog_timer
);
2498 /* Watchdog timer will disable itself if appropriate. */
2499 rx_ring
->unfinished_receives
= false;
2505 /* et131x_tx_dma_memory_alloc
2507 * Allocates memory that will be visible both to the device and to the CPU.
2508 * The OS will pass us packets, pointers to which we will insert in the Tx
2509 * Descriptor queue. The device will read this queue to find the packets in
2510 * memory. The device will update the "status" in memory each time it xmits a
2513 static int et131x_tx_dma_memory_alloc(struct et131x_adapter
*adapter
)
2516 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2518 /* Allocate memory for the TCB's (Transmit Control Block) */
2519 tx_ring
->tcb_ring
= kcalloc(NUM_TCB
, sizeof(struct tcb
),
2520 GFP_ATOMIC
| GFP_DMA
);
2521 if (!tx_ring
->tcb_ring
)
2524 desc_size
= (sizeof(struct tx_desc
) * NUM_DESC_PER_RING_TX
);
2525 tx_ring
->tx_desc_ring
= dma_alloc_coherent(&adapter
->pdev
->dev
,
2527 &tx_ring
->tx_desc_ring_pa
,
2529 if (!tx_ring
->tx_desc_ring
) {
2530 dev_err(&adapter
->pdev
->dev
,
2531 "Cannot alloc memory for Tx Ring\n");
2535 /* Save physical address
2537 * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
2538 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2539 * are ever returned, make sure the high part is retrieved here before
2540 * storing the adjusted address.
2542 /* Allocate memory for the Tx status block */
2543 tx_ring
->tx_status
= dma_alloc_coherent(&adapter
->pdev
->dev
,
2545 &tx_ring
->tx_status_pa
,
2547 if (!tx_ring
->tx_status_pa
) {
2548 dev_err(&adapter
->pdev
->dev
,
2549 "Cannot alloc memory for Tx status block\n");
2555 /* et131x_tx_dma_memory_free - Free all memory allocated within this module */
2556 static void et131x_tx_dma_memory_free(struct et131x_adapter
*adapter
)
2559 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2561 if (tx_ring
->tx_desc_ring
) {
2562 /* Free memory relating to Tx rings here */
2563 desc_size
= (sizeof(struct tx_desc
) * NUM_DESC_PER_RING_TX
);
2564 dma_free_coherent(&adapter
->pdev
->dev
,
2566 tx_ring
->tx_desc_ring
,
2567 tx_ring
->tx_desc_ring_pa
);
2568 tx_ring
->tx_desc_ring
= NULL
;
2571 /* Free memory for the Tx status block */
2572 if (tx_ring
->tx_status
) {
2573 dma_free_coherent(&adapter
->pdev
->dev
,
2576 tx_ring
->tx_status_pa
);
2578 tx_ring
->tx_status
= NULL
;
2580 /* Free the memory for the tcb structures */
2581 kfree(tx_ring
->tcb_ring
);
2584 /* nic_send_packet - NIC specific send handler for version B silicon.
2585 * @adapter: pointer to our adapter
2586 * @tcb: pointer to struct tcb
2588 static int nic_send_packet(struct et131x_adapter
*adapter
, struct tcb
*tcb
)
2591 struct tx_desc desc
[24]; /* 24 x 16 byte */
2593 u32 thiscopy
, remainder
;
2594 struct sk_buff
*skb
= tcb
->skb
;
2595 u32 nr_frags
= skb_shinfo(skb
)->nr_frags
+ 1;
2596 struct skb_frag_struct
*frags
= &skb_shinfo(skb
)->frags
[0];
2597 struct phy_device
*phydev
= adapter
->phydev
;
2598 dma_addr_t dma_addr
;
2599 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2601 /* Part of the optimizations of this send routine restrict us to
2602 * sending 24 fragments at a pass. In practice we should never see
2603 * more than 5 fragments.
2605 * NOTE: The older version of this function (below) can handle any
2606 * number of fragments. If needed, we can call this function,
2607 * although it is less efficient.
2610 /* nr_frags should be no more than 18. */
2611 BUILD_BUG_ON(MAX_SKB_FRAGS
+ 1 > 23);
2613 memset(desc
, 0, sizeof(struct tx_desc
) * (nr_frags
+ 1));
2615 for (i
= 0; i
< nr_frags
; i
++) {
2616 /* If there is something in this element, lets get a
2617 * descriptor from the ring and get the necessary data
2620 /* If the fragments are smaller than a standard MTU,
2621 * then map them to a single descriptor in the Tx
2622 * Desc ring. However, if they're larger, as is
2623 * possible with support for jumbo packets, then
2624 * split them each across 2 descriptors.
2626 * This will work until we determine why the hardware
2627 * doesn't seem to like large fragments.
2629 if (skb_headlen(skb
) <= 1514) {
2630 /* Low 16bits are length, high is vlan and
2631 * unused currently so zero
2633 desc
[frag
].len_vlan
= skb_headlen(skb
);
2634 dma_addr
= dma_map_single(&adapter
->pdev
->dev
,
2638 desc
[frag
].addr_lo
= lower_32_bits(dma_addr
);
2639 desc
[frag
].addr_hi
= upper_32_bits(dma_addr
);
2642 desc
[frag
].len_vlan
= skb_headlen(skb
) / 2;
2643 dma_addr
= dma_map_single(&adapter
->pdev
->dev
,
2645 (skb_headlen(skb
) / 2),
2647 desc
[frag
].addr_lo
= lower_32_bits(dma_addr
);
2648 desc
[frag
].addr_hi
= upper_32_bits(dma_addr
);
2651 desc
[frag
].len_vlan
= skb_headlen(skb
) / 2;
2652 dma_addr
= dma_map_single(&adapter
->pdev
->dev
,
2654 (skb_headlen(skb
) / 2),
2655 (skb_headlen(skb
) / 2),
2657 desc
[frag
].addr_lo
= lower_32_bits(dma_addr
);
2658 desc
[frag
].addr_hi
= upper_32_bits(dma_addr
);
2662 desc
[frag
].len_vlan
= frags
[i
- 1].size
;
2663 dma_addr
= skb_frag_dma_map(&adapter
->pdev
->dev
,
2668 desc
[frag
].addr_lo
= lower_32_bits(dma_addr
);
2669 desc
[frag
].addr_hi
= upper_32_bits(dma_addr
);
2674 if (phydev
&& phydev
->speed
== SPEED_1000
) {
2675 if (++tx_ring
->since_irq
== PARM_TX_NUM_BUFS_DEF
) {
2676 /* Last element & Interrupt flag */
2677 desc
[frag
- 1].flags
=
2678 TXDESC_FLAG_INTPROC
| TXDESC_FLAG_LASTPKT
;
2679 tx_ring
->since_irq
= 0;
2680 } else { /* Last element */
2681 desc
[frag
- 1].flags
= TXDESC_FLAG_LASTPKT
;
2684 desc
[frag
- 1].flags
=
2685 TXDESC_FLAG_INTPROC
| TXDESC_FLAG_LASTPKT
;
2688 desc
[0].flags
|= TXDESC_FLAG_FIRSTPKT
;
2690 tcb
->index_start
= tx_ring
->send_idx
;
2693 thiscopy
= NUM_DESC_PER_RING_TX
- INDEX10(tx_ring
->send_idx
);
2695 if (thiscopy
>= frag
) {
2699 remainder
= frag
- thiscopy
;
2702 memcpy(tx_ring
->tx_desc_ring
+ INDEX10(tx_ring
->send_idx
),
2704 sizeof(struct tx_desc
) * thiscopy
);
2706 add_10bit(&tx_ring
->send_idx
, thiscopy
);
2708 if (INDEX10(tx_ring
->send_idx
) == 0 ||
2709 INDEX10(tx_ring
->send_idx
) == NUM_DESC_PER_RING_TX
) {
2710 tx_ring
->send_idx
&= ~ET_DMA10_MASK
;
2711 tx_ring
->send_idx
^= ET_DMA10_WRAP
;
2715 memcpy(tx_ring
->tx_desc_ring
,
2717 sizeof(struct tx_desc
) * remainder
);
2719 add_10bit(&tx_ring
->send_idx
, remainder
);
2722 if (INDEX10(tx_ring
->send_idx
) == 0) {
2723 if (tx_ring
->send_idx
)
2724 tcb
->index
= NUM_DESC_PER_RING_TX
- 1;
2726 tcb
->index
= ET_DMA10_WRAP
|(NUM_DESC_PER_RING_TX
- 1);
2728 tcb
->index
= tx_ring
->send_idx
- 1;
2731 spin_lock(&adapter
->tcb_send_qlock
);
2733 if (tx_ring
->send_tail
)
2734 tx_ring
->send_tail
->next
= tcb
;
2736 tx_ring
->send_head
= tcb
;
2738 tx_ring
->send_tail
= tcb
;
2740 WARN_ON(tcb
->next
!= NULL
);
2744 spin_unlock(&adapter
->tcb_send_qlock
);
2746 /* Write the new write pointer back to the device. */
2747 writel(tx_ring
->send_idx
, &adapter
->regs
->txdma
.service_request
);
2749 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
2750 * timer to wake us up if this packet isn't followed by N more.
2752 if (phydev
&& phydev
->speed
== SPEED_1000
) {
2753 writel(PARM_TX_TIME_INT_DEF
* NANO_IN_A_MICRO
,
2754 &adapter
->regs
->global
.watchdog_timer
);
2759 /* send_packet - Do the work to send a packet
2761 * Assumption: Send spinlock has been acquired
2763 static int send_packet(struct sk_buff
*skb
, struct et131x_adapter
*adapter
)
2767 unsigned long flags
;
2768 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2770 /* All packets must have at least a MAC address and a protocol type */
2771 if (skb
->len
< ETH_HLEN
)
2774 /* Get a TCB for this packet */
2775 spin_lock_irqsave(&adapter
->tcb_ready_qlock
, flags
);
2777 tcb
= tx_ring
->tcb_qhead
;
2780 spin_unlock_irqrestore(&adapter
->tcb_ready_qlock
, flags
);
2784 tx_ring
->tcb_qhead
= tcb
->next
;
2786 if (tx_ring
->tcb_qhead
== NULL
)
2787 tx_ring
->tcb_qtail
= NULL
;
2789 spin_unlock_irqrestore(&adapter
->tcb_ready_qlock
, flags
);
2794 /* Call the NIC specific send handler. */
2795 status
= nic_send_packet(adapter
, tcb
);
2798 spin_lock_irqsave(&adapter
->tcb_ready_qlock
, flags
);
2800 if (tx_ring
->tcb_qtail
)
2801 tx_ring
->tcb_qtail
->next
= tcb
;
2803 /* Apparently ready Q is empty. */
2804 tx_ring
->tcb_qhead
= tcb
;
2806 tx_ring
->tcb_qtail
= tcb
;
2807 spin_unlock_irqrestore(&adapter
->tcb_ready_qlock
, flags
);
2810 WARN_ON(tx_ring
->used
> NUM_TCB
);
2814 /* free_send_packet - Recycle a struct tcb
2815 * @adapter: pointer to our adapter
2816 * @tcb: pointer to struct tcb
2818 * Complete the packet if necessary
2819 * Assumption - Send spinlock has been acquired
2821 static inline void free_send_packet(struct et131x_adapter
*adapter
,
2824 unsigned long flags
;
2825 struct tx_desc
*desc
= NULL
;
2826 struct net_device_stats
*stats
= &adapter
->netdev
->stats
;
2827 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2831 stats
->tx_bytes
+= tcb
->skb
->len
;
2833 /* Iterate through the TX descriptors on the ring
2834 * corresponding to this packet and umap the fragments
2838 desc
= tx_ring
->tx_desc_ring
+
2839 INDEX10(tcb
->index_start
);
2841 dma_addr
= desc
->addr_lo
;
2842 dma_addr
|= (u64
)desc
->addr_hi
<< 32;
2844 dma_unmap_single(&adapter
->pdev
->dev
,
2846 desc
->len_vlan
, DMA_TO_DEVICE
);
2848 add_10bit(&tcb
->index_start
, 1);
2849 if (INDEX10(tcb
->index_start
) >=
2850 NUM_DESC_PER_RING_TX
) {
2851 tcb
->index_start
&= ~ET_DMA10_MASK
;
2852 tcb
->index_start
^= ET_DMA10_WRAP
;
2854 } while (desc
!= tx_ring
->tx_desc_ring
+ INDEX10(tcb
->index
));
2856 dev_kfree_skb_any(tcb
->skb
);
2859 memset(tcb
, 0, sizeof(struct tcb
));
2861 /* Add the TCB to the Ready Q */
2862 spin_lock_irqsave(&adapter
->tcb_ready_qlock
, flags
);
2864 stats
->tx_packets
++;
2866 if (tx_ring
->tcb_qtail
)
2867 tx_ring
->tcb_qtail
->next
= tcb
;
2869 /* Apparently ready Q is empty. */
2870 tx_ring
->tcb_qhead
= tcb
;
2872 tx_ring
->tcb_qtail
= tcb
;
2874 spin_unlock_irqrestore(&adapter
->tcb_ready_qlock
, flags
);
2875 WARN_ON(tx_ring
->used
< 0);
2878 /* et131x_free_busy_send_packets - Free and complete the stopped active sends
2880 * Assumption - Send spinlock has been acquired
2882 static void et131x_free_busy_send_packets(struct et131x_adapter
*adapter
)
2885 unsigned long flags
;
2887 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2889 /* Any packets being sent? Check the first TCB on the send list */
2890 spin_lock_irqsave(&adapter
->tcb_send_qlock
, flags
);
2892 tcb
= tx_ring
->send_head
;
2894 while (tcb
!= NULL
&& freed
< NUM_TCB
) {
2895 struct tcb
*next
= tcb
->next
;
2897 tx_ring
->send_head
= next
;
2900 tx_ring
->send_tail
= NULL
;
2904 spin_unlock_irqrestore(&adapter
->tcb_send_qlock
, flags
);
2907 free_send_packet(adapter
, tcb
);
2909 spin_lock_irqsave(&adapter
->tcb_send_qlock
, flags
);
2911 tcb
= tx_ring
->send_head
;
2914 WARN_ON(freed
== NUM_TCB
);
2916 spin_unlock_irqrestore(&adapter
->tcb_send_qlock
, flags
);
2921 /* et131x_handle_send_pkts - Interrupt handler for sending processing
2923 * Re-claim the send resources, complete sends and get more to send from
2924 * the send wait queue.
2926 * Assumption - Send spinlock has been acquired
2928 static void et131x_handle_send_pkts(struct et131x_adapter
*adapter
)
2930 unsigned long flags
;
2934 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2936 serviced
= readl(&adapter
->regs
->txdma
.new_service_complete
);
2937 index
= INDEX10(serviced
);
2939 /* Has the ring wrapped? Process any descriptors that do not have
2940 * the same "wrap" indicator as the current completion indicator
2942 spin_lock_irqsave(&adapter
->tcb_send_qlock
, flags
);
2944 tcb
= tx_ring
->send_head
;
2947 ((serviced
^ tcb
->index
) & ET_DMA10_WRAP
) &&
2948 index
< INDEX10(tcb
->index
)) {
2950 tx_ring
->send_head
= tcb
->next
;
2951 if (tcb
->next
== NULL
)
2952 tx_ring
->send_tail
= NULL
;
2954 spin_unlock_irqrestore(&adapter
->tcb_send_qlock
, flags
);
2955 free_send_packet(adapter
, tcb
);
2956 spin_lock_irqsave(&adapter
->tcb_send_qlock
, flags
);
2958 /* Goto the next packet */
2959 tcb
= tx_ring
->send_head
;
2962 !((serviced
^ tcb
->index
) & ET_DMA10_WRAP
) &&
2963 index
> (tcb
->index
& ET_DMA10_MASK
)) {
2965 tx_ring
->send_head
= tcb
->next
;
2966 if (tcb
->next
== NULL
)
2967 tx_ring
->send_tail
= NULL
;
2969 spin_unlock_irqrestore(&adapter
->tcb_send_qlock
, flags
);
2970 free_send_packet(adapter
, tcb
);
2971 spin_lock_irqsave(&adapter
->tcb_send_qlock
, flags
);
2973 /* Goto the next packet */
2974 tcb
= tx_ring
->send_head
;
2977 /* Wake up the queue when we hit a low-water mark */
2978 if (tx_ring
->used
<= NUM_TCB
/ 3)
2979 netif_wake_queue(adapter
->netdev
);
2981 spin_unlock_irqrestore(&adapter
->tcb_send_qlock
, flags
);
2984 static int et131x_get_settings(struct net_device
*netdev
,
2985 struct ethtool_cmd
*cmd
)
2987 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
2989 return phy_ethtool_gset(adapter
->phydev
, cmd
);
2992 static int et131x_set_settings(struct net_device
*netdev
,
2993 struct ethtool_cmd
*cmd
)
2995 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
2997 return phy_ethtool_sset(adapter
->phydev
, cmd
);
3000 static int et131x_get_regs_len(struct net_device
*netdev
)
3002 #define ET131X_REGS_LEN 256
3003 return ET131X_REGS_LEN
* sizeof(u32
);
3006 static void et131x_get_regs(struct net_device
*netdev
,
3007 struct ethtool_regs
*regs
, void *regs_data
)
3009 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3010 struct address_map __iomem
*aregs
= adapter
->regs
;
3011 u32
*regs_buff
= regs_data
;
3015 memset(regs_data
, 0, et131x_get_regs_len(netdev
));
3017 regs
->version
= (1 << 24) | (adapter
->pdev
->revision
<< 16) |
3018 adapter
->pdev
->device
;
3021 et131x_mii_read(adapter
, MII_BMCR
, &tmp
);
3022 regs_buff
[num
++] = tmp
;
3023 et131x_mii_read(adapter
, MII_BMSR
, &tmp
);
3024 regs_buff
[num
++] = tmp
;
3025 et131x_mii_read(adapter
, MII_PHYSID1
, &tmp
);
3026 regs_buff
[num
++] = tmp
;
3027 et131x_mii_read(adapter
, MII_PHYSID2
, &tmp
);
3028 regs_buff
[num
++] = tmp
;
3029 et131x_mii_read(adapter
, MII_ADVERTISE
, &tmp
);
3030 regs_buff
[num
++] = tmp
;
3031 et131x_mii_read(adapter
, MII_LPA
, &tmp
);
3032 regs_buff
[num
++] = tmp
;
3033 et131x_mii_read(adapter
, MII_EXPANSION
, &tmp
);
3034 regs_buff
[num
++] = tmp
;
3035 /* Autoneg next page transmit reg */
3036 et131x_mii_read(adapter
, 0x07, &tmp
);
3037 regs_buff
[num
++] = tmp
;
3038 /* Link partner next page reg */
3039 et131x_mii_read(adapter
, 0x08, &tmp
);
3040 regs_buff
[num
++] = tmp
;
3041 et131x_mii_read(adapter
, MII_CTRL1000
, &tmp
);
3042 regs_buff
[num
++] = tmp
;
3043 et131x_mii_read(adapter
, MII_STAT1000
, &tmp
);
3044 regs_buff
[num
++] = tmp
;
3045 et131x_mii_read(adapter
, 0x0b, &tmp
);
3046 regs_buff
[num
++] = tmp
;
3047 et131x_mii_read(adapter
, 0x0c, &tmp
);
3048 regs_buff
[num
++] = tmp
;
3049 et131x_mii_read(adapter
, MII_MMD_CTRL
, &tmp
);
3050 regs_buff
[num
++] = tmp
;
3051 et131x_mii_read(adapter
, MII_MMD_DATA
, &tmp
);
3052 regs_buff
[num
++] = tmp
;
3053 et131x_mii_read(adapter
, MII_ESTATUS
, &tmp
);
3054 regs_buff
[num
++] = tmp
;
3056 et131x_mii_read(adapter
, PHY_INDEX_REG
, &tmp
);
3057 regs_buff
[num
++] = tmp
;
3058 et131x_mii_read(adapter
, PHY_DATA_REG
, &tmp
);
3059 regs_buff
[num
++] = tmp
;
3060 et131x_mii_read(adapter
, PHY_MPHY_CONTROL_REG
, &tmp
);
3061 regs_buff
[num
++] = tmp
;
3062 et131x_mii_read(adapter
, PHY_LOOPBACK_CONTROL
, &tmp
);
3063 regs_buff
[num
++] = tmp
;
3064 et131x_mii_read(adapter
, PHY_LOOPBACK_CONTROL
+ 1, &tmp
);
3065 regs_buff
[num
++] = tmp
;
3067 et131x_mii_read(adapter
, PHY_REGISTER_MGMT_CONTROL
, &tmp
);
3068 regs_buff
[num
++] = tmp
;
3069 et131x_mii_read(adapter
, PHY_CONFIG
, &tmp
);
3070 regs_buff
[num
++] = tmp
;
3071 et131x_mii_read(adapter
, PHY_PHY_CONTROL
, &tmp
);
3072 regs_buff
[num
++] = tmp
;
3073 et131x_mii_read(adapter
, PHY_INTERRUPT_MASK
, &tmp
);
3074 regs_buff
[num
++] = tmp
;
3075 et131x_mii_read(adapter
, PHY_INTERRUPT_STATUS
, &tmp
);
3076 regs_buff
[num
++] = tmp
;
3077 et131x_mii_read(adapter
, PHY_PHY_STATUS
, &tmp
);
3078 regs_buff
[num
++] = tmp
;
3079 et131x_mii_read(adapter
, PHY_LED_1
, &tmp
);
3080 regs_buff
[num
++] = tmp
;
3081 et131x_mii_read(adapter
, PHY_LED_2
, &tmp
);
3082 regs_buff
[num
++] = tmp
;
3085 regs_buff
[num
++] = readl(&aregs
->global
.txq_start_addr
);
3086 regs_buff
[num
++] = readl(&aregs
->global
.txq_end_addr
);
3087 regs_buff
[num
++] = readl(&aregs
->global
.rxq_start_addr
);
3088 regs_buff
[num
++] = readl(&aregs
->global
.rxq_end_addr
);
3089 regs_buff
[num
++] = readl(&aregs
->global
.pm_csr
);
3090 regs_buff
[num
++] = adapter
->stats
.interrupt_status
;
3091 regs_buff
[num
++] = readl(&aregs
->global
.int_mask
);
3092 regs_buff
[num
++] = readl(&aregs
->global
.int_alias_clr_en
);
3093 regs_buff
[num
++] = readl(&aregs
->global
.int_status_alias
);
3094 regs_buff
[num
++] = readl(&aregs
->global
.sw_reset
);
3095 regs_buff
[num
++] = readl(&aregs
->global
.slv_timer
);
3096 regs_buff
[num
++] = readl(&aregs
->global
.msi_config
);
3097 regs_buff
[num
++] = readl(&aregs
->global
.loopback
);
3098 regs_buff
[num
++] = readl(&aregs
->global
.watchdog_timer
);
3101 regs_buff
[num
++] = readl(&aregs
->txdma
.csr
);
3102 regs_buff
[num
++] = readl(&aregs
->txdma
.pr_base_hi
);
3103 regs_buff
[num
++] = readl(&aregs
->txdma
.pr_base_lo
);
3104 regs_buff
[num
++] = readl(&aregs
->txdma
.pr_num_des
);
3105 regs_buff
[num
++] = readl(&aregs
->txdma
.txq_wr_addr
);
3106 regs_buff
[num
++] = readl(&aregs
->txdma
.txq_wr_addr_ext
);
3107 regs_buff
[num
++] = readl(&aregs
->txdma
.txq_rd_addr
);
3108 regs_buff
[num
++] = readl(&aregs
->txdma
.dma_wb_base_hi
);
3109 regs_buff
[num
++] = readl(&aregs
->txdma
.dma_wb_base_lo
);
3110 regs_buff
[num
++] = readl(&aregs
->txdma
.service_request
);
3111 regs_buff
[num
++] = readl(&aregs
->txdma
.service_complete
);
3112 regs_buff
[num
++] = readl(&aregs
->txdma
.cache_rd_index
);
3113 regs_buff
[num
++] = readl(&aregs
->txdma
.cache_wr_index
);
3114 regs_buff
[num
++] = readl(&aregs
->txdma
.tx_dma_error
);
3115 regs_buff
[num
++] = readl(&aregs
->txdma
.desc_abort_cnt
);
3116 regs_buff
[num
++] = readl(&aregs
->txdma
.payload_abort_cnt
);
3117 regs_buff
[num
++] = readl(&aregs
->txdma
.writeback_abort_cnt
);
3118 regs_buff
[num
++] = readl(&aregs
->txdma
.desc_timeout_cnt
);
3119 regs_buff
[num
++] = readl(&aregs
->txdma
.payload_timeout_cnt
);
3120 regs_buff
[num
++] = readl(&aregs
->txdma
.writeback_timeout_cnt
);
3121 regs_buff
[num
++] = readl(&aregs
->txdma
.desc_error_cnt
);
3122 regs_buff
[num
++] = readl(&aregs
->txdma
.payload_error_cnt
);
3123 regs_buff
[num
++] = readl(&aregs
->txdma
.writeback_error_cnt
);
3124 regs_buff
[num
++] = readl(&aregs
->txdma
.dropped_tlp_cnt
);
3125 regs_buff
[num
++] = readl(&aregs
->txdma
.new_service_complete
);
3126 regs_buff
[num
++] = readl(&aregs
->txdma
.ethernet_packet_cnt
);
3129 regs_buff
[num
++] = readl(&aregs
->rxdma
.csr
);
3130 regs_buff
[num
++] = readl(&aregs
->rxdma
.dma_wb_base_hi
);
3131 regs_buff
[num
++] = readl(&aregs
->rxdma
.dma_wb_base_lo
);
3132 regs_buff
[num
++] = readl(&aregs
->rxdma
.num_pkt_done
);
3133 regs_buff
[num
++] = readl(&aregs
->rxdma
.max_pkt_time
);
3134 regs_buff
[num
++] = readl(&aregs
->rxdma
.rxq_rd_addr
);
3135 regs_buff
[num
++] = readl(&aregs
->rxdma
.rxq_rd_addr_ext
);
3136 regs_buff
[num
++] = readl(&aregs
->rxdma
.rxq_wr_addr
);
3137 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_base_hi
);
3138 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_base_lo
);
3139 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_num_des
);
3140 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_avail_offset
);
3141 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_full_offset
);
3142 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_access_index
);
3143 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_min_des
);
3144 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_base_lo
);
3145 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_base_hi
);
3146 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_num_des
);
3147 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_avail_offset
);
3148 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_full_offset
);
3149 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_rd_index
);
3150 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_min_des
);
3151 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_base_lo
);
3152 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_base_hi
);
3153 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_num_des
);
3154 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_avail_offset
);
3155 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_full_offset
);
3156 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_rd_index
);
3157 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_min_des
);
3160 static void et131x_get_drvinfo(struct net_device
*netdev
,
3161 struct ethtool_drvinfo
*info
)
3163 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3165 strlcpy(info
->driver
, DRIVER_NAME
, sizeof(info
->driver
));
3166 strlcpy(info
->version
, DRIVER_VERSION
, sizeof(info
->version
));
3167 strlcpy(info
->bus_info
, pci_name(adapter
->pdev
),
3168 sizeof(info
->bus_info
));
3171 static struct ethtool_ops et131x_ethtool_ops
= {
3172 .get_settings
= et131x_get_settings
,
3173 .set_settings
= et131x_set_settings
,
3174 .get_drvinfo
= et131x_get_drvinfo
,
3175 .get_regs_len
= et131x_get_regs_len
,
3176 .get_regs
= et131x_get_regs
,
3177 .get_link
= ethtool_op_get_link
,
3180 /* et131x_hwaddr_init - set up the MAC Address on the ET1310 */
3181 static void et131x_hwaddr_init(struct et131x_adapter
*adapter
)
3183 /* If have our default mac from init and no mac address from
3184 * EEPROM then we need to generate the last octet and set it on the
3187 if (is_zero_ether_addr(adapter
->rom_addr
)) {
3188 /* We need to randomly generate the last octet so we
3189 * decrease our chances of setting the mac address to
3190 * same as another one of our cards in the system
3192 get_random_bytes(&adapter
->addr
[5], 1);
3193 /* We have the default value in the register we are
3194 * working with so we need to copy the current
3195 * address into the permanent address
3197 memcpy(adapter
->rom_addr
,
3198 adapter
->addr
, ETH_ALEN
);
3200 /* We do not have an override address, so set the
3201 * current address to the permanent address and add
3204 memcpy(adapter
->addr
,
3205 adapter
->rom_addr
, ETH_ALEN
);
3209 /* et131x_pci_init - initial PCI setup
3211 * Perform the initial setup of PCI registers and if possible initialise
3212 * the MAC address. At this point the I/O registers have yet to be mapped
3214 static int et131x_pci_init(struct et131x_adapter
*adapter
,
3215 struct pci_dev
*pdev
)
3220 rc
= et131x_init_eeprom(adapter
);
3224 if (!pci_is_pcie(pdev
)) {
3225 dev_err(&pdev
->dev
, "Missing PCIe capabilities\n");
3229 /* Let's set up the PORT LOGIC Register. */
3231 /* Program the Ack/Nak latency and replay timers */
3232 max_payload
= pdev
->pcie_mpss
;
3234 if (max_payload
< 2) {
3235 static const u16 acknak
[2] = { 0x76, 0xD0 };
3236 static const u16 replay
[2] = { 0x1E0, 0x2ED };
3238 if (pci_write_config_word(pdev
, ET1310_PCI_ACK_NACK
,
3239 acknak
[max_payload
])) {
3241 "Could not write PCI config space for ACK/NAK\n");
3244 if (pci_write_config_word(pdev
, ET1310_PCI_REPLAY
,
3245 replay
[max_payload
])) {
3247 "Could not write PCI config space for Replay Timer\n");
3252 /* l0s and l1 latency timers. We are using default values.
3253 * Representing 001 for L0s and 010 for L1
3255 if (pci_write_config_byte(pdev
, ET1310_PCI_L0L1LATENCY
, 0x11)) {
3257 "Could not write PCI config space for Latency Timers\n");
3261 /* Change the max read size to 2k */
3262 if (pcie_set_readrq(pdev
, 2048)) {
3264 "Couldn't change PCI config space for Max read size\n");
3268 /* Get MAC address from config space if an eeprom exists, otherwise
3269 * the MAC address there will not be valid
3271 if (!adapter
->has_eeprom
) {
3272 et131x_hwaddr_init(adapter
);
3276 for (i
= 0; i
< ETH_ALEN
; i
++) {
3277 if (pci_read_config_byte(pdev
, ET1310_PCI_MAC_ADDRESS
+ i
,
3278 adapter
->rom_addr
+ i
)) {
3279 dev_err(&pdev
->dev
, "Could not read PCI config space for MAC address\n");
3283 ether_addr_copy(adapter
->addr
, adapter
->rom_addr
);
3291 /* et131x_error_timer_handler
3292 * @data: timer-specific variable; here a pointer to our adapter structure
3294 * The routine called when the error timer expires, to track the number of
3297 static void et131x_error_timer_handler(unsigned long data
)
3299 struct et131x_adapter
*adapter
= (struct et131x_adapter
*)data
;
3300 struct phy_device
*phydev
= adapter
->phydev
;
3302 if (et1310_in_phy_coma(adapter
)) {
3303 /* Bring the device immediately out of coma, to
3304 * prevent it from sleeping indefinitely, this
3305 * mechanism could be improved!
3307 et1310_disable_phy_coma(adapter
);
3308 adapter
->boot_coma
= 20;
3310 et1310_update_macstat_host_counters(adapter
);
3313 if (!phydev
->link
&& adapter
->boot_coma
< 11)
3314 adapter
->boot_coma
++;
3316 if (adapter
->boot_coma
== 10) {
3317 if (!phydev
->link
) {
3318 if (!et1310_in_phy_coma(adapter
)) {
3319 /* NOTE - This was originally a 'sync with
3320 * interrupt'. How to do that under Linux?
3322 et131x_enable_interrupts(adapter
);
3323 et1310_enable_phy_coma(adapter
);
3328 /* This is a periodic timer, so reschedule */
3329 mod_timer(&adapter
->error_timer
, jiffies
+ TX_ERROR_PERIOD
* HZ
/ 1000);
3332 /* et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx */
3333 static void et131x_adapter_memory_free(struct et131x_adapter
*adapter
)
3335 et131x_tx_dma_memory_free(adapter
);
3336 et131x_rx_dma_memory_free(adapter
);
3339 /* et131x_adapter_memory_alloc
3340 * Allocate all the memory blocks for send, receive and others.
3342 static int et131x_adapter_memory_alloc(struct et131x_adapter
*adapter
)
3346 /* Allocate memory for the Tx Ring */
3347 status
= et131x_tx_dma_memory_alloc(adapter
);
3349 dev_err(&adapter
->pdev
->dev
,
3350 "et131x_tx_dma_memory_alloc FAILED\n");
3351 et131x_tx_dma_memory_free(adapter
);
3354 /* Receive buffer memory allocation */
3355 status
= et131x_rx_dma_memory_alloc(adapter
);
3357 dev_err(&adapter
->pdev
->dev
,
3358 "et131x_rx_dma_memory_alloc FAILED\n");
3359 et131x_adapter_memory_free(adapter
);
3363 /* Init receive data structures */
3364 status
= et131x_init_recv(adapter
);
3366 dev_err(&adapter
->pdev
->dev
, "et131x_init_recv FAILED\n");
3367 et131x_adapter_memory_free(adapter
);
3372 static void et131x_adjust_link(struct net_device
*netdev
)
3374 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3375 struct phy_device
*phydev
= adapter
->phydev
;
3379 if (phydev
->link
== adapter
->link
)
3382 /* Check to see if we are in coma mode and if
3383 * so, disable it because we will not be able
3384 * to read PHY values until we are out.
3386 if (et1310_in_phy_coma(adapter
))
3387 et1310_disable_phy_coma(adapter
);
3389 adapter
->link
= phydev
->link
;
3390 phy_print_status(phydev
);
3393 adapter
->boot_coma
= 20;
3394 if (phydev
->speed
== SPEED_10
) {
3397 et131x_mii_read(adapter
, PHY_MPHY_CONTROL_REG
,
3399 et131x_mii_write(adapter
, phydev
->addr
,
3400 PHY_MPHY_CONTROL_REG
, register18
| 0x4);
3401 et131x_mii_write(adapter
, phydev
->addr
, PHY_INDEX_REG
,
3402 register18
| 0x8402);
3403 et131x_mii_write(adapter
, phydev
->addr
, PHY_DATA_REG
,
3405 et131x_mii_write(adapter
, phydev
->addr
,
3406 PHY_MPHY_CONTROL_REG
, register18
);
3409 et1310_config_flow_control(adapter
);
3411 if (phydev
->speed
== SPEED_1000
&&
3412 adapter
->registry_jumbo_packet
> 2048) {
3415 et131x_mii_read(adapter
, PHY_CONFIG
, ®
);
3416 reg
&= ~ET_PHY_CONFIG_TX_FIFO_DEPTH
;
3417 reg
|= ET_PHY_CONFIG_FIFO_DEPTH_32
;
3418 et131x_mii_write(adapter
, phydev
->addr
, PHY_CONFIG
,
3422 et131x_set_rx_dma_timer(adapter
);
3423 et1310_config_mac_regs2(adapter
);
3425 adapter
->boot_coma
= 0;
3427 if (phydev
->speed
== SPEED_10
) {
3430 et131x_mii_read(adapter
, PHY_MPHY_CONTROL_REG
,
3432 et131x_mii_write(adapter
, phydev
->addr
,
3433 PHY_MPHY_CONTROL_REG
, register18
| 0x4);
3434 et131x_mii_write(adapter
, phydev
->addr
,
3435 PHY_INDEX_REG
, register18
| 0x8402);
3436 et131x_mii_write(adapter
, phydev
->addr
,
3437 PHY_DATA_REG
, register18
| 511);
3438 et131x_mii_write(adapter
, phydev
->addr
,
3439 PHY_MPHY_CONTROL_REG
, register18
);
3442 /* Free the packets being actively sent & stopped */
3443 et131x_free_busy_send_packets(adapter
);
3445 /* Re-initialize the send structures */
3446 et131x_init_send(adapter
);
3448 /* Bring the device back to the state it was during
3449 * init prior to autonegotiation being complete. This
3450 * way, when we get the auto-neg complete interrupt,
3451 * we can complete init by calling config_mac_regs2.
3453 et131x_soft_reset(adapter
);
3455 /* Setup ET1310 as per the documentation */
3456 et131x_adapter_setup(adapter
);
3458 /* perform reset of tx/rx */
3459 et131x_disable_txrx(netdev
);
3460 et131x_enable_txrx(netdev
);
3464 static int et131x_mii_probe(struct net_device
*netdev
)
3466 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3467 struct phy_device
*phydev
= NULL
;
3469 phydev
= phy_find_first(adapter
->mii_bus
);
3471 dev_err(&adapter
->pdev
->dev
, "no PHY found\n");
3475 phydev
= phy_connect(netdev
, dev_name(&phydev
->dev
),
3476 &et131x_adjust_link
, PHY_INTERFACE_MODE_MII
);
3478 if (IS_ERR(phydev
)) {
3479 dev_err(&adapter
->pdev
->dev
, "Could not attach to PHY\n");
3480 return PTR_ERR(phydev
);
3483 phydev
->supported
&= (SUPPORTED_10baseT_Half
|
3484 SUPPORTED_10baseT_Full
|
3485 SUPPORTED_100baseT_Half
|
3486 SUPPORTED_100baseT_Full
|
3491 if (adapter
->pdev
->device
!= ET131X_PCI_DEVICE_ID_FAST
)
3492 phydev
->supported
|= SUPPORTED_1000baseT_Half
|
3493 SUPPORTED_1000baseT_Full
;
3495 phydev
->advertising
= phydev
->supported
;
3496 phydev
->autoneg
= AUTONEG_ENABLE
;
3497 adapter
->phydev
= phydev
;
3499 dev_info(&adapter
->pdev
->dev
,
3500 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3501 phydev
->drv
->name
, dev_name(&phydev
->dev
));
3506 /* et131x_adapter_init
3508 * Initialize the data structures for the et131x_adapter object and link
3509 * them together with the platform provided device structures.
3511 static struct et131x_adapter
*et131x_adapter_init(struct net_device
*netdev
,
3512 struct pci_dev
*pdev
)
3514 static const u8 default_mac
[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
3516 struct et131x_adapter
*adapter
;
3518 /* Allocate private adapter struct and copy in relevant information */
3519 adapter
= netdev_priv(netdev
);
3520 adapter
->pdev
= pci_dev_get(pdev
);
3521 adapter
->netdev
= netdev
;
3523 /* Initialize spinlocks here */
3524 spin_lock_init(&adapter
->tcb_send_qlock
);
3525 spin_lock_init(&adapter
->tcb_ready_qlock
);
3526 spin_lock_init(&adapter
->rcv_lock
);
3528 adapter
->registry_jumbo_packet
= 1514; /* 1514-9216 */
3530 /* Set the MAC address to a default */
3531 ether_addr_copy(adapter
->addr
, default_mac
);
3536 /* et131x_pci_remove
3538 * Registered in the pci_driver structure, this function is called when the
3539 * PCI subsystem detects that a PCI device which matches the information
3540 * contained in the pci_device_id table has been removed.
3542 static void et131x_pci_remove(struct pci_dev
*pdev
)
3544 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3545 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3547 unregister_netdev(netdev
);
3548 netif_napi_del(&adapter
->napi
);
3549 phy_disconnect(adapter
->phydev
);
3550 mdiobus_unregister(adapter
->mii_bus
);
3551 kfree(adapter
->mii_bus
->irq
);
3552 mdiobus_free(adapter
->mii_bus
);
3554 et131x_adapter_memory_free(adapter
);
3555 iounmap(adapter
->regs
);
3558 free_netdev(netdev
);
3559 pci_release_regions(pdev
);
3560 pci_disable_device(pdev
);
3563 /* et131x_up - Bring up a device for use. */
3564 static void et131x_up(struct net_device
*netdev
)
3566 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3568 et131x_enable_txrx(netdev
);
3569 phy_start(adapter
->phydev
);
3572 /* et131x_down - Bring down the device */
3573 static void et131x_down(struct net_device
*netdev
)
3575 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3577 /* Save the timestamp for the TX watchdog, prevent a timeout */
3578 netdev
->trans_start
= jiffies
;
3580 phy_stop(adapter
->phydev
);
3581 et131x_disable_txrx(netdev
);
3584 #ifdef CONFIG_PM_SLEEP
3585 static int et131x_suspend(struct device
*dev
)
3587 struct pci_dev
*pdev
= to_pci_dev(dev
);
3588 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3590 if (netif_running(netdev
)) {
3591 netif_device_detach(netdev
);
3592 et131x_down(netdev
);
3593 pci_save_state(pdev
);
3599 static int et131x_resume(struct device
*dev
)
3601 struct pci_dev
*pdev
= to_pci_dev(dev
);
3602 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3604 if (netif_running(netdev
)) {
3605 pci_restore_state(pdev
);
3607 netif_device_attach(netdev
);
3613 static SIMPLE_DEV_PM_OPS(et131x_pm_ops
, et131x_suspend
, et131x_resume
);
3614 #define ET131X_PM_OPS (&et131x_pm_ops)
3616 #define ET131X_PM_OPS NULL
3619 /* et131x_isr - The Interrupt Service Routine for the driver.
3620 * @irq: the IRQ on which the interrupt was received.
3621 * @dev_id: device-specific info (here a pointer to a net_device struct)
3623 * Returns a value indicating if the interrupt was handled.
3625 static irqreturn_t
et131x_isr(int irq
, void *dev_id
)
3627 bool handled
= true;
3628 bool enable_interrupts
= true;
3629 struct net_device
*netdev
= (struct net_device
*)dev_id
;
3630 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3631 struct address_map __iomem
*iomem
= adapter
->regs
;
3632 struct rx_ring
*rx_ring
= &adapter
->rx_ring
;
3633 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
3636 if (!netif_device_present(netdev
)) {
3638 enable_interrupts
= false;
3642 /* If the adapter is in low power state, then it should not
3643 * recognize any interrupt
3646 /* Disable Device Interrupts */
3647 et131x_disable_interrupts(adapter
);
3649 /* Get a copy of the value in the interrupt status register
3650 * so we can process the interrupting section
3652 status
= readl(&adapter
->regs
->global
.int_status
);
3654 if (adapter
->flowcontrol
== FLOW_TXONLY
||
3655 adapter
->flowcontrol
== FLOW_BOTH
) {
3656 status
&= ~INT_MASK_ENABLE
;
3658 status
&= ~INT_MASK_ENABLE_NO_FLOW
;
3661 /* Make sure this is our interrupt */
3664 et131x_enable_interrupts(adapter
);
3668 /* This is our interrupt, so process accordingly */
3669 if (status
& ET_INTR_WATCHDOG
) {
3670 struct tcb
*tcb
= tx_ring
->send_head
;
3673 if (++tcb
->stale
> 1)
3674 status
|= ET_INTR_TXDMA_ISR
;
3676 if (rx_ring
->unfinished_receives
)
3677 status
|= ET_INTR_RXDMA_XFR_DONE
;
3678 else if (tcb
== NULL
)
3679 writel(0, &adapter
->regs
->global
.watchdog_timer
);
3681 status
&= ~ET_INTR_WATCHDOG
;
3684 if (status
& (ET_INTR_RXDMA_XFR_DONE
| ET_INTR_TXDMA_ISR
)) {
3685 enable_interrupts
= false;
3686 napi_schedule(&adapter
->napi
);
3689 status
&= ~(ET_INTR_TXDMA_ISR
| ET_INTR_RXDMA_XFR_DONE
);
3694 /* Handle the TXDMA Error interrupt */
3695 if (status
& ET_INTR_TXDMA_ERR
) {
3696 /* Following read also clears the register (COR) */
3697 u32 txdma_err
= readl(&iomem
->txdma
.tx_dma_error
);
3699 dev_warn(&adapter
->pdev
->dev
,
3700 "TXDMA_ERR interrupt, error = %d\n",
3704 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
3705 if (status
& (ET_INTR_RXDMA_FB_R0_LOW
| ET_INTR_RXDMA_FB_R1_LOW
)) {
3706 /* This indicates the number of unused buffers in RXDMA free
3707 * buffer ring 0 is <= the limit you programmed. Free buffer
3708 * resources need to be returned. Free buffers are consumed as
3709 * packets are passed from the network to the host. The host
3710 * becomes aware of the packets from the contents of the packet
3711 * status ring. This ring is queried when the packet done
3712 * interrupt occurs. Packets are then passed to the OS. When
3713 * the OS is done with the packets the resources can be
3714 * returned to the ET1310 for re-use. This interrupt is one
3715 * method of returning resources.
3718 /* If the user has flow control on, then we will
3719 * send a pause packet, otherwise just exit
3721 if (adapter
->flowcontrol
== FLOW_TXONLY
||
3722 adapter
->flowcontrol
== FLOW_BOTH
) {
3725 /* Tell the device to send a pause packet via the back
3726 * pressure register (bp req and bp xon/xoff)
3728 pm_csr
= readl(&iomem
->global
.pm_csr
);
3729 if (!et1310_in_phy_coma(adapter
))
3730 writel(3, &iomem
->txmac
.bp_ctrl
);
3734 /* Handle Packet Status Ring Low Interrupt */
3735 if (status
& ET_INTR_RXDMA_STAT_LOW
) {
3736 /* Same idea as with the two Free Buffer Rings. Packets going
3737 * from the network to the host each consume a free buffer
3738 * resource and a packet status resource. These resources are
3739 * passed to the OS. When the OS is done with the resources,
3740 * they need to be returned to the ET1310. This is one method
3741 * of returning the resources.
3745 /* Handle RXDMA Error Interrupt */
3746 if (status
& ET_INTR_RXDMA_ERR
) {
3747 /* The rxdma_error interrupt is sent when a time-out on a
3748 * request issued by the JAGCore has occurred or a completion is
3749 * returned with an un-successful status. In both cases the
3750 * request is considered complete. The JAGCore will
3751 * automatically re-try the request in question. Normally
3752 * information on events like these are sent to the host using
3753 * the "Advanced Error Reporting" capability. This interrupt is
3754 * another way of getting similar information. The only thing
3755 * required is to clear the interrupt by reading the ISR in the
3756 * global resources. The JAGCore will do a re-try on the
3757 * request. Normally you should never see this interrupt. If
3758 * you start to see this interrupt occurring frequently then
3759 * something bad has occurred. A reset might be the thing to do.
3763 dev_warn(&adapter
->pdev
->dev
,
3764 "RxDMA_ERR interrupt, error %x\n",
3765 readl(&iomem
->txmac
.tx_test
));
3768 /* Handle the Wake on LAN Event */
3769 if (status
& ET_INTR_WOL
) {
3770 /* This is a secondary interrupt for wake on LAN. The driver
3771 * should never see this, if it does, something serious is
3772 * wrong. We will TRAP the message when we are in DBG mode,
3773 * otherwise we will ignore it.
3775 dev_err(&adapter
->pdev
->dev
, "WAKE_ON_LAN interrupt\n");
3778 /* Let's move on to the TxMac */
3779 if (status
& ET_INTR_TXMAC
) {
3780 u32 err
= readl(&iomem
->txmac
.err
);
3782 /* When any of the errors occur and TXMAC generates an
3783 * interrupt to report these errors, it usually means that
3784 * TXMAC has detected an error in the data stream retrieved
3785 * from the on-chip Tx Q. All of these errors are catastrophic
3786 * and TXMAC won't be able to recover data when these errors
3787 * occur. In a nutshell, the whole Tx path will have to be reset
3788 * and re-configured afterwards.
3790 dev_warn(&adapter
->pdev
->dev
,
3791 "TXMAC interrupt, error 0x%08x\n",
3794 /* If we are debugging, we want to see this error, otherwise we
3795 * just want the device to be reset and continue
3799 /* Handle RXMAC Interrupt */
3800 if (status
& ET_INTR_RXMAC
) {
3801 /* These interrupts are catastrophic to the device, what we need
3802 * to do is disable the interrupts and set the flag to cause us
3803 * to reset so we can solve this issue.
3805 /* MP_SET_FLAG( adapter, FMP_ADAPTER_HARDWARE_ERROR); */
3807 dev_warn(&adapter
->pdev
->dev
,
3808 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
3809 readl(&iomem
->rxmac
.err_reg
));
3811 dev_warn(&adapter
->pdev
->dev
,
3812 "Enable 0x%08x, Diag 0x%08x\n",
3813 readl(&iomem
->rxmac
.ctrl
),
3814 readl(&iomem
->rxmac
.rxq_diag
));
3816 /* If we are debugging, we want to see this error, otherwise we
3817 * just want the device to be reset and continue
3821 /* Handle MAC_STAT Interrupt */
3822 if (status
& ET_INTR_MAC_STAT
) {
3823 /* This means at least one of the un-masked counters in the
3824 * MAC_STAT block has rolled over. Use this to maintain the top,
3825 * software managed bits of the counter(s).
3827 et1310_handle_macstat_interrupt(adapter
);
3830 /* Handle SLV Timeout Interrupt */
3831 if (status
& ET_INTR_SLV_TIMEOUT
) {
3832 /* This means a timeout has occurred on a read or write request
3833 * to one of the JAGCore registers. The Global Resources block
3834 * has terminated the request and on a read request, returned a
3835 * "fake" value. The most likely reasons are: Bad Address or the
3836 * addressed module is in a power-down state and can't respond.
3841 if (enable_interrupts
)
3842 et131x_enable_interrupts(adapter
);
3844 return IRQ_RETVAL(handled
);
3847 static int et131x_poll(struct napi_struct
*napi
, int budget
)
3849 struct et131x_adapter
*adapter
=
3850 container_of(napi
, struct et131x_adapter
, napi
);
3851 int work_done
= et131x_handle_recv_pkts(adapter
, budget
);
3853 et131x_handle_send_pkts(adapter
);
3855 if (work_done
< budget
) {
3856 napi_complete(&adapter
->napi
);
3857 et131x_enable_interrupts(adapter
);
3863 /* et131x_stats - Return the current device statistics */
3864 static struct net_device_stats
*et131x_stats(struct net_device
*netdev
)
3866 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3867 struct net_device_stats
*stats
= &adapter
->netdev
->stats
;
3868 struct ce_stats
*devstat
= &adapter
->stats
;
3870 stats
->rx_errors
= devstat
->rx_length_errs
+
3871 devstat
->rx_align_errs
+
3872 devstat
->rx_crc_errs
+
3873 devstat
->rx_code_violations
+
3874 devstat
->rx_other_errs
;
3875 stats
->tx_errors
= devstat
->tx_max_pkt_errs
;
3876 stats
->multicast
= devstat
->multicast_pkts_rcvd
;
3877 stats
->collisions
= devstat
->tx_collisions
;
3879 stats
->rx_length_errors
= devstat
->rx_length_errs
;
3880 stats
->rx_over_errors
= devstat
->rx_overflows
;
3881 stats
->rx_crc_errors
= devstat
->rx_crc_errs
;
3882 stats
->rx_dropped
= devstat
->rcvd_pkts_dropped
;
3884 /* NOTE: Not used, can't find analogous statistics */
3885 /* stats->rx_frame_errors = devstat->; */
3886 /* stats->rx_fifo_errors = devstat->; */
3887 /* stats->rx_missed_errors = devstat->; */
3889 /* stats->tx_aborted_errors = devstat->; */
3890 /* stats->tx_carrier_errors = devstat->; */
3891 /* stats->tx_fifo_errors = devstat->; */
3892 /* stats->tx_heartbeat_errors = devstat->; */
3893 /* stats->tx_window_errors = devstat->; */
3897 /* et131x_open - Open the device for use. */
3898 static int et131x_open(struct net_device
*netdev
)
3900 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3901 struct pci_dev
*pdev
= adapter
->pdev
;
3902 unsigned int irq
= pdev
->irq
;
3905 /* Start the timer to track NIC errors */
3906 init_timer(&adapter
->error_timer
);
3907 adapter
->error_timer
.expires
= jiffies
+ TX_ERROR_PERIOD
* HZ
/ 1000;
3908 adapter
->error_timer
.function
= et131x_error_timer_handler
;
3909 adapter
->error_timer
.data
= (unsigned long)adapter
;
3910 add_timer(&adapter
->error_timer
);
3912 result
= request_irq(irq
, et131x_isr
,
3913 IRQF_SHARED
, netdev
->name
, netdev
);
3915 dev_err(&pdev
->dev
, "could not register IRQ %d\n", irq
);
3919 adapter
->flags
|= FMP_ADAPTER_INTERRUPT_IN_USE
;
3921 napi_enable(&adapter
->napi
);
3928 /* et131x_close - Close the device */
3929 static int et131x_close(struct net_device
*netdev
)
3931 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3933 et131x_down(netdev
);
3934 napi_disable(&adapter
->napi
);
3936 adapter
->flags
&= ~FMP_ADAPTER_INTERRUPT_IN_USE
;
3937 free_irq(adapter
->pdev
->irq
, netdev
);
3939 /* Stop the error timer */
3940 return del_timer_sync(&adapter
->error_timer
);
3943 /* et131x_ioctl - The I/O Control handler for the driver
3944 * @netdev: device on which the control request is being made
3945 * @reqbuf: a pointer to the IOCTL request buffer
3946 * @cmd: the IOCTL command code
3948 static int et131x_ioctl(struct net_device
*netdev
, struct ifreq
*reqbuf
,
3951 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3953 if (!adapter
->phydev
)
3956 return phy_mii_ioctl(adapter
->phydev
, reqbuf
, cmd
);
3959 /* et131x_set_packet_filter - Configures the Rx Packet filtering on the device
3960 * @adapter: pointer to our private adapter structure
3962 * FIXME: lot of dups with MAC code
3964 static int et131x_set_packet_filter(struct et131x_adapter
*adapter
)
3966 int filter
= adapter
->packet_filter
;
3970 ctrl
= readl(&adapter
->regs
->rxmac
.ctrl
);
3971 pf_ctrl
= readl(&adapter
->regs
->rxmac
.pf_ctrl
);
3973 /* Default to disabled packet filtering. Enable it in the individual
3974 * case statements that require the device to filter something
3978 /* Set us to be in promiscuous mode so we receive everything, this
3979 * is also true when we get a packet filter of 0
3981 if ((filter
& ET131X_PACKET_TYPE_PROMISCUOUS
) || filter
== 0)
3982 pf_ctrl
&= ~7; /* Clear filter bits */
3984 /* Set us up with Multicast packet filtering. Three cases are
3985 * possible - (1) we have a multi-cast list, (2) we receive ALL
3986 * multicast entries or (3) we receive none.
3988 if (filter
& ET131X_PACKET_TYPE_ALL_MULTICAST
)
3989 pf_ctrl
&= ~2; /* Multicast filter bit */
3991 et1310_setup_device_for_multicast(adapter
);
3996 /* Set us up with Unicast packet filtering */
3997 if (filter
& ET131X_PACKET_TYPE_DIRECTED
) {
3998 et1310_setup_device_for_unicast(adapter
);
4003 /* Set us up with Broadcast packet filtering */
4004 if (filter
& ET131X_PACKET_TYPE_BROADCAST
) {
4005 pf_ctrl
|= 1; /* Broadcast filter bit */
4011 /* Setup the receive mac configuration registers - Packet
4012 * Filter control + the enable / disable for packet filter
4013 * in the control reg.
4015 writel(pf_ctrl
, &adapter
->regs
->rxmac
.pf_ctrl
);
4016 writel(ctrl
, &adapter
->regs
->rxmac
.ctrl
);
4021 /* et131x_multicast - The handler to configure multicasting on the interface */
4022 static void et131x_multicast(struct net_device
*netdev
)
4024 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
4026 struct netdev_hw_addr
*ha
;
4029 /* Before we modify the platform-independent filter flags, store them
4030 * locally. This allows us to determine if anything's changed and if
4031 * we even need to bother the hardware
4033 packet_filter
= adapter
->packet_filter
;
4035 /* Clear the 'multicast' flag locally; because we only have a single
4036 * flag to check multicast, and multiple multicast addresses can be
4037 * set, this is the easiest way to determine if more than one
4038 * multicast address is being set.
4040 packet_filter
&= ~ET131X_PACKET_TYPE_MULTICAST
;
4042 /* Check the net_device flags and set the device independent flags
4045 if (netdev
->flags
& IFF_PROMISC
)
4046 adapter
->packet_filter
|= ET131X_PACKET_TYPE_PROMISCUOUS
;
4048 adapter
->packet_filter
&= ~ET131X_PACKET_TYPE_PROMISCUOUS
;
4050 if ((netdev
->flags
& IFF_ALLMULTI
) ||
4051 (netdev_mc_count(netdev
) > NIC_MAX_MCAST_LIST
))
4052 adapter
->packet_filter
|= ET131X_PACKET_TYPE_ALL_MULTICAST
;
4054 if (netdev_mc_count(netdev
) < 1) {
4055 adapter
->packet_filter
&= ~ET131X_PACKET_TYPE_ALL_MULTICAST
;
4056 adapter
->packet_filter
&= ~ET131X_PACKET_TYPE_MULTICAST
;
4058 adapter
->packet_filter
|= ET131X_PACKET_TYPE_MULTICAST
;
4061 /* Set values in the private adapter struct */
4063 netdev_for_each_mc_addr(ha
, netdev
) {
4064 if (i
== NIC_MAX_MCAST_LIST
)
4066 memcpy(adapter
->multicast_list
[i
++], ha
->addr
, ETH_ALEN
);
4068 adapter
->multicast_addr_count
= i
;
4070 /* Are the new flags different from the previous ones? If not, then no
4071 * action is required
4073 * NOTE - This block will always update the multicast_list with the
4074 * hardware, even if the addresses aren't the same.
4076 if (packet_filter
!= adapter
->packet_filter
)
4077 et131x_set_packet_filter(adapter
);
4080 /* et131x_tx - The handler to tx a packet on the device */
4081 static netdev_tx_t
et131x_tx(struct sk_buff
*skb
, struct net_device
*netdev
)
4083 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
4084 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
4086 /* stop the queue if it's getting full */
4087 if (tx_ring
->used
>= NUM_TCB
- 1 && !netif_queue_stopped(netdev
))
4088 netif_stop_queue(netdev
);
4090 /* Save the timestamp for the TX timeout watchdog */
4091 netdev
->trans_start
= jiffies
;
4093 /* TCB is not available */
4094 if (tx_ring
->used
>= NUM_TCB
)
4097 if ((adapter
->flags
& FMP_ADAPTER_FAIL_SEND_MASK
) ||
4098 !netif_carrier_ok(netdev
))
4101 if (send_packet(skb
, adapter
))
4104 return NETDEV_TX_OK
;
4107 dev_kfree_skb_any(skb
);
4108 adapter
->netdev
->stats
.tx_dropped
++;
4109 return NETDEV_TX_OK
;
4112 /* et131x_tx_timeout - Timeout handler
4114 * The handler called when a Tx request times out. The timeout period is
4115 * specified by the 'tx_timeo" element in the net_device structure (see
4116 * et131x_alloc_device() to see how this value is set).
4118 static void et131x_tx_timeout(struct net_device
*netdev
)
4120 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
4121 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
4123 unsigned long flags
;
4125 /* If the device is closed, ignore the timeout */
4126 if (~(adapter
->flags
& FMP_ADAPTER_INTERRUPT_IN_USE
))
4129 /* Any nonrecoverable hardware error?
4130 * Checks adapter->flags for any failure in phy reading
4132 if (adapter
->flags
& FMP_ADAPTER_NON_RECOVER_ERROR
)
4135 /* Hardware failure? */
4136 if (adapter
->flags
& FMP_ADAPTER_HARDWARE_ERROR
) {
4137 dev_err(&adapter
->pdev
->dev
, "hardware error - reset\n");
4141 /* Is send stuck? */
4142 spin_lock_irqsave(&adapter
->tcb_send_qlock
, flags
);
4143 tcb
= tx_ring
->send_head
;
4144 spin_unlock_irqrestore(&adapter
->tcb_send_qlock
, flags
);
4149 if (tcb
->count
> NIC_SEND_HANG_THRESHOLD
) {
4150 dev_warn(&adapter
->pdev
->dev
,
4151 "Send stuck - reset. tcb->WrIndex %x\n",
4154 adapter
->netdev
->stats
.tx_errors
++;
4156 /* perform reset of tx/rx */
4157 et131x_disable_txrx(netdev
);
4158 et131x_enable_txrx(netdev
);
4163 /* et131x_change_mtu - The handler called to change the MTU for the device */
4164 static int et131x_change_mtu(struct net_device
*netdev
, int new_mtu
)
4167 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
4169 /* Make sure the requested MTU is valid */
4170 if (new_mtu
< 64 || new_mtu
> 9216)
4173 et131x_disable_txrx(netdev
);
4175 /* Set the new MTU */
4176 netdev
->mtu
= new_mtu
;
4178 /* Free Rx DMA memory */
4179 et131x_adapter_memory_free(adapter
);
4181 /* Set the config parameter for Jumbo Packet support */
4182 adapter
->registry_jumbo_packet
= new_mtu
+ 14;
4183 et131x_soft_reset(adapter
);
4185 /* Alloc and init Rx DMA memory */
4186 result
= et131x_adapter_memory_alloc(adapter
);
4188 dev_warn(&adapter
->pdev
->dev
,
4189 "Change MTU failed; couldn't re-alloc DMA memory\n");
4193 et131x_init_send(adapter
);
4195 et131x_hwaddr_init(adapter
);
4196 memcpy(netdev
->dev_addr
, adapter
->addr
, ETH_ALEN
);
4198 /* Init the device with the new settings */
4199 et131x_adapter_setup(adapter
);
4200 et131x_enable_txrx(netdev
);
4205 static const struct net_device_ops et131x_netdev_ops
= {
4206 .ndo_open
= et131x_open
,
4207 .ndo_stop
= et131x_close
,
4208 .ndo_start_xmit
= et131x_tx
,
4209 .ndo_set_rx_mode
= et131x_multicast
,
4210 .ndo_tx_timeout
= et131x_tx_timeout
,
4211 .ndo_change_mtu
= et131x_change_mtu
,
4212 .ndo_set_mac_address
= eth_mac_addr
,
4213 .ndo_validate_addr
= eth_validate_addr
,
4214 .ndo_get_stats
= et131x_stats
,
4215 .ndo_do_ioctl
= et131x_ioctl
,
4218 /* et131x_pci_setup - Perform device initialization
4219 * @pdev: a pointer to the device's pci_dev structure
4220 * @ent: this device's entry in the pci_device_id table
4222 * Registered in the pci_driver structure, this function is called when the
4223 * PCI subsystem finds a new PCI device which matches the information
4224 * contained in the pci_device_id table. This routine is the equivalent to
4225 * a device insertion routine.
4227 static int et131x_pci_setup(struct pci_dev
*pdev
,
4228 const struct pci_device_id
*ent
)
4230 struct net_device
*netdev
;
4231 struct et131x_adapter
*adapter
;
4235 rc
= pci_enable_device(pdev
);
4237 dev_err(&pdev
->dev
, "pci_enable_device() failed\n");
4241 /* Perform some basic PCI checks */
4242 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
4243 dev_err(&pdev
->dev
, "Can't find PCI device's base address\n");
4248 rc
= pci_request_regions(pdev
, DRIVER_NAME
);
4250 dev_err(&pdev
->dev
, "Can't get PCI resources\n");
4254 pci_set_master(pdev
);
4256 /* Check the DMA addressing support of this device */
4257 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) &&
4258 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32))) {
4259 dev_err(&pdev
->dev
, "No usable DMA addressing method\n");
4261 goto err_release_res
;
4264 /* Allocate netdev and private adapter structs */
4265 netdev
= alloc_etherdev(sizeof(struct et131x_adapter
));
4267 dev_err(&pdev
->dev
, "Couldn't alloc netdev struct\n");
4269 goto err_release_res
;
4272 netdev
->watchdog_timeo
= ET131X_TX_TIMEOUT
;
4273 netdev
->netdev_ops
= &et131x_netdev_ops
;
4275 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
4276 netdev
->ethtool_ops
= &et131x_ethtool_ops
;
4278 adapter
= et131x_adapter_init(netdev
, pdev
);
4280 rc
= et131x_pci_init(adapter
, pdev
);
4284 /* Map the bus-relative registers to system virtual memory */
4285 adapter
->regs
= pci_ioremap_bar(pdev
, 0);
4286 if (!adapter
->regs
) {
4287 dev_err(&pdev
->dev
, "Cannot map device registers\n");
4292 /* If Phy COMA mode was enabled when we went down, disable it here. */
4293 writel(ET_PMCSR_INIT
, &adapter
->regs
->global
.pm_csr
);
4295 /* Issue a global reset to the et1310 */
4296 et131x_soft_reset(adapter
);
4298 /* Disable all interrupts (paranoid) */
4299 et131x_disable_interrupts(adapter
);
4301 /* Allocate DMA memory */
4302 rc
= et131x_adapter_memory_alloc(adapter
);
4304 dev_err(&pdev
->dev
, "Could not alloc adapter memory (DMA)\n");
4308 /* Init send data structures */
4309 et131x_init_send(adapter
);
4311 netif_napi_add(netdev
, &adapter
->napi
, et131x_poll
, 64);
4313 /* Copy address into the net_device struct */
4314 memcpy(netdev
->dev_addr
, adapter
->addr
, ETH_ALEN
);
4318 /* Setup the mii_bus struct */
4319 adapter
->mii_bus
= mdiobus_alloc();
4320 if (!adapter
->mii_bus
) {
4321 dev_err(&pdev
->dev
, "Alloc of mii_bus struct failed\n");
4325 adapter
->mii_bus
->name
= "et131x_eth_mii";
4326 snprintf(adapter
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%x",
4327 (adapter
->pdev
->bus
->number
<< 8) | adapter
->pdev
->devfn
);
4328 adapter
->mii_bus
->priv
= netdev
;
4329 adapter
->mii_bus
->read
= et131x_mdio_read
;
4330 adapter
->mii_bus
->write
= et131x_mdio_write
;
4331 adapter
->mii_bus
->irq
= kmalloc_array(PHY_MAX_ADDR
, sizeof(int),
4333 if (!adapter
->mii_bus
->irq
)
4336 for (ii
= 0; ii
< PHY_MAX_ADDR
; ii
++)
4337 adapter
->mii_bus
->irq
[ii
] = PHY_POLL
;
4339 rc
= mdiobus_register(adapter
->mii_bus
);
4341 dev_err(&pdev
->dev
, "failed to register MII bus\n");
4342 goto err_mdio_free_irq
;
4345 rc
= et131x_mii_probe(netdev
);
4347 dev_err(&pdev
->dev
, "failed to probe MII bus\n");
4348 goto err_mdio_unregister
;
4351 /* Setup et1310 as per the documentation */
4352 et131x_adapter_setup(adapter
);
4354 /* Init variable for counting how long we do not have link status */
4355 adapter
->boot_coma
= 0;
4356 et1310_disable_phy_coma(adapter
);
4358 /* We can enable interrupts now
4360 * NOTE - Because registration of interrupt handler is done in the
4361 * device's open(), defer enabling device interrupts to that
4365 /* Register the net_device struct with the Linux network layer */
4366 rc
= register_netdev(netdev
);
4368 dev_err(&pdev
->dev
, "register_netdev() failed\n");
4369 goto err_phy_disconnect
;
4372 /* Register the net_device struct with the PCI subsystem. Save a copy
4373 * of the PCI config space for this device now that the device has
4374 * been initialized, just in case it needs to be quickly restored.
4376 pci_set_drvdata(pdev
, netdev
);
4381 phy_disconnect(adapter
->phydev
);
4382 err_mdio_unregister
:
4383 mdiobus_unregister(adapter
->mii_bus
);
4385 kfree(adapter
->mii_bus
->irq
);
4387 mdiobus_free(adapter
->mii_bus
);
4389 et131x_adapter_memory_free(adapter
);
4391 iounmap(adapter
->regs
);
4394 free_netdev(netdev
);
4396 pci_release_regions(pdev
);
4398 pci_disable_device(pdev
);
4402 static const struct pci_device_id et131x_pci_table
[] = {
4403 { PCI_VDEVICE(ATT
, ET131X_PCI_DEVICE_ID_GIG
), 0UL},
4404 { PCI_VDEVICE(ATT
, ET131X_PCI_DEVICE_ID_FAST
), 0UL},
4407 MODULE_DEVICE_TABLE(pci
, et131x_pci_table
);
4409 static struct pci_driver et131x_driver
= {
4410 .name
= DRIVER_NAME
,
4411 .id_table
= et131x_pci_table
,
4412 .probe
= et131x_pci_setup
,
4413 .remove
= et131x_pci_remove
,
4414 .driver
.pm
= ET131X_PM_OPS
,
4417 module_pci_driver(et131x_driver
);