drivers/staging/et131x/et131x.h

   1 /*
   2  * Copyright © 2005 Agere Systems Inc.
   3  * All rights reserved.
   4  *   http://www.agere.com
   5  *
   6  * SOFTWARE LICENSE
   7  *
   8  * This software is provided subject to the following terms and conditions,
   9  * which you should read carefully before using the software.  Using this
  10  * software indicates your acceptance of these terms and conditions.  If you do
  11  * not agree with these terms and conditions, do not use the software.
  12  *
  13  * Copyright © 2005 Agere Systems Inc.
  14  * All rights reserved.
  15  *
  16  * Redistribution and use in source or binary forms, with or without
  17  * modifications, are permitted provided that the following conditions are met:
  18  *
  19  * . Redistributions of source code must retain the above copyright notice, this
  20  *    list of conditions and the following Disclaimer as comments in the code as
  21  *    well as in the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * . Redistributions in binary form must reproduce the above copyright notice,
  25  *    this list of conditions and the following Disclaimer in the documentation
  26  *    and/or other materials provided with the distribution.
  27  *
  28  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  29  *    may be used to endorse or promote products derived from this software
  30  *    without specific prior written permission.
  31  *
  32  * Disclaimer
  33  *
  34  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  35  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  36  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  37  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  38  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  39  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  40  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  41  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  42  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  43  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  44  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  45  * DAMAGE.
  46  *
  47  */
  48
  49 #define DRIVER_NAME "et131x"
  50 #define DRIVER_VERSION "v2.0"
  51
  52 /* EEPROM registers */
  53
  54 /* LBCIF Register Groups (addressed via 32-bit offsets) */
  55 #define LBCIF_DWORD0_GROUP       0xAC
  56 #define LBCIF_DWORD1_GROUP       0xB0
  57
  58 /* LBCIF Registers (addressed via 8-bit offsets) */
  59 #define LBCIF_ADDRESS_REGISTER   0xAC
  60 #define LBCIF_DATA_REGISTER      0xB0
  61 #define LBCIF_CONTROL_REGISTER   0xB1
  62 #define LBCIF_STATUS_REGISTER    0xB2
  63
  64 /* LBCIF Control Register Bits */
  65 #define LBCIF_CONTROL_SEQUENTIAL_READ   0x01
  66 #define LBCIF_CONTROL_PAGE_WRITE        0x02
  67 #define LBCIF_CONTROL_EEPROM_RELOAD     0x08
  68 #define LBCIF_CONTROL_TWO_BYTE_ADDR     0x20
  69 #define LBCIF_CONTROL_I2C_WRITE         0x40
  70 #define LBCIF_CONTROL_LBCIF_ENABLE      0x80
  71
  72 /* LBCIF Status Register Bits */
  73 #define LBCIF_STATUS_PHY_QUEUE_AVAIL    0x01
  74 #define LBCIF_STATUS_I2C_IDLE           0x02
  75 #define LBCIF_STATUS_ACK_ERROR          0x04
  76 #define LBCIF_STATUS_GENERAL_ERROR      0x08
  77 #define LBCIF_STATUS_CHECKSUM_ERROR     0x40
  78 #define LBCIF_STATUS_EEPROM_PRESENT     0x80
  79
  80 /* START OF GLOBAL REGISTER ADDRESS MAP */
  81 /*
  82  * 10bit registers
  83  *
  84  * Tx queue start address reg in global address map at address 0x0000
  85  * tx queue end address reg in global address map at address 0x0004
  86  * rx queue start address reg in global address map at address 0x0008
  87  * rx queue end address reg in global address map at address 0x000C
  88  */
  89
  90 /*
  91  * structure for power management control status reg in global address map
  92  * located at address 0x0010
  93  *      jagcore_rx_rdy  bit 9
  94  *      jagcore_tx_rdy  bit 8
  95  *      phy_lped_en     bit 7
  96  *      phy_sw_coma     bit 6
  97  *      rxclk_gate      bit 5
  98  *      txclk_gate      bit 4
  99  *      sysclk_gate     bit 3
 100  *      jagcore_rx_en   bit 2
 101  *      jagcore_tx_en   bit 1
 102  *      gigephy_en      bit 0
 103  */
 104 #define ET_PM_PHY_SW_COMA               0x40
 105 #define ET_PMCSR_INIT                   0x38
 106
 107 /*
 108  * Interrupt status reg at address 0x0018
 109  */
 110 #define ET_INTR_TXDMA_ISR       0x00000008
 111 #define ET_INTR_TXDMA_ERR       0x00000010
 112 #define ET_INTR_RXDMA_XFR_DONE  0x00000020
 113 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
 114 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
 115 #define ET_INTR_RXDMA_STAT_LOW  0x00000100
 116 #define ET_INTR_RXDMA_ERR       0x00000200
 117 #define ET_INTR_WATCHDOG        0x00004000
 118 #define ET_INTR_WOL             0x00008000
 119 #define ET_INTR_PHY             0x00010000
 120 #define ET_INTR_TXMAC           0x00020000
 121 #define ET_INTR_RXMAC           0x00040000
 122 #define ET_INTR_MAC_STAT        0x00080000
 123 #define ET_INTR_SLV_TIMEOUT     0x00100000
 124
 125 /*
 126  * Interrupt mask register at address 0x001C
 127  * Interrupt alias clear mask reg at address 0x0020
 128  * Interrupt status alias reg at address 0x0024
 129  *
 130  * Same masks as above
 131  */
 132
 133 /*
 134  * Software reset reg at address 0x0028
 135  * 0:   txdma_sw_reset
 136  * 1:   rxdma_sw_reset
 137  * 2:   txmac_sw_reset
 138  * 3:   rxmac_sw_reset
 139  * 4:   mac_sw_reset
 140  * 5:   mac_stat_sw_reset
 141  * 6:   mmc_sw_reset
 142  *31:   selfclr_disable
 143  */
 144 #define ET_RESET_ALL    0x007F
 145
 146 /*
 147  * SLV Timer reg at address 0x002C (low 24 bits)
 148  */
 149
 150 /*
 151  * MSI Configuration reg at address 0x0030
 152  */
 153 #define ET_MSI_VECTOR   0x0000001F
 154 #define ET_MSI_TC       0x00070000
 155
 156 /*
 157  * Loopback reg located at address 0x0034
 158  */
 159 #define ET_LOOP_MAC     0x00000001
 160 #define ET_LOOP_DMA     0x00000002
 161
 162 /*
 163  * GLOBAL Module of JAGCore Address Mapping
 164  * Located at address 0x0000
 165  */
 166 struct global_regs {                            /* Location: */
 167         u32 txq_start_addr;                     /*  0x0000 */
 168         u32 txq_end_addr;                       /*  0x0004 */
 169         u32 rxq_start_addr;                     /*  0x0008 */
 170         u32 rxq_end_addr;                       /*  0x000C */
 171         u32 pm_csr;                             /*  0x0010 */
 172         u32 unused;                             /*  0x0014 */
 173         u32 int_status;                         /*  0x0018 */
 174         u32 int_mask;                           /*  0x001C */
 175         u32 int_alias_clr_en;                   /*  0x0020 */
 176         u32 int_status_alias;                   /*  0x0024 */
 177         u32 sw_reset;                           /*  0x0028 */
 178         u32 slv_timer;                          /*  0x002C */
 179         u32 msi_config;                         /*  0x0030 */
 180         u32 loopback;                           /*  0x0034 */
 181         u32 watchdog_timer;                     /*  0x0038 */
 182 };
 183
 184 /* START OF TXDMA REGISTER ADDRESS MAP */
 185 /*
 186  * txdma control status reg at address 0x1000
 187  */
 188 #define ET_TXDMA_CSR_HALT       0x00000001
 189 #define ET_TXDMA_DROP_TLP       0x00000002
 190 #define ET_TXDMA_CACHE_THRS     0x000000F0
 191 #define ET_TXDMA_CACHE_SHIFT    4
 192 #define ET_TXDMA_SNGL_EPKT      0x00000100
 193 #define ET_TXDMA_CLASS          0x00001E00
 194
 195 /*
 196  * structure for txdma packet ring base address hi reg in txdma address map
 197  * located at address 0x1004
 198  * Defined earlier (u32)
 199  */
 200
 201 /*
 202  * structure for txdma packet ring base address low reg in txdma address map
 203  * located at address 0x1008
 204  * Defined earlier (u32)
 205  */
 206
 207 /*
 208  * structure for txdma packet ring number of descriptor reg in txdma address
 209  * map.  Located at address 0x100C
 210  *
 211  * 31-10: unused
 212  * 9-0: pr ndes
 213  */
 214 #define ET_DMA12_MASK           0x0FFF  /* 12 bit mask for DMA12W types */
 215 #define ET_DMA12_WRAP           0x1000
 216 #define ET_DMA10_MASK           0x03FF  /* 10 bit mask for DMA10W types */
 217 #define ET_DMA10_WRAP           0x0400
 218 #define ET_DMA4_MASK            0x000F  /* 4 bit mask for DMA4W types */
 219 #define ET_DMA4_WRAP            0x0010
 220
 221 #define INDEX12(x)      ((x) & ET_DMA12_MASK)
 222 #define INDEX10(x)      ((x) & ET_DMA10_MASK)
 223 #define INDEX4(x)       ((x) & ET_DMA4_MASK)
 224
 225 /*
 226  * 10bit DMA with wrap
 227  * txdma tx queue write address reg in txdma address map at 0x1010
 228  * txdma tx queue write address external reg in txdma address map at 0x1014
 229  * txdma tx queue read address reg in txdma address map at 0x1018
 230  *
 231  * u32
 232  * txdma status writeback address hi reg in txdma address map at0x101C
 233  * txdma status writeback address lo reg in txdma address map at 0x1020
 234  *
 235  * 10bit DMA with wrap
 236  * txdma service request reg in txdma address map at 0x1024
 237  * structure for txdma service complete reg in txdma address map at 0x1028
 238  *
 239  * 4bit DMA with wrap
 240  * txdma tx descriptor cache read index reg in txdma address map at 0x102C
 241  * txdma tx descriptor cache write index reg in txdma address map at 0x1030
 242  *
 243  * txdma error reg in txdma address map at address 0x1034
 244  * 0: PyldResend
 245  * 1: PyldRewind
 246  * 4: DescrResend
 247  * 5: DescrRewind
 248  * 8: WrbkResend
 249  * 9: WrbkRewind
 250  */
 251
 252 /*
 253  * Tx DMA Module of JAGCore Address Mapping
 254  * Located at address 0x1000
 255  */
 256 struct txdma_regs {                     /* Location: */
 257         u32 csr;                        /*  0x1000 */
 258         u32 pr_base_hi;                 /*  0x1004 */
 259         u32 pr_base_lo;                 /*  0x1008 */
 260         u32 pr_num_des;                 /*  0x100C */
 261         u32 txq_wr_addr;                /*  0x1010 */
 262         u32 txq_wr_addr_ext;            /*  0x1014 */
 263         u32 txq_rd_addr;                /*  0x1018 */
 264         u32 dma_wb_base_hi;             /*  0x101C */
 265         u32 dma_wb_base_lo;             /*  0x1020 */
 266         u32 service_request;            /*  0x1024 */
 267         u32 service_complete;           /*  0x1028 */
 268         u32 cache_rd_index;             /*  0x102C */
 269         u32 cache_wr_index;             /*  0x1030 */
 270         u32 tx_dma_error;               /*  0x1034 */
 271         u32 desc_abort_cnt;             /*  0x1038 */
 272         u32 payload_abort_cnt;          /*  0x103c */
 273         u32 writeback_abort_cnt;        /*  0x1040 */
 274         u32 desc_timeout_cnt;           /*  0x1044 */
 275         u32 payload_timeout_cnt;        /*  0x1048 */
 276         u32 writeback_timeout_cnt;      /*  0x104c */
 277         u32 desc_error_cnt;             /*  0x1050 */
 278         u32 payload_error_cnt;          /*  0x1054 */
 279         u32 writeback_error_cnt;        /*  0x1058 */
 280         u32 dropped_tlp_cnt;            /*  0x105c */
 281         u32 new_service_complete;       /*  0x1060 */
 282         u32 ethernet_packet_cnt;        /*  0x1064 */
 283 };
 284
 285 /* END OF TXDMA REGISTER ADDRESS MAP */
 286
 287 /* START OF RXDMA REGISTER ADDRESS MAP */
 288 /*
 289  * structure for control status reg in rxdma address map
 290  * Located at address 0x2000
 291  *
 292  * CSR
 293  * 0: halt
 294  * 1-3: tc
 295  * 4: fbr_big_endian
 296  * 5: psr_big_endian
 297  * 6: pkt_big_endian
 298  * 7: dma_big_endian
 299  * 8-9: fbr0_size
 300  * 10: fbr0_enable
 301  * 11-12: fbr1_size
 302  * 13: fbr1_enable
 303  * 14: unused
 304  * 15: pkt_drop_disable
 305  * 16: pkt_done_flush
 306  * 17: halt_status
 307  * 18-31: unused
 308  */
 309 #define ET_RXDMA_CSR_HALT               0x0001
 310 #define ET_RXDMA_CSR_FBR0_SIZE_LO       0x0100
 311 #define ET_RXDMA_CSR_FBR0_SIZE_HI       0x0200
 312 #define ET_RXDMA_CSR_FBR0_ENABLE        0x0400
 313 #define ET_RXDMA_CSR_FBR1_SIZE_LO       0x0800
 314 #define ET_RXDMA_CSR_FBR1_SIZE_HI       0x1000
 315 #define ET_RXDMA_CSR_FBR1_ENABLE        0x2000
 316 #define ET_RXDMA_CSR_HALT_STATUS        0x00020000
 317
 318 /*
 319  * structure for dma writeback lo reg in rxdma address map
 320  * located at address 0x2004
 321  * Defined earlier (u32)
 322  */
 323
 324 /*
 325  * structure for dma writeback hi reg in rxdma address map
 326  * located at address 0x2008
 327  * Defined earlier (u32)
 328  */
 329
 330 /*
 331  * structure for number of packets done reg in rxdma address map
 332  * located at address 0x200C
 333  *
 334  * 31-8: unused
 335  * 7-0: num done
 336  */
 337
 338 /*
 339  * structure for max packet time reg in rxdma address map
 340  * located at address 0x2010
 341  *
 342  * 31-18: unused
 343  * 17-0: time done
 344  */
 345
 346 /*
 347  * structure for rx queue read address reg in rxdma address map
 348  * located at address 0x2014
 349  * Defined earlier (u32)
 350  */
 351
 352 /*
 353  * structure for rx queue read address external reg in rxdma address map
 354  * located at address 0x2018
 355  * Defined earlier (u32)
 356  */
 357
 358 /*
 359  * structure for rx queue write address reg in rxdma address map
 360  * located at address 0x201C
 361  * Defined earlier (u32)
 362  */
 363
 364 /*
 365  * structure for packet status ring base address lo reg in rxdma address map
 366  * located at address 0x2020
 367  * Defined earlier (u32)
 368  */
 369
 370 /*
 371  * structure for packet status ring base address hi reg in rxdma address map
 372  * located at address 0x2024
 373  * Defined earlier (u32)
 374  */
 375
 376 /*
 377  * structure for packet status ring number of descriptors reg in rxdma address
 378  * map.  Located at address 0x2028
 379  *
 380  * 31-12: unused
 381  * 11-0: psr ndes
 382  */
 383 #define ET_RXDMA_PSR_NUM_DES_MASK       0xFFF
 384
 385 /*
 386  * structure for packet status ring available offset reg in rxdma address map
 387  * located at address 0x202C
 388  *
 389  * 31-13: unused
 390  * 12: psr avail wrap
 391  * 11-0: psr avail
 392  */
 393
 394 /*
 395  * structure for packet status ring full offset reg in rxdma address map
 396  * located at address 0x2030
 397  *
 398  * 31-13: unused
 399  * 12: psr full wrap
 400  * 11-0: psr full
 401  */
 402
 403 /*
 404  * structure for packet status ring access index reg in rxdma address map
 405  * located at address 0x2034
 406  *
 407  * 31-5: unused
 408  * 4-0: psr_ai
 409  */
 410
 411 /*
 412  * structure for packet status ring minimum descriptors reg in rxdma address
 413  * map.  Located at address 0x2038
 414  *
 415  * 31-12: unused
 416  * 11-0: psr_min
 417  */
 418
 419 /*
 420  * structure for free buffer ring base lo address reg in rxdma address map
 421  * located at address 0x203C
 422  * Defined earlier (u32)
 423  */
 424
 425 /*
 426  * structure for free buffer ring base hi address reg in rxdma address map
 427  * located at address 0x2040
 428  * Defined earlier (u32)
 429  */
 430
 431 /*
 432  * structure for free buffer ring number of descriptors reg in rxdma address
 433  * map.  Located at address 0x2044
 434  *
 435  * 31-10: unused
 436  * 9-0: fbr ndesc
 437  */
 438
 439 /*
 440  * structure for free buffer ring 0 available offset reg in rxdma address map
 441  * located at address 0x2048
 442  * Defined earlier (u32)
 443  */
 444
 445 /*
 446  * structure for free buffer ring 0 full offset reg in rxdma address map
 447  * located at address 0x204C
 448  * Defined earlier (u32)
 449  */
 450
 451 /*
 452  * structure for free buffer cache 0 full offset reg in rxdma address map
 453  * located at address 0x2050
 454  *
 455  * 31-5: unused
 456  * 4-0: fbc rdi
 457  */
 458
 459 /*
 460  * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
 461  * located at address 0x2054
 462  *
 463  * 31-10: unused
 464  * 9-0: fbr min
 465  */
 466
 467 /*
 468  * structure for free buffer ring 1 base address lo reg in rxdma address map
 469  * located at address 0x2058 - 0x205C
 470  * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
 471  */
 472
 473 /*
 474  * structure for free buffer ring 1 number of descriptors reg in rxdma address
 475  * map.  Located at address 0x2060
 476  * Defined earlier (RXDMA_FBR_NUM_DES_t)
 477  */
 478
 479 /*
 480  * structure for free buffer ring 1 available offset reg in rxdma address map
 481  * located at address 0x2064
 482  * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
 483  */
 484
 485 /*
 486  * structure for free buffer ring 1 full offset reg in rxdma address map
 487  * located at address 0x2068
 488  * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
 489  */
 490
 491 /*
 492  * structure for free buffer cache 1 read index reg in rxdma address map
 493  * located at address 0x206C
 494  * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
 495  */
 496
 497 /*
 498  * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
 499  * located at address 0x2070
 500  * Defined Earlier (RXDMA_FBR_MIN_DES_t)
 501  */
 502
 503 /*
 504  * Rx DMA Module of JAGCore Address Mapping
 505  * Located at address 0x2000
 506  */
 507 struct rxdma_regs {                                     /* Location: */
 508         u32 csr;                                        /*  0x2000 */
 509         u32 dma_wb_base_lo;                             /*  0x2004 */
 510         u32 dma_wb_base_hi;                             /*  0x2008 */
 511         u32 num_pkt_done;                               /*  0x200C */
 512         u32 max_pkt_time;                               /*  0x2010 */
 513         u32 rxq_rd_addr;                                /*  0x2014 */
 514         u32 rxq_rd_addr_ext;                            /*  0x2018 */
 515         u32 rxq_wr_addr;                                /*  0x201C */
 516         u32 psr_base_lo;                                /*  0x2020 */
 517         u32 psr_base_hi;                                /*  0x2024 */
 518         u32 psr_num_des;                                /*  0x2028 */
 519         u32 psr_avail_offset;                           /*  0x202C */
 520         u32 psr_full_offset;                            /*  0x2030 */
 521         u32 psr_access_index;                           /*  0x2034 */
 522         u32 psr_min_des;                                /*  0x2038 */
 523         u32 fbr0_base_lo;                               /*  0x203C */
 524         u32 fbr0_base_hi;                               /*  0x2040 */
 525         u32 fbr0_num_des;                               /*  0x2044 */
 526         u32 fbr0_avail_offset;                          /*  0x2048 */
 527         u32 fbr0_full_offset;                           /*  0x204C */
 528         u32 fbr0_rd_index;                              /*  0x2050 */
 529         u32 fbr0_min_des;                               /*  0x2054 */
 530         u32 fbr1_base_lo;                               /*  0x2058 */
 531         u32 fbr1_base_hi;                               /*  0x205C */
 532         u32 fbr1_num_des;                               /*  0x2060 */
 533         u32 fbr1_avail_offset;                          /*  0x2064 */
 534         u32 fbr1_full_offset;                           /*  0x2068 */
 535         u32 fbr1_rd_index;                              /*  0x206C */
 536         u32 fbr1_min_des;                               /*  0x2070 */
 537 };
 538
 539 /* END OF RXDMA REGISTER ADDRESS MAP */
 540
 541 /* START OF TXMAC REGISTER ADDRESS MAP */
 542 /*
 543  * structure for control reg in txmac address map
 544  * located at address 0x3000
 545  *
 546  * bits
 547  * 31-8: unused
 548  * 7: cklseg_disable
 549  * 6: ckbcnt_disable
 550  * 5: cksegnum
 551  * 4: async_disable
 552  * 3: fc_disable
 553  * 2: mcif_disable
 554  * 1: mif_disable
 555  * 0: txmac_en
 556  */
 557 #define ET_TX_CTRL_FC_DISABLE   0x0008
 558 #define ET_TX_CTRL_TXMAC_ENABLE 0x0001
 559
 560 /*
 561  * structure for shadow pointer reg in txmac address map
 562  * located at address 0x3004
 563  * 31-27: reserved
 564  * 26-16: txq rd ptr
 565  * 15-11: reserved
 566  * 10-0: txq wr ptr
 567  */
 568
 569 /*
 570  * structure for error count reg in txmac address map
 571  * located at address 0x3008
 572  *
 573  * 31-12: unused
 574  * 11-8: reserved
 575  * 7-4: txq_underrun
 576  * 3-0: fifo_underrun
 577  */
 578
 579 /*
 580  * structure for max fill reg in txmac address map
 581  * located at address 0x300C
 582  * 31-12: unused
 583  * 11-0: max fill
 584  */
 585
 586 /*
 587  * structure for cf parameter reg in txmac address map
 588  * located at address 0x3010
 589  * 31-16: cfep
 590  * 15-0: cfpt
 591  */
 592
 593 /*
 594  * structure for tx test reg in txmac address map
 595  * located at address 0x3014
 596  * 31-17: unused
 597  * 16: reserved
 598  * 15: txtest_en
 599  * 14-11: unused
 600  * 10-0: txq test pointer
 601  */
 602
 603 /*
 604  * structure for error reg in txmac address map
 605  * located at address 0x3018
 606  *
 607  * 31-9: unused
 608  * 8: fifo_underrun
 609  * 7-6: unused
 610  * 5: ctrl2_err
 611  * 4: txq_underrun
 612  * 3: bcnt_err
 613  * 2: lseg_err
 614  * 1: segnum_err
 615  * 0: seg0_err
 616  */
 617
 618 /*
 619  * structure for error interrupt reg in txmac address map
 620  * located at address 0x301C
 621  *
 622  * 31-9: unused
 623  * 8: fifo_underrun
 624  * 7-6: unused
 625  * 5: ctrl2_err
 626  * 4: txq_underrun
 627  * 3: bcnt_err
 628  * 2: lseg_err
 629  * 1: segnum_err
 630  * 0: seg0_err
 631  */
 632
 633 /*
 634  * structure for error interrupt reg in txmac address map
 635  * located at address 0x3020
 636  *
 637  * 31-2: unused
 638  * 1: bp_req
 639  * 0: bp_xonxoff
 640  */
 641
 642 /*
 643  * Tx MAC Module of JAGCore Address Mapping
 644  */
 645 struct txmac_regs {                     /* Location: */
 646         u32 ctl;                        /*  0x3000 */
 647         u32 shadow_ptr;                 /*  0x3004 */
 648         u32 err_cnt;                    /*  0x3008 */
 649         u32 max_fill;                   /*  0x300C */
 650         u32 cf_param;                   /*  0x3010 */
 651         u32 tx_test;                    /*  0x3014 */
 652         u32 err;                        /*  0x3018 */
 653         u32 err_int;                    /*  0x301C */
 654         u32 bp_ctrl;                    /*  0x3020 */
 655 };
 656
 657 /* END OF TXMAC REGISTER ADDRESS MAP */
 658
 659 /* START OF RXMAC REGISTER ADDRESS MAP */
 660
 661 /*
 662  * structure for rxmac control reg in rxmac address map
 663  * located at address 0x4000
 664  *
 665  * 31-7: reserved
 666  * 6: rxmac_int_disable
 667  * 5: async_disable
 668  * 4: mif_disable
 669  * 3: wol_disable
 670  * 2: pkt_filter_disable
 671  * 1: mcif_disable
 672  * 0: rxmac_en
 673  */
 674 #define ET_RX_CTRL_WOL_DISABLE  0x0008
 675 #define ET_RX_CTRL_RXMAC_ENABLE 0x0001
 676
 677 /*
 678  * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
 679  * located at address 0x4004
 680  * 31-16: crc
 681  * 15-12: reserved
 682  * 11: ignore_pp
 683  * 10: ignore_mp
 684  * 9: clr_intr
 685  * 8: ignore_link_chg
 686  * 7: ignore_uni
 687  * 6: ignore_multi
 688  * 5: ignore_broad
 689  * 4-0: valid_crc 4-0
 690  */
 691
 692 /*
 693  * structure for CRC 1 and CRC 2 reg in rxmac address map
 694  * located at address 0x4008
 695  *
 696  * 31-16: crc2
 697  * 15-0: crc1
 698  */
 699
 700 /*
 701  * structure for CRC 3 and CRC 4 reg in rxmac address map
 702  * located at address 0x400C
 703  *
 704  * 31-16: crc4
 705  * 15-0: crc3
 706  */
 707
 708 /*
 709  * structure for Wake On Lan Source Address Lo reg in rxmac address map
 710  * located at address 0x4010
 711  *
 712  * 31-24: sa3
 713  * 23-16: sa4
 714  * 15-8: sa5
 715  * 7-0: sa6
 716  */
 717 #define ET_RX_WOL_LO_SA3_SHIFT 24
 718 #define ET_RX_WOL_LO_SA4_SHIFT 16
 719 #define ET_RX_WOL_LO_SA5_SHIFT 8
 720
 721 /*
 722  * structure for Wake On Lan Source Address Hi reg in rxmac address map
 723  * located at address 0x4014
 724  *
 725  * 31-16: reserved
 726  * 15-8: sa1
 727  * 7-0: sa2
 728  */
 729 #define ET_RX_WOL_HI_SA1_SHIFT 8
 730
 731 /*
 732  * structure for Wake On Lan mask reg in rxmac address map
 733  * located at address 0x4018 - 0x4064
 734  * Defined earlier (u32)
 735  */
 736
 737 /*
 738  * structure for Unicast Packet Filter Address 1 reg in rxmac address map
 739  * located at address 0x4068
 740  *
 741  * 31-24: addr1_3
 742  * 23-16: addr1_4
 743  * 15-8: addr1_5
 744  * 7-0: addr1_6
 745  */
 746 #define ET_RX_UNI_PF_ADDR1_3_SHIFT 24
 747 #define ET_RX_UNI_PF_ADDR1_4_SHIFT 16
 748 #define ET_RX_UNI_PF_ADDR1_5_SHIFT 8
 749
 750 /*
 751  * structure for Unicast Packet Filter Address 2 reg in rxmac address map
 752  * located at address 0x406C
 753  *
 754  * 31-24: addr2_3
 755  * 23-16: addr2_4
 756  * 15-8: addr2_5
 757  * 7-0: addr2_6
 758  */
 759 #define ET_RX_UNI_PF_ADDR2_3_SHIFT 24
 760 #define ET_RX_UNI_PF_ADDR2_4_SHIFT 16
 761 #define ET_RX_UNI_PF_ADDR2_5_SHIFT 8
 762
 763 /*
 764  * structure for Unicast Packet Filter Address 1 & 2 reg in rxmac address map
 765  * located at address 0x4070
 766  *
 767  * 31-24: addr2_1
 768  * 23-16: addr2_2
 769  * 15-8: addr1_1
 770  * 7-0: addr1_2
 771  */
 772 #define ET_RX_UNI_PF_ADDR2_1_SHIFT 24
 773 #define ET_RX_UNI_PF_ADDR2_2_SHIFT 16
 774 #define ET_RX_UNI_PF_ADDR1_1_SHIFT 8
 775
 776 /*
 777  * structure for Multicast Hash reg in rxmac address map
 778  * located at address 0x4074 - 0x4080
 779  * Defined earlier (u32)
 780  */
 781
 782 /*
 783  * structure for Packet Filter Control reg in rxmac address map
 784  * located at address 0x4084
 785  *
 786  * 31-23: unused
 787  * 22-16: min_pkt_size
 788  * 15-4: unused
 789  * 3: filter_frag_en
 790  * 2: filter_uni_en
 791  * 1: filter_multi_en
 792  * 0: filter_broad_en
 793  */
 794 #define ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT           16
 795 #define ET_RX_PFCTRL_FRAG_FILTER_ENABLE         0x0008
 796 #define ET_RX_PFCTRL_UNICST_FILTER_ENABLE       0x0004
 797 #define ET_RX_PFCTRL_MLTCST_FILTER_ENABLE       0x0002
 798 #define ET_RX_PFCTRL_BRDCST_FILTER_ENABLE       0x0001
 799
 800 /*
 801  * structure for Memory Controller Interface Control Max Segment reg in rxmac
 802  * address map.  Located at address 0x4088
 803  *
 804  * 31-10: reserved
 805  * 9-2: max_size
 806  * 1: fc_en
 807  * 0: seg_en
 808  */
 809 #define ET_RX_MCIF_CTRL_MAX_SEG_SIZE_SHIFT      2
 810 #define ET_RX_MCIF_CTRL_MAX_SEG_FC_ENABLE       0x0002
 811 #define ET_RX_MCIF_CTRL_MAX_SEG_ENABLE          0x0001
 812
 813 /*
 814  * structure for Memory Controller Interface Water Mark reg in rxmac address
 815  * map.  Located at address 0x408C
 816  *
 817  * 31-26: unused
 818  * 25-16: mark_hi
 819  * 15-10: unused
 820  * 9-0: mark_lo
 821  */
 822
 823 /*
 824  * structure for Rx Queue Dialog reg in rxmac address map.
 825  * located at address 0x4090
 826  *
 827  * 31-26: reserved
 828  * 25-16: rd_ptr
 829  * 15-10: reserved
 830  * 9-0: wr_ptr
 831  */
 832
 833 /*
 834  * structure for space available reg in rxmac address map.
 835  * located at address 0x4094
 836  *
 837  * 31-17: reserved
 838  * 16: space_avail_en
 839  * 15-10: reserved
 840  * 9-0: space_avail
 841  */
 842
 843 /*
 844  * structure for management interface reg in rxmac address map.
 845  * located at address 0x4098
 846  *
 847  * 31-18: reserved
 848  * 17: drop_pkt_en
 849  * 16-0: drop_pkt_mask
 850  */
 851
 852 /*
 853  * structure for Error reg in rxmac address map.
 854  * located at address 0x409C
 855  *
 856  * 31-4: unused
 857  * 3: mif
 858  * 2: async
 859  * 1: pkt_filter
 860  * 0: mcif
 861  */
 862
 863 /*
 864  * Rx MAC Module of JAGCore Address Mapping
 865  */
 866 struct rxmac_regs {                                     /* Location: */
 867         u32 ctrl;                                       /*  0x4000 */
 868         u32 crc0;                                       /*  0x4004 */
 869         u32 crc12;                                      /*  0x4008 */
 870         u32 crc34;                                      /*  0x400C */
 871         u32 sa_lo;                                      /*  0x4010 */
 872         u32 sa_hi;                                      /*  0x4014 */
 873         u32 mask0_word0;                                /*  0x4018 */
 874         u32 mask0_word1;                                /*  0x401C */
 875         u32 mask0_word2;                                /*  0x4020 */
 876         u32 mask0_word3;                                /*  0x4024 */
 877         u32 mask1_word0;                                /*  0x4028 */
 878         u32 mask1_word1;                                /*  0x402C */
 879         u32 mask1_word2;                                /*  0x4030 */
 880         u32 mask1_word3;                                /*  0x4034 */
 881         u32 mask2_word0;                                /*  0x4038 */
 882         u32 mask2_word1;                                /*  0x403C */
 883         u32 mask2_word2;                                /*  0x4040 */
 884         u32 mask2_word3;                                /*  0x4044 */
 885         u32 mask3_word0;                                /*  0x4048 */
 886         u32 mask3_word1;                                /*  0x404C */
 887         u32 mask3_word2;                                /*  0x4050 */
 888         u32 mask3_word3;                                /*  0x4054 */
 889         u32 mask4_word0;                                /*  0x4058 */
 890         u32 mask4_word1;                                /*  0x405C */
 891         u32 mask4_word2;                                /*  0x4060 */
 892         u32 mask4_word3;                                /*  0x4064 */
 893         u32 uni_pf_addr1;                               /*  0x4068 */
 894         u32 uni_pf_addr2;                               /*  0x406C */
 895         u32 uni_pf_addr3;                               /*  0x4070 */
 896         u32 multi_hash1;                                /*  0x4074 */
 897         u32 multi_hash2;                                /*  0x4078 */
 898         u32 multi_hash3;                                /*  0x407C */
 899         u32 multi_hash4;                                /*  0x4080 */
 900         u32 pf_ctrl;                                    /*  0x4084 */
 901         u32 mcif_ctrl_max_seg;                          /*  0x4088 */
 902         u32 mcif_water_mark;                            /*  0x408C */
 903         u32 rxq_diag;                                   /*  0x4090 */
 904         u32 space_avail;                                /*  0x4094 */
 905
 906         u32 mif_ctrl;                                   /*  0x4098 */
 907         u32 err_reg;                                    /*  0x409C */
 908 };
 909
 910 /* END OF RXMAC REGISTER ADDRESS MAP */
 911
 912 /* START OF MAC REGISTER ADDRESS MAP */
 913 /*
 914  * structure for configuration #1 reg in mac address map.
 915  * located at address 0x5000
 916  *
 917  * 31: soft reset
 918  * 30: sim reset
 919  * 29-20: reserved
 920  * 19: reset rx mc
 921  * 18: reset tx mc
 922  * 17: reset rx func
 923  * 16: reset tx fnc
 924  * 15-9: reserved
 925  * 8: loopback
 926  * 7-6: reserved
 927  * 5: rx flow
 928  * 4: tx flow
 929  * 3: syncd rx en
 930  * 2: rx enable
 931  * 1: syncd tx en
 932  * 0: tx enable
 933  */
 934 #define ET_MAC_CFG1_SOFT_RESET          0x80000000
 935 #define ET_MAC_CFG1_SIM_RESET           0x40000000
 936 #define ET_MAC_CFG1_RESET_RXMC          0x00080000
 937 #define ET_MAC_CFG1_RESET_TXMC          0x00040000
 938 #define ET_MAC_CFG1_RESET_RXFUNC        0x00020000
 939 #define ET_MAC_CFG1_RESET_TXFUNC        0x00010000
 940 #define ET_MAC_CFG1_LOOPBACK            0x00000100
 941 #define ET_MAC_CFG1_RX_FLOW             0x00000020
 942 #define ET_MAC_CFG1_TX_FLOW             0x00000010
 943 #define ET_MAC_CFG1_RX_ENABLE           0x00000004
 944 #define ET_MAC_CFG1_TX_ENABLE           0x00000001
 945 #define ET_MAC_CFG1_WAIT                0x0000000A      /* RX & TX syncd */
 946
 947 /*
 948  * structure for configuration #2 reg in mac address map.
 949  * located at address 0x5004
 950  * 31-16: reserved
 951  * 15-12: preamble
 952  * 11-10: reserved
 953  * 9-8: if mode
 954  * 7-6: reserved
 955  * 5: huge frame
 956  * 4: length check
 957  * 3: undefined
 958  * 2: pad crc
 959  * 1: crc enable
 960  * 0: full duplex
 961  */
 962 #define ET_MAC_CFG2_PREAMBLE_SHIFT      12
 963 #define ET_MAC_CFG2_IFMODE_MASK         0x0300
 964 #define ET_MAC_CFG2_IFMODE_1000         0x0200
 965 #define ET_MAC_CFG2_IFMODE_100          0x0100
 966 #define ET_MAC_CFG2_IFMODE_HUGE_FRAME   0x0020
 967 #define ET_MAC_CFG2_IFMODE_LEN_CHECK    0x0010
 968 #define ET_MAC_CFG2_IFMODE_PAD_CRC      0x0004
 969 #define ET_MAC_CFG2_IFMODE_CRC_ENABLE   0x0002
 970 #define ET_MAC_CFG2_IFMODE_FULL_DPLX    0x0001
 971
 972 /*
 973  * structure for Interpacket gap reg in mac address map.
 974  * located at address 0x5008
 975  *
 976  * 31: reserved
 977  * 30-24: non B2B ipg 1
 978  * 23: undefined
 979  * 22-16: non B2B ipg 2
 980  * 15-8: Min ifg enforce
 981  * 7-0: B2B ipg
 982  *
 983  * structure for half duplex reg in mac address map.
 984  * located at address 0x500C
 985  * 31-24: reserved
 986  * 23-20: Alt BEB trunc
 987  * 19: Alt BEB enable
 988  * 18: BP no backoff
 989  * 17: no backoff
 990  * 16: excess defer
 991  * 15-12: re-xmit max
 992  * 11-10: reserved
 993  * 9-0: collision window
 994  */
 995
 996 /*
 997  * structure for Maximum Frame Length reg in mac address map.
 998  * located at address 0x5010: bits 0-15 hold the length.
 999  */
1000
1001 /*
1002  * structure for Reserve 1 reg in mac address map.
1003  * located at address 0x5014 - 0x5018
1004  * Defined earlier (u32)
1005  */
1006
1007 /*
1008  * structure for Test reg in mac address map.
1009  * located at address 0x501C
1010  * test: bits 0-2, rest unused
1011  */
1012
1013 /*
1014  * structure for MII Management Configuration reg in mac address map.
1015  * located at address 0x5020
1016  *
1017  * 31: reset MII mgmt
1018  * 30-6: unused
1019  * 5: scan auto increment
1020  * 4: preamble suppress
1021  * 3: undefined
1022  * 2-0: mgmt clock reset
1023  */
1024 #define ET_MAC_MIIMGMT_CLK_RST  0x0007
1025
1026 /*
1027  * structure for MII Management Command reg in mac address map.
1028  * located at address 0x5024
1029  * bit 1: scan cycle
1030  * bit 0: read cycle
1031  */
1032
1033 /*
1034  * structure for MII Management Address reg in mac address map.
1035  * located at address 0x5028
1036  * 31-13: reserved
1037  * 12-8: phy addr
1038  * 7-5: reserved
1039  * 4-0: register
1040  */
1041 #define ET_MAC_MII_ADDR(phy, reg)       ((phy) << 8 | (reg))
1042
1043 /*
1044  * structure for MII Management Control reg in mac address map.
1045  * located at address 0x502C
1046  * 31-16: reserved
1047  * 15-0: phy control
1048  */
1049
1050 /*
1051  * structure for MII Management Status reg in mac address map.
1052  * located at address 0x5030
1053  * 31-16: reserved
1054  * 15-0: phy control
1055  */
1056 #define ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK 0xFFFF
1057
1058 /*
1059  * structure for MII Management Indicators reg in mac address map.
1060  * located at address 0x5034
1061  * 31-3: reserved
1062  * 2: not valid
1063  * 1: scanning
1064  * 0: busy
1065  */
1066 #define ET_MAC_MGMT_BUSY        0x00000001      /* busy */
1067 #define ET_MAC_MGMT_WAIT        0x00000005      /* busy | not valid */
1068
1069 /*
1070  * structure for Interface Control reg in mac address map.
1071  * located at address 0x5038
1072  *
1073  * 31: reset if module
1074  * 30-28: reserved
1075  * 27: tbi mode
1076  * 26: ghd mode
1077  * 25: lhd mode
1078  * 24: phy mode
1079  * 23: reset per mii
1080  * 22-17: reserved
1081  * 16: speed
1082  * 15: reset pe100x
1083  * 14-11: reserved
1084  * 10: force quiet
1085  * 9: no cipher
1086  * 8: disable link fail
1087  * 7: reset gpsi
1088  * 6-1: reserved
1089  * 0: enable jabber protection
1090  */
1091 #define ET_MAC_IFCTRL_GHDMODE   (1 << 26)
1092 #define ET_MAC_IFCTRL_PHYMODE   (1 << 24)
1093
1094 /*
1095  * structure for Interface Status reg in mac address map.
1096  * located at address 0x503C
1097  *
1098  * 31-10: reserved
1099  * 9: excess_defer
1100  * 8: clash
1101  * 7: phy_jabber
1102  * 6: phy_link_ok
1103  * 5: phy_full_duplex
1104  * 4: phy_speed
1105  * 3: pe100x_link_fail
1106  * 2: pe10t_loss_carrier
1107  * 1: pe10t_sqe_error
1108  * 0: pe10t_jabber
1109  */
1110
1111 /*
1112  * structure for Mac Station Address, Part 1 reg in mac address map.
1113  * located at address 0x5040
1114  *
1115  * 31-24: Octet6
1116  * 23-16: Octet5
1117  * 15-8: Octet4
1118  * 7-0: Octet3
1119  */
1120 #define ET_MAC_STATION_ADDR1_OC6_SHIFT 24
1121 #define ET_MAC_STATION_ADDR1_OC5_SHIFT 16
1122 #define ET_MAC_STATION_ADDR1_OC4_SHIFT 8
1123
1124 /*
1125  * structure for Mac Station Address, Part 2 reg in mac address map.
1126  * located at address 0x5044
1127  *
1128  * 31-24: Octet2
1129  * 23-16: Octet1
1130  * 15-0: reserved
1131  */
1132 #define ET_MAC_STATION_ADDR2_OC2_SHIFT 24
1133 #define ET_MAC_STATION_ADDR2_OC1_SHIFT 16
1134
1135 /*
1136  * MAC Module of JAGCore Address Mapping
1137  */
1138 struct mac_regs {                                       /* Location: */
1139         u32 cfg1;                                       /*  0x5000 */
1140         u32 cfg2;                                       /*  0x5004 */
1141         u32 ipg;                                        /*  0x5008 */
1142         u32 hfdp;                                       /*  0x500C */
1143         u32 max_fm_len;                                 /*  0x5010 */
1144         u32 rsv1;                                       /*  0x5014 */
1145         u32 rsv2;                                       /*  0x5018 */
1146         u32 mac_test;                                   /*  0x501C */
1147         u32 mii_mgmt_cfg;                               /*  0x5020 */
1148         u32 mii_mgmt_cmd;                               /*  0x5024 */
1149         u32 mii_mgmt_addr;                              /*  0x5028 */
1150         u32 mii_mgmt_ctrl;                              /*  0x502C */
1151         u32 mii_mgmt_stat;                              /*  0x5030 */
1152         u32 mii_mgmt_indicator;                         /*  0x5034 */
1153         u32 if_ctrl;                                    /*  0x5038 */
1154         u32 if_stat;                                    /*  0x503C */
1155         u32 station_addr_1;                             /*  0x5040 */
1156         u32 station_addr_2;                             /*  0x5044 */
1157 };
1158
1159 /* END OF MAC REGISTER ADDRESS MAP */
1160
1161 /* START OF MAC STAT REGISTER ADDRESS MAP */
1162 /*
1163  * structure for Carry Register One and it's Mask Register reg located in mac
1164  * stat address map address 0x6130 and 0x6138.
1165  *
1166  * 31: tr64
1167  * 30: tr127
1168  * 29: tr255
1169  * 28: tr511
1170  * 27: tr1k
1171  * 26: trmax
1172  * 25: trmgv
1173  * 24-17: unused
1174  * 16: rbyt
1175  * 15: rpkt
1176  * 14: rfcs
1177  * 13: rmca
1178  * 12: rbca
1179  * 11: rxcf
1180  * 10: rxpf
1181  * 9: rxuo
1182  * 8: raln
1183  * 7: rflr
1184  * 6: rcde
1185  * 5: rcse
1186  * 4: rund
1187  * 3: rovr
1188  * 2: rfrg
1189  * 1: rjbr
1190  * 0: rdrp
1191  */
1192
1193 /*
1194  * structure for Carry Register Two Mask Register reg in mac stat address map.
1195  * located at address 0x613C
1196  *
1197  * 31-20: unused
1198  * 19: tjbr
1199  * 18: tfcs
1200  * 17: txcf
1201  * 16: tovr
1202  * 15: tund
1203  * 14: trfg
1204  * 13: tbyt
1205  * 12: tpkt
1206  * 11: tmca
1207  * 10: tbca
1208  * 9: txpf
1209  * 8: tdfr
1210  * 7: tedf
1211  * 6: tscl
1212  * 5: tmcl
1213  * 4: tlcl
1214  * 3: txcl
1215  * 2: tncl
1216  * 1: tpfh
1217  * 0: tdrp
1218  */
1219
1220 /*
1221  * MAC STATS Module of JAGCore Address Mapping
1222  */
1223 struct macstat_regs {                   /* Location: */
1224         u32 pad[32];                    /*  0x6000 - 607C */
1225
1226         /* counters */
1227         u32 txrx_0_64_byte_frames;      /*  0x6080 */
1228         u32 txrx_65_127_byte_frames;    /*  0x6084 */
1229         u32 txrx_128_255_byte_frames;   /*  0x6088 */
1230         u32 txrx_256_511_byte_frames;   /*  0x608C */
1231         u32 txrx_512_1023_byte_frames;  /*  0x6090 */
1232         u32 txrx_1024_1518_byte_frames; /*  0x6094 */
1233         u32 txrx_1519_1522_gvln_frames; /*  0x6098 */
1234         u32 rx_bytes;                   /*  0x609C */
1235         u32 rx_packets;                 /*  0x60A0 */
1236         u32 rx_fcs_errs;                /*  0x60A4 */
1237         u32 rx_multicast_packets;       /*  0x60A8 */
1238         u32 rx_broadcast_packets;       /*  0x60AC */
1239         u32 rx_control_frames;          /*  0x60B0 */
1240         u32 rx_pause_frames;            /*  0x60B4 */
1241         u32 rx_unknown_opcodes;         /*  0x60B8 */
1242         u32 rx_align_errs;              /*  0x60BC */
1243         u32 rx_frame_len_errs;          /*  0x60C0 */
1244         u32 rx_code_errs;               /*  0x60C4 */
1245         u32 rx_carrier_sense_errs;      /*  0x60C8 */
1246         u32 rx_undersize_packets;       /*  0x60CC */
1247         u32 rx_oversize_packets;        /*  0x60D0 */
1248         u32 rx_fragment_packets;        /*  0x60D4 */
1249         u32 rx_jabbers;                 /*  0x60D8 */
1250         u32 rx_drops;                   /*  0x60DC */
1251         u32 tx_bytes;                   /*  0x60E0 */
1252         u32 tx_packets;                 /*  0x60E4 */
1253         u32 tx_multicast_packets;       /*  0x60E8 */
1254         u32 tx_broadcast_packets;       /*  0x60EC */
1255         u32 tx_pause_frames;            /*  0x60F0 */
1256         u32 tx_deferred;                /*  0x60F4 */
1257         u32 tx_excessive_deferred;      /*  0x60F8 */
1258         u32 tx_single_collisions;       /*  0x60FC */
1259         u32 tx_multiple_collisions;     /*  0x6100 */
1260         u32 tx_late_collisions;         /*  0x6104 */
1261         u32 tx_excessive_collisions;    /*  0x6108 */
1262         u32 tx_total_collisions;        /*  0x610C */
1263         u32 tx_pause_honored_frames;    /*  0x6110 */
1264         u32 tx_drops;                   /*  0x6114 */
1265         u32 tx_jabbers;                 /*  0x6118 */
1266         u32 tx_fcs_errs;                /*  0x611C */
1267         u32 tx_control_frames;          /*  0x6120 */
1268         u32 tx_oversize_frames;         /*  0x6124 */
1269         u32 tx_undersize_frames;        /*  0x6128 */
1270         u32 tx_fragments;               /*  0x612C */
1271         u32 carry_reg1;                 /*  0x6130 */
1272         u32 carry_reg2;                 /*  0x6134 */
1273         u32 carry_reg1_mask;            /*  0x6138 */
1274         u32 carry_reg2_mask;            /*  0x613C */
1275 };
1276
1277 /* END OF MAC STAT REGISTER ADDRESS MAP */
1278
1279 /* START OF MMC REGISTER ADDRESS MAP */
1280 /*
1281  * Main Memory Controller Control reg in mmc address map.
1282  * located at address 0x7000
1283  */
1284 #define ET_MMC_ENABLE           1
1285 #define ET_MMC_ARB_DISABLE      2
1286 #define ET_MMC_RXMAC_DISABLE    4
1287 #define ET_MMC_TXMAC_DISABLE    8
1288 #define ET_MMC_TXDMA_DISABLE    16
1289 #define ET_MMC_RXDMA_DISABLE    32
1290 #define ET_MMC_FORCE_CE         64
1291
1292 /*
1293  * Main Memory Controller Host Memory Access Address reg in mmc
1294  * address map.  Located at address 0x7004. Top 16 bits hold the address bits
1295  */
1296 #define ET_SRAM_REQ_ACCESS      1
1297 #define ET_SRAM_WR_ACCESS       2
1298 #define ET_SRAM_IS_CTRL         4
1299
1300 /*
1301  * structure for Main Memory Controller Host Memory Access Data reg in mmc
1302  * address map.  Located at address 0x7008 - 0x7014
1303  * Defined earlier (u32)
1304  */
1305
1306 /*
1307  * Memory Control Module of JAGCore Address Mapping
1308  */
1309 struct mmc_regs {               /* Location: */
1310         u32 mmc_ctrl;           /*  0x7000 */
1311         u32 sram_access;        /*  0x7004 */
1312         u32 sram_word1;         /*  0x7008 */
1313         u32 sram_word2;         /*  0x700C */
1314         u32 sram_word3;         /*  0x7010 */
1315         u32 sram_word4;         /*  0x7014 */
1316 };
1317
1318 /* END OF MMC REGISTER ADDRESS MAP */
1319
1320 /*
1321  * JAGCore Address Mapping
1322  */
1323 struct address_map {
1324         struct global_regs global;
1325         /* unused section of global address map */
1326         u8 unused_global[4096 - sizeof(struct global_regs)];
1327         struct txdma_regs txdma;
1328         /* unused section of txdma address map */
1329         u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
1330         struct rxdma_regs rxdma;
1331         /* unused section of rxdma address map */
1332         u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
1333         struct txmac_regs txmac;
1334         /* unused section of txmac address map */
1335         u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
1336         struct rxmac_regs rxmac;
1337         /* unused section of rxmac address map */
1338         u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)];
1339         struct mac_regs mac;
1340         /* unused section of mac address map */
1341         u8 unused_mac[4096 - sizeof(struct mac_regs)];
1342         struct macstat_regs macstat;
1343         /* unused section of mac stat address map */
1344         u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
1345         struct mmc_regs mmc;
1346         /* unused section of mmc address map */
1347         u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
1348         /* unused section of address map */
1349         u8 unused_[1015808];
1350         u8 unused_exp_rom[4096];        /* MGS-size TBD */
1351         u8 unused__[524288];    /* unused section of address map */
1352 };
1353
1354 /*
1355  * Defines for generic MII registers 0x00 -> 0x0F can be found in
1356  * include/linux/mii.h
1357  */
1358 /* some defines for modem registers that seem to be 'reserved' */
1359 #define PHY_INDEX_REG              0x10
1360 #define PHY_DATA_REG               0x11
1361 #define PHY_MPHY_CONTROL_REG       0x12
1362
1363 /* defines for specified registers */
1364 #define PHY_LOOPBACK_CONTROL       0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
1365                                         /* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
1366 #define PHY_REGISTER_MGMT_CONTROL  0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG     21 */
1367 #define PHY_CONFIG                 0x16 /* TRU_VMI_CONFIGURATION_REG      22 */
1368 #define PHY_PHY_CONTROL            0x17 /* TRU_VMI_PHY_CONTROL_REG        23 */
1369 #define PHY_INTERRUPT_MASK         0x18 /* TRU_VMI_INTERRUPT_MASK_REG     24 */
1370 #define PHY_INTERRUPT_STATUS       0x19 /* TRU_VMI_INTERRUPT_STATUS_REG   25 */
1371 #define PHY_PHY_STATUS             0x1A /* TRU_VMI_PHY_STATUS_REG         26 */
1372 #define PHY_LED_1                  0x1B /* TRU_VMI_LED_CONTROL_1_REG      27 */
1373 #define PHY_LED_2                  0x1C /* TRU_VMI_LED_CONTROL_2_REG      28 */
1374                                         /* TRU_VMI_LINK_CONTROL_REG       29 */
1375                                         /* TRU_VMI_TIMING_CONTROL_REG        */
1376
1377 /* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
1378 #define ET_1000BT_MSTR_SLV 0x4000
1379
1380 /* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
1381
1382 /* MI Register 19: Loopback Control Reg(0x13)
1383  *      15:     mii_en
1384  *      14:     pcs_en
1385  *      13:     pmd_en
1386  *      12:     all_digital_en
1387  *      11:     replica_en
1388  *      10:     line_driver_en
1389  *      9-0:    reserved
1390  */
1391
1392 /* MI Register 20: Reserved Reg(0x14) */
1393
1394 /* MI Register 21: Management Interface Control Reg(0x15)
1395  *      15-11:  reserved
1396  *      10-4:   mi_error_count
1397  *      3:      reserved
1398  *      2:      ignore_10g_fr
1399  *      1:      reserved
1400  *      0:      preamble_suppress_en
1401  */
1402
1403 /* MI Register 22: PHY Configuration Reg(0x16)
1404  *      15:     crs_tx_en
1405  *      14:     reserved
1406  *      13-12:  tx_fifo_depth
1407  *      11-10:  speed_downshift
1408  *      9:      pbi_detect
1409  *      8:      tbi_rate
1410  *      7:      alternate_np
1411  *      6:      group_mdio_en
1412  *      5:      tx_clock_en
1413  *      4:      sys_clock_en
1414  *      3:      reserved
1415  *      2-0:    mac_if_mode
1416  */
1417 #define ET_PHY_CONFIG_TX_FIFO_DEPTH     0x3000
1418
1419 #define ET_PHY_CONFIG_FIFO_DEPTH_8      0x0000
1420 #define ET_PHY_CONFIG_FIFO_DEPTH_16     0x1000
1421 #define ET_PHY_CONFIG_FIFO_DEPTH_32     0x2000
1422 #define ET_PHY_CONFIG_FIFO_DEPTH_64     0x3000
1423
1424 /* MI Register 23: PHY CONTROL Reg(0x17)
1425  *      15:     reserved
1426  *      14:     tdr_en
1427  *      13:     reserved
1428  *      12-11:  downshift_attempts
1429  *      10-6:   reserved
1430  *      5:      jabber_10baseT
1431  *      4:      sqe_10baseT
1432  *      3:      tp_loopback_10baseT
1433  *      2:      preamble_gen_en
1434  *      1:      reserved
1435  *      0:      force_int
1436  */
1437
1438 /* MI Register 24: Interrupt Mask Reg(0x18)
1439  *      15-10:  reserved
1440  *      9:      mdio_sync_lost
1441  *      8:      autoneg_status
1442  *      7:      hi_bit_err
1443  *      6:      np_rx
1444  *      5:      err_counter_full
1445  *      4:      fifo_over_underflow
1446  *      3:      rx_status
1447  *      2:      link_status
1448  *      1:      automatic_speed
1449  *      0:      int_en
1450  */
1451
1452 /* MI Register 25: Interrupt Status Reg(0x19)
1453  *      15-10:  reserved
1454  *      9:      mdio_sync_lost
1455  *      8:      autoneg_status
1456  *      7:      hi_bit_err
1457  *      6:      np_rx
1458  *      5:      err_counter_full
1459  *      4:      fifo_over_underflow
1460  *      3:      rx_status
1461  *      2:      link_status
1462  *      1:      automatic_speed
1463  *      0:      int_en
1464  */
1465
1466 /* MI Register 26: PHY Status Reg(0x1A)
1467  *      15:     reserved
1468  *      14-13:  autoneg_fault
1469  *      12:     autoneg_status
1470  *      11:     mdi_x_status
1471  *      10:     polarity_status
1472  *      9-8:    speed_status
1473  *      7:      duplex_status
1474  *      6:      link_status
1475  *      5:      tx_status
1476  *      4:      rx_status
1477  *      3:      collision_status
1478  *      2:      autoneg_en
1479  *      1:      pause_en
1480  *      0:      asymmetric_dir
1481  */
1482 #define ET_PHY_AUTONEG_STATUS   0x1000
1483 #define ET_PHY_POLARITY_STATUS  0x0400
1484 #define ET_PHY_SPEED_STATUS     0x0300
1485 #define ET_PHY_DUPLEX_STATUS    0x0080
1486 #define ET_PHY_LSTATUS          0x0040
1487 #define ET_PHY_AUTONEG_ENABLE   0x0020
1488
1489 /* MI Register 27: LED Control Reg 1(0x1B)
1490  *      15-14:  reserved
1491  *      13-12:  led_dup_indicate
1492  *      11-10:  led_10baseT
1493  *      9-8:    led_collision
1494  *      7-4:    reserved
1495  *      3-2:    pulse_dur
1496  *      1:      pulse_stretch1
1497  *      0:      pulse_stretch0
1498  */
1499
1500 /* MI Register 28: LED Control Reg 2(0x1C)
1501  *      15-12:  led_link
1502  *      11-8:   led_tx_rx
1503  *      7-4:    led_100BaseTX
1504  *      3-0:    led_1000BaseT
1505  */
1506 #define ET_LED2_LED_LINK        0xF000
1507 #define ET_LED2_LED_TXRX        0x0F00
1508 #define ET_LED2_LED_100TX       0x00F0
1509 #define ET_LED2_LED_1000T       0x000F
1510
1511 /* defines for LED control reg 2 values */
1512 #define LED_VAL_1000BT                  0x0
1513 #define LED_VAL_100BTX                  0x1
1514 #define LED_VAL_10BT                    0x2
1515 #define LED_VAL_1000BT_100BTX           0x3 /* 1000BT on, 100BTX blink */
1516 #define LED_VAL_LINKON                  0x4
1517 #define LED_VAL_TX                      0x5
1518 #define LED_VAL_RX                      0x6
1519 #define LED_VAL_TXRX                    0x7 /* TX or RX */
1520 #define LED_VAL_DUPLEXFULL              0x8
1521 #define LED_VAL_COLLISION               0x9
1522 #define LED_VAL_LINKON_ACTIVE           0xA /* Link on, activity blink */
1523 #define LED_VAL_LINKON_RECV             0xB /* Link on, receive blink */
1524 #define LED_VAL_DUPLEXFULL_COLLISION    0xC /* Duplex on, collision blink */
1525 #define LED_VAL_BLINK                   0xD
1526 #define LED_VAL_ON                      0xE
1527 #define LED_VAL_OFF                     0xF
1528
1529 #define LED_LINK_SHIFT                  12
1530 #define LED_TXRX_SHIFT                  8
1531 #define LED_100TX_SHIFT                 4
1532
1533 /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */