2 * FBTFT driver for the RA8875 LCD Controller
3 * Copyright by Pf@nne & NOTRO
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
21 #include <linux/gpio.h>
24 #define DRVNAME "fb_ra8875"
26 static int write_spi(struct fbtft_par
*par
, void *buf
, size_t len
)
28 struct spi_transfer t
= {
35 fbtft_par_dbg_hex(DEBUG_WRITE
, par
, par
->info
->device
, u8
, buf
, len
,
36 "%s(len=%d): ", __func__
, len
);
39 dev_err(par
->info
->device
,
40 "%s: par->spi is unexpectedly NULL\n", __func__
);
45 if (par
->txbuf
.dma
&& buf
== par
->txbuf
.buf
) {
46 t
.tx_dma
= par
->txbuf
.dma
;
49 spi_message_add_tail(&t
, &m
);
50 return spi_sync(par
->spi
, &m
);
53 static int init_display(struct fbtft_par
*par
)
55 gpio_set_value(par
->gpio
.dc
, 1);
57 fbtft_par_dbg(DEBUG_INIT_DISPLAY
, par
,
59 fbtft_par_dbg(DEBUG_INIT_DISPLAY
, par
,
60 "display size %dx%d\n",
64 par
->fbtftops
.reset(par
);
66 if ((par
->info
->var
.xres
== 320) && (par
->info
->var
.yres
== 240)) {
67 /* PLL clock frequency */
68 write_reg(par
, 0x88, 0x0A);
69 write_reg(par
, 0x89, 0x02);
71 /* color deep / MCU Interface */
72 write_reg(par
, 0x10, 0x0C);
73 /* pixel clock period */
74 write_reg(par
, 0x04, 0x03);
76 /* horizontal settings */
77 write_reg(par
, 0x14, 0x27);
78 write_reg(par
, 0x15, 0x00);
79 write_reg(par
, 0x16, 0x05);
80 write_reg(par
, 0x17, 0x04);
81 write_reg(par
, 0x18, 0x03);
82 /* vertical settings */
83 write_reg(par
, 0x19, 0xEF);
84 write_reg(par
, 0x1A, 0x00);
85 write_reg(par
, 0x1B, 0x05);
86 write_reg(par
, 0x1C, 0x00);
87 write_reg(par
, 0x1D, 0x0E);
88 write_reg(par
, 0x1E, 0x00);
89 write_reg(par
, 0x1F, 0x02);
90 } else if ((par
->info
->var
.xres
== 480) &&
91 (par
->info
->var
.yres
== 272)) {
92 /* PLL clock frequency */
93 write_reg(par
, 0x88, 0x0A);
94 write_reg(par
, 0x89, 0x02);
96 /* color deep / MCU Interface */
97 write_reg(par
, 0x10, 0x0C);
98 /* pixel clock period */
99 write_reg(par
, 0x04, 0x82);
101 /* horizontal settings */
102 write_reg(par
, 0x14, 0x3B);
103 write_reg(par
, 0x15, 0x00);
104 write_reg(par
, 0x16, 0x01);
105 write_reg(par
, 0x17, 0x00);
106 write_reg(par
, 0x18, 0x05);
107 /* vertical settings */
108 write_reg(par
, 0x19, 0x0F);
109 write_reg(par
, 0x1A, 0x01);
110 write_reg(par
, 0x1B, 0x02);
111 write_reg(par
, 0x1C, 0x00);
112 write_reg(par
, 0x1D, 0x07);
113 write_reg(par
, 0x1E, 0x00);
114 write_reg(par
, 0x1F, 0x09);
115 } else if ((par
->info
->var
.xres
== 640) &&
116 (par
->info
->var
.yres
== 480)) {
117 /* PLL clock frequency */
118 write_reg(par
, 0x88, 0x0B);
119 write_reg(par
, 0x89, 0x02);
121 /* color deep / MCU Interface */
122 write_reg(par
, 0x10, 0x0C);
123 /* pixel clock period */
124 write_reg(par
, 0x04, 0x01);
126 /* horizontal settings */
127 write_reg(par
, 0x14, 0x4F);
128 write_reg(par
, 0x15, 0x05);
129 write_reg(par
, 0x16, 0x0F);
130 write_reg(par
, 0x17, 0x01);
131 write_reg(par
, 0x18, 0x00);
132 /* vertical settings */
133 write_reg(par
, 0x19, 0xDF);
134 write_reg(par
, 0x1A, 0x01);
135 write_reg(par
, 0x1B, 0x0A);
136 write_reg(par
, 0x1C, 0x00);
137 write_reg(par
, 0x1D, 0x0E);
138 write_reg(par
, 0x1E, 0x00);
139 write_reg(par
, 0x1F, 0x01);
140 } else if ((par
->info
->var
.xres
== 800) &&
141 (par
->info
->var
.yres
== 480)) {
142 /* PLL clock frequency */
143 write_reg(par
, 0x88, 0x0B);
144 write_reg(par
, 0x89, 0x02);
146 /* color deep / MCU Interface */
147 write_reg(par
, 0x10, 0x0C);
148 /* pixel clock period */
149 write_reg(par
, 0x04, 0x81);
151 /* horizontal settings */
152 write_reg(par
, 0x14, 0x63);
153 write_reg(par
, 0x15, 0x03);
154 write_reg(par
, 0x16, 0x03);
155 write_reg(par
, 0x17, 0x02);
156 write_reg(par
, 0x18, 0x00);
157 /* vertical settings */
158 write_reg(par
, 0x19, 0xDF);
159 write_reg(par
, 0x1A, 0x01);
160 write_reg(par
, 0x1B, 0x14);
161 write_reg(par
, 0x1C, 0x00);
162 write_reg(par
, 0x1D, 0x06);
163 write_reg(par
, 0x1E, 0x00);
164 write_reg(par
, 0x1F, 0x01);
166 dev_err(par
->info
->device
, "display size is not supported!!");
171 write_reg(par
, 0x8a, 0x81);
172 write_reg(par
, 0x8b, 0xFF);
176 write_reg(par
, 0x01, 0x80);
182 static void set_addr_win(struct fbtft_par
*par
, int xs
, int ys
, int xe
, int ye
)
184 /* Set_Active_Window */
185 write_reg(par
, 0x30, xs
& 0x00FF);
186 write_reg(par
, 0x31, (xs
& 0xFF00) >> 8);
187 write_reg(par
, 0x32, ys
& 0x00FF);
188 write_reg(par
, 0x33, (ys
& 0xFF00) >> 8);
189 write_reg(par
, 0x34, (xs
+ xe
) & 0x00FF);
190 write_reg(par
, 0x35, ((xs
+ xe
) & 0xFF00) >> 8);
191 write_reg(par
, 0x36, (ys
+ ye
) & 0x00FF);
192 write_reg(par
, 0x37, ((ys
+ ye
) & 0xFF00) >> 8);
194 /* Set_Memory_Write_Cursor */
195 write_reg(par
, 0x46, xs
& 0xff);
196 write_reg(par
, 0x47, (xs
>> 8) & 0x03);
197 write_reg(par
, 0x48, ys
& 0xff);
198 write_reg(par
, 0x49, (ys
>> 8) & 0x01);
200 write_reg(par
, 0x02);
203 static void write_reg8_bus8(struct fbtft_par
*par
, int len
, ...)
209 /* slow down spi-speed for writing registers */
210 par
->fbtftops
.write
= write_spi
;
212 if (unlikely(par
->debug
& DEBUG_WRITE_REGISTER
)) {
214 for (i
= 0; i
< len
; i
++)
215 buf
[i
] = (u8
)va_arg(args
, unsigned int);
217 fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER
, par
, par
->info
->device
,
218 u8
, buf
, len
, "%s: ", __func__
);
223 *buf
= (u8
)va_arg(args
, unsigned int);
224 ret
= par
->fbtftops
.write(par
, par
->buf
, 2);
227 dev_err(par
->info
->device
, "write() failed and returned %dn",
236 buf
= (u8
*)par
->buf
;
240 *buf
++ = (u8
)va_arg(args
, unsigned int);
242 ret
= par
->fbtftops
.write(par
, par
->buf
, len
+ 1);
245 dev_err(par
->info
->device
,
246 "write() failed and returned %dn", ret
);
252 /* restore user spi-speed */
253 par
->fbtftops
.write
= fbtft_write_spi
;
257 static int write_vmem16_bus8(struct fbtft_par
*par
, size_t offset
, size_t len
)
260 u16
*txbuf16
= par
->txbuf
.buf
;
263 size_t tx_array_size
;
266 size_t startbyte_size
= 0;
268 fbtft_par_dbg(DEBUG_WRITE_VMEM
, par
, "%s(offset=%zu, len=%zu)\n",
269 __func__
, offset
, len
);
272 vmem16
= (u16
*)(par
->info
->screen_buffer
+ offset
);
273 tx_array_size
= par
->txbuf
.len
/ 2;
274 txbuf16
= par
->txbuf
.buf
+ 1;
276 *(u8
*)(par
->txbuf
.buf
) = 0x00;
280 to_copy
= min(tx_array_size
, remain
);
281 dev_dbg(par
->info
->device
, " to_copy=%zu, remain=%zu\n",
282 to_copy
, remain
- to_copy
);
284 for (i
= 0; i
< to_copy
; i
++)
285 txbuf16
[i
] = cpu_to_be16(vmem16
[i
]);
287 vmem16
= vmem16
+ to_copy
;
288 ret
= par
->fbtftops
.write(par
, par
->txbuf
.buf
,
289 startbyte_size
+ to_copy
* 2);
298 static struct fbtft_display display
= {
301 .init_display
= init_display
,
302 .set_addr_win
= set_addr_win
,
303 .write_register
= write_reg8_bus8
,
304 .write_vmem
= write_vmem16_bus8
,
309 FBTFT_REGISTER_DRIVER(DRVNAME
, "raio,ra8875", &display
);
311 MODULE_ALIAS("spi:" DRVNAME
);
312 MODULE_ALIAS("platform:" DRVNAME
);
313 MODULE_ALIAS("spi:ra8875");
314 MODULE_ALIAS("platform:ra8875");
316 MODULE_DESCRIPTION("FB driver for the RA8875 LCD Controller");
317 MODULE_AUTHOR("Pf@nne");
318 MODULE_LICENSE("GPL");
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