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85659613ae624e38d58e303c6fa5a36a80fcda25
[deliverable/linux.git] / drivers / staging / gma500 / psb_intel_display.c
1 /*
2 * Copyright © 2006-2011 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 * Authors:
18 * Eric Anholt <eric@anholt.net>
19 */
20
21 #include <linux/i2c.h>
22 #include <linux/pm_runtime.h>
23
24 #include <drm/drmP.h>
25 #include "framebuffer.h"
26 #include "psb_drv.h"
27 #include "psb_intel_drv.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_display.h"
30 #include "power.h"
31
32 #include "mdfld_output.h"
33
34 struct psb_intel_clock_t {
35 /* given values */
36 int n;
37 int m1, m2;
38 int p1, p2;
39 /* derived values */
40 int dot;
41 int vco;
42 int m;
43 int p;
44 };
45
46 struct psb_intel_range_t {
47 int min, max;
48 };
49
50 struct psb_intel_p2_t {
51 int dot_limit;
52 int p2_slow, p2_fast;
53 };
54
55 #define INTEL_P2_NUM 2
56
57 struct psb_intel_limit_t {
58 struct psb_intel_range_t dot, vco, n, m, m1, m2, p, p1;
59 struct psb_intel_p2_t p2;
60 };
61
62 #define I8XX_DOT_MIN 25000
63 #define I8XX_DOT_MAX 350000
64 #define I8XX_VCO_MIN 930000
65 #define I8XX_VCO_MAX 1400000
66 #define I8XX_N_MIN 3
67 #define I8XX_N_MAX 16
68 #define I8XX_M_MIN 96
69 #define I8XX_M_MAX 140
70 #define I8XX_M1_MIN 18
71 #define I8XX_M1_MAX 26
72 #define I8XX_M2_MIN 6
73 #define I8XX_M2_MAX 16
74 #define I8XX_P_MIN 4
75 #define I8XX_P_MAX 128
76 #define I8XX_P1_MIN 2
77 #define I8XX_P1_MAX 33
78 #define I8XX_P1_LVDS_MIN 1
79 #define I8XX_P1_LVDS_MAX 6
80 #define I8XX_P2_SLOW 4
81 #define I8XX_P2_FAST 2
82 #define I8XX_P2_LVDS_SLOW 14
83 #define I8XX_P2_LVDS_FAST 14 /* No fast option */
84 #define I8XX_P2_SLOW_LIMIT 165000
85
86 #define I9XX_DOT_MIN 20000
87 #define I9XX_DOT_MAX 400000
88 #define I9XX_VCO_MIN 1400000
89 #define I9XX_VCO_MAX 2800000
90 #define I9XX_N_MIN 3
91 #define I9XX_N_MAX 8
92 #define I9XX_M_MIN 70
93 #define I9XX_M_MAX 120
94 #define I9XX_M1_MIN 10
95 #define I9XX_M1_MAX 20
96 #define I9XX_M2_MIN 5
97 #define I9XX_M2_MAX 9
98 #define I9XX_P_SDVO_DAC_MIN 5
99 #define I9XX_P_SDVO_DAC_MAX 80
100 #define I9XX_P_LVDS_MIN 7
101 #define I9XX_P_LVDS_MAX 98
102 #define I9XX_P1_MIN 1
103 #define I9XX_P1_MAX 8
104 #define I9XX_P2_SDVO_DAC_SLOW 10
105 #define I9XX_P2_SDVO_DAC_FAST 5
106 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
107 #define I9XX_P2_LVDS_SLOW 14
108 #define I9XX_P2_LVDS_FAST 7
109 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
110
111 #define INTEL_LIMIT_I8XX_DVO_DAC 0
112 #define INTEL_LIMIT_I8XX_LVDS 1
113 #define INTEL_LIMIT_I9XX_SDVO_DAC 2
114 #define INTEL_LIMIT_I9XX_LVDS 3
115
116 static const struct psb_intel_limit_t psb_intel_limits[] = {
117 { /* INTEL_LIMIT_I8XX_DVO_DAC */
118 .dot = {.min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX},
119 .vco = {.min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX},
120 .n = {.min = I8XX_N_MIN, .max = I8XX_N_MAX},
121 .m = {.min = I8XX_M_MIN, .max = I8XX_M_MAX},
122 .m1 = {.min = I8XX_M1_MIN, .max = I8XX_M1_MAX},
123 .m2 = {.min = I8XX_M2_MIN, .max = I8XX_M2_MAX},
124 .p = {.min = I8XX_P_MIN, .max = I8XX_P_MAX},
125 .p1 = {.min = I8XX_P1_MIN, .max = I8XX_P1_MAX},
126 .p2 = {.dot_limit = I8XX_P2_SLOW_LIMIT,
127 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST},
128 },
129 { /* INTEL_LIMIT_I8XX_LVDS */
130 .dot = {.min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX},
131 .vco = {.min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX},
132 .n = {.min = I8XX_N_MIN, .max = I8XX_N_MAX},
133 .m = {.min = I8XX_M_MIN, .max = I8XX_M_MAX},
134 .m1 = {.min = I8XX_M1_MIN, .max = I8XX_M1_MAX},
135 .m2 = {.min = I8XX_M2_MIN, .max = I8XX_M2_MAX},
136 .p = {.min = I8XX_P_MIN, .max = I8XX_P_MAX},
137 .p1 = {.min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX},
138 .p2 = {.dot_limit = I8XX_P2_SLOW_LIMIT,
139 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST},
140 },
141 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
142 .dot = {.min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
143 .vco = {.min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX},
144 .n = {.min = I9XX_N_MIN, .max = I9XX_N_MAX},
145 .m = {.min = I9XX_M_MIN, .max = I9XX_M_MAX},
146 .m1 = {.min = I9XX_M1_MIN, .max = I9XX_M1_MAX},
147 .m2 = {.min = I9XX_M2_MIN, .max = I9XX_M2_MAX},
148 .p = {.min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX},
149 .p1 = {.min = I9XX_P1_MIN, .max = I9XX_P1_MAX},
150 .p2 = {.dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
151 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast =
152 I9XX_P2_SDVO_DAC_FAST},
153 },
154 { /* INTEL_LIMIT_I9XX_LVDS */
155 .dot = {.min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
156 .vco = {.min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX},
157 .n = {.min = I9XX_N_MIN, .max = I9XX_N_MAX},
158 .m = {.min = I9XX_M_MIN, .max = I9XX_M_MAX},
159 .m1 = {.min = I9XX_M1_MIN, .max = I9XX_M1_MAX},
160 .m2 = {.min = I9XX_M2_MIN, .max = I9XX_M2_MAX},
161 .p = {.min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX},
162 .p1 = {.min = I9XX_P1_MIN, .max = I9XX_P1_MAX},
163 /* The single-channel range is 25-112Mhz, and dual-channel
164 * is 80-224Mhz. Prefer single channel as much as possible.
165 */
166 .p2 = {.dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
167 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST},
168 },
169 };
170
171 static const struct psb_intel_limit_t *psb_intel_limit(struct drm_crtc *crtc)
172 {
173 const struct psb_intel_limit_t *limit;
174
175 if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
176 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
177 else
178 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
179 return limit;
180 }
181
182 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
183
184 static void i8xx_clock(int refclk, struct psb_intel_clock_t *clock)
185 {
186 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
187 clock->p = clock->p1 * clock->p2;
188 clock->vco = refclk * clock->m / (clock->n + 2);
189 clock->dot = clock->vco / clock->p;
190 }
191
192 /** Derive the pixel clock for the given refclk and divisors for 9xx chips. */
193
194 static void i9xx_clock(int refclk, struct psb_intel_clock_t *clock)
195 {
196 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
197 clock->p = clock->p1 * clock->p2;
198 clock->vco = refclk * clock->m / (clock->n + 2);
199 clock->dot = clock->vco / clock->p;
200 }
201
202 static void psb_intel_clock(struct drm_device *dev, int refclk,
203 struct psb_intel_clock_t *clock)
204 {
205 return i9xx_clock(refclk, clock);
206 }
207
208 /**
209 * Returns whether any output on the specified pipe is of the specified type
210 */
211 bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type)
212 {
213 struct drm_device *dev = crtc->dev;
214 struct drm_mode_config *mode_config = &dev->mode_config;
215 struct drm_connector *l_entry;
216
217 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
218 if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
219 struct psb_intel_output *psb_intel_output =
220 to_psb_intel_output(l_entry);
221 if (psb_intel_output->type == type)
222 return true;
223 }
224 }
225 return false;
226 }
227
228 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
229 /**
230 * Returns whether the given set of divisors are valid for a given refclk with
231 * the given connectors.
232 */
233
234 static bool psb_intel_PLL_is_valid(struct drm_crtc *crtc,
235 struct psb_intel_clock_t *clock)
236 {
237 const struct psb_intel_limit_t *limit = psb_intel_limit(crtc);
238
239 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
240 INTELPllInvalid("p1 out of range\n");
241 if (clock->p < limit->p.min || limit->p.max < clock->p)
242 INTELPllInvalid("p out of range\n");
243 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
244 INTELPllInvalid("m2 out of range\n");
245 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
246 INTELPllInvalid("m1 out of range\n");
247 if (clock->m1 <= clock->m2)
248 INTELPllInvalid("m1 <= m2\n");
249 if (clock->m < limit->m.min || limit->m.max < clock->m)
250 INTELPllInvalid("m out of range\n");
251 if (clock->n < limit->n.min || limit->n.max < clock->n)
252 INTELPllInvalid("n out of range\n");
253 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
254 INTELPllInvalid("vco out of range\n");
255 /* XXX: We may need to be checking "Dot clock"
256 * depending on the multiplier, connector, etc.,
257 * rather than just a single range.
258 */
259 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
260 INTELPllInvalid("dot out of range\n");
261
262 return true;
263 }
264
265 /**
266 * Returns a set of divisors for the desired target clock with the given
267 * refclk, or FALSE. The returned values represent the clock equation:
268 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
269 */
270 static bool psb_intel_find_best_PLL(struct drm_crtc *crtc, int target,
271 int refclk,
272 struct psb_intel_clock_t *best_clock)
273 {
274 struct drm_device *dev = crtc->dev;
275 struct psb_intel_clock_t clock;
276 const struct psb_intel_limit_t *limit = psb_intel_limit(crtc);
277 int err = target;
278
279 if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
280 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
281 /*
282 * For LVDS, if the panel is on, just rely on its current
283 * settings for dual-channel. We haven't figured out how to
284 * reliably set up different single/dual channel state, if we
285 * even can.
286 */
287 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
288 LVDS_CLKB_POWER_UP)
289 clock.p2 = limit->p2.p2_fast;
290 else
291 clock.p2 = limit->p2.p2_slow;
292 } else {
293 if (target < limit->p2.dot_limit)
294 clock.p2 = limit->p2.p2_slow;
295 else
296 clock.p2 = limit->p2.p2_fast;
297 }
298
299 memset(best_clock, 0, sizeof(*best_clock));
300
301 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
302 clock.m1++) {
303 for (clock.m2 = limit->m2.min;
304 clock.m2 < clock.m1 && clock.m2 <= limit->m2.max;
305 clock.m2++) {
306 for (clock.n = limit->n.min;
307 clock.n <= limit->n.max; clock.n++) {
308 for (clock.p1 = limit->p1.min;
309 clock.p1 <= limit->p1.max;
310 clock.p1++) {
311 int this_err;
312
313 psb_intel_clock(dev, refclk, &clock);
314
315 if (!psb_intel_PLL_is_valid
316 (crtc, &clock))
317 continue;
318
319 this_err = abs(clock.dot - target);
320 if (this_err < err) {
321 *best_clock = clock;
322 err = this_err;
323 }
324 }
325 }
326 }
327 }
328
329 return err != target;
330 }
331
332 void psb_intel_wait_for_vblank(struct drm_device *dev)
333 {
334 /* Wait for 20ms, i.e. one cycle at 50hz. */
335 mdelay(20);
336 }
337
338 int psb_intel_pipe_set_base(struct drm_crtc *crtc,
339 int x, int y, struct drm_framebuffer *old_fb)
340 {
341 struct drm_device *dev = crtc->dev;
342 /* struct drm_i915_master_private *master_priv; */
343 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
344 struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
345 int pipe = psb_intel_crtc->pipe;
346 unsigned long start, offset;
347 int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
348 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
349 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
350 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
351 u32 dspcntr;
352 int ret = 0;
353
354 if (!gma_power_begin(dev, true))
355 return 0;
356
357 /* no fb bound */
358 if (!crtc->fb) {
359 dev_dbg(dev->dev, "No FB bound\n");
360 goto psb_intel_pipe_cleaner;
361 }
362
363 /* We are displaying this buffer, make sure it is actually loaded
364 into the GTT */
365 ret = psb_gtt_pin(psbfb->gtt);
366 if (ret < 0)
367 goto psb_intel_pipe_set_base_exit;
368 start = psbfb->gtt->offset;
369
370 offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
371
372 REG_WRITE(dspstride, crtc->fb->pitches[0]);
373
374 dspcntr = REG_READ(dspcntr_reg);
375 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
376
377 switch (crtc->fb->bits_per_pixel) {
378 case 8:
379 dspcntr |= DISPPLANE_8BPP;
380 break;
381 case 16:
382 if (crtc->fb->depth == 15)
383 dspcntr |= DISPPLANE_15_16BPP;
384 else
385 dspcntr |= DISPPLANE_16BPP;
386 break;
387 case 24:
388 case 32:
389 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
390 break;
391 default:
392 dev_err(dev->dev, "Unknown color depth\n");
393 ret = -EINVAL;
394 psb_gtt_unpin(psbfb->gtt);
395 goto psb_intel_pipe_set_base_exit;
396 }
397 REG_WRITE(dspcntr_reg, dspcntr);
398
399
400 if (0 /* FIXMEAC - check what PSB needs */) {
401 REG_WRITE(dspbase, offset);
402 REG_READ(dspbase);
403 REG_WRITE(dspsurf, start);
404 REG_READ(dspsurf);
405 } else {
406 REG_WRITE(dspbase, start + offset);
407 REG_READ(dspbase);
408 }
409
410 psb_intel_pipe_cleaner:
411 /* If there was a previous display we can now unpin it */
412 if (old_fb)
413 psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
414
415 psb_intel_pipe_set_base_exit:
416 gma_power_end(dev);
417 return ret;
418 }
419
420 /**
421 * Sets the power management mode of the pipe and plane.
422 *
423 * This code should probably grow support for turning the cursor off and back
424 * on appropriately at the same time as we're turning the pipe off/on.
425 */
426 static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
427 {
428 struct drm_device *dev = crtc->dev;
429 /* struct drm_i915_master_private *master_priv; */
430 /* struct drm_i915_private *dev_priv = dev->dev_private; */
431 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
432 int pipe = psb_intel_crtc->pipe;
433 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
434 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
435 int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE;
436 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
437 u32 temp;
438 bool enabled;
439
440 /* XXX: When our outputs are all unaware of DPMS modes other than off
441 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
442 */
443 switch (mode) {
444 case DRM_MODE_DPMS_ON:
445 case DRM_MODE_DPMS_STANDBY:
446 case DRM_MODE_DPMS_SUSPEND:
447 /* Enable the DPLL */
448 temp = REG_READ(dpll_reg);
449 if ((temp & DPLL_VCO_ENABLE) == 0) {
450 REG_WRITE(dpll_reg, temp);
451 REG_READ(dpll_reg);
452 /* Wait for the clocks to stabilize. */
453 udelay(150);
454 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
455 REG_READ(dpll_reg);
456 /* Wait for the clocks to stabilize. */
457 udelay(150);
458 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
459 REG_READ(dpll_reg);
460 /* Wait for the clocks to stabilize. */
461 udelay(150);
462 }
463
464 /* Enable the pipe */
465 temp = REG_READ(pipeconf_reg);
466 if ((temp & PIPEACONF_ENABLE) == 0)
467 REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
468
469 /* Enable the plane */
470 temp = REG_READ(dspcntr_reg);
471 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
472 REG_WRITE(dspcntr_reg,
473 temp | DISPLAY_PLANE_ENABLE);
474 /* Flush the plane changes */
475 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
476 }
477
478 psb_intel_crtc_load_lut(crtc);
479
480 /* Give the overlay scaler a chance to enable
481 * if it's on this pipe */
482 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
483 break;
484 case DRM_MODE_DPMS_OFF:
485 /* Give the overlay scaler a chance to disable
486 * if it's on this pipe */
487 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
488
489 /* Disable the VGA plane that we never use */
490 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
491
492 /* Disable display plane */
493 temp = REG_READ(dspcntr_reg);
494 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
495 REG_WRITE(dspcntr_reg,
496 temp & ~DISPLAY_PLANE_ENABLE);
497 /* Flush the plane changes */
498 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
499 REG_READ(dspbase_reg);
500 }
501
502 /* Next, disable display pipes */
503 temp = REG_READ(pipeconf_reg);
504 if ((temp & PIPEACONF_ENABLE) != 0) {
505 REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
506 REG_READ(pipeconf_reg);
507 }
508
509 /* Wait for vblank for the disable to take effect. */
510 psb_intel_wait_for_vblank(dev);
511
512 temp = REG_READ(dpll_reg);
513 if ((temp & DPLL_VCO_ENABLE) != 0) {
514 REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
515 REG_READ(dpll_reg);
516 }
517
518 /* Wait for the clocks to turn off. */
519 udelay(150);
520 break;
521 }
522
523 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
524
525 /*Set FIFO Watermarks*/
526 REG_WRITE(DSPARB, 0x3F3E);
527 }
528
529 static void psb_intel_crtc_prepare(struct drm_crtc *crtc)
530 {
531 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
532 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
533 }
534
535 static void psb_intel_crtc_commit(struct drm_crtc *crtc)
536 {
537 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
538 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
539 }
540
541 void psb_intel_encoder_prepare(struct drm_encoder *encoder)
542 {
543 struct drm_encoder_helper_funcs *encoder_funcs =
544 encoder->helper_private;
545 /* lvds has its own version of prepare see psb_intel_lvds_prepare */
546 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
547 }
548
549 void psb_intel_encoder_commit(struct drm_encoder *encoder)
550 {
551 struct drm_encoder_helper_funcs *encoder_funcs =
552 encoder->helper_private;
553 /* lvds has its own version of commit see psb_intel_lvds_commit */
554 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
555 }
556
557 static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc,
558 struct drm_display_mode *mode,
559 struct drm_display_mode *adjusted_mode)
560 {
561 return true;
562 }
563
564
565 /**
566 * Return the pipe currently connected to the panel fitter,
567 * or -1 if the panel fitter is not present or not in use
568 */
569 static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
570 {
571 u32 pfit_control;
572
573 pfit_control = REG_READ(PFIT_CONTROL);
574
575 /* See if the panel fitter is in use */
576 if ((pfit_control & PFIT_ENABLE) == 0)
577 return -1;
578 /* Must be on PIPE 1 for PSB */
579 return 1;
580 }
581
582 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
583 struct drm_display_mode *mode,
584 struct drm_display_mode *adjusted_mode,
585 int x, int y,
586 struct drm_framebuffer *old_fb)
587 {
588 struct drm_device *dev = crtc->dev;
589 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
590 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
591 int pipe = psb_intel_crtc->pipe;
592 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
593 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
594 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
595 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
596 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
597 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
598 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
599 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
600 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
601 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
602 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
603 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
604 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
605 int refclk;
606 struct psb_intel_clock_t clock;
607 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
608 bool ok, is_sdvo = false, is_dvo = false;
609 bool is_crt = false, is_lvds = false, is_tv = false;
610 struct drm_mode_config *mode_config = &dev->mode_config;
611 struct drm_connector *connector;
612
613 /* No scan out no play */
614 if (crtc->fb == NULL) {
615 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
616 return 0;
617 }
618
619 list_for_each_entry(connector, &mode_config->connector_list, head) {
620 struct psb_intel_output *psb_intel_output =
621 to_psb_intel_output(connector);
622
623 if (!connector->encoder
624 || connector->encoder->crtc != crtc)
625 continue;
626
627 switch (psb_intel_output->type) {
628 case INTEL_OUTPUT_LVDS:
629 is_lvds = true;
630 break;
631 case INTEL_OUTPUT_SDVO:
632 is_sdvo = true;
633 break;
634 case INTEL_OUTPUT_DVO:
635 is_dvo = true;
636 break;
637 case INTEL_OUTPUT_TVOUT:
638 is_tv = true;
639 break;
640 case INTEL_OUTPUT_ANALOG:
641 is_crt = true;
642 break;
643 }
644 }
645
646 refclk = 96000;
647
648 ok = psb_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk,
649 &clock);
650 if (!ok) {
651 dev_err(dev->dev, "Couldn't find PLL settings for mode!\n");
652 return 0;
653 }
654
655 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
656
657 dpll = DPLL_VGA_MODE_DIS;
658 if (is_lvds) {
659 dpll |= DPLLB_MODE_LVDS;
660 dpll |= DPLL_DVO_HIGH_SPEED;
661 } else
662 dpll |= DPLLB_MODE_DAC_SERIAL;
663 if (is_sdvo) {
664 int sdvo_pixel_multiply =
665 adjusted_mode->clock / mode->clock;
666 dpll |= DPLL_DVO_HIGH_SPEED;
667 dpll |=
668 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
669 }
670
671 /* compute bitmask from p1 value */
672 dpll |= (1 << (clock.p1 - 1)) << 16;
673 switch (clock.p2) {
674 case 5:
675 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
676 break;
677 case 7:
678 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
679 break;
680 case 10:
681 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
682 break;
683 case 14:
684 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
685 break;
686 }
687
688 if (is_tv) {
689 /* XXX: just matching BIOS for now */
690 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
691 dpll |= 3;
692 }
693 dpll |= PLL_REF_INPUT_DREFCLK;
694
695 /* setup pipeconf */
696 pipeconf = REG_READ(pipeconf_reg);
697
698 /* Set up the display plane register */
699 dspcntr = DISPPLANE_GAMMA_ENABLE;
700
701 if (pipe == 0)
702 dspcntr |= DISPPLANE_SEL_PIPE_A;
703 else
704 dspcntr |= DISPPLANE_SEL_PIPE_B;
705
706 dspcntr |= DISPLAY_PLANE_ENABLE;
707 pipeconf |= PIPEACONF_ENABLE;
708 dpll |= DPLL_VCO_ENABLE;
709
710
711 /* Disable the panel fitter if it was on our pipe */
712 if (psb_intel_panel_fitter_pipe(dev) == pipe)
713 REG_WRITE(PFIT_CONTROL, 0);
714
715 drm_mode_debug_printmodeline(mode);
716
717 if (dpll & DPLL_VCO_ENABLE) {
718 REG_WRITE(fp_reg, fp);
719 REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
720 REG_READ(dpll_reg);
721 udelay(150);
722 }
723
724 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
725 * This is an exception to the general rule that mode_set doesn't turn
726 * things on.
727 */
728 if (is_lvds) {
729 u32 lvds = REG_READ(LVDS);
730
731 lvds &= ~LVDS_PIPEB_SELECT;
732 if (pipe == 1)
733 lvds |= LVDS_PIPEB_SELECT;
734
735 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
736 /* Set the B0-B3 data pairs corresponding to
737 * whether we're going to
738 * set the DPLLs for dual-channel mode or not.
739 */
740 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
741 if (clock.p2 == 7)
742 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
743
744 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
745 * appropriately here, but we need to look more
746 * thoroughly into how panels behave in the two modes.
747 */
748
749 REG_WRITE(LVDS, lvds);
750 REG_READ(LVDS);
751 }
752
753 REG_WRITE(fp_reg, fp);
754 REG_WRITE(dpll_reg, dpll);
755 REG_READ(dpll_reg);
756 /* Wait for the clocks to stabilize. */
757 udelay(150);
758
759 /* write it again -- the BIOS does, after all */
760 REG_WRITE(dpll_reg, dpll);
761
762 REG_READ(dpll_reg);
763 /* Wait for the clocks to stabilize. */
764 udelay(150);
765
766 REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
767 ((adjusted_mode->crtc_htotal - 1) << 16));
768 REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
769 ((adjusted_mode->crtc_hblank_end - 1) << 16));
770 REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
771 ((adjusted_mode->crtc_hsync_end - 1) << 16));
772 REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
773 ((adjusted_mode->crtc_vtotal - 1) << 16));
774 REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
775 ((adjusted_mode->crtc_vblank_end - 1) << 16));
776 REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
777 ((adjusted_mode->crtc_vsync_end - 1) << 16));
778 /* pipesrc and dspsize control the size that is scaled from,
779 * which should always be the user's requested size.
780 */
781 REG_WRITE(dspsize_reg,
782 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
783 REG_WRITE(dsppos_reg, 0);
784 REG_WRITE(pipesrc_reg,
785 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
786 REG_WRITE(pipeconf_reg, pipeconf);
787 REG_READ(pipeconf_reg);
788
789 psb_intel_wait_for_vblank(dev);
790
791 REG_WRITE(dspcntr_reg, dspcntr);
792
793 /* Flush the plane changes */
794 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
795
796 psb_intel_wait_for_vblank(dev);
797
798 return 0;
799 }
800
801 /** Loads the palette/gamma unit for the CRTC with the prepared values */
802 void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
803 {
804 struct drm_device *dev = crtc->dev;
805 struct drm_psb_private *dev_priv =
806 (struct drm_psb_private *)dev->dev_private;
807 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
808 int palreg = PALETTE_A;
809 int i;
810
811 /* The clocks have to be on to load the palette. */
812 if (!crtc->enabled)
813 return;
814
815 switch (psb_intel_crtc->pipe) {
816 case 0:
817 break;
818 case 1:
819 palreg = PALETTE_B;
820 break;
821 case 2:
822 palreg = PALETTE_C;
823 break;
824 default:
825 dev_err(dev->dev, "Illegal Pipe Number.\n");
826 return;
827 }
828
829 if (gma_power_begin(dev, false)) {
830 for (i = 0; i < 256; i++) {
831 REG_WRITE(palreg + 4 * i,
832 ((psb_intel_crtc->lut_r[i] +
833 psb_intel_crtc->lut_adj[i]) << 16) |
834 ((psb_intel_crtc->lut_g[i] +
835 psb_intel_crtc->lut_adj[i]) << 8) |
836 (psb_intel_crtc->lut_b[i] +
837 psb_intel_crtc->lut_adj[i]));
838 }
839 gma_power_end(dev);
840 } else {
841 for (i = 0; i < 256; i++) {
842 dev_priv->save_palette_a[i] =
843 ((psb_intel_crtc->lut_r[i] +
844 psb_intel_crtc->lut_adj[i]) << 16) |
845 ((psb_intel_crtc->lut_g[i] +
846 psb_intel_crtc->lut_adj[i]) << 8) |
847 (psb_intel_crtc->lut_b[i] +
848 psb_intel_crtc->lut_adj[i]);
849 }
850
851 }
852 }
853
854 /**
855 * Save HW states of giving crtc
856 */
857 static void psb_intel_crtc_save(struct drm_crtc *crtc)
858 {
859 struct drm_device *dev = crtc->dev;
860 /* struct drm_psb_private *dev_priv =
861 (struct drm_psb_private *)dev->dev_private; */
862 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
863 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
864 int pipeA = (psb_intel_crtc->pipe == 0);
865 uint32_t paletteReg;
866 int i;
867
868 if (!crtc_state) {
869 dev_err(dev->dev, "No CRTC state found\n");
870 return;
871 }
872
873 crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR);
874 crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF);
875 crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC);
876 crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0);
877 crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1);
878 crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B);
879 crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B);
880 crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B);
881 crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B);
882 crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B);
883 crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B);
884 crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B);
885 crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE);
886
887 /*NOTE: DSPSIZE DSPPOS only for psb*/
888 crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE);
889 crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS);
890
891 crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE);
892
893 paletteReg = pipeA ? PALETTE_A : PALETTE_B;
894 for (i = 0; i < 256; ++i)
895 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
896 }
897
898 /**
899 * Restore HW states of giving crtc
900 */
901 static void psb_intel_crtc_restore(struct drm_crtc *crtc)
902 {
903 struct drm_device *dev = crtc->dev;
904 /* struct drm_psb_private * dev_priv =
905 (struct drm_psb_private *)dev->dev_private; */
906 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
907 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
908 /* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */
909 int pipeA = (psb_intel_crtc->pipe == 0);
910 uint32_t paletteReg;
911 int i;
912
913 if (!crtc_state) {
914 dev_err(dev->dev, "No crtc state\n");
915 return;
916 }
917
918 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
919 REG_WRITE(pipeA ? DPLL_A : DPLL_B,
920 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
921 REG_READ(pipeA ? DPLL_A : DPLL_B);
922 udelay(150);
923 }
924
925 REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0);
926 REG_READ(pipeA ? FPA0 : FPB0);
927
928 REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1);
929 REG_READ(pipeA ? FPA1 : FPB1);
930
931 REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL);
932 REG_READ(pipeA ? DPLL_A : DPLL_B);
933 udelay(150);
934
935 REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL);
936 REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK);
937 REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC);
938 REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL);
939 REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK);
940 REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC);
941 REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE);
942
943 REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE);
944 REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS);
945
946 REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC);
947 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
948 REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF);
949
950 psb_intel_wait_for_vblank(dev);
951
952 REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR);
953 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
954
955 psb_intel_wait_for_vblank(dev);
956
957 paletteReg = pipeA ? PALETTE_A : PALETTE_B;
958 for (i = 0; i < 256; ++i)
959 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
960 }
961
962 static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
963 struct drm_file *file_priv,
964 uint32_t handle,
965 uint32_t width, uint32_t height)
966 {
967 struct drm_device *dev = crtc->dev;
968 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
969 int pipe = psb_intel_crtc->pipe;
970 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
971 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
972 uint32_t temp;
973 size_t addr = 0;
974 struct gtt_range *gt;
975 struct drm_gem_object *obj;
976 int ret;
977
978 /* if we want to turn of the cursor ignore width and height */
979 if (!handle) {
980 /* turn off the cursor */
981 temp = CURSOR_MODE_DISABLE;
982
983 if (gma_power_begin(dev, false)) {
984 REG_WRITE(control, temp);
985 REG_WRITE(base, 0);
986 gma_power_end(dev);
987 }
988
989 /* Unpin the old GEM object */
990 if (psb_intel_crtc->cursor_obj) {
991 gt = container_of(psb_intel_crtc->cursor_obj,
992 struct gtt_range, gem);
993 psb_gtt_unpin(gt);
994 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
995 psb_intel_crtc->cursor_obj = NULL;
996 }
997
998 return 0;
999 }
1000
1001 /* Currently we only support 64x64 cursors */
1002 if (width != 64 || height != 64) {
1003 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n");
1004 return -EINVAL;
1005 }
1006
1007 obj = drm_gem_object_lookup(dev, file_priv, handle);
1008 if (!obj)
1009 return -ENOENT;
1010
1011 if (obj->size < width * height * 4) {
1012 dev_dbg(dev->dev, "buffer is to small\n");
1013 return -ENOMEM;
1014 }
1015
1016 gt = container_of(obj, struct gtt_range, gem);
1017
1018 /* Pin the memory into the GTT */
1019 ret = psb_gtt_pin(gt);
1020 if (ret) {
1021 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
1022 return ret;
1023 }
1024
1025
1026 addr = gt->offset; /* Or resource.start ??? */
1027
1028 psb_intel_crtc->cursor_addr = addr;
1029
1030 temp = 0;
1031 /* set the pipe for the cursor */
1032 temp |= (pipe << 28);
1033 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1034
1035 if (gma_power_begin(dev, false)) {
1036 REG_WRITE(control, temp);
1037 REG_WRITE(base, addr);
1038 gma_power_end(dev);
1039 }
1040
1041 /* unpin the old bo */
1042 if (psb_intel_crtc->cursor_obj) {
1043 gt = container_of(psb_intel_crtc->cursor_obj,
1044 struct gtt_range, gem);
1045 psb_gtt_unpin(gt);
1046 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1047 psb_intel_crtc->cursor_obj = obj;
1048 }
1049 return 0;
1050 }
1051
1052 static int psb_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1053 {
1054 struct drm_device *dev = crtc->dev;
1055 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1056 int pipe = psb_intel_crtc->pipe;
1057 uint32_t temp = 0;
1058 uint32_t addr;
1059
1060
1061 if (x < 0) {
1062 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1063 x = -x;
1064 }
1065 if (y < 0) {
1066 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1067 y = -y;
1068 }
1069
1070 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1071 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1072
1073 addr = psb_intel_crtc->cursor_addr;
1074
1075 if (gma_power_begin(dev, false)) {
1076 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1077 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);
1078 gma_power_end(dev);
1079 }
1080 return 0;
1081 }
1082
1083 void psb_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
1084 u16 *green, u16 *blue, uint32_t type, uint32_t size)
1085 {
1086 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1087 int i;
1088
1089 if (size != 256)
1090 return;
1091
1092 for (i = 0; i < 256; i++) {
1093 psb_intel_crtc->lut_r[i] = red[i] >> 8;
1094 psb_intel_crtc->lut_g[i] = green[i] >> 8;
1095 psb_intel_crtc->lut_b[i] = blue[i] >> 8;
1096 }
1097
1098 psb_intel_crtc_load_lut(crtc);
1099 }
1100
1101 static int psb_crtc_set_config(struct drm_mode_set *set)
1102 {
1103 int ret;
1104 struct drm_device *dev = set->crtc->dev;
1105
1106 pm_runtime_forbid(&dev->pdev->dev);
1107 ret = drm_crtc_helper_set_config(set);
1108 pm_runtime_allow(&dev->pdev->dev);
1109 return ret;
1110 }
1111
1112 /* Returns the clock of the currently programmed mode of the given pipe. */
1113 static int psb_intel_crtc_clock_get(struct drm_device *dev,
1114 struct drm_crtc *crtc)
1115 {
1116 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1117 int pipe = psb_intel_crtc->pipe;
1118 u32 dpll;
1119 u32 fp;
1120 struct psb_intel_clock_t clock;
1121 bool is_lvds;
1122 struct drm_psb_private *dev_priv = dev->dev_private;
1123
1124 if (gma_power_begin(dev, false)) {
1125 dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B);
1126 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1127 fp = REG_READ((pipe == 0) ? FPA0 : FPB0);
1128 else
1129 fp = REG_READ((pipe == 0) ? FPA1 : FPB1);
1130 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
1131 gma_power_end(dev);
1132 } else {
1133 dpll = (pipe == 0) ?
1134 dev_priv->saveDPLL_A : dev_priv->saveDPLL_B;
1135
1136 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1137 fp = (pipe == 0) ?
1138 dev_priv->saveFPA0 :
1139 dev_priv->saveFPB0;
1140 else
1141 fp = (pipe == 0) ?
1142 dev_priv->saveFPA1 :
1143 dev_priv->saveFPB1;
1144
1145 is_lvds = (pipe == 1) && (dev_priv->saveLVDS & LVDS_PORT_EN);
1146 }
1147
1148 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1149 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1150 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1151
1152 if (is_lvds) {
1153 clock.p1 =
1154 ffs((dpll &
1155 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1156 DPLL_FPA01_P1_POST_DIV_SHIFT);
1157 clock.p2 = 14;
1158
1159 if ((dpll & PLL_REF_INPUT_MASK) ==
1160 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1161 /* XXX: might not be 66MHz */
1162 i8xx_clock(66000, &clock);
1163 } else
1164 i8xx_clock(48000, &clock);
1165 } else {
1166 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1167 clock.p1 = 2;
1168 else {
1169 clock.p1 =
1170 ((dpll &
1171 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1172 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1173 }
1174 if (dpll & PLL_P2_DIVIDE_BY_4)
1175 clock.p2 = 4;
1176 else
1177 clock.p2 = 2;
1178
1179 i8xx_clock(48000, &clock);
1180 }
1181
1182 /* XXX: It would be nice to validate the clocks, but we can't reuse
1183 * i830PllIsValid() because it relies on the xf86_config connector
1184 * configuration being accurate, which it isn't necessarily.
1185 */
1186
1187 return clock.dot;
1188 }
1189
1190 /** Returns the currently programmed mode of the given pipe. */
1191 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
1192 struct drm_crtc *crtc)
1193 {
1194 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1195 int pipe = psb_intel_crtc->pipe;
1196 struct drm_display_mode *mode;
1197 int htot;
1198 int hsync;
1199 int vtot;
1200 int vsync;
1201 struct drm_psb_private *dev_priv = dev->dev_private;
1202
1203 if (gma_power_begin(dev, false)) {
1204 htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
1205 hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
1206 vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
1207 vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1208 gma_power_end(dev);
1209 } else {
1210 htot = (pipe == 0) ?
1211 dev_priv->saveHTOTAL_A : dev_priv->saveHTOTAL_B;
1212 hsync = (pipe == 0) ?
1213 dev_priv->saveHSYNC_A : dev_priv->saveHSYNC_B;
1214 vtot = (pipe == 0) ?
1215 dev_priv->saveVTOTAL_A : dev_priv->saveVTOTAL_B;
1216 vsync = (pipe == 0) ?
1217 dev_priv->saveVSYNC_A : dev_priv->saveVSYNC_B;
1218 }
1219
1220 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1221 if (!mode)
1222 return NULL;
1223
1224 mode->clock = psb_intel_crtc_clock_get(dev, crtc);
1225 mode->hdisplay = (htot & 0xffff) + 1;
1226 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1227 mode->hsync_start = (hsync & 0xffff) + 1;
1228 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1229 mode->vdisplay = (vtot & 0xffff) + 1;
1230 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1231 mode->vsync_start = (vsync & 0xffff) + 1;
1232 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1233
1234 drm_mode_set_name(mode);
1235 drm_mode_set_crtcinfo(mode, 0);
1236
1237 return mode;
1238 }
1239
1240 void psb_intel_crtc_destroy(struct drm_crtc *crtc)
1241 {
1242 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1243 struct gtt_range *gt;
1244
1245 /* Unpin the old GEM object */
1246 if (psb_intel_crtc->cursor_obj) {
1247 gt = container_of(psb_intel_crtc->cursor_obj,
1248 struct gtt_range, gem);
1249 psb_gtt_unpin(gt);
1250 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1251 psb_intel_crtc->cursor_obj = NULL;
1252 }
1253 kfree(psb_intel_crtc->crtc_state);
1254 drm_crtc_cleanup(crtc);
1255 kfree(psb_intel_crtc);
1256 }
1257
1258 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
1259 .dpms = psb_intel_crtc_dpms,
1260 .mode_fixup = psb_intel_crtc_mode_fixup,
1261 .mode_set = psb_intel_crtc_mode_set,
1262 .mode_set_base = psb_intel_pipe_set_base,
1263 .prepare = psb_intel_crtc_prepare,
1264 .commit = psb_intel_crtc_commit,
1265 };
1266
1267 const struct drm_crtc_funcs psb_intel_crtc_funcs = {
1268 .save = psb_intel_crtc_save,
1269 .restore = psb_intel_crtc_restore,
1270 .cursor_set = psb_intel_crtc_cursor_set,
1271 .cursor_move = psb_intel_crtc_cursor_move,
1272 .gamma_set = psb_intel_crtc_gamma_set,
1273 .set_config = psb_crtc_set_config,
1274 .destroy = psb_intel_crtc_destroy,
1275 };
1276
1277 /*
1278 * Set the default value of cursor control and base register
1279 * to zero. This is a workaround for h/w defect on Oaktrail
1280 */
1281 static void psb_intel_cursor_init(struct drm_device *dev, int pipe)
1282 {
1283 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
1284 u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
1285
1286 REG_WRITE(control[pipe], 0);
1287 REG_WRITE(base[pipe], 0);
1288 }
1289
1290 void psb_intel_crtc_init(struct drm_device *dev, int pipe,
1291 struct psb_intel_mode_device *mode_dev)
1292 {
1293 struct drm_psb_private *dev_priv = dev->dev_private;
1294 struct psb_intel_crtc *psb_intel_crtc;
1295 int i;
1296 uint16_t *r_base, *g_base, *b_base;
1297
1298 /* We allocate a extra array of drm_connector pointers
1299 * for fbdev after the crtc */
1300 psb_intel_crtc =
1301 kzalloc(sizeof(struct psb_intel_crtc) +
1302 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
1303 GFP_KERNEL);
1304 if (psb_intel_crtc == NULL)
1305 return;
1306
1307 psb_intel_crtc->crtc_state =
1308 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
1309 if (!psb_intel_crtc->crtc_state) {
1310 dev_err(dev->dev, "Crtc state error: No memory\n");
1311 kfree(psb_intel_crtc);
1312 return;
1313 }
1314
1315 /* Set the CRTC operations from the chip specific data */
1316 drm_crtc_init(dev, &psb_intel_crtc->base, dev_priv->ops->crtc_funcs);
1317
1318 drm_mode_crtc_set_gamma_size(&psb_intel_crtc->base, 256);
1319 psb_intel_crtc->pipe = pipe;
1320 psb_intel_crtc->plane = pipe;
1321
1322 r_base = psb_intel_crtc->base.gamma_store;
1323 g_base = r_base + 256;
1324 b_base = g_base + 256;
1325 for (i = 0; i < 256; i++) {
1326 psb_intel_crtc->lut_r[i] = i;
1327 psb_intel_crtc->lut_g[i] = i;
1328 psb_intel_crtc->lut_b[i] = i;
1329 r_base[i] = i << 8;
1330 g_base[i] = i << 8;
1331 b_base[i] = i << 8;
1332
1333 psb_intel_crtc->lut_adj[i] = 0;
1334 }
1335
1336 psb_intel_crtc->mode_dev = mode_dev;
1337 psb_intel_crtc->cursor_addr = 0;
1338
1339 drm_crtc_helper_add(&psb_intel_crtc->base,
1340 dev_priv->ops->crtc_helper);
1341
1342 /* Setup the array of drm_connector pointer array */
1343 psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base;
1344 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
1345 dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] != NULL);
1346 dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] =
1347 &psb_intel_crtc->base;
1348 dev_priv->pipe_to_crtc_mapping[psb_intel_crtc->pipe] =
1349 &psb_intel_crtc->base;
1350 psb_intel_crtc->mode_set.connectors =
1351 (struct drm_connector **) (psb_intel_crtc + 1);
1352 psb_intel_crtc->mode_set.num_connectors = 0;
1353 psb_intel_cursor_init(dev, pipe);
1354 }
1355
1356 int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1357 struct drm_file *file_priv)
1358 {
1359 struct drm_psb_private *dev_priv = dev->dev_private;
1360 struct drm_psb_get_pipe_from_crtc_id_arg *pipe_from_crtc_id = data;
1361 struct drm_mode_object *drmmode_obj;
1362 struct psb_intel_crtc *crtc;
1363
1364 if (!dev_priv) {
1365 dev_err(dev->dev, "called with no initialization\n");
1366 return -EINVAL;
1367 }
1368
1369 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
1370 DRM_MODE_OBJECT_CRTC);
1371
1372 if (!drmmode_obj) {
1373 dev_err(dev->dev, "no such CRTC id\n");
1374 return -EINVAL;
1375 }
1376
1377 crtc = to_psb_intel_crtc(obj_to_crtc(drmmode_obj));
1378 pipe_from_crtc_id->pipe = crtc->pipe;
1379
1380 return 0;
1381 }
1382
1383 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
1384 {
1385 struct drm_crtc *crtc = NULL;
1386
1387 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1388 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1389 if (psb_intel_crtc->pipe == pipe)
1390 break;
1391 }
1392 return crtc;
1393 }
1394
1395 int psb_intel_connector_clones(struct drm_device *dev, int type_mask)
1396 {
1397 int index_mask = 0;
1398 struct drm_connector *connector;
1399 int entry = 0;
1400
1401 list_for_each_entry(connector, &dev->mode_config.connector_list,
1402 head) {
1403 struct psb_intel_output *psb_intel_output =
1404 to_psb_intel_output(connector);
1405 if (type_mask & (1 << psb_intel_output->type))
1406 index_mask |= (1 << entry);
1407 entry++;
1408 }
1409 return index_mask;
1410 }
1411
1412
1413 void psb_intel_modeset_cleanup(struct drm_device *dev)
1414 {
1415 drm_mode_config_cleanup(dev);
1416 }
1417
1418
1419 /* current intel driver doesn't take advantage of encoders
1420 always give back the encoder for the connector
1421 */
1422 struct drm_encoder *psb_intel_best_encoder(struct drm_connector *connector)
1423 {
1424 struct psb_intel_output *psb_intel_output =
1425 to_psb_intel_output(connector);
1426
1427 return &psb_intel_output->enc;
1428 }
1429
Linux kernel - Deliverables
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