drivers/staging/iio/accel/lis3l02dq_ring.c

   1 #include <linux/interrupt.h>
   2 #include <linux/gpio.h>
   3 #include <linux/mutex.h>
   4 #include <linux/kernel.h>
   5 #include <linux/spi/spi.h>
   6 #include <linux/slab.h>
   7 #include <linux/export.h>
   8
   9 #include <linux/iio/iio.h>
  10 #include "../ring_sw.h"
  11 #include <linux/iio/kfifo_buf.h>
  12 #include <linux/iio/trigger.h>
  13 #include <linux/iio/trigger_consumer.h>
  14 #include "lis3l02dq.h"
  15
  16 /**
  17  * combine_8_to_16() utility function to munge to u8s into u16
  18  **/
  19 static inline u16 combine_8_to_16(u8 lower, u8 upper)
  20 {
  21         u16 _lower = lower;
  22         u16 _upper = upper;
  23         return _lower | (_upper << 8);
  24 }
  25
  26 /**
  27  * lis3l02dq_data_rdy_trig_poll() the event handler for the data rdy trig
  28  **/
  29 irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private)
  30 {
  31         struct iio_dev *indio_dev = private;
  32         struct lis3l02dq_state *st = iio_priv(indio_dev);
  33
  34         if (st->trigger_on) {
  35                 iio_trigger_poll(st->trig, iio_get_time_ns());
  36                 return IRQ_HANDLED;
  37         } else
  38                 return IRQ_WAKE_THREAD;
  39 }
  40
  41 static const u8 read_all_tx_array[] = {
  42         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_L_ADDR), 0,
  43         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_H_ADDR), 0,
  44         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_L_ADDR), 0,
  45         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_H_ADDR), 0,
  46         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_L_ADDR), 0,
  47         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_H_ADDR), 0,
  48 };
  49
  50 /**
  51  * lis3l02dq_read_all() Reads all channels currently selected
  52  * @st:         device specific state
  53  * @rx_array:   (dma capable) receive array, must be at least
  54  *              4*number of channels
  55  **/
  56 static int lis3l02dq_read_all(struct iio_dev *indio_dev, u8 *rx_array)
  57 {
  58         struct lis3l02dq_state *st = iio_priv(indio_dev);
  59         struct spi_transfer *xfers;
  60         struct spi_message msg;
  61         int ret, i, j = 0;
  62
  63         xfers = kcalloc(bitmap_weight(indio_dev->active_scan_mask,
  64                                       indio_dev->masklength) * 2,
  65                         sizeof(*xfers), GFP_KERNEL);
  66         if (!xfers)
  67                 return -ENOMEM;
  68
  69         mutex_lock(&st->buf_lock);
  70
  71         for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++)
  72                 if (test_bit(i, indio_dev->active_scan_mask)) {
  73                         /* lower byte */
  74                         xfers[j].tx_buf = st->tx + 2*j;
  75                         st->tx[2*j] = read_all_tx_array[i*4];
  76                         st->tx[2*j + 1] = 0;
  77                         if (rx_array)
  78                                 xfers[j].rx_buf = rx_array + j*2;
  79                         xfers[j].bits_per_word = 8;
  80                         xfers[j].len = 2;
  81                         xfers[j].cs_change = 1;
  82                         j++;
  83
  84                         /* upper byte */
  85                         xfers[j].tx_buf = st->tx + 2*j;
  86                         st->tx[2*j] = read_all_tx_array[i*4 + 2];
  87                         st->tx[2*j + 1] = 0;
  88                         if (rx_array)
  89                                 xfers[j].rx_buf = rx_array + j*2;
  90                         xfers[j].bits_per_word = 8;
  91                         xfers[j].len = 2;
  92                         xfers[j].cs_change = 1;
  93                         j++;
  94                 }
  95
  96         /* After these are transmitted, the rx_buff should have
  97          * values in alternate bytes
  98          */
  99         spi_message_init(&msg);
 100         for (j = 0; j < bitmap_weight(indio_dev->active_scan_mask,
 101                                       indio_dev->masklength) * 2; j++)
 102                 spi_message_add_tail(&xfers[j], &msg);
 103
 104         ret = spi_sync(st->us, &msg);
 105         mutex_unlock(&st->buf_lock);
 106         kfree(xfers);
 107
 108         return ret;
 109 }
 110
 111 static int lis3l02dq_get_buffer_element(struct iio_dev *indio_dev,
 112                                 u8 *buf)
 113 {
 114         int ret, i;
 115         u8 *rx_array ;
 116         s16 *data = (s16 *)buf;
 117         int scan_count = bitmap_weight(indio_dev->active_scan_mask,
 118                                        indio_dev->masklength);
 119
 120         rx_array = kzalloc(4 * scan_count, GFP_KERNEL);
 121         if (rx_array == NULL)
 122                 return -ENOMEM;
 123         ret = lis3l02dq_read_all(indio_dev, rx_array);
 124         if (ret < 0) {
 125                 kfree(rx_array);
 126                 return ret;
 127         }
 128         for (i = 0; i < scan_count; i++)
 129                 data[i] = combine_8_to_16(rx_array[i*4+1],
 130                                         rx_array[i*4+3]);
 131         kfree(rx_array);
 132
 133         return i*sizeof(data[0]);
 134 }
 135
 136 static irqreturn_t lis3l02dq_trigger_handler(int irq, void *p)
 137 {
 138         struct iio_poll_func *pf = p;
 139         struct iio_dev *indio_dev = pf->indio_dev;
 140         struct iio_buffer *buffer = indio_dev->buffer;
 141         int len = 0;
 142         char *data;
 143
 144         data = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
 145         if (data == NULL) {
 146                 dev_err(indio_dev->dev.parent,
 147                         "memory alloc failed in buffer bh");
 148                 goto done;
 149         }
 150
 151         if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
 152                 len = lis3l02dq_get_buffer_element(indio_dev, data);
 153
 154           /* Guaranteed to be aligned with 8 byte boundary */
 155         if (indio_dev->scan_timestamp)
 156                 *(s64 *)((u8 *)data + ALIGN(len, sizeof(s64)))
 157                         = pf->timestamp;
 158         buffer->access->store_to(buffer, (u8 *)data, pf->timestamp);
 159
 160         kfree(data);
 161 done:
 162         iio_trigger_notify_done(indio_dev->trig);
 163         return IRQ_HANDLED;
 164 }
 165
 166 /* Caller responsible for locking as necessary. */
 167 static int
 168 __lis3l02dq_write_data_ready_config(struct iio_dev *indio_dev, bool state)
 169 {
 170         int ret;
 171         u8 valold;
 172         bool currentlyset;
 173         struct lis3l02dq_state *st = iio_priv(indio_dev);
 174
 175 /* Get the current event mask register */
 176         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 177                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 178                                        &valold);
 179         if (ret)
 180                 goto error_ret;
 181 /* Find out if data ready is already on */
 182         currentlyset
 183                 = valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
 184
 185 /* Disable requested */
 186         if (!state && currentlyset) {
 187                 /* disable the data ready signal */
 188                 valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
 189
 190                 /* The double write is to overcome a hardware bug?*/
 191                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 192                                                 LIS3L02DQ_REG_CTRL_2_ADDR,
 193                                                 valold);
 194                 if (ret)
 195                         goto error_ret;
 196                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 197                                                 LIS3L02DQ_REG_CTRL_2_ADDR,
 198                                                 valold);
 199                 if (ret)
 200                         goto error_ret;
 201                 st->trigger_on = false;
 202 /* Enable requested */
 203         } else if (state && !currentlyset) {
 204                 /* if not set, enable requested */
 205                 /* first disable all events */
 206                 ret = lis3l02dq_disable_all_events(indio_dev);
 207                 if (ret < 0)
 208                         goto error_ret;
 209
 210                 valold = ret |
 211                         LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
 212
 213                 st->trigger_on = true;
 214                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 215                                                 LIS3L02DQ_REG_CTRL_2_ADDR,
 216                                                 valold);
 217                 if (ret)
 218                         goto error_ret;
 219         }
 220
 221         return 0;
 222 error_ret:
 223         return ret;
 224 }
 225
 226 /**
 227  * lis3l02dq_data_rdy_trigger_set_state() set datardy interrupt state
 228  *
 229  * If disabling the interrupt also does a final read to ensure it is clear.
 230  * This is only important in some cases where the scan enable elements are
 231  * switched before the buffer is reenabled.
 232  **/
 233 static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
 234                                                 bool state)
 235 {
 236         struct iio_dev *indio_dev = trig->private_data;
 237         int ret = 0;
 238         u8 t;
 239
 240         __lis3l02dq_write_data_ready_config(indio_dev, state);
 241         if (state == false) {
 242                 /*
 243                  * A possible quirk with the handler is currently worked around
 244                  *  by ensuring outstanding read events are cleared.
 245                  */
 246                 ret = lis3l02dq_read_all(indio_dev, NULL);
 247         }
 248         lis3l02dq_spi_read_reg_8(indio_dev,
 249                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 250                                  &t);
 251         return ret;
 252 }
 253
 254 /**
 255  * lis3l02dq_trig_try_reen() try renabling irq for data rdy trigger
 256  * @trig:       the datardy trigger
 257  */
 258 static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
 259 {
 260         struct iio_dev *indio_dev = trig->private_data;
 261         struct lis3l02dq_state *st = iio_priv(indio_dev);
 262         int i;
 263
 264         /* If gpio still high (or high again) */
 265         /* In theory possible we will need to do this several times */
 266         for (i = 0; i < 5; i++)
 267                 if (gpio_get_value(irq_to_gpio(st->us->irq)))
 268                         lis3l02dq_read_all(indio_dev, NULL);
 269                 else
 270                         break;
 271         if (i == 5)
 272                 printk(KERN_INFO
 273                        "Failed to clear the interrupt for lis3l02dq\n");
 274
 275         /* irq reenabled so success! */
 276         return 0;
 277 }
 278
 279 static const struct iio_trigger_ops lis3l02dq_trigger_ops = {
 280         .owner = THIS_MODULE,
 281         .set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state,
 282         .try_reenable = &lis3l02dq_trig_try_reen,
 283 };
 284
 285 int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
 286 {
 287         int ret;
 288         struct lis3l02dq_state *st = iio_priv(indio_dev);
 289
 290         st->trig = iio_trigger_alloc("lis3l02dq-dev%d", indio_dev->id);
 291         if (!st->trig) {
 292                 ret = -ENOMEM;
 293                 goto error_ret;
 294         }
 295
 296         st->trig->dev.parent = &st->us->dev;
 297         st->trig->ops = &lis3l02dq_trigger_ops;
 298         st->trig->private_data = indio_dev;
 299         ret = iio_trigger_register(st->trig);
 300         if (ret)
 301                 goto error_free_trig;
 302
 303         return 0;
 304
 305 error_free_trig:
 306         iio_trigger_free(st->trig);
 307 error_ret:
 308         return ret;
 309 }
 310
 311 void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
 312 {
 313         struct lis3l02dq_state *st = iio_priv(indio_dev);
 314
 315         iio_trigger_unregister(st->trig);
 316         iio_trigger_free(st->trig);
 317 }
 318
 319 void lis3l02dq_unconfigure_buffer(struct iio_dev *indio_dev)
 320 {
 321         iio_dealloc_pollfunc(indio_dev->pollfunc);
 322         lis3l02dq_free_buf(indio_dev->buffer);
 323 }
 324
 325 static int lis3l02dq_buffer_postenable(struct iio_dev *indio_dev)
 326 {
 327         /* Disable unwanted channels otherwise the interrupt will not clear */
 328         u8 t;
 329         int ret;
 330         bool oneenabled = false;
 331
 332         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 333                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 334                                        &t);
 335         if (ret)
 336                 goto error_ret;
 337
 338         if (test_bit(0, indio_dev->active_scan_mask)) {
 339                 t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
 340                 oneenabled = true;
 341         } else
 342                 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
 343         if (test_bit(1, indio_dev->active_scan_mask)) {
 344                 t |= LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
 345                 oneenabled = true;
 346         } else
 347                 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
 348         if (test_bit(2, indio_dev->active_scan_mask)) {
 349                 t |= LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
 350                 oneenabled = true;
 351         } else
 352                 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
 353
 354         if (!oneenabled) /* what happens in this case is unknown */
 355                 return -EINVAL;
 356         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 357                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 358                                         t);
 359         if (ret)
 360                 goto error_ret;
 361
 362         return iio_triggered_buffer_postenable(indio_dev);
 363 error_ret:
 364         return ret;
 365 }
 366
 367 /* Turn all channels on again */
 368 static int lis3l02dq_buffer_predisable(struct iio_dev *indio_dev)
 369 {
 370         u8 t;
 371         int ret;
 372
 373         ret = iio_triggered_buffer_predisable(indio_dev);
 374         if (ret)
 375                 goto error_ret;
 376
 377         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 378                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 379                                        &t);
 380         if (ret)
 381                 goto error_ret;
 382         t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE |
 383                 LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE |
 384                 LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
 385
 386         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 387                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 388                                         t);
 389
 390 error_ret:
 391         return ret;
 392 }
 393
 394 static const struct iio_buffer_setup_ops lis3l02dq_buffer_setup_ops = {
 395         .preenable = &iio_sw_buffer_preenable,
 396         .postenable = &lis3l02dq_buffer_postenable,
 397         .predisable = &lis3l02dq_buffer_predisable,
 398 };
 399
 400 int lis3l02dq_configure_buffer(struct iio_dev *indio_dev)
 401 {
 402         int ret;
 403         struct iio_buffer *buffer;
 404
 405         buffer = lis3l02dq_alloc_buf(indio_dev);
 406         if (!buffer)
 407                 return -ENOMEM;
 408
 409         indio_dev->buffer = buffer;
 410
 411         buffer->scan_timestamp = true;
 412         indio_dev->setup_ops = &lis3l02dq_buffer_setup_ops;
 413
 414         /* Functions are NULL as we set handler below */
 415         indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
 416                                                  &lis3l02dq_trigger_handler,
 417                                                  0,
 418                                                  indio_dev,
 419                                                  "lis3l02dq_consumer%d",
 420                                                  indio_dev->id);
 421
 422         if (indio_dev->pollfunc == NULL) {
 423                 ret = -ENOMEM;
 424                 goto error_iio_sw_rb_free;
 425         }
 426
 427         indio_dev->modes |= INDIO_BUFFER_TRIGGERED;
 428         return 0;
 429
 430 error_iio_sw_rb_free:
 431         lis3l02dq_free_buf(indio_dev->buffer);
 432         return ret;
 433 }