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Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into...
[deliverable/linux.git] / drivers / staging / iio / adc / ad7192.c
1 /*
2 * AD7190 AD7192 AD7195 SPI ADC driver
3 *
4 * Copyright 2011-2012 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
19
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26
27 #include "ad7192.h"
28
29 /* Registers */
30 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
31 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
33 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
34 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
35 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
36 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
37 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit
38 * (AD7792)/24-bit (AD7192)) */
39 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register
40 * (RW, 16-bit (AD7792)/24-bit (AD7192)) */
41
42 /* Communications Register Bit Designations (AD7192_REG_COMM) */
43 #define AD7192_COMM_WEN (1 << 7) /* Write Enable */
44 #define AD7192_COMM_WRITE (0 << 6) /* Write Operation */
45 #define AD7192_COMM_READ (1 << 6) /* Read Operation */
46 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
47 #define AD7192_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */
48
49 /* Status Register Bit Designations (AD7192_REG_STAT) */
50 #define AD7192_STAT_RDY (1 << 7) /* Ready */
51 #define AD7192_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */
52 #define AD7192_STAT_NOREF (1 << 5) /* Error no external reference */
53 #define AD7192_STAT_PARITY (1 << 4) /* Parity */
54 #define AD7192_STAT_CH3 (1 << 2) /* Channel 3 */
55 #define AD7192_STAT_CH2 (1 << 1) /* Channel 2 */
56 #define AD7192_STAT_CH1 (1 << 0) /* Channel 1 */
57
58 /* Mode Register Bit Designations (AD7192_REG_MODE) */
59 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
60 #define AD7192_MODE_DAT_STA (1 << 20) /* Status Register transmission */
61 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
62 #define AD7192_MODE_SINC3 (1 << 15) /* SINC3 Filter Select */
63 #define AD7192_MODE_ACX (1 << 14) /* AC excitation enable(AD7195 only)*/
64 #define AD7192_MODE_ENPAR (1 << 13) /* Parity Enable */
65 #define AD7192_MODE_CLKDIV (1 << 12) /* Clock divide by 2 (AD7190/2 only)*/
66 #define AD7192_MODE_SCYCLE (1 << 11) /* Single cycle conversion */
67 #define AD7192_MODE_REJ60 (1 << 10) /* 50/60Hz notch filter */
68 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
69
70 /* Mode Register: AD7192_MODE_SEL options */
71 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
72 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
73 #define AD7192_MODE_IDLE 2 /* Idle Mode */
74 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
75 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
76 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
77 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
78 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
79
80 /* Mode Register: AD7192_MODE_CLKSRC options */
81 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected
82 * from MCLK1 to MCLK2 */
83 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
84 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not
85 * available at the MCLK2 pin */
86 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available
87 * at the MCLK2 pin */
88
89
90 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
91
92 #define AD7192_CONF_CHOP (1 << 23) /* CHOP enable */
93 #define AD7192_CONF_REFSEL (1 << 20) /* REFIN1/REFIN2 Reference Select */
94 #define AD7192_CONF_CHAN(x) (((x) & 0xFF) << 8) /* Channel select */
95 #define AD7192_CONF_BURN (1 << 7) /* Burnout current enable */
96 #define AD7192_CONF_REFDET (1 << 6) /* Reference detect enable */
97 #define AD7192_CONF_BUF (1 << 4) /* Buffered Mode Enable */
98 #define AD7192_CONF_UNIPOLAR (1 << 3) /* Unipolar/Bipolar Enable */
99 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
100
101 #define AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */
102 #define AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */
103 #define AD7192_CH_TEMP 2 /* Temp Sensor */
104 #define AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */
105 #define AD7192_CH_AIN1 4 /* AIN1 - AINCOM */
106 #define AD7192_CH_AIN2 5 /* AIN2 - AINCOM */
107 #define AD7192_CH_AIN3 6 /* AIN3 - AINCOM */
108 #define AD7192_CH_AIN4 7 /* AIN4 - AINCOM */
109
110 /* ID Register Bit Designations (AD7192_REG_ID) */
111 #define ID_AD7190 0x4
112 #define ID_AD7192 0x0
113 #define ID_AD7195 0x6
114 #define AD7192_ID_MASK 0x0F
115
116 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
117 #define AD7192_GPOCON_BPDSW (1 << 6) /* Bridge power-down switch enable */
118 #define AD7192_GPOCON_GP32EN (1 << 5) /* Digital Output P3 and P2 enable */
119 #define AD7192_GPOCON_GP10EN (1 << 4) /* Digital Output P1 and P0 enable */
120 #define AD7192_GPOCON_P3DAT (1 << 3) /* P3 state */
121 #define AD7192_GPOCON_P2DAT (1 << 2) /* P2 state */
122 #define AD7192_GPOCON_P1DAT (1 << 1) /* P1 state */
123 #define AD7192_GPOCON_P0DAT (1 << 0) /* P0 state */
124
125 #define AD7192_INT_FREQ_MHz 4915200
126
127 /* NOTE:
128 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
129 * In order to avoid contentions on the SPI bus, it's therefore necessary
130 * to use spi bus locking.
131 *
132 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
133 */
134
135 struct ad7192_state {
136 struct spi_device *spi;
137 struct iio_trigger *trig;
138 struct regulator *reg;
139 struct ad7192_platform_data *pdata;
140 wait_queue_head_t wq_data_avail;
141 bool done;
142 bool irq_dis;
143 u16 int_vref_mv;
144 u32 mclk;
145 u32 f_order;
146 u32 mode;
147 u32 conf;
148 u32 scale_avail[8][2];
149 u8 gpocon;
150 u8 devid;
151 /*
152 * DMA (thus cache coherency maintenance) requires the
153 * transfer buffers to live in their own cache lines.
154 */
155 u8 data[4] ____cacheline_aligned;
156 };
157
158 static int __ad7192_write_reg(struct ad7192_state *st, bool locked,
159 bool cs_change, unsigned char reg,
160 unsigned size, unsigned val)
161 {
162 u8 *data = st->data;
163 struct spi_transfer t = {
164 .tx_buf = data,
165 .len = size + 1,
166 .cs_change = cs_change,
167 };
168 struct spi_message m;
169
170 data[0] = AD7192_COMM_WRITE | AD7192_COMM_ADDR(reg);
171
172 switch (size) {
173 case 3:
174 data[1] = val >> 16;
175 data[2] = val >> 8;
176 data[3] = val;
177 break;
178 case 2:
179 data[1] = val >> 8;
180 data[2] = val;
181 break;
182 case 1:
183 data[1] = val;
184 break;
185 default:
186 return -EINVAL;
187 }
188
189 spi_message_init(&m);
190 spi_message_add_tail(&t, &m);
191
192 if (locked)
193 return spi_sync_locked(st->spi, &m);
194 else
195 return spi_sync(st->spi, &m);
196 }
197
198 static int ad7192_write_reg(struct ad7192_state *st,
199 unsigned reg, unsigned size, unsigned val)
200 {
201 return __ad7192_write_reg(st, false, false, reg, size, val);
202 }
203
204 static int __ad7192_read_reg(struct ad7192_state *st, bool locked,
205 bool cs_change, unsigned char reg,
206 int *val, unsigned size)
207 {
208 u8 *data = st->data;
209 int ret;
210 struct spi_transfer t[] = {
211 {
212 .tx_buf = data,
213 .len = 1,
214 }, {
215 .rx_buf = data,
216 .len = size,
217 .cs_change = cs_change,
218 },
219 };
220 struct spi_message m;
221
222 data[0] = AD7192_COMM_READ | AD7192_COMM_ADDR(reg);
223
224 spi_message_init(&m);
225 spi_message_add_tail(&t[0], &m);
226 spi_message_add_tail(&t[1], &m);
227
228 if (locked)
229 ret = spi_sync_locked(st->spi, &m);
230 else
231 ret = spi_sync(st->spi, &m);
232
233 if (ret < 0)
234 return ret;
235
236 switch (size) {
237 case 3:
238 *val = data[0] << 16 | data[1] << 8 | data[2];
239 break;
240 case 2:
241 *val = data[0] << 8 | data[1];
242 break;
243 case 1:
244 *val = data[0];
245 break;
246 default:
247 return -EINVAL;
248 }
249
250 return 0;
251 }
252
253 static int ad7192_read_reg(struct ad7192_state *st,
254 unsigned reg, int *val, unsigned size)
255 {
256 return __ad7192_read_reg(st, 0, 0, reg, val, size);
257 }
258
259 static int ad7192_read(struct ad7192_state *st, unsigned ch,
260 unsigned len, int *val)
261 {
262 int ret;
263 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
264 AD7192_CONF_CHAN(1 << ch);
265 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
266 AD7192_MODE_SEL(AD7192_MODE_SINGLE);
267
268 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
269
270 spi_bus_lock(st->spi->master);
271 st->done = false;
272
273 ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode);
274 if (ret < 0)
275 goto out;
276
277 st->irq_dis = false;
278 enable_irq(st->spi->irq);
279 wait_event_interruptible(st->wq_data_avail, st->done);
280
281 ret = __ad7192_read_reg(st, 1, 0, AD7192_REG_DATA, val, len);
282 out:
283 spi_bus_unlock(st->spi->master);
284
285 return ret;
286 }
287
288 static int ad7192_calibrate(struct ad7192_state *st, unsigned mode, unsigned ch)
289 {
290 int ret;
291
292 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
293 AD7192_CONF_CHAN(1 << ch);
294 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | AD7192_MODE_SEL(mode);
295
296 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
297
298 spi_bus_lock(st->spi->master);
299 st->done = false;
300
301 ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3,
302 (st->devid != ID_AD7195) ?
303 st->mode | AD7192_MODE_CLKDIV :
304 st->mode);
305 if (ret < 0)
306 goto out;
307
308 st->irq_dis = false;
309 enable_irq(st->spi->irq);
310 wait_event_interruptible(st->wq_data_avail, st->done);
311
312 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
313 AD7192_MODE_SEL(AD7192_MODE_IDLE);
314
315 ret = __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode);
316 out:
317 spi_bus_unlock(st->spi->master);
318
319 return ret;
320 }
321
322 static const u8 ad7192_calib_arr[8][2] = {
323 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
324 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
325 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
326 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
327 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
328 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
329 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
330 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
331 };
332
333 static int ad7192_calibrate_all(struct ad7192_state *st)
334 {
335 int i, ret;
336
337 for (i = 0; i < ARRAY_SIZE(ad7192_calib_arr); i++) {
338 ret = ad7192_calibrate(st, ad7192_calib_arr[i][0],
339 ad7192_calib_arr[i][1]);
340 if (ret)
341 goto out;
342 }
343
344 return 0;
345 out:
346 dev_err(&st->spi->dev, "Calibration failed\n");
347 return ret;
348 }
349
350 static int ad7192_setup(struct ad7192_state *st)
351 {
352 struct iio_dev *indio_dev = spi_get_drvdata(st->spi);
353 struct ad7192_platform_data *pdata = st->pdata;
354 unsigned long long scale_uv;
355 int i, ret, id;
356 u8 ones[6];
357
358 /* reset the serial interface */
359 memset(&ones, 0xFF, 6);
360 ret = spi_write(st->spi, &ones, 6);
361 if (ret < 0)
362 goto out;
363 msleep(1); /* Wait for at least 500us */
364
365 /* write/read test for device presence */
366 ret = ad7192_read_reg(st, AD7192_REG_ID, &id, 1);
367 if (ret)
368 goto out;
369
370 id &= AD7192_ID_MASK;
371
372 if (id != st->devid)
373 dev_warn(&st->spi->dev, "device ID query failed (0x%X)\n", id);
374
375 switch (pdata->clock_source_sel) {
376 case AD7192_CLK_EXT_MCLK1_2:
377 case AD7192_CLK_EXT_MCLK2:
378 st->mclk = AD7192_INT_FREQ_MHz;
379 break;
380 case AD7192_CLK_INT:
381 case AD7192_CLK_INT_CO:
382 if (pdata->ext_clk_Hz)
383 st->mclk = pdata->ext_clk_Hz;
384 else
385 st->mclk = AD7192_INT_FREQ_MHz;
386 break;
387 default:
388 ret = -EINVAL;
389 goto out;
390 }
391
392 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
393 AD7192_MODE_CLKSRC(pdata->clock_source_sel) |
394 AD7192_MODE_RATE(480);
395
396 st->conf = AD7192_CONF_GAIN(0);
397
398 if (pdata->rej60_en)
399 st->mode |= AD7192_MODE_REJ60;
400
401 if (pdata->sinc3_en)
402 st->mode |= AD7192_MODE_SINC3;
403
404 if (pdata->refin2_en && (st->devid != ID_AD7195))
405 st->conf |= AD7192_CONF_REFSEL;
406
407 if (pdata->chop_en) {
408 st->conf |= AD7192_CONF_CHOP;
409 if (pdata->sinc3_en)
410 st->f_order = 3; /* SINC 3rd order */
411 else
412 st->f_order = 4; /* SINC 4th order */
413 } else {
414 st->f_order = 1;
415 }
416
417 if (pdata->buf_en)
418 st->conf |= AD7192_CONF_BUF;
419
420 if (pdata->unipolar_en)
421 st->conf |= AD7192_CONF_UNIPOLAR;
422
423 if (pdata->burnout_curr_en)
424 st->conf |= AD7192_CONF_BURN;
425
426 ret = ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode);
427 if (ret)
428 goto out;
429
430 ret = ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
431 if (ret)
432 goto out;
433
434 ret = ad7192_calibrate_all(st);
435 if (ret)
436 goto out;
437
438 /* Populate available ADC input ranges */
439 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
440 scale_uv = ((u64)st->int_vref_mv * 100000000)
441 >> (indio_dev->channels[0].scan_type.realbits -
442 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
443 scale_uv >>= i;
444
445 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
446 st->scale_avail[i][0] = scale_uv;
447 }
448
449 return 0;
450 out:
451 dev_err(&st->spi->dev, "setup failed\n");
452 return ret;
453 }
454
455 static int ad7192_ring_preenable(struct iio_dev *indio_dev)
456 {
457 struct ad7192_state *st = iio_priv(indio_dev);
458 unsigned channel;
459 int ret;
460
461 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
462 return -EINVAL;
463
464 ret = iio_sw_buffer_preenable(indio_dev);
465 if (ret < 0)
466 return ret;
467
468 channel = find_first_bit(indio_dev->active_scan_mask,
469 indio_dev->masklength);
470
471 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
472 AD7192_MODE_SEL(AD7192_MODE_CONT);
473 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
474 AD7192_CONF_CHAN(1 << indio_dev->channels[channel].address);
475
476 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
477
478 spi_bus_lock(st->spi->master);
479 __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode);
480
481 st->irq_dis = false;
482 enable_irq(st->spi->irq);
483
484 return 0;
485 }
486
487 static int ad7192_ring_postdisable(struct iio_dev *indio_dev)
488 {
489 struct ad7192_state *st = iio_priv(indio_dev);
490
491 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
492 AD7192_MODE_SEL(AD7192_MODE_IDLE);
493
494 st->done = false;
495 wait_event_interruptible(st->wq_data_avail, st->done);
496
497 if (!st->irq_dis)
498 disable_irq_nosync(st->spi->irq);
499
500 __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode);
501
502 return spi_bus_unlock(st->spi->master);
503 }
504
505 /**
506 * ad7192_trigger_handler() bh of trigger launched polling to ring buffer
507 **/
508 static irqreturn_t ad7192_trigger_handler(int irq, void *p)
509 {
510 struct iio_poll_func *pf = p;
511 struct iio_dev *indio_dev = pf->indio_dev;
512 struct iio_buffer *ring = indio_dev->buffer;
513 struct ad7192_state *st = iio_priv(indio_dev);
514 s64 dat64[2];
515 s32 *dat32 = (s32 *)dat64;
516
517 if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
518 __ad7192_read_reg(st, 1, 1, AD7192_REG_DATA,
519 dat32,
520 indio_dev->channels[0].scan_type.realbits/8);
521
522 /* Guaranteed to be aligned with 8 byte boundary */
523 if (indio_dev->scan_timestamp)
524 dat64[1] = pf->timestamp;
525
526 ring->access->store_to(ring, (u8 *)dat64, pf->timestamp);
527
528 iio_trigger_notify_done(indio_dev->trig);
529 st->irq_dis = false;
530 enable_irq(st->spi->irq);
531
532 return IRQ_HANDLED;
533 }
534
535 static const struct iio_buffer_setup_ops ad7192_ring_setup_ops = {
536 .preenable = &ad7192_ring_preenable,
537 .postenable = &iio_triggered_buffer_postenable,
538 .predisable = &iio_triggered_buffer_predisable,
539 .postdisable = &ad7192_ring_postdisable,
540 .validate_scan_mask = &iio_validate_scan_mask_onehot,
541 };
542
543 static int ad7192_register_ring_funcs_and_init(struct iio_dev *indio_dev)
544 {
545 return iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
546 &ad7192_trigger_handler, &ad7192_ring_setup_ops);
547 }
548
549 static void ad7192_ring_cleanup(struct iio_dev *indio_dev)
550 {
551 iio_triggered_buffer_cleanup(indio_dev);
552 }
553
554 /**
555 * ad7192_data_rdy_trig_poll() the event handler for the data rdy trig
556 **/
557 static irqreturn_t ad7192_data_rdy_trig_poll(int irq, void *private)
558 {
559 struct ad7192_state *st = iio_priv(private);
560
561 st->done = true;
562 wake_up_interruptible(&st->wq_data_avail);
563 disable_irq_nosync(irq);
564 st->irq_dis = true;
565 iio_trigger_poll(st->trig, iio_get_time_ns());
566
567 return IRQ_HANDLED;
568 }
569
570 static struct iio_trigger_ops ad7192_trigger_ops = {
571 .owner = THIS_MODULE,
572 };
573
574 static int ad7192_probe_trigger(struct iio_dev *indio_dev)
575 {
576 struct ad7192_state *st = iio_priv(indio_dev);
577 int ret;
578
579 st->trig = iio_trigger_alloc("%s-dev%d",
580 spi_get_device_id(st->spi)->name,
581 indio_dev->id);
582 if (st->trig == NULL) {
583 ret = -ENOMEM;
584 goto error_ret;
585 }
586 st->trig->ops = &ad7192_trigger_ops;
587 ret = request_irq(st->spi->irq,
588 ad7192_data_rdy_trig_poll,
589 IRQF_TRIGGER_LOW,
590 spi_get_device_id(st->spi)->name,
591 indio_dev);
592 if (ret)
593 goto error_free_trig;
594
595 disable_irq_nosync(st->spi->irq);
596 st->irq_dis = true;
597 st->trig->dev.parent = &st->spi->dev;
598 st->trig->private_data = indio_dev;
599
600 ret = iio_trigger_register(st->trig);
601
602 /* select default trigger */
603 indio_dev->trig = st->trig;
604 if (ret)
605 goto error_free_irq;
606
607 return 0;
608
609 error_free_irq:
610 free_irq(st->spi->irq, indio_dev);
611 error_free_trig:
612 iio_trigger_free(st->trig);
613 error_ret:
614 return ret;
615 }
616
617 static void ad7192_remove_trigger(struct iio_dev *indio_dev)
618 {
619 struct ad7192_state *st = iio_priv(indio_dev);
620
621 iio_trigger_unregister(st->trig);
622 free_irq(st->spi->irq, indio_dev);
623 iio_trigger_free(st->trig);
624 }
625
626 static ssize_t ad7192_read_frequency(struct device *dev,
627 struct device_attribute *attr,
628 char *buf)
629 {
630 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
631 struct ad7192_state *st = iio_priv(indio_dev);
632
633 return sprintf(buf, "%d\n", st->mclk /
634 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)));
635 }
636
637 static ssize_t ad7192_write_frequency(struct device *dev,
638 struct device_attribute *attr,
639 const char *buf,
640 size_t len)
641 {
642 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
643 struct ad7192_state *st = iio_priv(indio_dev);
644 unsigned long lval;
645 int div, ret;
646
647 ret = strict_strtoul(buf, 10, &lval);
648 if (ret)
649 return ret;
650 if (lval == 0)
651 return -EINVAL;
652
653 mutex_lock(&indio_dev->mlock);
654 if (iio_buffer_enabled(indio_dev)) {
655 mutex_unlock(&indio_dev->mlock);
656 return -EBUSY;
657 }
658
659 div = st->mclk / (lval * st->f_order * 1024);
660 if (div < 1 || div > 1023) {
661 ret = -EINVAL;
662 goto out;
663 }
664
665 st->mode &= ~AD7192_MODE_RATE(-1);
666 st->mode |= AD7192_MODE_RATE(div);
667 ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode);
668
669 out:
670 mutex_unlock(&indio_dev->mlock);
671
672 return ret ? ret : len;
673 }
674
675 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
676 ad7192_read_frequency,
677 ad7192_write_frequency);
678
679
680 static ssize_t ad7192_show_scale_available(struct device *dev,
681 struct device_attribute *attr, char *buf)
682 {
683 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
684 struct ad7192_state *st = iio_priv(indio_dev);
685 int i, len = 0;
686
687 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
688 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
689 st->scale_avail[i][1]);
690
691 len += sprintf(buf + len, "\n");
692
693 return len;
694 }
695
696 static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available,
697 in_voltage-voltage_scale_available,
698 S_IRUGO, ad7192_show_scale_available, NULL, 0);
699
700 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
701 ad7192_show_scale_available, NULL, 0);
702
703 static ssize_t ad7192_show_ac_excitation(struct device *dev,
704 struct device_attribute *attr,
705 char *buf)
706 {
707 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
708 struct ad7192_state *st = iio_priv(indio_dev);
709
710 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
711 }
712
713 static ssize_t ad7192_show_bridge_switch(struct device *dev,
714 struct device_attribute *attr,
715 char *buf)
716 {
717 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
718 struct ad7192_state *st = iio_priv(indio_dev);
719
720 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
721 }
722
723 static ssize_t ad7192_set(struct device *dev,
724 struct device_attribute *attr,
725 const char *buf,
726 size_t len)
727 {
728 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
729 struct ad7192_state *st = iio_priv(indio_dev);
730 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
731 int ret;
732 bool val;
733
734 ret = strtobool(buf, &val);
735 if (ret < 0)
736 return ret;
737
738 mutex_lock(&indio_dev->mlock);
739 if (iio_buffer_enabled(indio_dev)) {
740 mutex_unlock(&indio_dev->mlock);
741 return -EBUSY;
742 }
743
744 switch ((u32) this_attr->address) {
745 case AD7192_REG_GPOCON:
746 if (val)
747 st->gpocon |= AD7192_GPOCON_BPDSW;
748 else
749 st->gpocon &= ~AD7192_GPOCON_BPDSW;
750
751 ad7192_write_reg(st, AD7192_REG_GPOCON, 1, st->gpocon);
752 break;
753 case AD7192_REG_MODE:
754 if (val)
755 st->mode |= AD7192_MODE_ACX;
756 else
757 st->mode &= ~AD7192_MODE_ACX;
758
759 ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode);
760 break;
761 default:
762 ret = -EINVAL;
763 }
764
765 mutex_unlock(&indio_dev->mlock);
766
767 return ret ? ret : len;
768 }
769
770 static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR,
771 ad7192_show_bridge_switch, ad7192_set,
772 AD7192_REG_GPOCON);
773
774 static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR,
775 ad7192_show_ac_excitation, ad7192_set,
776 AD7192_REG_MODE);
777
778 static struct attribute *ad7192_attributes[] = {
779 &iio_dev_attr_sampling_frequency.dev_attr.attr,
780 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
781 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
782 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
783 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
784 NULL
785 };
786
787 static const struct attribute_group ad7192_attribute_group = {
788 .attrs = ad7192_attributes,
789 };
790
791 static struct attribute *ad7195_attributes[] = {
792 &iio_dev_attr_sampling_frequency.dev_attr.attr,
793 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
794 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
795 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
796 NULL
797 };
798
799 static const struct attribute_group ad7195_attribute_group = {
800 .attrs = ad7195_attributes,
801 };
802
803 static unsigned int ad7192_get_temp_scale(bool unipolar)
804 {
805 return unipolar ? 2815 * 2 : 2815;
806 }
807
808 static int ad7192_read_raw(struct iio_dev *indio_dev,
809 struct iio_chan_spec const *chan,
810 int *val,
811 int *val2,
812 long m)
813 {
814 struct ad7192_state *st = iio_priv(indio_dev);
815 int ret, smpl = 0;
816 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
817
818 switch (m) {
819 case IIO_CHAN_INFO_RAW:
820 mutex_lock(&indio_dev->mlock);
821 if (iio_buffer_enabled(indio_dev))
822 ret = -EBUSY;
823 else
824 ret = ad7192_read(st, chan->address,
825 chan->scan_type.realbits / 8, &smpl);
826 mutex_unlock(&indio_dev->mlock);
827
828 if (ret < 0)
829 return ret;
830
831 *val = (smpl >> chan->scan_type.shift) &
832 ((1 << (chan->scan_type.realbits)) - 1);
833
834 return IIO_VAL_INT;
835
836 case IIO_CHAN_INFO_SCALE:
837 switch (chan->type) {
838 case IIO_VOLTAGE:
839 mutex_lock(&indio_dev->mlock);
840 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
841 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
842 mutex_unlock(&indio_dev->mlock);
843 return IIO_VAL_INT_PLUS_NANO;
844 case IIO_TEMP:
845 *val = 0;
846 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
847 return IIO_VAL_INT_PLUS_NANO;
848 default:
849 return -EINVAL;
850 }
851 case IIO_CHAN_INFO_OFFSET:
852 if (!unipolar)
853 *val = -(1 << (chan->scan_type.realbits - 1));
854 else
855 *val = 0;
856 /* Kelvin to Celsius */
857 if (chan->type == IIO_TEMP)
858 *val -= 273 * ad7192_get_temp_scale(unipolar);
859 return IIO_VAL_INT;
860 }
861
862 return -EINVAL;
863 }
864
865 static int ad7192_write_raw(struct iio_dev *indio_dev,
866 struct iio_chan_spec const *chan,
867 int val,
868 int val2,
869 long mask)
870 {
871 struct ad7192_state *st = iio_priv(indio_dev);
872 int ret, i;
873 unsigned int tmp;
874
875 mutex_lock(&indio_dev->mlock);
876 if (iio_buffer_enabled(indio_dev)) {
877 mutex_unlock(&indio_dev->mlock);
878 return -EBUSY;
879 }
880
881 switch (mask) {
882 case IIO_CHAN_INFO_SCALE:
883 ret = -EINVAL;
884 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
885 if (val2 == st->scale_avail[i][1]) {
886 tmp = st->conf;
887 st->conf &= ~AD7192_CONF_GAIN(-1);
888 st->conf |= AD7192_CONF_GAIN(i);
889
890 if (tmp != st->conf) {
891 ad7192_write_reg(st, AD7192_REG_CONF,
892 3, st->conf);
893 ad7192_calibrate_all(st);
894 }
895 ret = 0;
896 }
897 break;
898 default:
899 ret = -EINVAL;
900 }
901
902 mutex_unlock(&indio_dev->mlock);
903
904 return ret;
905 }
906
907 static int ad7192_validate_trigger(struct iio_dev *indio_dev,
908 struct iio_trigger *trig)
909 {
910 if (indio_dev->trig != trig)
911 return -EINVAL;
912
913 return 0;
914 }
915
916 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
917 struct iio_chan_spec const *chan,
918 long mask)
919 {
920 return IIO_VAL_INT_PLUS_NANO;
921 }
922
923 static const struct iio_info ad7192_info = {
924 .read_raw = &ad7192_read_raw,
925 .write_raw = &ad7192_write_raw,
926 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
927 .attrs = &ad7192_attribute_group,
928 .validate_trigger = ad7192_validate_trigger,
929 .driver_module = THIS_MODULE,
930 };
931
932 static const struct iio_info ad7195_info = {
933 .read_raw = &ad7192_read_raw,
934 .write_raw = &ad7192_write_raw,
935 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
936 .attrs = &ad7195_attribute_group,
937 .validate_trigger = ad7192_validate_trigger,
938 .driver_module = THIS_MODULE,
939 };
940
941 #define AD7192_CHAN_DIFF(_chan, _chan2, _name, _address, _si) \
942 { .type = IIO_VOLTAGE, \
943 .differential = 1, \
944 .indexed = 1, \
945 .extend_name = _name, \
946 .channel = _chan, \
947 .channel2 = _chan2, \
948 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
949 IIO_CHAN_INFO_SCALE_SHARED_BIT | \
950 IIO_CHAN_INFO_OFFSET_SHARED_BIT, \
951 .address = _address, \
952 .scan_index = _si, \
953 .scan_type = IIO_ST('u', 24, 32, 0)}
954
955 #define AD7192_CHAN(_chan, _address, _si) \
956 { .type = IIO_VOLTAGE, \
957 .indexed = 1, \
958 .channel = _chan, \
959 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
960 IIO_CHAN_INFO_SCALE_SHARED_BIT | \
961 IIO_CHAN_INFO_OFFSET_SHARED_BIT, \
962 .address = _address, \
963 .scan_index = _si, \
964 .scan_type = IIO_ST('u', 24, 32, 0)}
965
966 #define AD7192_CHAN_TEMP(_chan, _address, _si) \
967 { .type = IIO_TEMP, \
968 .indexed = 1, \
969 .channel = _chan, \
970 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
971 IIO_CHAN_INFO_SCALE_SEPARATE_BIT, \
972 .address = _address, \
973 .scan_index = _si, \
974 .scan_type = IIO_ST('u', 24, 32, 0)}
975
976 static struct iio_chan_spec ad7192_channels[] = {
977 AD7192_CHAN_DIFF(1, 2, NULL, AD7192_CH_AIN1P_AIN2M, 0),
978 AD7192_CHAN_DIFF(3, 4, NULL, AD7192_CH_AIN3P_AIN4M, 1),
979 AD7192_CHAN_TEMP(0, AD7192_CH_TEMP, 2),
980 AD7192_CHAN_DIFF(2, 2, "shorted", AD7192_CH_AIN2P_AIN2M, 3),
981 AD7192_CHAN(1, AD7192_CH_AIN1, 4),
982 AD7192_CHAN(2, AD7192_CH_AIN2, 5),
983 AD7192_CHAN(3, AD7192_CH_AIN3, 6),
984 AD7192_CHAN(4, AD7192_CH_AIN4, 7),
985 IIO_CHAN_SOFT_TIMESTAMP(8),
986 };
987
988 static int __devinit ad7192_probe(struct spi_device *spi)
989 {
990 struct ad7192_platform_data *pdata = spi->dev.platform_data;
991 struct ad7192_state *st;
992 struct iio_dev *indio_dev;
993 int ret , voltage_uv = 0;
994
995 if (!pdata) {
996 dev_err(&spi->dev, "no platform data?\n");
997 return -ENODEV;
998 }
999
1000 if (!spi->irq) {
1001 dev_err(&spi->dev, "no IRQ?\n");
1002 return -ENODEV;
1003 }
1004
1005 indio_dev = iio_device_alloc(sizeof(*st));
1006 if (indio_dev == NULL)
1007 return -ENOMEM;
1008
1009 st = iio_priv(indio_dev);
1010
1011 st->reg = regulator_get(&spi->dev, "vcc");
1012 if (!IS_ERR(st->reg)) {
1013 ret = regulator_enable(st->reg);
1014 if (ret)
1015 goto error_put_reg;
1016
1017 voltage_uv = regulator_get_voltage(st->reg);
1018 }
1019
1020 st->pdata = pdata;
1021
1022 if (pdata && pdata->vref_mv)
1023 st->int_vref_mv = pdata->vref_mv;
1024 else if (voltage_uv)
1025 st->int_vref_mv = voltage_uv / 1000;
1026 else
1027 dev_warn(&spi->dev, "reference voltage undefined\n");
1028
1029 spi_set_drvdata(spi, indio_dev);
1030 st->spi = spi;
1031 st->devid = spi_get_device_id(spi)->driver_data;
1032 indio_dev->dev.parent = &spi->dev;
1033 indio_dev->name = spi_get_device_id(spi)->name;
1034 indio_dev->modes = INDIO_DIRECT_MODE;
1035 indio_dev->channels = ad7192_channels;
1036 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
1037 if (st->devid == ID_AD7195)
1038 indio_dev->info = &ad7195_info;
1039 else
1040 indio_dev->info = &ad7192_info;
1041
1042 init_waitqueue_head(&st->wq_data_avail);
1043
1044 ret = ad7192_register_ring_funcs_and_init(indio_dev);
1045 if (ret)
1046 goto error_disable_reg;
1047
1048 ret = ad7192_probe_trigger(indio_dev);
1049 if (ret)
1050 goto error_ring_cleanup;
1051
1052 ret = ad7192_setup(st);
1053 if (ret)
1054 goto error_remove_trigger;
1055
1056 ret = iio_device_register(indio_dev);
1057 if (ret < 0)
1058 goto error_remove_trigger;
1059 return 0;
1060
1061 error_remove_trigger:
1062 ad7192_remove_trigger(indio_dev);
1063 error_ring_cleanup:
1064 ad7192_ring_cleanup(indio_dev);
1065 error_disable_reg:
1066 if (!IS_ERR(st->reg))
1067 regulator_disable(st->reg);
1068 error_put_reg:
1069 if (!IS_ERR(st->reg))
1070 regulator_put(st->reg);
1071
1072 iio_device_free(indio_dev);
1073
1074 return ret;
1075 }
1076
1077 static int ad7192_remove(struct spi_device *spi)
1078 {
1079 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1080 struct ad7192_state *st = iio_priv(indio_dev);
1081
1082 iio_device_unregister(indio_dev);
1083 ad7192_remove_trigger(indio_dev);
1084 ad7192_ring_cleanup(indio_dev);
1085
1086 if (!IS_ERR(st->reg)) {
1087 regulator_disable(st->reg);
1088 regulator_put(st->reg);
1089 }
1090
1091 return 0;
1092 }
1093
1094 static const struct spi_device_id ad7192_id[] = {
1095 {"ad7190", ID_AD7190},
1096 {"ad7192", ID_AD7192},
1097 {"ad7195", ID_AD7195},
1098 {}
1099 };
1100 MODULE_DEVICE_TABLE(spi, ad7192_id);
1101
1102 static struct spi_driver ad7192_driver = {
1103 .driver = {
1104 .name = "ad7192",
1105 .owner = THIS_MODULE,
1106 },
1107 .probe = ad7192_probe,
1108 .remove = __devexit_p(ad7192_remove),
1109 .id_table = ad7192_id,
1110 };
1111 module_spi_driver(ad7192_driver);
1112
1113 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
1114 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7195 ADC");
1115 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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