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staging: iio: push the main buffer chrdev down to the top level.
[deliverable/linux.git] / drivers / staging / iio / adc / max1363_core.c
1 /*
2 * iio/adc/max1363.c
3 * Copyright (C) 2008-2010 Jonathan Cameron
4 *
5 * based on linux/drivers/i2c/chips/max123x
6 * Copyright (C) 2002-2004 Stefan Eletzhofer
7 *
8 * based on linux/drivers/acron/char/pcf8583.c
9 * Copyright (C) 2000 Russell King
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * max1363.c
16 *
17 * Partial support for max1363 and similar chips.
18 *
19 * Not currently implemented.
20 *
21 * - Control of internal reference.
22 */
23
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/kernel.h>
27 #include <linux/sysfs.h>
28 #include <linux/list.h>
29 #include <linux/i2c.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/slab.h>
32 #include <linux/err.h>
33 #include <linux/module.h>
34
35 #include "../iio.h"
36 #include "../sysfs.h"
37 #include "../ring_generic.h"
38
39 #include "max1363.h"
40
41 #define MAX1363_MODE_SINGLE(_num, _mask) { \
42 .conf = MAX1363_CHANNEL_SEL(_num) \
43 | MAX1363_CONFIG_SCAN_SINGLE_1 \
44 | MAX1363_CONFIG_SE, \
45 .modemask = _mask, \
46 }
47
48 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
49 .conf = MAX1363_CHANNEL_SEL(_num) \
50 | MAX1363_CONFIG_SCAN_TO_CS \
51 | MAX1363_CONFIG_SE, \
52 .modemask = _mask, \
53 }
54
55 /* note not available for max1363 hence naming */
56 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
57 .conf = MAX1363_CHANNEL_SEL(_num) \
58 | MAX1236_SCAN_MID_TO_CHANNEL \
59 | MAX1363_CONFIG_SE, \
60 .modemask = _mask \
61 }
62
63 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
64 .conf = MAX1363_CHANNEL_SEL(_nump) \
65 | MAX1363_CONFIG_SCAN_SINGLE_1 \
66 | MAX1363_CONFIG_DE, \
67 .modemask = _mask \
68 }
69
70 /* Can't think how to automate naming so specify for now */
71 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
72 .conf = MAX1363_CHANNEL_SEL(_num) \
73 | MAX1363_CONFIG_SCAN_TO_CS \
74 | MAX1363_CONFIG_DE, \
75 .modemask = _mask \
76 }
77
78 /* note only available for max1363 hence naming */
79 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
80 .conf = MAX1363_CHANNEL_SEL(_num) \
81 | MAX1236_SCAN_MID_TO_CHANNEL \
82 | MAX1363_CONFIG_SE, \
83 .modemask = _mask \
84 }
85
86 static const struct max1363_mode max1363_mode_table[] = {
87 /* All of the single channel options first */
88 MAX1363_MODE_SINGLE(0, 1 << 0),
89 MAX1363_MODE_SINGLE(1, 1 << 1),
90 MAX1363_MODE_SINGLE(2, 1 << 2),
91 MAX1363_MODE_SINGLE(3, 1 << 3),
92 MAX1363_MODE_SINGLE(4, 1 << 4),
93 MAX1363_MODE_SINGLE(5, 1 << 5),
94 MAX1363_MODE_SINGLE(6, 1 << 6),
95 MAX1363_MODE_SINGLE(7, 1 << 7),
96 MAX1363_MODE_SINGLE(8, 1 << 8),
97 MAX1363_MODE_SINGLE(9, 1 << 9),
98 MAX1363_MODE_SINGLE(10, 1 << 10),
99 MAX1363_MODE_SINGLE(11, 1 << 11),
100
101 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
102 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
103 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
104 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
105 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
106 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
107 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
108 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
109 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
110 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
111 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
112 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
113
114 /* The multichannel scans next */
115 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
116 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
117 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
118 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
119 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
120 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
121 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
122 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
123 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
124 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
125 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
126 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
127 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
128 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
129 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
130 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
131 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
132
133 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
134 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
135 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
136 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
137 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
138 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
139 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
140 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
141 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
142 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
143 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
144 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
145 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
146 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
147 };
148
149 const struct max1363_mode
150 *max1363_match_mode(u32 mask, const struct max1363_chip_info *ci)
151 {
152 int i;
153 if (mask)
154 for (i = 0; i < ci->num_modes; i++)
155 if (!((~max1363_mode_table[ci->mode_list[i]].modemask) &
156 mask))
157 return &max1363_mode_table[ci->mode_list[i]];
158 return NULL;
159 }
160
161 static int max1363_write_basic_config(struct i2c_client *client,
162 unsigned char d1,
163 unsigned char d2)
164 {
165 u8 tx_buf[2] = {d1, d2};
166
167 return i2c_master_send(client, tx_buf, 2);
168 }
169
170 int max1363_set_scan_mode(struct max1363_state *st)
171 {
172 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
173 | MAX1363_SCAN_MASK
174 | MAX1363_SE_DE_MASK);
175 st->configbyte |= st->current_mode->conf;
176
177 return max1363_write_basic_config(st->client,
178 st->setupbyte,
179 st->configbyte);
180 }
181
182 static int max1363_read_single_chan(struct iio_dev *indio_dev,
183 struct iio_chan_spec const *chan,
184 int *val,
185 long m)
186 {
187 int ret = 0;
188 s32 data;
189 char rxbuf[2];
190 long mask;
191 struct max1363_state *st = iio_priv(indio_dev);
192 struct i2c_client *client = st->client;
193
194 mutex_lock(&indio_dev->mlock);
195 /*
196 * If monitor mode is enabled, the method for reading a single
197 * channel will have to be rather different and has not yet
198 * been implemented.
199 */
200 if (st->monitor_on) {
201 ret = -EBUSY;
202 goto error_ret;
203 }
204
205 /* If ring buffer capture is occurring, query the buffer */
206 if (iio_ring_enabled(indio_dev)) {
207 mask = max1363_mode_table[chan->address].modemask;
208 data = max1363_single_channel_from_ring(mask, st);
209 if (data < 0) {
210 ret = data;
211 goto error_ret;
212 }
213 } else {
214 /* Check to see if current scan mode is correct */
215 if (st->current_mode != &max1363_mode_table[chan->address]) {
216 /* Update scan mode if needed */
217 st->current_mode = &max1363_mode_table[chan->address];
218 ret = max1363_set_scan_mode(st);
219 if (ret < 0)
220 goto error_ret;
221 }
222 if (st->chip_info->bits != 8) {
223 /* Get reading */
224 data = i2c_master_recv(client, rxbuf, 2);
225 if (data < 0) {
226 ret = data;
227 goto error_ret;
228 }
229 data = (s32)(rxbuf[1]) | ((s32)(rxbuf[0] & 0x0F)) << 8;
230 } else {
231 /* Get reading */
232 data = i2c_master_recv(client, rxbuf, 1);
233 if (data < 0) {
234 ret = data;
235 goto error_ret;
236 }
237 data = rxbuf[0];
238 }
239 }
240 *val = data;
241 error_ret:
242 mutex_unlock(&indio_dev->mlock);
243 return ret;
244
245 }
246
247 static int max1363_read_raw(struct iio_dev *indio_dev,
248 struct iio_chan_spec const *chan,
249 int *val,
250 int *val2,
251 long m)
252 {
253 struct max1363_state *st = iio_priv(indio_dev);
254 int ret;
255 switch (m) {
256 case 0:
257 ret = max1363_read_single_chan(indio_dev, chan, val, m);
258 if (ret < 0)
259 return ret;
260 return IIO_VAL_INT;
261 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
262 if ((1 << (st->chip_info->bits + 1)) >
263 st->chip_info->int_vref_mv) {
264 *val = 0;
265 *val2 = 500000;
266 return IIO_VAL_INT_PLUS_MICRO;
267 } else {
268 *val = (st->chip_info->int_vref_mv)
269 >> st->chip_info->bits;
270 return IIO_VAL_INT;
271 }
272 default:
273 return -EINVAL;
274 }
275 return 0;
276 }
277
278 /* Applies to max1363 */
279 static const enum max1363_modes max1363_mode_list[] = {
280 _s0, _s1, _s2, _s3,
281 s0to1, s0to2, s0to3,
282 d0m1, d2m3, d1m0, d3m2,
283 d0m1to2m3, d1m0to3m2,
284 };
285
286 #define MAX1363_EV_M \
287 (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) \
288 | IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
289 #define MAX1363_INFO_MASK (1 << IIO_CHAN_INFO_SCALE_SHARED)
290
291 static struct iio_chan_spec max1363_channels[] = {
292 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK,
293 _s0, 0, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
294 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
295 _s1, 1, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
296 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK,
297 _s2, 2, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
298 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK,
299 _s3, 3, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
300 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK,
301 d0m1, 4, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
302 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK,
303 d2m3, 5, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
304 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
305 d1m0, 6, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
306 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK,
307 d3m2, 7, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
308 IIO_CHAN_SOFT_TIMESTAMP(8)
309 };
310
311 static struct iio_chan_spec max1361_channels[] = {
312 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK,
313 _s0, 0, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
314 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
315 _s1, 1, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
316 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK,
317 _s2, 2, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
318 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK,
319 _s3, 3, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
320 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK,
321 d0m1, 4, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
322 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK,
323 d2m3, 5, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
324 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
325 d1m0, 6, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
326 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK,
327 d3m2, 7, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
328 IIO_CHAN_SOFT_TIMESTAMP(8)
329 };
330
331 #define MAX1363_CHAN_U(num, address, scan_index, bits) \
332 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, num, 0, MAX1363_INFO_MASK, \
333 address, scan_index, IIO_ST('u', bits, \
334 (bits == 8) ? 8 : 16, 0), 0)
335 /* bipolar channel */
336 #define MAX1363_CHAN_B(num, num2, address, scan_index, bits) \
337 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, num, num2, MAX1363_INFO_MASK,\
338 address, scan_index, IIO_ST('s', bits, \
339 (bits == 8) ? 8 : 16, 0), 0)
340
341 #define MAX1363_4X_CHANS(bits) { \
342 MAX1363_CHAN_U(0, _s0, 0, bits), \
343 MAX1363_CHAN_U(1, _s1, 1, bits), \
344 MAX1363_CHAN_U(2, _s2, 2, bits), \
345 MAX1363_CHAN_U(3, _s3, 3, bits), \
346 MAX1363_CHAN_B(0, 1, d0m1, 4, bits), \
347 MAX1363_CHAN_B(2, 3, d2m3, 5, bits), \
348 MAX1363_CHAN_B(1, 0, d1m0, 6, bits), \
349 MAX1363_CHAN_B(3, 2, d3m2, 7, bits), \
350 IIO_CHAN_SOFT_TIMESTAMP(8) \
351 }
352
353 static struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8);
354 static struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10);
355 static struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12);
356
357 /* Appies to max1236, max1237 */
358 static const enum max1363_modes max1236_mode_list[] = {
359 _s0, _s1, _s2, _s3,
360 s0to1, s0to2, s0to3,
361 d0m1, d2m3, d1m0, d3m2,
362 d0m1to2m3, d1m0to3m2,
363 s2to3,
364 };
365
366 /* Applies to max1238, max1239 */
367 static const enum max1363_modes max1238_mode_list[] = {
368 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
369 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
370 s0to7, s0to8, s0to9, s0to10, s0to11,
371 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
372 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
373 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
374 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
375 s6to7, s6to8, s6to9, s6to10, s6to11,
376 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
377 };
378
379 #define MAX1363_12X_CHANS(bits) { \
380 MAX1363_CHAN_U(0, _s0, 0, bits), \
381 MAX1363_CHAN_U(1, _s1, 1, bits), \
382 MAX1363_CHAN_U(2, _s2, 2, bits), \
383 MAX1363_CHAN_U(3, _s3, 3, bits), \
384 MAX1363_CHAN_U(4, _s4, 4, bits), \
385 MAX1363_CHAN_U(5, _s5, 5, bits), \
386 MAX1363_CHAN_U(6, _s6, 6, bits), \
387 MAX1363_CHAN_U(7, _s7, 7, bits), \
388 MAX1363_CHAN_U(8, _s8, 8, bits), \
389 MAX1363_CHAN_U(9, _s9, 9, bits), \
390 MAX1363_CHAN_U(10, _s10, 10, bits), \
391 MAX1363_CHAN_U(11, _s11, 11, bits), \
392 MAX1363_CHAN_B(0, 1, d0m1, 12, bits), \
393 MAX1363_CHAN_B(2, 3, d2m3, 13, bits), \
394 MAX1363_CHAN_B(4, 5, d4m5, 14, bits), \
395 MAX1363_CHAN_B(6, 7, d6m7, 15, bits), \
396 MAX1363_CHAN_B(8, 9, d8m9, 16, bits), \
397 MAX1363_CHAN_B(10, 11, d10m11, 17, bits), \
398 MAX1363_CHAN_B(1, 0, d1m0, 18, bits), \
399 MAX1363_CHAN_B(3, 2, d3m2, 19, bits), \
400 MAX1363_CHAN_B(5, 4, d5m4, 20, bits), \
401 MAX1363_CHAN_B(7, 6, d7m6, 21, bits), \
402 MAX1363_CHAN_B(9, 8, d9m8, 22, bits), \
403 MAX1363_CHAN_B(11, 10, d11m10, 23, bits), \
404 IIO_CHAN_SOFT_TIMESTAMP(24) \
405 }
406 static struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
407 static struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
408 static struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
409
410 static const enum max1363_modes max11607_mode_list[] = {
411 _s0, _s1, _s2, _s3,
412 s0to1, s0to2, s0to3,
413 s2to3,
414 d0m1, d2m3, d1m0, d3m2,
415 d0m1to2m3, d1m0to3m2,
416 };
417
418 static const enum max1363_modes max11608_mode_list[] = {
419 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
420 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
421 s6to7,
422 d0m1, d2m3, d4m5, d6m7,
423 d1m0, d3m2, d5m4, d7m6,
424 d0m1to2m3, d0m1to4m5, d0m1to6m7,
425 d1m0to3m2, d1m0to5m4, d1m0to7m6,
426 };
427
428 #define MAX1363_8X_CHANS(bits) { \
429 MAX1363_CHAN_U(0, _s0, 0, bits), \
430 MAX1363_CHAN_U(1, _s1, 1, bits), \
431 MAX1363_CHAN_U(2, _s2, 2, bits), \
432 MAX1363_CHAN_U(3, _s3, 3, bits), \
433 MAX1363_CHAN_U(4, _s4, 4, bits), \
434 MAX1363_CHAN_U(5, _s5, 5, bits), \
435 MAX1363_CHAN_U(6, _s6, 6, bits), \
436 MAX1363_CHAN_U(7, _s7, 7, bits), \
437 MAX1363_CHAN_B(0, 1, d0m1, 8, bits), \
438 MAX1363_CHAN_B(2, 3, d2m3, 9, bits), \
439 MAX1363_CHAN_B(4, 5, d4m5, 10, bits), \
440 MAX1363_CHAN_B(6, 7, d6m7, 11, bits), \
441 MAX1363_CHAN_B(1, 0, d1m0, 12, bits), \
442 MAX1363_CHAN_B(3, 2, d3m2, 13, bits), \
443 MAX1363_CHAN_B(5, 4, d5m4, 14, bits), \
444 MAX1363_CHAN_B(7, 6, d7m6, 15, bits), \
445 IIO_CHAN_SOFT_TIMESTAMP(16) \
446 }
447 static struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
448 static struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
449 static struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
450
451 static const enum max1363_modes max11644_mode_list[] = {
452 _s0, _s1, s0to1, d0m1, d1m0,
453 };
454
455 #define MAX1363_2X_CHANS(bits) { \
456 MAX1363_CHAN_U(0, _s0, 0, bits), \
457 MAX1363_CHAN_U(1, _s1, 1, bits), \
458 MAX1363_CHAN_B(0, 1, d0m1, 2, bits), \
459 MAX1363_CHAN_B(1, 0, d1m0, 3, bits), \
460 IIO_CHAN_SOFT_TIMESTAMP(4) \
461 }
462
463 static struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
464 static struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
465
466 enum { max1361,
467 max1362,
468 max1363,
469 max1364,
470 max1036,
471 max1037,
472 max1038,
473 max1039,
474 max1136,
475 max1137,
476 max1138,
477 max1139,
478 max1236,
479 max1237,
480 max1238,
481 max1239,
482 max11600,
483 max11601,
484 max11602,
485 max11603,
486 max11604,
487 max11605,
488 max11606,
489 max11607,
490 max11608,
491 max11609,
492 max11610,
493 max11611,
494 max11612,
495 max11613,
496 max11614,
497 max11615,
498 max11616,
499 max11617,
500 max11644,
501 max11645,
502 max11646,
503 max11647
504 };
505
506 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
507 8300, 4200, 2000, 1000 };
508
509 static ssize_t max1363_monitor_show_freq(struct device *dev,
510 struct device_attribute *attr,
511 char *buf)
512 {
513 struct max1363_state *st = iio_priv(dev_get_drvdata(dev));
514 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
515 }
516
517 static ssize_t max1363_monitor_store_freq(struct device *dev,
518 struct device_attribute *attr,
519 const char *buf,
520 size_t len)
521 {
522 struct iio_dev *indio_dev = dev_get_drvdata(dev);
523 struct max1363_state *st = iio_priv(indio_dev);
524 int i, ret;
525 unsigned long val;
526 bool found = false;
527
528 ret = strict_strtoul(buf, 10, &val);
529 if (ret)
530 return -EINVAL;
531 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
532 if (val == max1363_monitor_speeds[i]) {
533 found = true;
534 break;
535 }
536 if (!found)
537 return -EINVAL;
538
539 mutex_lock(&indio_dev->mlock);
540 st->monitor_speed = i;
541 mutex_unlock(&indio_dev->mlock);
542
543 return 0;
544 }
545
546 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
547 max1363_monitor_show_freq,
548 max1363_monitor_store_freq);
549
550 static IIO_CONST_ATTR(sampling_frequency_available,
551 "133000 665000 33300 16600 8300 4200 2000 1000");
552
553 static int max1363_read_thresh(struct iio_dev *indio_dev,
554 int event_code,
555 int *val)
556 {
557 struct max1363_state *st = iio_priv(indio_dev);
558 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
559 *val = st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
560 else
561 *val = st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
562 return 0;
563 }
564
565 static int max1363_write_thresh(struct iio_dev *indio_dev,
566 int event_code,
567 int val)
568 {
569 struct max1363_state *st = iio_priv(indio_dev);
570 /* make it handle signed correctly as well */
571 switch (st->chip_info->bits) {
572 case 10:
573 if (val > 0x3FF)
574 return -EINVAL;
575 break;
576 case 12:
577 if (val > 0xFFF)
578 return -EINVAL;
579 break;
580 }
581
582 switch (IIO_EVENT_CODE_EXTRACT_DIR(event_code)) {
583 case IIO_EV_DIR_FALLING:
584 st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
585 break;
586 case IIO_EV_DIR_RISING:
587 st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
588 break;
589 }
590
591 return 0;
592 }
593
594 static const int max1363_event_codes[] = {
595 IIO_UNMOD_EVENT_CODE(IIO_IN, 0, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
596 IIO_UNMOD_EVENT_CODE(IIO_IN, 1, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
597 IIO_UNMOD_EVENT_CODE(IIO_IN, 2, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
598 IIO_UNMOD_EVENT_CODE(IIO_IN, 3, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
599 IIO_UNMOD_EVENT_CODE(IIO_IN, 0, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
600 IIO_UNMOD_EVENT_CODE(IIO_IN, 1, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
601 IIO_UNMOD_EVENT_CODE(IIO_IN, 2, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
602 IIO_UNMOD_EVENT_CODE(IIO_IN, 3, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
603 };
604
605 static irqreturn_t max1363_event_handler(int irq, void *private)
606 {
607 struct iio_dev *indio_dev = private;
608 struct max1363_state *st = iio_priv(indio_dev);
609 s64 timestamp = iio_get_time_ns();
610 unsigned long mask, loc;
611 u8 rx;
612 u8 tx[2] = { st->setupbyte,
613 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
614
615 i2c_master_recv(st->client, &rx, 1);
616 mask = rx;
617 for_each_set_bit(loc, &mask, 8)
618 iio_push_event(indio_dev, 0, max1363_event_codes[loc],
619 timestamp);
620 i2c_master_send(st->client, tx, 2);
621
622 return IRQ_HANDLED;
623 }
624
625 static int max1363_read_event_config(struct iio_dev *indio_dev,
626 int event_code)
627 {
628 struct max1363_state *st = iio_priv(indio_dev);
629
630 int val;
631 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
632 mutex_lock(&indio_dev->mlock);
633 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
634 val = (1 << number) & st->mask_low;
635 else
636 val = (1 << number) & st->mask_high;
637 mutex_unlock(&indio_dev->mlock);
638
639 return val;
640 }
641
642 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
643 {
644 u8 *tx_buf;
645 int ret, i = 3, j;
646 unsigned long numelements;
647 int len;
648 long modemask;
649
650 if (!enabled) {
651 /* transition to ring capture is not currently supported */
652 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
653 st->configbyte &= ~MAX1363_SCAN_MASK;
654 st->monitor_on = false;
655 return max1363_write_basic_config(st->client,
656 st->setupbyte,
657 st->configbyte);
658 }
659
660 /* Ensure we are in the relevant mode */
661 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
662 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
663 | MAX1363_SCAN_MASK
664 | MAX1363_SE_DE_MASK);
665 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
666 if ((st->mask_low | st->mask_high) & 0x0F) {
667 st->configbyte |= max1363_mode_table[s0to3].conf;
668 modemask = max1363_mode_table[s0to3].modemask;
669 } else if ((st->mask_low | st->mask_high) & 0x30) {
670 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
671 modemask = max1363_mode_table[d0m1to2m3].modemask;
672 } else {
673 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
674 modemask = max1363_mode_table[d1m0to3m2].modemask;
675 }
676 numelements = hweight_long(modemask);
677 len = 3 * numelements + 3;
678 tx_buf = kmalloc(len, GFP_KERNEL);
679 if (!tx_buf) {
680 ret = -ENOMEM;
681 goto error_ret;
682 }
683 tx_buf[0] = st->configbyte;
684 tx_buf[1] = st->setupbyte;
685 tx_buf[2] = (st->monitor_speed << 1);
686
687 /*
688 * So we need to do yet another bit of nefarious scan mode
689 * setup to match what we need.
690 */
691 for (j = 0; j < 8; j++)
692 if (modemask & (1 << j)) {
693 /* Establish the mode is in the scan */
694 if (st->mask_low & (1 << j)) {
695 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
696 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
697 } else if (j < 4) {
698 tx_buf[i] = 0;
699 tx_buf[i + 1] = 0;
700 } else {
701 tx_buf[i] = 0x80;
702 tx_buf[i + 1] = 0;
703 }
704 if (st->mask_high & (1 << j)) {
705 tx_buf[i + 1] |=
706 (st->thresh_high[j] >> 8) & 0x0F;
707 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
708 } else if (j < 4) {
709 tx_buf[i + 1] |= 0x0F;
710 tx_buf[i + 2] = 0xFF;
711 } else {
712 tx_buf[i + 1] |= 0x07;
713 tx_buf[i + 2] = 0xFF;
714 }
715 i += 3;
716 }
717
718
719 ret = i2c_master_send(st->client, tx_buf, len);
720 if (ret < 0)
721 goto error_ret;
722 if (ret != len) {
723 ret = -EIO;
724 goto error_ret;
725 }
726
727 /*
728 * Now that we hopefully have sensible thresholds in place it is
729 * time to turn the interrupts on.
730 * It is unclear from the data sheet if this should be necessary
731 * (i.e. whether monitor mode setup is atomic) but it appears to
732 * be in practice.
733 */
734 tx_buf[0] = st->setupbyte;
735 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
736 ret = i2c_master_send(st->client, tx_buf, 2);
737 if (ret < 0)
738 goto error_ret;
739 if (ret != 2) {
740 ret = -EIO;
741 goto error_ret;
742 }
743 ret = 0;
744 st->monitor_on = true;
745 error_ret:
746
747 kfree(tx_buf);
748
749 return ret;
750 }
751
752 /*
753 * To keep this manageable we always use one of 3 scan modes.
754 * Scan 0...3, 0-1,2-3 and 1-0,3-2
755 */
756
757 static inline int __max1363_check_event_mask(int thismask, int checkmask)
758 {
759 int ret = 0;
760 /* Is it unipolar */
761 if (thismask < 4) {
762 if (checkmask & ~0x0F) {
763 ret = -EBUSY;
764 goto error_ret;
765 }
766 } else if (thismask < 6) {
767 if (checkmask & ~0x30) {
768 ret = -EBUSY;
769 goto error_ret;
770 }
771 } else if (checkmask & ~0xC0)
772 ret = -EBUSY;
773 error_ret:
774 return ret;
775 }
776
777 static int max1363_write_event_config(struct iio_dev *indio_dev,
778 int event_code,
779 int state)
780 {
781 int ret = 0;
782 struct max1363_state *st = iio_priv(indio_dev);
783 u16 unifiedmask;
784 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
785
786 mutex_lock(&indio_dev->mlock);
787 unifiedmask = st->mask_low | st->mask_high;
788 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) {
789
790 if (state == 0)
791 st->mask_low &= ~(1 << number);
792 else {
793 ret = __max1363_check_event_mask((1 << number),
794 unifiedmask);
795 if (ret)
796 goto error_ret;
797 st->mask_low |= (1 << number);
798 }
799 } else {
800 if (state == 0)
801 st->mask_high &= ~(1 << number);
802 else {
803 ret = __max1363_check_event_mask((1 << number),
804 unifiedmask);
805 if (ret)
806 goto error_ret;
807 st->mask_high |= (1 << number);
808 }
809 }
810
811 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
812 error_ret:
813 mutex_unlock(&indio_dev->mlock);
814
815 return ret;
816 }
817
818 /*
819 * As with scan_elements, only certain sets of these can
820 * be combined.
821 */
822 static struct attribute *max1363_event_attributes[] = {
823 &iio_dev_attr_sampling_frequency.dev_attr.attr,
824 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
825 NULL,
826 };
827
828 static struct attribute_group max1363_event_attribute_group = {
829 .attrs = max1363_event_attributes,
830 .name = "events",
831 };
832
833 #define MAX1363_EVENT_FUNCS \
834
835
836 static const struct iio_info max1238_info = {
837 .read_raw = &max1363_read_raw,
838 .driver_module = THIS_MODULE,
839 };
840
841 static const struct iio_info max1363_info = {
842 .read_event_value = &max1363_read_thresh,
843 .write_event_value = &max1363_write_thresh,
844 .read_event_config = &max1363_read_event_config,
845 .write_event_config = &max1363_write_event_config,
846 .read_raw = &max1363_read_raw,
847 .driver_module = THIS_MODULE,
848 .num_interrupt_lines = 1,
849 .event_attrs = &max1363_event_attribute_group,
850 };
851
852 /* max1363 and max1368 tested - rest from data sheet */
853 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
854 [max1361] = {
855 .bits = 10,
856 .int_vref_mv = 2048,
857 .mode_list = max1363_mode_list,
858 .num_modes = ARRAY_SIZE(max1363_mode_list),
859 .default_mode = s0to3,
860 .channels = max1361_channels,
861 .num_channels = ARRAY_SIZE(max1361_channels),
862 .info = &max1363_info,
863 },
864 [max1362] = {
865 .bits = 10,
866 .int_vref_mv = 4096,
867 .mode_list = max1363_mode_list,
868 .num_modes = ARRAY_SIZE(max1363_mode_list),
869 .default_mode = s0to3,
870 .channels = max1361_channels,
871 .num_channels = ARRAY_SIZE(max1361_channels),
872 .info = &max1363_info,
873 },
874 [max1363] = {
875 .bits = 12,
876 .int_vref_mv = 2048,
877 .mode_list = max1363_mode_list,
878 .num_modes = ARRAY_SIZE(max1363_mode_list),
879 .default_mode = s0to3,
880 .channels = max1363_channels,
881 .num_channels = ARRAY_SIZE(max1363_channels),
882 .info = &max1363_info,
883 },
884 [max1364] = {
885 .bits = 12,
886 .int_vref_mv = 4096,
887 .mode_list = max1363_mode_list,
888 .num_modes = ARRAY_SIZE(max1363_mode_list),
889 .default_mode = s0to3,
890 .channels = max1363_channels,
891 .num_channels = ARRAY_SIZE(max1363_channels),
892 .info = &max1363_info,
893 },
894 [max1036] = {
895 .bits = 8,
896 .int_vref_mv = 4096,
897 .mode_list = max1236_mode_list,
898 .num_modes = ARRAY_SIZE(max1236_mode_list),
899 .default_mode = s0to3,
900 .info = &max1238_info,
901 .channels = max1036_channels,
902 .num_channels = ARRAY_SIZE(max1036_channels),
903 },
904 [max1037] = {
905 .bits = 8,
906 .int_vref_mv = 2048,
907 .mode_list = max1236_mode_list,
908 .num_modes = ARRAY_SIZE(max1236_mode_list),
909 .default_mode = s0to3,
910 .info = &max1238_info,
911 .channels = max1036_channels,
912 .num_channels = ARRAY_SIZE(max1036_channels),
913 },
914 [max1038] = {
915 .bits = 8,
916 .int_vref_mv = 4096,
917 .mode_list = max1238_mode_list,
918 .num_modes = ARRAY_SIZE(max1238_mode_list),
919 .default_mode = s0to11,
920 .info = &max1238_info,
921 .channels = max1038_channels,
922 .num_channels = ARRAY_SIZE(max1038_channels),
923 },
924 [max1039] = {
925 .bits = 8,
926 .int_vref_mv = 2048,
927 .mode_list = max1238_mode_list,
928 .num_modes = ARRAY_SIZE(max1238_mode_list),
929 .default_mode = s0to11,
930 .info = &max1238_info,
931 .channels = max1038_channels,
932 .num_channels = ARRAY_SIZE(max1038_channels),
933 },
934 [max1136] = {
935 .bits = 10,
936 .int_vref_mv = 4096,
937 .mode_list = max1236_mode_list,
938 .num_modes = ARRAY_SIZE(max1236_mode_list),
939 .default_mode = s0to3,
940 .info = &max1238_info,
941 .channels = max1136_channels,
942 .num_channels = ARRAY_SIZE(max1136_channels),
943 },
944 [max1137] = {
945 .bits = 10,
946 .int_vref_mv = 2048,
947 .mode_list = max1236_mode_list,
948 .num_modes = ARRAY_SIZE(max1236_mode_list),
949 .default_mode = s0to3,
950 .info = &max1238_info,
951 .channels = max1136_channels,
952 .num_channels = ARRAY_SIZE(max1136_channels),
953 },
954 [max1138] = {
955 .bits = 10,
956 .int_vref_mv = 4096,
957 .mode_list = max1238_mode_list,
958 .num_modes = ARRAY_SIZE(max1238_mode_list),
959 .default_mode = s0to11,
960 .info = &max1238_info,
961 .channels = max1138_channels,
962 .num_channels = ARRAY_SIZE(max1138_channels),
963 },
964 [max1139] = {
965 .bits = 10,
966 .int_vref_mv = 2048,
967 .mode_list = max1238_mode_list,
968 .num_modes = ARRAY_SIZE(max1238_mode_list),
969 .default_mode = s0to11,
970 .info = &max1238_info,
971 .channels = max1138_channels,
972 .num_channels = ARRAY_SIZE(max1138_channels),
973 },
974 [max1236] = {
975 .bits = 12,
976 .int_vref_mv = 4096,
977 .mode_list = max1236_mode_list,
978 .num_modes = ARRAY_SIZE(max1236_mode_list),
979 .default_mode = s0to3,
980 .info = &max1238_info,
981 .channels = max1236_channels,
982 .num_channels = ARRAY_SIZE(max1236_channels),
983 },
984 [max1237] = {
985 .bits = 12,
986 .int_vref_mv = 2048,
987 .mode_list = max1236_mode_list,
988 .num_modes = ARRAY_SIZE(max1236_mode_list),
989 .default_mode = s0to3,
990 .info = &max1238_info,
991 .channels = max1236_channels,
992 .num_channels = ARRAY_SIZE(max1236_channels),
993 },
994 [max1238] = {
995 .bits = 12,
996 .int_vref_mv = 4096,
997 .mode_list = max1238_mode_list,
998 .num_modes = ARRAY_SIZE(max1238_mode_list),
999 .default_mode = s0to11,
1000 .info = &max1238_info,
1001 .channels = max1238_channels,
1002 .num_channels = ARRAY_SIZE(max1238_channels),
1003 },
1004 [max1239] = {
1005 .bits = 12,
1006 .int_vref_mv = 2048,
1007 .mode_list = max1238_mode_list,
1008 .num_modes = ARRAY_SIZE(max1238_mode_list),
1009 .default_mode = s0to11,
1010 .info = &max1238_info,
1011 .channels = max1238_channels,
1012 .num_channels = ARRAY_SIZE(max1238_channels),
1013 },
1014 [max11600] = {
1015 .bits = 8,
1016 .int_vref_mv = 4096,
1017 .mode_list = max11607_mode_list,
1018 .num_modes = ARRAY_SIZE(max11607_mode_list),
1019 .default_mode = s0to3,
1020 .info = &max1238_info,
1021 .channels = max1036_channels,
1022 .num_channels = ARRAY_SIZE(max1036_channels),
1023 },
1024 [max11601] = {
1025 .bits = 8,
1026 .int_vref_mv = 2048,
1027 .mode_list = max11607_mode_list,
1028 .num_modes = ARRAY_SIZE(max11607_mode_list),
1029 .default_mode = s0to3,
1030 .info = &max1238_info,
1031 .channels = max1036_channels,
1032 .num_channels = ARRAY_SIZE(max1036_channels),
1033 },
1034 [max11602] = {
1035 .bits = 8,
1036 .int_vref_mv = 4096,
1037 .mode_list = max11608_mode_list,
1038 .num_modes = ARRAY_SIZE(max11608_mode_list),
1039 .default_mode = s0to7,
1040 .info = &max1238_info,
1041 .channels = max11602_channels,
1042 .num_channels = ARRAY_SIZE(max11602_channels),
1043 },
1044 [max11603] = {
1045 .bits = 8,
1046 .int_vref_mv = 2048,
1047 .mode_list = max11608_mode_list,
1048 .num_modes = ARRAY_SIZE(max11608_mode_list),
1049 .default_mode = s0to7,
1050 .info = &max1238_info,
1051 .channels = max11602_channels,
1052 .num_channels = ARRAY_SIZE(max11602_channels),
1053 },
1054 [max11604] = {
1055 .bits = 8,
1056 .int_vref_mv = 4098,
1057 .mode_list = max1238_mode_list,
1058 .num_modes = ARRAY_SIZE(max1238_mode_list),
1059 .default_mode = s0to11,
1060 .info = &max1238_info,
1061 .channels = max1238_channels,
1062 .num_channels = ARRAY_SIZE(max1238_channels),
1063 },
1064 [max11605] = {
1065 .bits = 8,
1066 .int_vref_mv = 2048,
1067 .mode_list = max1238_mode_list,
1068 .num_modes = ARRAY_SIZE(max1238_mode_list),
1069 .default_mode = s0to11,
1070 .info = &max1238_info,
1071 .channels = max1238_channels,
1072 .num_channels = ARRAY_SIZE(max1238_channels),
1073 },
1074 [max11606] = {
1075 .bits = 10,
1076 .int_vref_mv = 4096,
1077 .mode_list = max11607_mode_list,
1078 .num_modes = ARRAY_SIZE(max11607_mode_list),
1079 .default_mode = s0to3,
1080 .info = &max1238_info,
1081 .channels = max1136_channels,
1082 .num_channels = ARRAY_SIZE(max1136_channels),
1083 },
1084 [max11607] = {
1085 .bits = 10,
1086 .int_vref_mv = 2048,
1087 .mode_list = max11607_mode_list,
1088 .num_modes = ARRAY_SIZE(max11607_mode_list),
1089 .default_mode = s0to3,
1090 .info = &max1238_info,
1091 .channels = max1136_channels,
1092 .num_channels = ARRAY_SIZE(max1136_channels),
1093 },
1094 [max11608] = {
1095 .bits = 10,
1096 .int_vref_mv = 4096,
1097 .mode_list = max11608_mode_list,
1098 .num_modes = ARRAY_SIZE(max11608_mode_list),
1099 .default_mode = s0to7,
1100 .info = &max1238_info,
1101 .channels = max11608_channels,
1102 .num_channels = ARRAY_SIZE(max11608_channels),
1103 },
1104 [max11609] = {
1105 .bits = 10,
1106 .int_vref_mv = 2048,
1107 .mode_list = max11608_mode_list,
1108 .num_modes = ARRAY_SIZE(max11608_mode_list),
1109 .default_mode = s0to7,
1110 .info = &max1238_info,
1111 .channels = max11608_channels,
1112 .num_channels = ARRAY_SIZE(max11608_channels),
1113 },
1114 [max11610] = {
1115 .bits = 10,
1116 .int_vref_mv = 4098,
1117 .mode_list = max1238_mode_list,
1118 .num_modes = ARRAY_SIZE(max1238_mode_list),
1119 .default_mode = s0to11,
1120 .info = &max1238_info,
1121 .channels = max1238_channels,
1122 .num_channels = ARRAY_SIZE(max1238_channels),
1123 },
1124 [max11611] = {
1125 .bits = 10,
1126 .int_vref_mv = 2048,
1127 .mode_list = max1238_mode_list,
1128 .num_modes = ARRAY_SIZE(max1238_mode_list),
1129 .default_mode = s0to11,
1130 .info = &max1238_info,
1131 .channels = max1238_channels,
1132 .num_channels = ARRAY_SIZE(max1238_channels),
1133 },
1134 [max11612] = {
1135 .bits = 12,
1136 .int_vref_mv = 4096,
1137 .mode_list = max11607_mode_list,
1138 .num_modes = ARRAY_SIZE(max11607_mode_list),
1139 .default_mode = s0to3,
1140 .info = &max1238_info,
1141 .channels = max1363_channels,
1142 .num_channels = ARRAY_SIZE(max1363_channels),
1143 },
1144 [max11613] = {
1145 .bits = 12,
1146 .int_vref_mv = 2048,
1147 .mode_list = max11607_mode_list,
1148 .num_modes = ARRAY_SIZE(max11607_mode_list),
1149 .default_mode = s0to3,
1150 .info = &max1238_info,
1151 .channels = max1363_channels,
1152 .num_channels = ARRAY_SIZE(max1363_channels),
1153 },
1154 [max11614] = {
1155 .bits = 12,
1156 .int_vref_mv = 4096,
1157 .mode_list = max11608_mode_list,
1158 .num_modes = ARRAY_SIZE(max11608_mode_list),
1159 .default_mode = s0to7,
1160 .info = &max1238_info,
1161 .channels = max11614_channels,
1162 .num_channels = ARRAY_SIZE(max11614_channels),
1163 },
1164 [max11615] = {
1165 .bits = 12,
1166 .int_vref_mv = 2048,
1167 .mode_list = max11608_mode_list,
1168 .num_modes = ARRAY_SIZE(max11608_mode_list),
1169 .default_mode = s0to7,
1170 .info = &max1238_info,
1171 .channels = max11614_channels,
1172 .num_channels = ARRAY_SIZE(max11614_channels),
1173 },
1174 [max11616] = {
1175 .bits = 12,
1176 .int_vref_mv = 4098,
1177 .mode_list = max1238_mode_list,
1178 .num_modes = ARRAY_SIZE(max1238_mode_list),
1179 .default_mode = s0to11,
1180 .info = &max1238_info,
1181 .channels = max1238_channels,
1182 .num_channels = ARRAY_SIZE(max1238_channels),
1183 },
1184 [max11617] = {
1185 .bits = 12,
1186 .int_vref_mv = 2048,
1187 .mode_list = max1238_mode_list,
1188 .num_modes = ARRAY_SIZE(max1238_mode_list),
1189 .default_mode = s0to11,
1190 .info = &max1238_info,
1191 .channels = max1238_channels,
1192 .num_channels = ARRAY_SIZE(max1238_channels),
1193 },
1194 [max11644] = {
1195 .bits = 12,
1196 .int_vref_mv = 2048,
1197 .mode_list = max11644_mode_list,
1198 .num_modes = ARRAY_SIZE(max11644_mode_list),
1199 .default_mode = s0to1,
1200 .info = &max1238_info,
1201 .channels = max11644_channels,
1202 .num_channels = ARRAY_SIZE(max11644_channels),
1203 },
1204 [max11645] = {
1205 .bits = 12,
1206 .int_vref_mv = 4096,
1207 .mode_list = max11644_mode_list,
1208 .num_modes = ARRAY_SIZE(max11644_mode_list),
1209 .default_mode = s0to1,
1210 .info = &max1238_info,
1211 .channels = max11644_channels,
1212 .num_channels = ARRAY_SIZE(max11644_channels),
1213 },
1214 [max11646] = {
1215 .bits = 10,
1216 .int_vref_mv = 2048,
1217 .mode_list = max11644_mode_list,
1218 .num_modes = ARRAY_SIZE(max11644_mode_list),
1219 .default_mode = s0to1,
1220 .info = &max1238_info,
1221 .channels = max11646_channels,
1222 .num_channels = ARRAY_SIZE(max11646_channels),
1223 },
1224 [max11647] = {
1225 .bits = 10,
1226 .int_vref_mv = 4096,
1227 .mode_list = max11644_mode_list,
1228 .num_modes = ARRAY_SIZE(max11644_mode_list),
1229 .default_mode = s0to1,
1230 .info = &max1238_info,
1231 .channels = max11646_channels,
1232 .num_channels = ARRAY_SIZE(max11646_channels),
1233 },
1234 };
1235
1236
1237
1238 static int max1363_initial_setup(struct max1363_state *st)
1239 {
1240 st->setupbyte = MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD
1241 | MAX1363_SETUP_POWER_UP_INT_REF
1242 | MAX1363_SETUP_INT_CLOCK
1243 | MAX1363_SETUP_UNIPOLAR
1244 | MAX1363_SETUP_NORESET;
1245
1246 /* Set scan mode writes the config anyway so wait until then*/
1247 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1248 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1249 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1250
1251 return max1363_set_scan_mode(st);
1252 }
1253
1254 static int __devinit max1363_probe(struct i2c_client *client,
1255 const struct i2c_device_id *id)
1256 {
1257 int ret, i, regdone = 0;
1258 struct max1363_state *st;
1259 struct iio_dev *indio_dev;
1260 struct regulator *reg;
1261
1262 reg = regulator_get(&client->dev, "vcc");
1263 if (IS_ERR(reg)) {
1264 ret = PTR_ERR(reg);
1265 goto error_out;
1266 }
1267
1268 ret = regulator_enable(reg);
1269 if (ret)
1270 goto error_put_reg;
1271
1272 indio_dev = iio_allocate_device(sizeof(struct max1363_state));
1273 if (indio_dev == NULL) {
1274 ret = -ENOMEM;
1275 goto error_disable_reg;
1276 }
1277 st = iio_priv(indio_dev);
1278 st->reg = reg;
1279 /* this is only used for device removal purposes */
1280 i2c_set_clientdata(client, indio_dev);
1281
1282 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1283 st->client = client;
1284
1285 indio_dev->available_scan_masks
1286 = kzalloc(sizeof(*indio_dev->available_scan_masks)*
1287 (st->chip_info->num_modes + 1), GFP_KERNEL);
1288 if (!indio_dev->available_scan_masks) {
1289 ret = -ENOMEM;
1290 goto error_free_device;
1291 }
1292
1293 for (i = 0; i < st->chip_info->num_modes; i++)
1294 indio_dev->available_scan_masks[i] =
1295 max1363_mode_table[st->chip_info->mode_list[i]]
1296 .modemask;
1297 /* Estabilish that the iio_dev is a child of the i2c device */
1298 indio_dev->dev.parent = &client->dev;
1299 indio_dev->name = id->name;
1300 indio_dev->channels = st->chip_info->channels;
1301 indio_dev->num_channels = st->chip_info->num_channels;
1302 indio_dev->info = st->chip_info->info;
1303 indio_dev->modes = INDIO_DIRECT_MODE;
1304 indio_dev->channels = st->chip_info->channels;
1305 indio_dev->num_channels = st->chip_info->num_channels;
1306 ret = max1363_initial_setup(st);
1307 if (ret < 0)
1308 goto error_free_available_scan_masks;
1309
1310 ret = max1363_register_ring_funcs_and_init(indio_dev);
1311 if (ret)
1312 goto error_free_available_scan_masks;
1313
1314 ret = iio_device_register(indio_dev);
1315 if (ret)
1316 goto error_cleanup_ring;
1317 regdone = 1;
1318 ret = iio_ring_buffer_register_ex(indio_dev, 0,
1319 st->chip_info->channels,
1320 st->chip_info->num_channels);
1321 if (ret)
1322 goto error_cleanup_ring;
1323
1324 if (client->irq) {
1325 ret = request_threaded_irq(st->client->irq,
1326 NULL,
1327 &max1363_event_handler,
1328 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1329 "max1363_event",
1330 indio_dev);
1331
1332 if (ret)
1333 goto error_uninit_ring;
1334 }
1335
1336 return 0;
1337
1338 error_uninit_ring:
1339 iio_ring_buffer_unregister(indio_dev);
1340 error_cleanup_ring:
1341 max1363_ring_cleanup(indio_dev);
1342 error_free_available_scan_masks:
1343 kfree(indio_dev->available_scan_masks);
1344 error_free_device:
1345 if (!regdone)
1346 iio_free_device(indio_dev);
1347 else
1348 iio_device_unregister(indio_dev);
1349 error_disable_reg:
1350 regulator_disable(reg);
1351 error_put_reg:
1352 regulator_put(reg);
1353 error_out:
1354 return ret;
1355 }
1356
1357 static int max1363_remove(struct i2c_client *client)
1358 {
1359 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1360 struct max1363_state *st = iio_priv(indio_dev);
1361 struct regulator *reg = st->reg;
1362
1363 if (client->irq)
1364 free_irq(st->client->irq, indio_dev);
1365 iio_ring_buffer_unregister(indio_dev);
1366 max1363_ring_cleanup(indio_dev);
1367 kfree(indio_dev->available_scan_masks);
1368 if (!IS_ERR(reg)) {
1369 regulator_disable(reg);
1370 regulator_put(reg);
1371 }
1372 iio_device_unregister(indio_dev);
1373
1374 return 0;
1375 }
1376
1377 static const struct i2c_device_id max1363_id[] = {
1378 { "max1361", max1361 },
1379 { "max1362", max1362 },
1380 { "max1363", max1363 },
1381 { "max1364", max1364 },
1382 { "max1036", max1036 },
1383 { "max1037", max1037 },
1384 { "max1038", max1038 },
1385 { "max1039", max1039 },
1386 { "max1136", max1136 },
1387 { "max1137", max1137 },
1388 { "max1138", max1138 },
1389 { "max1139", max1139 },
1390 { "max1236", max1236 },
1391 { "max1237", max1237 },
1392 { "max1238", max1238 },
1393 { "max1239", max1239 },
1394 { "max11600", max11600 },
1395 { "max11601", max11601 },
1396 { "max11602", max11602 },
1397 { "max11603", max11603 },
1398 { "max11604", max11604 },
1399 { "max11605", max11605 },
1400 { "max11606", max11606 },
1401 { "max11607", max11607 },
1402 { "max11608", max11608 },
1403 { "max11609", max11609 },
1404 { "max11610", max11610 },
1405 { "max11611", max11611 },
1406 { "max11612", max11612 },
1407 { "max11613", max11613 },
1408 { "max11614", max11614 },
1409 { "max11615", max11615 },
1410 { "max11616", max11616 },
1411 { "max11617", max11617 },
1412 {}
1413 };
1414
1415 MODULE_DEVICE_TABLE(i2c, max1363_id);
1416
1417 static struct i2c_driver max1363_driver = {
1418 .driver = {
1419 .name = "max1363",
1420 },
1421 .probe = max1363_probe,
1422 .remove = max1363_remove,
1423 .id_table = max1363_id,
1424 };
1425
1426 static __init int max1363_init(void)
1427 {
1428 return i2c_add_driver(&max1363_driver);
1429 }
1430
1431 static __exit void max1363_exit(void)
1432 {
1433 i2c_del_driver(&max1363_driver);
1434 }
1435
1436 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
1437 MODULE_DESCRIPTION("Maxim 1363 ADC");
1438 MODULE_LICENSE("GPL v2");
1439
1440 module_init(max1363_init);
1441 module_exit(max1363_exit);
Linux kernel - Deliverables
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